Timothy Mulrooney / SX1272Liby

first draft

Dependents:   LoRaWAN-demo-72_tjm frdm_LoRa_Connect_Woodstream_Demo_tjm frdm_LoRa_Connect_Woodstream_Demo_jlc

Fork of SX1272Lib by Semtech

sx1272/sx1272-hal.cpp@3:73a1f904eaa5, 2016-03-09 (annotated)

Committer:
tmulrooney
Date:
Wed Mar 09 15:13:46 2016 +0000
Revision:
3:73a1f904eaa5
Parent:
2:cd1093b6676f
Child:
4:352d0947f887
first draft

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mluis 0:45c4f0364ca4 1 /*
mluis 0:45c4f0364ca4 2 / _____) _ | |
mluis 0:45c4f0364ca4 3 ( (____ _____ ____ _| |_ _____ ____| |__
mluis 0:45c4f0364ca4 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
mluis 0:45c4f0364ca4 5 _____) ) ____| | | || |_| ____( (___| | | |
mluis 0:45c4f0364ca4 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 0:45c4f0364ca4 7 (C) 2015 Semtech
mluis 0:45c4f0364ca4 8
mluis 0:45c4f0364ca4 9 Description: -
mluis 0:45c4f0364ca4 10
mluis 0:45c4f0364ca4 11 License: Revised BSD License, see LICENSE.TXT file include in the project
mluis 0:45c4f0364ca4 12
mluis 0:45c4f0364ca4 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
mluis 0:45c4f0364ca4 14 */
mluis 0:45c4f0364ca4 15 #include "sx1272-hal.h"
mluis 0:45c4f0364ca4 16
GregCr 2:cd1093b6676f 17 const RadioRegisters_t SX1272MB2xAS::RadioRegsInit[] = RADIO_INIT_REGISTERS_VALUE;
mluis 0:45c4f0364ca4 18
GregCr 2:cd1093b6676f 19 SX1272MB2xAS::SX1272MB2xAS( RadioEvents_t *events,
mluis 0:45c4f0364ca4 20 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
mluis 0:45c4f0364ca4 21 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5,
mluis 0:45c4f0364ca4 22 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 23 PinName rfSwitchCntr1, PinName rfSwitchCntr2 )
dudmuck 1:b0372ef620d0 24 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 25 PinName txctl, PinName rxctl )
mluis 0:45c4f0364ca4 26 #else
mluis 0:45c4f0364ca4 27 PinName antSwitch )
mluis 0:45c4f0364ca4 28 #endif
tmulrooney 3:73a1f904eaa5 29 // : SX1272( events, mosi, miso, sclk, nss, reset, dio0, dio1, dio2, dio3, dio4, dio5 ),
tmulrooney 3:73a1f904eaa5 30 : SX1272( events, PTD6, PTD7, PTD5, PTD4, reset, PTC2, PTB1, PTC3, PTB0, PTC4, PTC1 ),
mluis 0:45c4f0364ca4 31 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 32 RfSwitchCntr1( rfSwitchCntr1 ),
mluis 0:45c4f0364ca4 33 RfSwitchCntr2( rfSwitchCntr2 ),
dudmuck 1:b0372ef620d0 34 PwrAmpCntr( PD_2 )
dudmuck 1:b0372ef620d0 35 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 36 TxCtl ( txctl ),
dudmuck 1:b0372ef620d0 37 RxCtl ( rxctl )
mluis 0:45c4f0364ca4 38 #else
tmulrooney 3:73a1f904eaa5 39 // AntSwitch( antSwitch ),
tmulrooney 3:73a1f904eaa5 40 AntSwitch( PTC6 ),
mluis 0:45c4f0364ca4 41 #if( defined ( TARGET_NUCLEO_L152RE ) )
dudmuck 1:b0372ef620d0 42 Fake( D8 )
mluis 0:45c4f0364ca4 43 #else
mluis 0:45c4f0364ca4 44 Fake( A3 )
mluis 0:45c4f0364ca4 45 #endif
mluis 0:45c4f0364ca4 46 #endif
mluis 0:45c4f0364ca4 47 {
mluis 0:45c4f0364ca4 48 this->RadioEvents = events;
mluis 0:45c4f0364ca4 49
mluis 0:45c4f0364ca4 50 Reset( );
mluis 0:45c4f0364ca4 51
mluis 0:45c4f0364ca4 52 IoInit( );
mluis 0:45c4f0364ca4 53
mluis 0:45c4f0364ca4 54 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 55
mluis 0:45c4f0364ca4 56 IoIrqInit( dioIrq );
mluis 0:45c4f0364ca4 57
mluis 0:45c4f0364ca4 58 RadioRegistersInit( );
mluis 0:45c4f0364ca4 59
mluis 0:45c4f0364ca4 60 SetModem( MODEM_FSK );
mluis 0:45c4f0364ca4 61
mluis 0:45c4f0364ca4 62 this->settings.State = RF_IDLE ;
mluis 0:45c4f0364ca4 63 }
mluis 0:45c4f0364ca4 64
GregCr 2:cd1093b6676f 65 SX1272MB2xAS::SX1272MB2xAS( RadioEvents_t *events )
mluis 0:45c4f0364ca4 66 #if defined ( TARGET_NUCLEO_L152RE )
mluis 0:45c4f0364ca4 67 : SX1272( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, A3, D9 ), // For NUCLEO L152RE dio4 is on port A3
mluis 0:45c4f0364ca4 68 AntSwitch( A4 ),
mluis 0:45c4f0364ca4 69 Fake( D8 )
mluis 0:45c4f0364ca4 70 #elif defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 71 : SX1272( events, PB_15, PB_14, PB_13, PB_12, PC_2, PC_6, PC_10, PC_11, PC_8, PC_9, PC_12 ),
mluis 0:45c4f0364ca4 72 RfSwitchCntr1( PC_4 ),
mluis 0:45c4f0364ca4 73 RfSwitchCntr2( PC_13 ),
mluis 0:45c4f0364ca4 74 PwrAmpCntr( PD_2 )
dudmuck 1:b0372ef620d0 75 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 76 : SX1272( events, LORA_MOSI, LORA_MISO, LORA_SCK, LORA_NSS, LORA_RESET, LORA_DIO0, LORA_DIO1, LORA_DIO2, LORA_DIO3, LORA_DIO4, LORA_DIO5 ),
dudmuck 1:b0372ef620d0 77 TxCtl( LORA_TXCTL ),
dudmuck 1:b0372ef620d0 78 RxCtl( LORA_RXCTL )
mluis 0:45c4f0364ca4 79 #else
tmulrooney 3:73a1f904eaa5 80 // : SX1272( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
tmulrooney 3:73a1f904eaa5 81 // AntSwitch( A4 ),
tmulrooney 3:73a1f904eaa5 82 : SX1272( events, PTD6, PTD7, PTD5, PTD4, A0, PTC2, PTB1, PTC3, PTB0, PTC4, PTC1 ),
tmulrooney 3:73a1f904eaa5 83 AntSwitch( PTC6 ),
mluis 0:45c4f0364ca4 84 Fake( A3 )
mluis 0:45c4f0364ca4 85 #endif
mluis 0:45c4f0364ca4 86 {
mluis 0:45c4f0364ca4 87 this->RadioEvents = events;
mluis 0:45c4f0364ca4 88
mluis 0:45c4f0364ca4 89 Reset( );
mluis 0:45c4f0364ca4 90
mluis 0:45c4f0364ca4 91 boardConnected = UNKNOWN;
mluis 0:45c4f0364ca4 92
mluis 0:45c4f0364ca4 93 DetectBoardType( );
mluis 0:45c4f0364ca4 94
mluis 0:45c4f0364ca4 95 IoInit( );
mluis 0:45c4f0364ca4 96
mluis 0:45c4f0364ca4 97 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 98 IoIrqInit( dioIrq );
mluis 0:45c4f0364ca4 99
mluis 0:45c4f0364ca4 100 RadioRegistersInit( );
mluis 0:45c4f0364ca4 101
mluis 0:45c4f0364ca4 102 SetModem( MODEM_FSK );
mluis 0:45c4f0364ca4 103
mluis 0:45c4f0364ca4 104 this->settings.State = RF_IDLE ;
mluis 0:45c4f0364ca4 105 }
mluis 0:45c4f0364ca4 106
mluis 0:45c4f0364ca4 107 //-------------------------------------------------------------------------
mluis 0:45c4f0364ca4 108 // Board relative functions
mluis 0:45c4f0364ca4 109 //-------------------------------------------------------------------------
GregCr 2:cd1093b6676f 110 uint8_t SX1272MB2xAS::DetectBoardType( void )
mluis 0:45c4f0364ca4 111 {
mluis 0:45c4f0364ca4 112 if( boardConnected == UNKNOWN )
mluis 0:45c4f0364ca4 113 {
mluis 0:45c4f0364ca4 114 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 115 boardConnected = NA_MOTE_72;
dudmuck 1:b0372ef620d0 116 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 117 boardConnected = MDOT_F411RE;
mluis 0:45c4f0364ca4 118 #else
mluis 0:45c4f0364ca4 119 this->AntSwitch.input( );
mluis 0:45c4f0364ca4 120 wait_ms( 1 );
mluis 0:45c4f0364ca4 121 if( this->AntSwitch == 1 )
mluis 0:45c4f0364ca4 122 {
mluis 0:45c4f0364ca4 123 boardConnected = SX1272MB1DCS;
mluis 0:45c4f0364ca4 124 }
mluis 0:45c4f0364ca4 125 else
mluis 0:45c4f0364ca4 126 {
GregCr 2:cd1093b6676f 127 boardConnected = SX1272MB2XAS;
mluis 0:45c4f0364ca4 128 }
mluis 0:45c4f0364ca4 129 this->AntSwitch.output( );
mluis 0:45c4f0364ca4 130 wait_ms( 1 );
mluis 0:45c4f0364ca4 131 #endif
mluis 0:45c4f0364ca4 132 }
mluis 0:45c4f0364ca4 133 return ( boardConnected );
mluis 0:45c4f0364ca4 134 }
mluis 0:45c4f0364ca4 135
GregCr 2:cd1093b6676f 136 void SX1272MB2xAS::IoInit( void )
mluis 0:45c4f0364ca4 137 {
mluis 0:45c4f0364ca4 138 AntSwInit( );
mluis 0:45c4f0364ca4 139 SpiInit( );
mluis 0:45c4f0364ca4 140 }
mluis 0:45c4f0364ca4 141
GregCr 2:cd1093b6676f 142 void SX1272MB2xAS::RadioRegistersInit( )
mluis 0:45c4f0364ca4 143 {
mluis 0:45c4f0364ca4 144 uint8_t i = 0;
mluis 0:45c4f0364ca4 145 for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
mluis 0:45c4f0364ca4 146 {
mluis 0:45c4f0364ca4 147 SetModem( RadioRegsInit[i].Modem );
mluis 0:45c4f0364ca4 148 Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
mluis 0:45c4f0364ca4 149 }
mluis 0:45c4f0364ca4 150 }
mluis 0:45c4f0364ca4 151
GregCr 2:cd1093b6676f 152 void SX1272MB2xAS::SpiInit( void )
mluis 0:45c4f0364ca4 153 {
mluis 0:45c4f0364ca4 154 nss = 1;
mluis 0:45c4f0364ca4 155 spi.format( 8,0 );
mluis 0:45c4f0364ca4 156 uint32_t frequencyToSet = 8000000;
dudmuck 1:b0372ef620d0 157 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_MOTE_L152RC ) || defined ( TARGET_LPC11U6X ) || defined ( TARGET_MTS_MDOT_F411RE ) )
mluis 0:45c4f0364ca4 158 spi.frequency( frequencyToSet );
mluis 0:45c4f0364ca4 159 #elif( defined ( TARGET_KL25Z ) ) //busclock frequency is halved -> double the spi frequency to compensate
mluis 0:45c4f0364ca4 160 spi.frequency( frequencyToSet * 2 );
mluis 0:45c4f0364ca4 161 #else
mluis 0:45c4f0364ca4 162 #warning "Check the board's SPI frequency"
mluis 0:45c4f0364ca4 163 #endif
mluis 0:45c4f0364ca4 164 wait(0.1);
mluis 0:45c4f0364ca4 165 }
mluis 0:45c4f0364ca4 166
GregCr 2:cd1093b6676f 167 void SX1272MB2xAS::IoIrqInit( DioIrqHandler *irqHandlers )
mluis 0:45c4f0364ca4 168 {
mluis 0:45c4f0364ca4 169 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_MOTE_L152RC ) || defined ( TARGET_LPC11U6X ) )
mluis 0:45c4f0364ca4 170 dio0.mode( PullDown );
mluis 0:45c4f0364ca4 171 dio1.mode( PullDown );
mluis 0:45c4f0364ca4 172 dio2.mode( PullDown );
mluis 0:45c4f0364ca4 173 dio3.mode( PullDown );
mluis 0:45c4f0364ca4 174 dio4.mode( PullDown );
mluis 0:45c4f0364ca4 175 #endif
GregCr 2:cd1093b6676f 176 dio0.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[0] ) );
GregCr 2:cd1093b6676f 177 dio1.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[1] ) );
GregCr 2:cd1093b6676f 178 dio2.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[2] ) );
GregCr 2:cd1093b6676f 179 dio3.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[3] ) );
GregCr 2:cd1093b6676f 180 dio4.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[4] ) );
mluis 0:45c4f0364ca4 181 }
mluis 0:45c4f0364ca4 182
GregCr 2:cd1093b6676f 183 void SX1272MB2xAS::IoDeInit( void )
mluis 0:45c4f0364ca4 184 {
mluis 0:45c4f0364ca4 185 //nothing
mluis 0:45c4f0364ca4 186 }
mluis 0:45c4f0364ca4 187
GregCr 2:cd1093b6676f 188 uint8_t SX1272MB2xAS::GetPaSelect( uint32_t channel )
mluis 0:45c4f0364ca4 189 {
dudmuck 1:b0372ef620d0 190 if( boardConnected == SX1272MB1DCS || boardConnected == MDOT_F411RE )
mluis 0:45c4f0364ca4 191 {
mluis 0:45c4f0364ca4 192 return RF_PACONFIG_PASELECT_PABOOST;
mluis 0:45c4f0364ca4 193 }
mluis 0:45c4f0364ca4 194 else
mluis 0:45c4f0364ca4 195 {
mluis 0:45c4f0364ca4 196 return RF_PACONFIG_PASELECT_RFO;
mluis 0:45c4f0364ca4 197 }
mluis 0:45c4f0364ca4 198 }
mluis 0:45c4f0364ca4 199
GregCr 2:cd1093b6676f 200 void SX1272MB2xAS::SetAntSwLowPower( bool status )
mluis 0:45c4f0364ca4 201 {
mluis 0:45c4f0364ca4 202 if( isRadioActive != status )
mluis 0:45c4f0364ca4 203 {
mluis 0:45c4f0364ca4 204 isRadioActive = status;
mluis 0:45c4f0364ca4 205
mluis 0:45c4f0364ca4 206 if( status == false )
mluis 0:45c4f0364ca4 207 {
mluis 0:45c4f0364ca4 208 AntSwInit( );
mluis 0:45c4f0364ca4 209 }
mluis 0:45c4f0364ca4 210 else
mluis 0:45c4f0364ca4 211 {
mluis 0:45c4f0364ca4 212 AntSwDeInit( );
mluis 0:45c4f0364ca4 213 }
mluis 0:45c4f0364ca4 214 }
mluis 0:45c4f0364ca4 215 }
mluis 0:45c4f0364ca4 216
GregCr 2:cd1093b6676f 217 void SX1272MB2xAS::AntSwInit( void )
mluis 0:45c4f0364ca4 218 {
mluis 0:45c4f0364ca4 219 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 220 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 221 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 222 this->PwrAmpCntr = 0;
dudmuck 1:b0372ef620d0 223 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 224 this->TxCtl = 0;
dudmuck 1:b0372ef620d0 225 this->RxCtl = 0;
mluis 0:45c4f0364ca4 226 #else
mluis 0:45c4f0364ca4 227 this->AntSwitch = 0;
mluis 0:45c4f0364ca4 228 #endif
mluis 0:45c4f0364ca4 229 }
mluis 0:45c4f0364ca4 230
GregCr 2:cd1093b6676f 231 void SX1272MB2xAS::AntSwDeInit( void )
mluis 0:45c4f0364ca4 232 {
mluis 0:45c4f0364ca4 233 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 234 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 235 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 236 this->PwrAmpCntr = 0;
dudmuck 1:b0372ef620d0 237 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 238 this->TxCtl = 0;
dudmuck 1:b0372ef620d0 239 this->RxCtl = 0;
mluis 0:45c4f0364ca4 240 #else
mluis 0:45c4f0364ca4 241 this->AntSwitch = 0;
mluis 0:45c4f0364ca4 242 #endif
mluis 0:45c4f0364ca4 243 }
mluis 0:45c4f0364ca4 244
GregCr 2:cd1093b6676f 245 void SX1272MB2xAS::SetAntSw( uint8_t rxTx )
mluis 0:45c4f0364ca4 246 {
mluis 0:45c4f0364ca4 247 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 248 switch( this->currentOpMode )
mluis 0:45c4f0364ca4 249 {
mluis 0:45c4f0364ca4 250 case RFLR_OPMODE_TRANSMITTER:
mluis 0:45c4f0364ca4 251 if( ( Read( REG_PACONFIG ) & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
mluis 0:45c4f0364ca4 252 {
mluis 0:45c4f0364ca4 253 this->RfSwitchCntr1 = 1;
mluis 0:45c4f0364ca4 254 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 255 }
mluis 0:45c4f0364ca4 256 else
mluis 0:45c4f0364ca4 257 {
mluis 0:45c4f0364ca4 258 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 259 this->RfSwitchCntr2 = 1;
mluis 0:45c4f0364ca4 260 }
mluis 0:45c4f0364ca4 261 break;
mluis 0:45c4f0364ca4 262 case RFLR_OPMODE_RECEIVER:
mluis 0:45c4f0364ca4 263 case RFLR_OPMODE_RECEIVER_SINGLE:
mluis 0:45c4f0364ca4 264 case RFLR_OPMODE_CAD:
mluis 0:45c4f0364ca4 265 this->RfSwitchCntr1 = 1;
mluis 0:45c4f0364ca4 266 this->RfSwitchCntr2 = 1;
mluis 0:45c4f0364ca4 267 break;
mluis 0:45c4f0364ca4 268 default:
mluis 0:45c4f0364ca4 269 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 270 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 271 this->PwrAmpCntr = 0;
mluis 0:45c4f0364ca4 272 break;
mluis 0:45c4f0364ca4 273 }
dudmuck 1:b0372ef620d0 274 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 275 if( this->rxTx == rxTx )
dudmuck 1:b0372ef620d0 276 {
dudmuck 1:b0372ef620d0 277 //no need to go further
dudmuck 1:b0372ef620d0 278 return;
dudmuck 1:b0372ef620d0 279 }
dudmuck 1:b0372ef620d0 280
dudmuck 1:b0372ef620d0 281 /* SKY13350 */
dudmuck 1:b0372ef620d0 282 this->rxTx = rxTx;
dudmuck 1:b0372ef620d0 283
dudmuck 1:b0372ef620d0 284 // 1: Tx, 0: Rx
dudmuck 1:b0372ef620d0 285 if( rxTx != 0 )
dudmuck 1:b0372ef620d0 286 {
dudmuck 1:b0372ef620d0 287 this->TxCtl = 1;
dudmuck 1:b0372ef620d0 288 this->RxCtl = 0;
dudmuck 1:b0372ef620d0 289 }
dudmuck 1:b0372ef620d0 290 else
dudmuck 1:b0372ef620d0 291 {
dudmuck 1:b0372ef620d0 292 this->TxCtl = 0;
dudmuck 1:b0372ef620d0 293 this->RxCtl = 1;
dudmuck 1:b0372ef620d0 294 }
mluis 0:45c4f0364ca4 295 #else
mluis 0:45c4f0364ca4 296 if( this->rxTx == rxTx )
mluis 0:45c4f0364ca4 297 {
mluis 0:45c4f0364ca4 298 //no need to go further
mluis 0:45c4f0364ca4 299 return;
mluis 0:45c4f0364ca4 300 }
mluis 0:45c4f0364ca4 301
mluis 0:45c4f0364ca4 302 this->rxTx = rxTx;
mluis 0:45c4f0364ca4 303
mluis 0:45c4f0364ca4 304 // 1: Tx, 0: Rx
mluis 0:45c4f0364ca4 305 if( rxTx != 0 )
mluis 0:45c4f0364ca4 306 {
mluis 0:45c4f0364ca4 307 this->AntSwitch = 1;
mluis 0:45c4f0364ca4 308 }
mluis 0:45c4f0364ca4 309 else
mluis 0:45c4f0364ca4 310 {
mluis 0:45c4f0364ca4 311 this->AntSwitch = 0;
mluis 0:45c4f0364ca4 312 }
mluis 0:45c4f0364ca4 313 #endif
mluis 0:45c4f0364ca4 314 }
mluis 0:45c4f0364ca4 315
GregCr 2:cd1093b6676f 316 bool SX1272MB2xAS::CheckRfFrequency( uint32_t frequency )
mluis 0:45c4f0364ca4 317 {
mluis 0:45c4f0364ca4 318 //TODO: Implement check, currently all frequencies are supported
mluis 0:45c4f0364ca4 319 return true;
mluis 0:45c4f0364ca4 320 }
mluis 0:45c4f0364ca4 321
mluis 0:45c4f0364ca4 322
GregCr 2:cd1093b6676f 323 void SX1272MB2xAS::Reset( void )
mluis 0:45c4f0364ca4 324 {
mluis 0:45c4f0364ca4 325 reset.output();
mluis 0:45c4f0364ca4 326 reset = 0;
mluis 0:45c4f0364ca4 327 wait_ms( 1 );
mluis 0:45c4f0364ca4 328 reset.input();
mluis 0:45c4f0364ca4 329 wait_ms( 6 );
mluis 0:45c4f0364ca4 330 }
mluis 0:45c4f0364ca4 331
GregCr 2:cd1093b6676f 332 void SX1272MB2xAS::Write( uint8_t addr, uint8_t data )
mluis 0:45c4f0364ca4 333 {
mluis 0:45c4f0364ca4 334 Write( addr, &data, 1 );
mluis 0:45c4f0364ca4 335 }
mluis 0:45c4f0364ca4 336
GregCr 2:cd1093b6676f 337 uint8_t SX1272MB2xAS::Read( uint8_t addr )
mluis 0:45c4f0364ca4 338 {
mluis 0:45c4f0364ca4 339 uint8_t data;
mluis 0:45c4f0364ca4 340 Read( addr, &data, 1 );
mluis 0:45c4f0364ca4 341 return data;
mluis 0:45c4f0364ca4 342 }
mluis 0:45c4f0364ca4 343
GregCr 2:cd1093b6676f 344 void SX1272MB2xAS::Write( uint8_t addr, uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 345 {
mluis 0:45c4f0364ca4 346 uint8_t i;
mluis 0:45c4f0364ca4 347
mluis 0:45c4f0364ca4 348 nss = 0;
mluis 0:45c4f0364ca4 349 spi.write( addr | 0x80 );
mluis 0:45c4f0364ca4 350 for( i = 0; i < size; i++ )
mluis 0:45c4f0364ca4 351 {
mluis 0:45c4f0364ca4 352 spi.write( buffer[i] );
mluis 0:45c4f0364ca4 353 }
mluis 0:45c4f0364ca4 354 nss = 1;
mluis 0:45c4f0364ca4 355 }
mluis 0:45c4f0364ca4 356
GregCr 2:cd1093b6676f 357 void SX1272MB2xAS::Read( uint8_t addr, uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 358 {
mluis 0:45c4f0364ca4 359 uint8_t i;
mluis 0:45c4f0364ca4 360
mluis 0:45c4f0364ca4 361 nss = 0;
mluis 0:45c4f0364ca4 362 spi.write( addr & 0x7F );
mluis 0:45c4f0364ca4 363 for( i = 0; i < size; i++ )
mluis 0:45c4f0364ca4 364 {
mluis 0:45c4f0364ca4 365 buffer[i] = spi.write( 0 );
mluis 0:45c4f0364ca4 366 }
mluis 0:45c4f0364ca4 367 nss = 1;
mluis 0:45c4f0364ca4 368 }
mluis 0:45c4f0364ca4 369
GregCr 2:cd1093b6676f 370 void SX1272MB2xAS::WriteFifo( uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 371 {
mluis 0:45c4f0364ca4 372 Write( 0, buffer, size );
mluis 0:45c4f0364ca4 373 }
mluis 0:45c4f0364ca4 374
GregCr 2:cd1093b6676f 375 void SX1272MB2xAS::ReadFifo( uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 376 {
mluis 0:45c4f0364ca4 377 Read( 0, buffer, size );
mluis 0:45c4f0364ca4 378 }