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targets/cmsis/core_caFunc.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
141:a2b798ec44f6 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file core_caFunc.h
<> 144:ef7eb2e8f9f7 3 * @brief CMSIS Cortex-A Core Function Access Header File
<> 144:ef7eb2e8f9f7 4 * @version V3.10
<> 144:ef7eb2e8f9f7 5 * @date 30 Oct 2013
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * @note
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 ******************************************************************************/
<> 144:ef7eb2e8f9f7 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
<> 144:ef7eb2e8f9f7 11
<> 144:ef7eb2e8f9f7 12 All rights reserved.
<> 144:ef7eb2e8f9f7 13 Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 14 modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 - Redistributions of source code must retain the above copyright
<> 144:ef7eb2e8f9f7 16 notice, this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 - Redistributions in binary form must reproduce the above copyright
<> 144:ef7eb2e8f9f7 18 notice, this list of conditions and the following disclaimer in the
<> 144:ef7eb2e8f9f7 19 documentation and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 - Neither the name of ARM nor the names of its contributors may be used
<> 144:ef7eb2e8f9f7 21 to endorse or promote products derived from this software without
<> 144:ef7eb2e8f9f7 22 specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 144:ef7eb2e8f9f7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 144:ef7eb2e8f9f7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 144:ef7eb2e8f9f7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 144:ef7eb2e8f9f7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 144:ef7eb2e8f9f7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 144:ef7eb2e8f9f7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 144:ef7eb2e8f9f7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 144:ef7eb2e8f9f7 34 POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 35 ---------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 #ifndef __CORE_CAFUNC_H__
<> 144:ef7eb2e8f9f7 39 #define __CORE_CAFUNC_H__
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /* ########################### Core Function Access ########################### */
<> 144:ef7eb2e8f9f7 43 /** \ingroup CMSIS_Core_FunctionInterface
<> 144:ef7eb2e8f9f7 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
<> 144:ef7eb2e8f9f7 45 @{
<> 144:ef7eb2e8f9f7 46 */
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 144:ef7eb2e8f9f7 49 /* ARM armcc specific functions */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 #if (__ARMCC_VERSION < 400677)
<> 144:ef7eb2e8f9f7 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
<> 144:ef7eb2e8f9f7 53 #endif
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 #define MODE_USR 0x10
<> 144:ef7eb2e8f9f7 56 #define MODE_FIQ 0x11
<> 144:ef7eb2e8f9f7 57 #define MODE_IRQ 0x12
<> 144:ef7eb2e8f9f7 58 #define MODE_SVC 0x13
<> 144:ef7eb2e8f9f7 59 #define MODE_MON 0x16
<> 144:ef7eb2e8f9f7 60 #define MODE_ABT 0x17
<> 144:ef7eb2e8f9f7 61 #define MODE_HYP 0x1A
<> 144:ef7eb2e8f9f7 62 #define MODE_UND 0x1B
<> 144:ef7eb2e8f9f7 63 #define MODE_SYS 0x1F
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /** \brief Get APSR Register
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 This function returns the content of the APSR Register.
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 \return APSR Register value
<> 144:ef7eb2e8f9f7 70 */
<> 144:ef7eb2e8f9f7 71 __STATIC_INLINE uint32_t __get_APSR(void)
<> 144:ef7eb2e8f9f7 72 {
<> 144:ef7eb2e8f9f7 73 register uint32_t __regAPSR __ASM("apsr");
<> 144:ef7eb2e8f9f7 74 return(__regAPSR);
<> 144:ef7eb2e8f9f7 75 }
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /** \brief Get CPSR Register
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 This function returns the content of the CPSR Register.
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 \return CPSR Register value
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84 __STATIC_INLINE uint32_t __get_CPSR(void)
<> 144:ef7eb2e8f9f7 85 {
<> 144:ef7eb2e8f9f7 86 register uint32_t __regCPSR __ASM("cpsr");
<> 144:ef7eb2e8f9f7 87 return(__regCPSR);
<> 144:ef7eb2e8f9f7 88 }
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /** \brief Set Stack Pointer
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 This function assigns the given value to the current stack pointer.
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 \param [in] topOfStack Stack Pointer value to set
<> 144:ef7eb2e8f9f7 95 */
<> 144:ef7eb2e8f9f7 96 register uint32_t __regSP __ASM("sp");
<> 144:ef7eb2e8f9f7 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
<> 144:ef7eb2e8f9f7 98 {
<> 144:ef7eb2e8f9f7 99 __regSP = topOfStack;
<> 144:ef7eb2e8f9f7 100 }
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /** \brief Get link register
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 This function returns the value of the link register
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 \return Value of link register
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109 register uint32_t __reglr __ASM("lr");
<> 144:ef7eb2e8f9f7 110 __STATIC_INLINE uint32_t __get_LR(void)
<> 144:ef7eb2e8f9f7 111 {
<> 144:ef7eb2e8f9f7 112 return(__reglr);
<> 144:ef7eb2e8f9f7 113 }
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /** \brief Set link register
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 This function sets the value of the link register
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 \param [in] lr LR value to set
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121 __STATIC_INLINE void __set_LR(uint32_t lr)
<> 144:ef7eb2e8f9f7 122 {
<> 144:ef7eb2e8f9f7 123 __reglr = lr;
<> 144:ef7eb2e8f9f7 124 }
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /** \brief Set Process Stack Pointer
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
<> 144:ef7eb2e8f9f7 133 {
<> 144:ef7eb2e8f9f7 134 ARM
<> 144:ef7eb2e8f9f7 135 PRESERVE8
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
<> 144:ef7eb2e8f9f7 138 MRS R1, CPSR
<> 144:ef7eb2e8f9f7 139 CPS #MODE_SYS ;no effect in USR mode
<> 144:ef7eb2e8f9f7 140 MOV SP, R0
<> 144:ef7eb2e8f9f7 141 MSR CPSR_c, R1 ;no effect in USR mode
<> 144:ef7eb2e8f9f7 142 ISB
<> 144:ef7eb2e8f9f7 143 BX LR
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 }
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /** \brief Set User Mode
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 This function changes the processor state to User Mode
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151 __STATIC_ASM void __set_CPS_USR(void)
<> 144:ef7eb2e8f9f7 152 {
<> 144:ef7eb2e8f9f7 153 ARM
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 CPS #MODE_USR
<> 144:ef7eb2e8f9f7 156 BX LR
<> 144:ef7eb2e8f9f7 157 }
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /** \brief Enable FIQ
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
<> 144:ef7eb2e8f9f7 163 Can only be executed in Privileged modes.
<> 144:ef7eb2e8f9f7 164 */
<> 144:ef7eb2e8f9f7 165 #define __enable_fault_irq __enable_fiq
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /** \brief Disable FIQ
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
<> 144:ef7eb2e8f9f7 171 Can only be executed in Privileged modes.
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173 #define __disable_fault_irq __disable_fiq
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /** \brief Get FPSCR
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 This function returns the current value of the Floating Point Status/Control register.
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 \return Floating Point Status/Control register value
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
<> 144:ef7eb2e8f9f7 183 {
<> 144:ef7eb2e8f9f7 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 144:ef7eb2e8f9f7 185 register uint32_t __regfpscr __ASM("fpscr");
<> 144:ef7eb2e8f9f7 186 return(__regfpscr);
<> 144:ef7eb2e8f9f7 187 #else
<> 144:ef7eb2e8f9f7 188 return(0);
<> 144:ef7eb2e8f9f7 189 #endif
<> 144:ef7eb2e8f9f7 190 }
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /** \brief Set FPSCR
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 This function assigns the given value to the Floating Point Status/Control register.
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 \param [in] fpscr Floating Point Status/Control value to set
<> 144:ef7eb2e8f9f7 198 */
<> 144:ef7eb2e8f9f7 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
<> 144:ef7eb2e8f9f7 200 {
<> 144:ef7eb2e8f9f7 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 144:ef7eb2e8f9f7 202 register uint32_t __regfpscr __ASM("fpscr");
<> 144:ef7eb2e8f9f7 203 __regfpscr = (fpscr);
<> 144:ef7eb2e8f9f7 204 #endif
<> 144:ef7eb2e8f9f7 205 }
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /** \brief Get FPEXC
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 This function returns the current value of the Floating Point Exception Control register.
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 \return Floating Point Exception Control register value
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
<> 144:ef7eb2e8f9f7 214 {
<> 144:ef7eb2e8f9f7 215 #if (__FPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 216 register uint32_t __regfpexc __ASM("fpexc");
<> 144:ef7eb2e8f9f7 217 return(__regfpexc);
<> 144:ef7eb2e8f9f7 218 #else
<> 144:ef7eb2e8f9f7 219 return(0);
<> 144:ef7eb2e8f9f7 220 #endif
<> 144:ef7eb2e8f9f7 221 }
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /** \brief Set FPEXC
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 This function assigns the given value to the Floating Point Exception Control register.
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 \param [in] fpscr Floating Point Exception Control value to set
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 #if (__FPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 233 register uint32_t __regfpexc __ASM("fpexc");
<> 144:ef7eb2e8f9f7 234 __regfpexc = (fpexc);
<> 144:ef7eb2e8f9f7 235 #endif
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /** \brief Get CPACR
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 This function returns the current value of the Coprocessor Access Control register.
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 \return Coprocessor Access Control register value
<> 144:ef7eb2e8f9f7 243 */
<> 144:ef7eb2e8f9f7 244 __STATIC_INLINE uint32_t __get_CPACR(void)
<> 144:ef7eb2e8f9f7 245 {
<> 144:ef7eb2e8f9f7 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
<> 144:ef7eb2e8f9f7 247 return __regCPACR;
<> 144:ef7eb2e8f9f7 248 }
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /** \brief Set CPACR
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 This function assigns the given value to the Coprocessor Access Control register.
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 \param [in] cpacr Coprocessor Acccess Control value to set
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
<> 144:ef7eb2e8f9f7 257 {
<> 144:ef7eb2e8f9f7 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
<> 144:ef7eb2e8f9f7 259 __regCPACR = cpacr;
<> 144:ef7eb2e8f9f7 260 __ISB();
<> 144:ef7eb2e8f9f7 261 }
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /** \brief Get CBAR
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 This function returns the value of the Configuration Base Address register.
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 \return Configuration Base Address register value
<> 144:ef7eb2e8f9f7 268 */
<> 144:ef7eb2e8f9f7 269 __STATIC_INLINE uint32_t __get_CBAR() {
<> 144:ef7eb2e8f9f7 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
<> 144:ef7eb2e8f9f7 271 return(__regCBAR);
<> 144:ef7eb2e8f9f7 272 }
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /** \brief Get TTBR0
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 This function returns the value of the Translation Table Base Register 0.
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 \return Translation Table Base Register 0 value
<> 144:ef7eb2e8f9f7 279 */
<> 144:ef7eb2e8f9f7 280 __STATIC_INLINE uint32_t __get_TTBR0() {
<> 144:ef7eb2e8f9f7 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
<> 144:ef7eb2e8f9f7 282 return(__regTTBR0);
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /** \brief Set TTBR0
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 This function assigns the given value to the Translation Table Base Register 0.
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
<> 144:ef7eb2e8f9f7 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
<> 144:ef7eb2e8f9f7 293 __regTTBR0 = ttbr0;
<> 144:ef7eb2e8f9f7 294 __ISB();
<> 144:ef7eb2e8f9f7 295 }
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /** \brief Get DACR
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 This function returns the value of the Domain Access Control Register.
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 \return Domain Access Control Register value
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303 __STATIC_INLINE uint32_t __get_DACR() {
<> 144:ef7eb2e8f9f7 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
<> 144:ef7eb2e8f9f7 305 return(__regDACR);
<> 144:ef7eb2e8f9f7 306 }
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /** \brief Set DACR
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 This function assigns the given value to the Domain Access Control Register.
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 \param [in] dacr Domain Access Control Register value to set
<> 144:ef7eb2e8f9f7 313 */
<> 144:ef7eb2e8f9f7 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
<> 144:ef7eb2e8f9f7 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
<> 144:ef7eb2e8f9f7 316 __regDACR = dacr;
<> 144:ef7eb2e8f9f7 317 __ISB();
<> 144:ef7eb2e8f9f7 318 }
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /******************************** Cache and BTAC enable ****************************************************/
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /** \brief Set SCTLR
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 This function assigns the given value to the System Control Register.
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 \param [in] sctlr System Control Register value to set
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
<> 144:ef7eb2e8f9f7 329 {
<> 144:ef7eb2e8f9f7 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
<> 144:ef7eb2e8f9f7 331 __regSCTLR = sctlr;
<> 144:ef7eb2e8f9f7 332 }
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /** \brief Get SCTLR
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 This function returns the value of the System Control Register.
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 \return System Control Register value
<> 144:ef7eb2e8f9f7 339 */
<> 144:ef7eb2e8f9f7 340 __STATIC_INLINE uint32_t __get_SCTLR() {
<> 144:ef7eb2e8f9f7 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
<> 144:ef7eb2e8f9f7 342 return(__regSCTLR);
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /** \brief Enable Caches
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 Enable Caches
<> 144:ef7eb2e8f9f7 348 */
<> 144:ef7eb2e8f9f7 349 __STATIC_INLINE void __enable_caches(void) {
<> 144:ef7eb2e8f9f7 350 // Set I bit 12 to enable I Cache
<> 144:ef7eb2e8f9f7 351 // Set C bit 2 to enable D Cache
<> 144:ef7eb2e8f9f7 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
<> 144:ef7eb2e8f9f7 353 }
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /** \brief Disable Caches
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 Disable Caches
<> 144:ef7eb2e8f9f7 358 */
<> 144:ef7eb2e8f9f7 359 __STATIC_INLINE void __disable_caches(void) {
<> 144:ef7eb2e8f9f7 360 // Clear I bit 12 to disable I Cache
<> 144:ef7eb2e8f9f7 361 // Clear C bit 2 to disable D Cache
<> 144:ef7eb2e8f9f7 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
<> 144:ef7eb2e8f9f7 363 __ISB();
<> 144:ef7eb2e8f9f7 364 }
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /** \brief Enable BTAC
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 Enable BTAC
<> 144:ef7eb2e8f9f7 369 */
<> 144:ef7eb2e8f9f7 370 __STATIC_INLINE void __enable_btac(void) {
<> 144:ef7eb2e8f9f7 371 // Set Z bit 11 to enable branch prediction
<> 144:ef7eb2e8f9f7 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
<> 144:ef7eb2e8f9f7 373 __ISB();
<> 144:ef7eb2e8f9f7 374 }
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /** \brief Disable BTAC
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 Disable BTAC
<> 144:ef7eb2e8f9f7 379 */
<> 144:ef7eb2e8f9f7 380 __STATIC_INLINE void __disable_btac(void) {
<> 144:ef7eb2e8f9f7 381 // Clear Z bit 11 to disable branch prediction
<> 144:ef7eb2e8f9f7 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
<> 144:ef7eb2e8f9f7 383 }
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /** \brief Enable MMU
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 Enable MMU
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390 __STATIC_INLINE void __enable_mmu(void) {
<> 144:ef7eb2e8f9f7 391 // Set M bit 0 to enable the MMU
<> 144:ef7eb2e8f9f7 392 // Set AFE bit to enable simplified access permissions model
<> 144:ef7eb2e8f9f7 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
<> 144:ef7eb2e8f9f7 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
<> 144:ef7eb2e8f9f7 395 __ISB();
<> 144:ef7eb2e8f9f7 396 }
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 /** \brief Disable MMU
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 Disable MMU
<> 144:ef7eb2e8f9f7 401 */
<> 144:ef7eb2e8f9f7 402 __STATIC_INLINE void __disable_mmu(void) {
<> 144:ef7eb2e8f9f7 403 // Clear M bit 0 to disable the MMU
<> 144:ef7eb2e8f9f7 404 __set_SCTLR( __get_SCTLR() & ~1);
<> 144:ef7eb2e8f9f7 405 __ISB();
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /******************************** TLB maintenance operations ************************************************/
<> 144:ef7eb2e8f9f7 409 /** \brief Invalidate the whole tlb
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 TLBIALL. Invalidate the whole tlb
<> 144:ef7eb2e8f9f7 412 */
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
<> 144:ef7eb2e8f9f7 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
<> 144:ef7eb2e8f9f7 416 __TLBIALL = 0;
<> 144:ef7eb2e8f9f7 417 __DSB();
<> 144:ef7eb2e8f9f7 418 __ISB();
<> 144:ef7eb2e8f9f7 419 }
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /******************************** BTB maintenance operations ************************************************/
<> 144:ef7eb2e8f9f7 422 /** \brief Invalidate entire branch predictor array
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 BPIALL. Branch Predictor Invalidate All.
<> 144:ef7eb2e8f9f7 425 */
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 __STATIC_INLINE void __v7_inv_btac(void) {
<> 144:ef7eb2e8f9f7 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
<> 144:ef7eb2e8f9f7 429 __BPIALL = 0;
<> 144:ef7eb2e8f9f7 430 __DSB(); //ensure completion of the invalidation
<> 144:ef7eb2e8f9f7 431 __ISB(); //ensure instruction fetch path sees new state
<> 144:ef7eb2e8f9f7 432 }
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /******************************** L1 cache operations ******************************************************/
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 /** \brief Invalidate the whole I$
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 ICIALLU. Instruction Cache Invalidate All to PoU
<> 144:ef7eb2e8f9f7 440 */
<> 144:ef7eb2e8f9f7 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
<> 144:ef7eb2e8f9f7 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
<> 144:ef7eb2e8f9f7 443 __ICIALLU = 0;
<> 144:ef7eb2e8f9f7 444 __DSB(); //ensure completion of the invalidation
<> 144:ef7eb2e8f9f7 445 __ISB(); //ensure instruction fetch path sees new I cache state
<> 144:ef7eb2e8f9f7 446 }
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /** \brief Clean D$ by MVA
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 DCCMVAC. Data cache clean by MVA to PoC
<> 144:ef7eb2e8f9f7 451 */
<> 144:ef7eb2e8f9f7 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
<> 144:ef7eb2e8f9f7 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
<> 144:ef7eb2e8f9f7 454 __DCCMVAC = (uint32_t)va;
<> 144:ef7eb2e8f9f7 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
<> 144:ef7eb2e8f9f7 456 }
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /** \brief Invalidate D$ by MVA
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 DCIMVAC. Data cache invalidate by MVA to PoC
<> 144:ef7eb2e8f9f7 461 */
<> 144:ef7eb2e8f9f7 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
<> 144:ef7eb2e8f9f7 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
<> 144:ef7eb2e8f9f7 464 __DCIMVAC = (uint32_t)va;
<> 144:ef7eb2e8f9f7 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
<> 144:ef7eb2e8f9f7 466 }
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /** \brief Clean and Invalidate D$ by MVA
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
<> 144:ef7eb2e8f9f7 471 */
<> 144:ef7eb2e8f9f7 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
<> 144:ef7eb2e8f9f7 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
<> 144:ef7eb2e8f9f7 474 __DCCIMVAC = (uint32_t)va;
<> 144:ef7eb2e8f9f7 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
<> 144:ef7eb2e8f9f7 476 }
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 /** \brief Clean and Invalidate the entire data or unified cache
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
<> 144:ef7eb2e8f9f7 481 */
<> 144:ef7eb2e8f9f7 482 #pragma push
<> 144:ef7eb2e8f9f7 483 #pragma arm
<> 144:ef7eb2e8f9f7 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
<> 144:ef7eb2e8f9f7 485 ARM
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 PUSH {R4-R11}
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
<> 144:ef7eb2e8f9f7 490 ANDS R3, R6, #0x07000000 // Extract coherency level
<> 144:ef7eb2e8f9f7 491 MOV R3, R3, LSR #23 // Total cache levels << 1
<> 144:ef7eb2e8f9f7 492 BEQ Finished // If 0, no need to clean
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 MOV R10, #0 // R10 holds current cache level << 1
<> 144:ef7eb2e8f9f7 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
<> 144:ef7eb2e8f9f7 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
<> 144:ef7eb2e8f9f7 497 AND R1, R1, #7 // Isolate those lower 3 bits
<> 144:ef7eb2e8f9f7 498 CMP R1, #2
<> 144:ef7eb2e8f9f7 499 BLT Skip // No cache or only instruction cache at this level
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
<> 144:ef7eb2e8f9f7 502 ISB // ISB to sync the change to the CacheSizeID reg
<> 144:ef7eb2e8f9f7 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
<> 144:ef7eb2e8f9f7 504 AND R2, R1, #7 // Extract the line length field
<> 144:ef7eb2e8f9f7 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
<> 144:ef7eb2e8f9f7 506 LDR R4, =0x3FF
<> 144:ef7eb2e8f9f7 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
<> 144:ef7eb2e8f9f7 508 CLZ R5, R4 // R5 is the bit position of the way size increment
<> 144:ef7eb2e8f9f7 509 LDR R7, =0x7FFF
<> 144:ef7eb2e8f9f7 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
<> 144:ef7eb2e8f9f7 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
<> 144:ef7eb2e8f9f7 516 CMP R0, #0
<> 144:ef7eb2e8f9f7 517 BNE Dccsw
<> 144:ef7eb2e8f9f7 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
<> 144:ef7eb2e8f9f7 519 B cont
<> 144:ef7eb2e8f9f7 520 Dccsw CMP R0, #1
<> 144:ef7eb2e8f9f7 521 BNE Dccisw
<> 144:ef7eb2e8f9f7 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
<> 144:ef7eb2e8f9f7 523 B cont
<> 144:ef7eb2e8f9f7 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
<> 144:ef7eb2e8f9f7 525 cont SUBS R9, R9, #1 // Decrement the Way number
<> 144:ef7eb2e8f9f7 526 BGE Loop3
<> 144:ef7eb2e8f9f7 527 SUBS R7, R7, #1 // Decrement the Set number
<> 144:ef7eb2e8f9f7 528 BGE Loop2
<> 144:ef7eb2e8f9f7 529 Skip ADD R10, R10, #2 // Increment the cache number
<> 144:ef7eb2e8f9f7 530 CMP R3, R10
<> 144:ef7eb2e8f9f7 531 BGT Loop1
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 Finished
<> 144:ef7eb2e8f9f7 534 DSB
<> 144:ef7eb2e8f9f7 535 POP {R4-R11}
<> 144:ef7eb2e8f9f7 536 BX lr
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 }
<> 144:ef7eb2e8f9f7 539 #pragma pop
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /** \brief Invalidate the whole D$
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 DCISW. Invalidate by Set/Way
<> 144:ef7eb2e8f9f7 545 */
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
<> 144:ef7eb2e8f9f7 548 __v7_all_cache(0);
<> 144:ef7eb2e8f9f7 549 }
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /** \brief Clean the whole D$
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 DCCSW. Clean by Set/Way
<> 144:ef7eb2e8f9f7 554 */
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
<> 144:ef7eb2e8f9f7 557 __v7_all_cache(1);
<> 144:ef7eb2e8f9f7 558 }
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /** \brief Clean and invalidate the whole D$
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 DCCISW. Clean and Invalidate by Set/Way
<> 144:ef7eb2e8f9f7 563 */
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
<> 144:ef7eb2e8f9f7 566 __v7_all_cache(2);
<> 144:ef7eb2e8f9f7 567 }
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 #include "core_ca_mmu.h"
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 #define __inline inline
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 inline static uint32_t __disable_irq_iar() {
<> 144:ef7eb2e8f9f7 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
<> 144:ef7eb2e8f9f7 577 __disable_irq();
<> 144:ef7eb2e8f9f7 578 return irq_dis;
<> 144:ef7eb2e8f9f7 579 }
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 #define MODE_USR 0x10
<> 144:ef7eb2e8f9f7 582 #define MODE_FIQ 0x11
<> 144:ef7eb2e8f9f7 583 #define MODE_IRQ 0x12
<> 144:ef7eb2e8f9f7 584 #define MODE_SVC 0x13
<> 144:ef7eb2e8f9f7 585 #define MODE_MON 0x16
<> 144:ef7eb2e8f9f7 586 #define MODE_ABT 0x17
<> 144:ef7eb2e8f9f7 587 #define MODE_HYP 0x1A
<> 144:ef7eb2e8f9f7 588 #define MODE_UND 0x1B
<> 144:ef7eb2e8f9f7 589 #define MODE_SYS 0x1F
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /** \brief Set Process Stack Pointer
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
<> 144:ef7eb2e8f9f7 596 */
<> 144:ef7eb2e8f9f7 597 // from rt_CMSIS.c
<> 144:ef7eb2e8f9f7 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
<> 144:ef7eb2e8f9f7 599 __asm(
<> 144:ef7eb2e8f9f7 600 " ARM\n"
<> 144:ef7eb2e8f9f7 601 // " PRESERVE8\n"
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
<> 144:ef7eb2e8f9f7 604 " MRS R1, CPSR \n"
<> 144:ef7eb2e8f9f7 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
<> 144:ef7eb2e8f9f7 606 " MOV SP, R0 \n"
<> 144:ef7eb2e8f9f7 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
<> 144:ef7eb2e8f9f7 608 " ISB \n"
<> 144:ef7eb2e8f9f7 609 " BX LR \n");
<> 144:ef7eb2e8f9f7 610 }
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /** \brief Set User Mode
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 This function changes the processor state to User Mode
<> 144:ef7eb2e8f9f7 615 */
<> 144:ef7eb2e8f9f7 616 // from rt_CMSIS.c
<> 144:ef7eb2e8f9f7 617 __arm static inline void __set_CPS_USR(void) {
<> 144:ef7eb2e8f9f7 618 __asm(
<> 144:ef7eb2e8f9f7 619 " ARM \n"
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 " CPS #0x10 \n" // MODE_USR
<> 144:ef7eb2e8f9f7 622 " BX LR\n");
<> 144:ef7eb2e8f9f7 623 }
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /** \brief Set TTBR0
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 This function assigns the given value to the Translation Table Base Register 0.
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
<> 144:ef7eb2e8f9f7 630 */
<> 144:ef7eb2e8f9f7 631 // from mmu_Renesas_RZ_A1.c
<> 144:ef7eb2e8f9f7 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
<> 144:ef7eb2e8f9f7 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
<> 144:ef7eb2e8f9f7 634 __ISB();
<> 144:ef7eb2e8f9f7 635 }
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 /** \brief Set DACR
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 This function assigns the given value to the Domain Access Control Register.
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 \param [in] dacr Domain Access Control Register value to set
<> 144:ef7eb2e8f9f7 642 */
<> 144:ef7eb2e8f9f7 643 // from mmu_Renesas_RZ_A1.c
<> 144:ef7eb2e8f9f7 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
<> 144:ef7eb2e8f9f7 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
<> 144:ef7eb2e8f9f7 646 __ISB();
<> 144:ef7eb2e8f9f7 647 }
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 /******************************** Cache and BTAC enable ****************************************************/
<> 144:ef7eb2e8f9f7 651 /** \brief Set SCTLR
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 This function assigns the given value to the System Control Register.
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 \param [in] sctlr System Control Register value to set
<> 144:ef7eb2e8f9f7 656 */
<> 144:ef7eb2e8f9f7 657 // from __enable_mmu()
<> 144:ef7eb2e8f9f7 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
<> 144:ef7eb2e8f9f7 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
<> 144:ef7eb2e8f9f7 660 }
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /** \brief Get SCTLR
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 This function returns the value of the System Control Register.
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 \return System Control Register value
<> 144:ef7eb2e8f9f7 667 */
<> 144:ef7eb2e8f9f7 668 // from __enable_mmu()
<> 144:ef7eb2e8f9f7 669 __STATIC_INLINE uint32_t __get_SCTLR() {
<> 144:ef7eb2e8f9f7 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
<> 144:ef7eb2e8f9f7 671 return __regSCTLR;
<> 144:ef7eb2e8f9f7 672 }
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 /** \brief Enable Caches
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 Enable Caches
<> 144:ef7eb2e8f9f7 677 */
<> 144:ef7eb2e8f9f7 678 // from system_Renesas_RZ_A1.c
<> 144:ef7eb2e8f9f7 679 __STATIC_INLINE void __enable_caches(void) {
<> 144:ef7eb2e8f9f7 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
<> 144:ef7eb2e8f9f7 681 }
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 /** \brief Enable BTAC
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 Enable BTAC
<> 144:ef7eb2e8f9f7 686 */
<> 144:ef7eb2e8f9f7 687 // from system_Renesas_RZ_A1.c
<> 144:ef7eb2e8f9f7 688 __STATIC_INLINE void __enable_btac(void) {
<> 144:ef7eb2e8f9f7 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
<> 144:ef7eb2e8f9f7 690 __ISB();
<> 144:ef7eb2e8f9f7 691 }
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 /** \brief Enable MMU
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 Enable MMU
<> 144:ef7eb2e8f9f7 696 */
<> 144:ef7eb2e8f9f7 697 // from system_Renesas_RZ_A1.c
<> 144:ef7eb2e8f9f7 698 __STATIC_INLINE void __enable_mmu(void) {
<> 144:ef7eb2e8f9f7 699 // Set M bit 0 to enable the MMU
<> 144:ef7eb2e8f9f7 700 // Set AFE bit to enable simplified access permissions model
<> 144:ef7eb2e8f9f7 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
<> 144:ef7eb2e8f9f7 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
<> 144:ef7eb2e8f9f7 703 __ISB();
<> 144:ef7eb2e8f9f7 704 }
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 /******************************** TLB maintenance operations ************************************************/
<> 144:ef7eb2e8f9f7 707 /** \brief Invalidate the whole tlb
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 TLBIALL. Invalidate the whole tlb
<> 144:ef7eb2e8f9f7 710 */
<> 144:ef7eb2e8f9f7 711 // from system_Renesas_RZ_A1.c
<> 144:ef7eb2e8f9f7 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
<> 144:ef7eb2e8f9f7 713 uint32_t val = 0;
<> 144:ef7eb2e8f9f7 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
<> 144:ef7eb2e8f9f7 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
<> 144:ef7eb2e8f9f7 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
<> 144:ef7eb2e8f9f7 717 __DSB();
<> 144:ef7eb2e8f9f7 718 __ISB();
<> 144:ef7eb2e8f9f7 719 }
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /******************************** BTB maintenance operations ************************************************/
<> 144:ef7eb2e8f9f7 722 /** \brief Invalidate entire branch predictor array
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 BPIALL. Branch Predictor Invalidate All.
<> 144:ef7eb2e8f9f7 725 */
<> 144:ef7eb2e8f9f7 726 // from system_Renesas_RZ_A1.c
<> 144:ef7eb2e8f9f7 727 __STATIC_INLINE void __v7_inv_btac(void) {
<> 144:ef7eb2e8f9f7 728 uint32_t val = 0;
<> 144:ef7eb2e8f9f7 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
<> 144:ef7eb2e8f9f7 730 __DSB(); //ensure completion of the invalidation
<> 144:ef7eb2e8f9f7 731 __ISB(); //ensure instruction fetch path sees new state
<> 144:ef7eb2e8f9f7 732 }
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734
<> 144:ef7eb2e8f9f7 735 /******************************** L1 cache operations ******************************************************/
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /** \brief Invalidate the whole I$
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 ICIALLU. Instruction Cache Invalidate All to PoU
<> 144:ef7eb2e8f9f7 740 */
<> 144:ef7eb2e8f9f7 741 // from system_Renesas_RZ_A1.c
<> 144:ef7eb2e8f9f7 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
<> 144:ef7eb2e8f9f7 743 uint32_t val = 0;
<> 144:ef7eb2e8f9f7 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
<> 144:ef7eb2e8f9f7 745 __DSB(); //ensure completion of the invalidation
<> 144:ef7eb2e8f9f7 746 __ISB(); //ensure instruction fetch path sees new I cache state
<> 144:ef7eb2e8f9f7 747 }
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 // from __v7_inv_dcache_all()
<> 144:ef7eb2e8f9f7 750 __arm static inline void __v7_all_cache(uint32_t op) {
<> 144:ef7eb2e8f9f7 751 __asm(
<> 144:ef7eb2e8f9f7 752 " ARM \n"
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 " PUSH {R4-R11} \n"
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
<> 144:ef7eb2e8f9f7 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
<> 144:ef7eb2e8f9f7 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
<> 144:ef7eb2e8f9f7 759 " BEQ Finished\n" // If 0, no need to clean
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 " MOV R10, #0\n" // R10 holds current cache level << 1
<> 144:ef7eb2e8f9f7 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
<> 144:ef7eb2e8f9f7 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
<> 144:ef7eb2e8f9f7 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
<> 144:ef7eb2e8f9f7 765 " CMP R1, #2 \n"
<> 144:ef7eb2e8f9f7 766 " BLT Skip \n" // No cache or only instruction cache at this level
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
<> 144:ef7eb2e8f9f7 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
<> 144:ef7eb2e8f9f7 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
<> 144:ef7eb2e8f9f7 771 " AND R2, R1, #7 \n" // Extract the line length field
<> 144:ef7eb2e8f9f7 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
<> 144:ef7eb2e8f9f7 773 " movw R4, #0x3FF \n"
<> 144:ef7eb2e8f9f7 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
<> 144:ef7eb2e8f9f7 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
<> 144:ef7eb2e8f9f7 776 " movw R7, #0x7FFF \n"
<> 144:ef7eb2e8f9f7 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
<> 144:ef7eb2e8f9f7 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
<> 144:ef7eb2e8f9f7 783 " CMP R0, #0 \n"
<> 144:ef7eb2e8f9f7 784 " BNE Dccsw \n"
<> 144:ef7eb2e8f9f7 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
<> 144:ef7eb2e8f9f7 786 " B cont \n"
<> 144:ef7eb2e8f9f7 787 "Dccsw: CMP R0, #1 \n"
<> 144:ef7eb2e8f9f7 788 " BNE Dccisw \n"
<> 144:ef7eb2e8f9f7 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
<> 144:ef7eb2e8f9f7 790 " B cont \n"
<> 144:ef7eb2e8f9f7 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
<> 144:ef7eb2e8f9f7 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
<> 144:ef7eb2e8f9f7 793 " BGE Loop3 \n"
<> 144:ef7eb2e8f9f7 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
<> 144:ef7eb2e8f9f7 795 " BGE Loop2 \n"
<> 144:ef7eb2e8f9f7 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
<> 144:ef7eb2e8f9f7 797 " CMP R3, R10 \n"
<> 144:ef7eb2e8f9f7 798 " BGT Loop1 \n"
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 "Finished: \n"
<> 144:ef7eb2e8f9f7 801 " DSB \n"
<> 144:ef7eb2e8f9f7 802 " POP {R4-R11} \n"
<> 144:ef7eb2e8f9f7 803 " BX lr \n" );
<> 144:ef7eb2e8f9f7 804 }
<> 144:ef7eb2e8f9f7 805
<> 144:ef7eb2e8f9f7 806 /** \brief Invalidate the whole D$
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 DCISW. Invalidate by Set/Way
<> 144:ef7eb2e8f9f7 809 */
<> 144:ef7eb2e8f9f7 810 // from system_Renesas_RZ_A1.c
<> 144:ef7eb2e8f9f7 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
<> 144:ef7eb2e8f9f7 812 __v7_all_cache(0);
<> 144:ef7eb2e8f9f7 813 }
<> 144:ef7eb2e8f9f7 814 /** \brief Clean and Invalidate D$ by MVA
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
<> 144:ef7eb2e8f9f7 817 */
<> 144:ef7eb2e8f9f7 818 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
<> 144:ef7eb2e8f9f7 819 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
<> 144:ef7eb2e8f9f7 820 __DMB();
<> 144:ef7eb2e8f9f7 821 }
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 #include "core_ca_mmu.h"
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
<> 144:ef7eb2e8f9f7 826 /* GNU gcc specific functions */
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 #define MODE_USR 0x10
<> 144:ef7eb2e8f9f7 829 #define MODE_FIQ 0x11
<> 144:ef7eb2e8f9f7 830 #define MODE_IRQ 0x12
<> 144:ef7eb2e8f9f7 831 #define MODE_SVC 0x13
<> 144:ef7eb2e8f9f7 832 #define MODE_MON 0x16
<> 144:ef7eb2e8f9f7 833 #define MODE_ABT 0x17
<> 144:ef7eb2e8f9f7 834 #define MODE_HYP 0x1A
<> 144:ef7eb2e8f9f7 835 #define MODE_UND 0x1B
<> 144:ef7eb2e8f9f7 836 #define MODE_SYS 0x1F
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
<> 144:ef7eb2e8f9f7 840 {
<> 144:ef7eb2e8f9f7 841 __ASM volatile ("cpsie i");
<> 144:ef7eb2e8f9f7 842 }
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 /** \brief Disable IRQ Interrupts
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 This function disables IRQ interrupts by setting the I-bit in the CPSR.
<> 144:ef7eb2e8f9f7 847 Can only be executed in Privileged modes.
<> 144:ef7eb2e8f9f7 848 */
<> 144:ef7eb2e8f9f7 849 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
<> 144:ef7eb2e8f9f7 850 {
<> 144:ef7eb2e8f9f7 851 uint32_t result;
<> 144:ef7eb2e8f9f7 852
<> 144:ef7eb2e8f9f7 853 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
<> 144:ef7eb2e8f9f7 854 __ASM volatile ("cpsid i");
<> 144:ef7eb2e8f9f7 855 return(result & 0x80);
<> 144:ef7eb2e8f9f7 856 }
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858
<> 144:ef7eb2e8f9f7 859 /** \brief Get APSR Register
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 This function returns the content of the APSR Register.
<> 144:ef7eb2e8f9f7 862
<> 144:ef7eb2e8f9f7 863 \return APSR Register value
<> 144:ef7eb2e8f9f7 864 */
<> 144:ef7eb2e8f9f7 865 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
<> 144:ef7eb2e8f9f7 866 {
<> 144:ef7eb2e8f9f7 867 #if 1
<> 144:ef7eb2e8f9f7 868 register uint32_t __regAPSR;
<> 144:ef7eb2e8f9f7 869 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
<> 144:ef7eb2e8f9f7 870 #else
<> 144:ef7eb2e8f9f7 871 register uint32_t __regAPSR __ASM("apsr");
<> 144:ef7eb2e8f9f7 872 #endif
<> 144:ef7eb2e8f9f7 873 return(__regAPSR);
<> 144:ef7eb2e8f9f7 874 }
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 /** \brief Get CPSR Register
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 This function returns the content of the CPSR Register.
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 \return CPSR Register value
<> 144:ef7eb2e8f9f7 882 */
<> 144:ef7eb2e8f9f7 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
<> 144:ef7eb2e8f9f7 884 {
<> 144:ef7eb2e8f9f7 885 #if 1
<> 144:ef7eb2e8f9f7 886 register uint32_t __regCPSR;
<> 144:ef7eb2e8f9f7 887 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
<> 144:ef7eb2e8f9f7 888 #else
<> 144:ef7eb2e8f9f7 889 register uint32_t __regCPSR __ASM("cpsr");
<> 144:ef7eb2e8f9f7 890 #endif
<> 144:ef7eb2e8f9f7 891 return(__regCPSR);
<> 144:ef7eb2e8f9f7 892 }
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 #if 0
<> 144:ef7eb2e8f9f7 895 /** \brief Set Stack Pointer
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 This function assigns the given value to the current stack pointer.
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 \param [in] topOfStack Stack Pointer value to set
<> 144:ef7eb2e8f9f7 900 */
<> 144:ef7eb2e8f9f7 901 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
<> 144:ef7eb2e8f9f7 902 {
<> 144:ef7eb2e8f9f7 903 register uint32_t __regSP __ASM("sp");
<> 144:ef7eb2e8f9f7 904 __regSP = topOfStack;
<> 144:ef7eb2e8f9f7 905 }
<> 144:ef7eb2e8f9f7 906 #endif
<> 144:ef7eb2e8f9f7 907
<> 144:ef7eb2e8f9f7 908 /** \brief Get link register
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 This function returns the value of the link register
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 \return Value of link register
<> 144:ef7eb2e8f9f7 913 */
<> 144:ef7eb2e8f9f7 914 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
<> 144:ef7eb2e8f9f7 915 {
<> 144:ef7eb2e8f9f7 916 register uint32_t __reglr __ASM("lr");
<> 144:ef7eb2e8f9f7 917 return(__reglr);
<> 144:ef7eb2e8f9f7 918 }
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 #if 0
<> 144:ef7eb2e8f9f7 921 /** \brief Set link register
<> 144:ef7eb2e8f9f7 922
<> 144:ef7eb2e8f9f7 923 This function sets the value of the link register
<> 144:ef7eb2e8f9f7 924
<> 144:ef7eb2e8f9f7 925 \param [in] lr LR value to set
<> 144:ef7eb2e8f9f7 926 */
<> 144:ef7eb2e8f9f7 927 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
<> 144:ef7eb2e8f9f7 928 {
<> 144:ef7eb2e8f9f7 929 register uint32_t __reglr __ASM("lr");
<> 144:ef7eb2e8f9f7 930 __reglr = lr;
<> 144:ef7eb2e8f9f7 931 }
<> 144:ef7eb2e8f9f7 932 #endif
<> 144:ef7eb2e8f9f7 933
<> 144:ef7eb2e8f9f7 934 /** \brief Set Process Stack Pointer
<> 144:ef7eb2e8f9f7 935
<> 144:ef7eb2e8f9f7 936 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
<> 144:ef7eb2e8f9f7 937
<> 144:ef7eb2e8f9f7 938 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
<> 144:ef7eb2e8f9f7 939 */
<> 144:ef7eb2e8f9f7 940 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
<> 144:ef7eb2e8f9f7 941 {
<> 144:ef7eb2e8f9f7 942 __asm__ volatile (
<> 144:ef7eb2e8f9f7 943 ".ARM;"
<> 144:ef7eb2e8f9f7 944 ".eabi_attribute Tag_ABI_align8_preserved,1;"
<> 144:ef7eb2e8f9f7 945
<> 144:ef7eb2e8f9f7 946 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
<> 144:ef7eb2e8f9f7 947 "MRS R1, CPSR;"
<> 144:ef7eb2e8f9f7 948 "CPS %0;" /* ;no effect in USR mode */
<> 144:ef7eb2e8f9f7 949 "MOV SP, R0;"
<> 144:ef7eb2e8f9f7 950 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
<> 144:ef7eb2e8f9f7 951 "ISB;"
<> 144:ef7eb2e8f9f7 952 //"BX LR;"
<> 144:ef7eb2e8f9f7 953 :
<> 144:ef7eb2e8f9f7 954 : "i"(MODE_SYS)
<> 144:ef7eb2e8f9f7 955 : "r0", "r1");
<> 144:ef7eb2e8f9f7 956 return;
<> 144:ef7eb2e8f9f7 957 }
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /** \brief Set User Mode
<> 144:ef7eb2e8f9f7 960
<> 144:ef7eb2e8f9f7 961 This function changes the processor state to User Mode
<> 144:ef7eb2e8f9f7 962 */
<> 144:ef7eb2e8f9f7 963 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
<> 144:ef7eb2e8f9f7 964 {
<> 144:ef7eb2e8f9f7 965 __asm__ volatile (
<> 144:ef7eb2e8f9f7 966 ".ARM;"
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968 "CPS %0;"
<> 144:ef7eb2e8f9f7 969 //"BX LR;"
<> 144:ef7eb2e8f9f7 970 :
<> 144:ef7eb2e8f9f7 971 : "i"(MODE_USR)
<> 144:ef7eb2e8f9f7 972 : );
<> 144:ef7eb2e8f9f7 973 return;
<> 144:ef7eb2e8f9f7 974 }
<> 144:ef7eb2e8f9f7 975
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 /** \brief Enable FIQ
<> 144:ef7eb2e8f9f7 978
<> 144:ef7eb2e8f9f7 979 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
<> 144:ef7eb2e8f9f7 980 Can only be executed in Privileged modes.
<> 144:ef7eb2e8f9f7 981 */
<> 144:ef7eb2e8f9f7 982 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
<> 144:ef7eb2e8f9f7 983
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 /** \brief Disable FIQ
<> 144:ef7eb2e8f9f7 986
<> 144:ef7eb2e8f9f7 987 This function disables FIQ interrupts by setting the F-bit in the CPSR.
<> 144:ef7eb2e8f9f7 988 Can only be executed in Privileged modes.
<> 144:ef7eb2e8f9f7 989 */
<> 144:ef7eb2e8f9f7 990 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
<> 144:ef7eb2e8f9f7 991
<> 144:ef7eb2e8f9f7 992
<> 144:ef7eb2e8f9f7 993 /** \brief Get FPSCR
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995 This function returns the current value of the Floating Point Status/Control register.
<> 144:ef7eb2e8f9f7 996
<> 144:ef7eb2e8f9f7 997 \return Floating Point Status/Control register value
<> 144:ef7eb2e8f9f7 998 */
<> 144:ef7eb2e8f9f7 999 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
<> 144:ef7eb2e8f9f7 1000 {
<> 144:ef7eb2e8f9f7 1001 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 144:ef7eb2e8f9f7 1002 #if 1
<> 144:ef7eb2e8f9f7 1003 uint32_t result;
<> 144:ef7eb2e8f9f7 1004
<> 144:ef7eb2e8f9f7 1005 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
<> 144:ef7eb2e8f9f7 1006 return (result);
<> 144:ef7eb2e8f9f7 1007 #else
<> 144:ef7eb2e8f9f7 1008 register uint32_t __regfpscr __ASM("fpscr");
<> 144:ef7eb2e8f9f7 1009 return(__regfpscr);
<> 144:ef7eb2e8f9f7 1010 #endif
<> 144:ef7eb2e8f9f7 1011 #else
<> 144:ef7eb2e8f9f7 1012 return(0);
<> 144:ef7eb2e8f9f7 1013 #endif
<> 144:ef7eb2e8f9f7 1014 }
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016
<> 144:ef7eb2e8f9f7 1017 /** \brief Set FPSCR
<> 144:ef7eb2e8f9f7 1018
<> 144:ef7eb2e8f9f7 1019 This function assigns the given value to the Floating Point Status/Control register.
<> 144:ef7eb2e8f9f7 1020
<> 144:ef7eb2e8f9f7 1021 \param [in] fpscr Floating Point Status/Control value to set
<> 144:ef7eb2e8f9f7 1022 */
<> 144:ef7eb2e8f9f7 1023 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
<> 144:ef7eb2e8f9f7 1024 {
<> 144:ef7eb2e8f9f7 1025 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 144:ef7eb2e8f9f7 1026 #if 1
<> 144:ef7eb2e8f9f7 1027 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
<> 144:ef7eb2e8f9f7 1028 #else
<> 144:ef7eb2e8f9f7 1029 register uint32_t __regfpscr __ASM("fpscr");
<> 144:ef7eb2e8f9f7 1030 __regfpscr = (fpscr);
<> 144:ef7eb2e8f9f7 1031 #endif
<> 144:ef7eb2e8f9f7 1032 #endif
<> 144:ef7eb2e8f9f7 1033 }
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 /** \brief Get FPEXC
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 This function returns the current value of the Floating Point Exception Control register.
<> 144:ef7eb2e8f9f7 1038
<> 144:ef7eb2e8f9f7 1039 \return Floating Point Exception Control register value
<> 144:ef7eb2e8f9f7 1040 */
<> 144:ef7eb2e8f9f7 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
<> 144:ef7eb2e8f9f7 1042 {
<> 144:ef7eb2e8f9f7 1043 #if (__FPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 1044 #if 1
<> 144:ef7eb2e8f9f7 1045 uint32_t result;
<> 144:ef7eb2e8f9f7 1046
<> 144:ef7eb2e8f9f7 1047 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
<> 144:ef7eb2e8f9f7 1048 return (result);
<> 144:ef7eb2e8f9f7 1049 #else
<> 144:ef7eb2e8f9f7 1050 register uint32_t __regfpexc __ASM("fpexc");
<> 144:ef7eb2e8f9f7 1051 return(__regfpexc);
<> 144:ef7eb2e8f9f7 1052 #endif
<> 144:ef7eb2e8f9f7 1053 #else
<> 144:ef7eb2e8f9f7 1054 return(0);
<> 144:ef7eb2e8f9f7 1055 #endif
<> 144:ef7eb2e8f9f7 1056 }
<> 144:ef7eb2e8f9f7 1057
<> 144:ef7eb2e8f9f7 1058
<> 144:ef7eb2e8f9f7 1059 /** \brief Set FPEXC
<> 144:ef7eb2e8f9f7 1060
<> 144:ef7eb2e8f9f7 1061 This function assigns the given value to the Floating Point Exception Control register.
<> 144:ef7eb2e8f9f7 1062
<> 144:ef7eb2e8f9f7 1063 \param [in] fpscr Floating Point Exception Control value to set
<> 144:ef7eb2e8f9f7 1064 */
<> 144:ef7eb2e8f9f7 1065 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
<> 144:ef7eb2e8f9f7 1066 {
<> 144:ef7eb2e8f9f7 1067 #if (__FPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 1068 #if 1
<> 144:ef7eb2e8f9f7 1069 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
<> 144:ef7eb2e8f9f7 1070 #else
<> 144:ef7eb2e8f9f7 1071 register uint32_t __regfpexc __ASM("fpexc");
<> 144:ef7eb2e8f9f7 1072 __regfpexc = (fpexc);
<> 144:ef7eb2e8f9f7 1073 #endif
<> 144:ef7eb2e8f9f7 1074 #endif
<> 144:ef7eb2e8f9f7 1075 }
<> 144:ef7eb2e8f9f7 1076
<> 144:ef7eb2e8f9f7 1077 /** \brief Get CPACR
<> 144:ef7eb2e8f9f7 1078
<> 144:ef7eb2e8f9f7 1079 This function returns the current value of the Coprocessor Access Control register.
<> 144:ef7eb2e8f9f7 1080
<> 144:ef7eb2e8f9f7 1081 \return Coprocessor Access Control register value
<> 144:ef7eb2e8f9f7 1082 */
<> 144:ef7eb2e8f9f7 1083 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
<> 144:ef7eb2e8f9f7 1084 {
<> 144:ef7eb2e8f9f7 1085 #if 1
<> 144:ef7eb2e8f9f7 1086 register uint32_t __regCPACR;
<> 144:ef7eb2e8f9f7 1087 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
<> 144:ef7eb2e8f9f7 1088 #else
<> 144:ef7eb2e8f9f7 1089 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
<> 144:ef7eb2e8f9f7 1090 #endif
<> 144:ef7eb2e8f9f7 1091 return __regCPACR;
<> 144:ef7eb2e8f9f7 1092 }
<> 144:ef7eb2e8f9f7 1093
<> 144:ef7eb2e8f9f7 1094 /** \brief Set CPACR
<> 144:ef7eb2e8f9f7 1095
<> 144:ef7eb2e8f9f7 1096 This function assigns the given value to the Coprocessor Access Control register.
<> 144:ef7eb2e8f9f7 1097
<> 144:ef7eb2e8f9f7 1098 \param [in] cpacr Coprocessor Acccess Control value to set
<> 144:ef7eb2e8f9f7 1099 */
<> 144:ef7eb2e8f9f7 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
<> 144:ef7eb2e8f9f7 1101 {
<> 144:ef7eb2e8f9f7 1102 #if 1
<> 144:ef7eb2e8f9f7 1103 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
<> 144:ef7eb2e8f9f7 1104 #else
<> 144:ef7eb2e8f9f7 1105 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
<> 144:ef7eb2e8f9f7 1106 __regCPACR = cpacr;
<> 144:ef7eb2e8f9f7 1107 #endif
<> 144:ef7eb2e8f9f7 1108 __ISB();
<> 144:ef7eb2e8f9f7 1109 }
<> 144:ef7eb2e8f9f7 1110
<> 144:ef7eb2e8f9f7 1111 /** \brief Get CBAR
<> 144:ef7eb2e8f9f7 1112
<> 144:ef7eb2e8f9f7 1113 This function returns the value of the Configuration Base Address register.
<> 144:ef7eb2e8f9f7 1114
<> 144:ef7eb2e8f9f7 1115 \return Configuration Base Address register value
<> 144:ef7eb2e8f9f7 1116 */
<> 144:ef7eb2e8f9f7 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
<> 144:ef7eb2e8f9f7 1118 #if 1
<> 144:ef7eb2e8f9f7 1119 register uint32_t __regCBAR;
<> 144:ef7eb2e8f9f7 1120 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
<> 144:ef7eb2e8f9f7 1121 #else
<> 144:ef7eb2e8f9f7 1122 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
<> 144:ef7eb2e8f9f7 1123 #endif
<> 144:ef7eb2e8f9f7 1124 return(__regCBAR);
<> 144:ef7eb2e8f9f7 1125 }
<> 144:ef7eb2e8f9f7 1126
<> 144:ef7eb2e8f9f7 1127 /** \brief Get TTBR0
<> 144:ef7eb2e8f9f7 1128
<> 144:ef7eb2e8f9f7 1129 This function returns the value of the Translation Table Base Register 0.
<> 144:ef7eb2e8f9f7 1130
<> 144:ef7eb2e8f9f7 1131 \return Translation Table Base Register 0 value
<> 144:ef7eb2e8f9f7 1132 */
<> 144:ef7eb2e8f9f7 1133 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
<> 144:ef7eb2e8f9f7 1134 #if 1
<> 144:ef7eb2e8f9f7 1135 register uint32_t __regTTBR0;
<> 144:ef7eb2e8f9f7 1136 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
<> 144:ef7eb2e8f9f7 1137 #else
<> 144:ef7eb2e8f9f7 1138 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
<> 144:ef7eb2e8f9f7 1139 #endif
<> 144:ef7eb2e8f9f7 1140 return(__regTTBR0);
<> 144:ef7eb2e8f9f7 1141 }
<> 144:ef7eb2e8f9f7 1142
<> 144:ef7eb2e8f9f7 1143 /** \brief Set TTBR0
<> 144:ef7eb2e8f9f7 1144
<> 144:ef7eb2e8f9f7 1145 This function assigns the given value to the Translation Table Base Register 0.
<> 144:ef7eb2e8f9f7 1146
<> 144:ef7eb2e8f9f7 1147 \param [in] ttbr0 Translation Table Base Register 0 value to set
<> 144:ef7eb2e8f9f7 1148 */
<> 144:ef7eb2e8f9f7 1149 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
<> 144:ef7eb2e8f9f7 1150 #if 1
<> 144:ef7eb2e8f9f7 1151 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
<> 144:ef7eb2e8f9f7 1152 #else
<> 144:ef7eb2e8f9f7 1153 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
<> 144:ef7eb2e8f9f7 1154 __regTTBR0 = ttbr0;
<> 144:ef7eb2e8f9f7 1155 #endif
<> 144:ef7eb2e8f9f7 1156 __ISB();
<> 144:ef7eb2e8f9f7 1157 }
<> 144:ef7eb2e8f9f7 1158
<> 144:ef7eb2e8f9f7 1159 /** \brief Get DACR
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 This function returns the value of the Domain Access Control Register.
<> 144:ef7eb2e8f9f7 1162
<> 144:ef7eb2e8f9f7 1163 \return Domain Access Control Register value
<> 144:ef7eb2e8f9f7 1164 */
<> 144:ef7eb2e8f9f7 1165 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
<> 144:ef7eb2e8f9f7 1166 #if 1
<> 144:ef7eb2e8f9f7 1167 register uint32_t __regDACR;
<> 144:ef7eb2e8f9f7 1168 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
<> 144:ef7eb2e8f9f7 1169 #else
<> 144:ef7eb2e8f9f7 1170 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
<> 144:ef7eb2e8f9f7 1171 #endif
<> 144:ef7eb2e8f9f7 1172 return(__regDACR);
<> 144:ef7eb2e8f9f7 1173 }
<> 144:ef7eb2e8f9f7 1174
<> 144:ef7eb2e8f9f7 1175 /** \brief Set DACR
<> 144:ef7eb2e8f9f7 1176
<> 144:ef7eb2e8f9f7 1177 This function assigns the given value to the Domain Access Control Register.
<> 144:ef7eb2e8f9f7 1178
<> 144:ef7eb2e8f9f7 1179 \param [in] dacr Domain Access Control Register value to set
<> 144:ef7eb2e8f9f7 1180 */
<> 144:ef7eb2e8f9f7 1181 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
<> 144:ef7eb2e8f9f7 1182 #if 1
<> 144:ef7eb2e8f9f7 1183 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
<> 144:ef7eb2e8f9f7 1184 #else
<> 144:ef7eb2e8f9f7 1185 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
<> 144:ef7eb2e8f9f7 1186 __regDACR = dacr;
<> 144:ef7eb2e8f9f7 1187 #endif
<> 144:ef7eb2e8f9f7 1188 __ISB();
<> 144:ef7eb2e8f9f7 1189 }
<> 144:ef7eb2e8f9f7 1190
<> 144:ef7eb2e8f9f7 1191 /******************************** Cache and BTAC enable ****************************************************/
<> 144:ef7eb2e8f9f7 1192
<> 144:ef7eb2e8f9f7 1193 /** \brief Set SCTLR
<> 144:ef7eb2e8f9f7 1194
<> 144:ef7eb2e8f9f7 1195 This function assigns the given value to the System Control Register.
<> 144:ef7eb2e8f9f7 1196
<> 144:ef7eb2e8f9f7 1197 \param [in] sctlr System Control Register value to set
<> 144:ef7eb2e8f9f7 1198 */
<> 144:ef7eb2e8f9f7 1199 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
<> 144:ef7eb2e8f9f7 1200 {
<> 144:ef7eb2e8f9f7 1201 #if 1
<> 144:ef7eb2e8f9f7 1202 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
<> 144:ef7eb2e8f9f7 1203 #else
<> 144:ef7eb2e8f9f7 1204 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
<> 144:ef7eb2e8f9f7 1205 __regSCTLR = sctlr;
<> 144:ef7eb2e8f9f7 1206 #endif
<> 144:ef7eb2e8f9f7 1207 }
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 /** \brief Get SCTLR
<> 144:ef7eb2e8f9f7 1210
<> 144:ef7eb2e8f9f7 1211 This function returns the value of the System Control Register.
<> 144:ef7eb2e8f9f7 1212
<> 144:ef7eb2e8f9f7 1213 \return System Control Register value
<> 144:ef7eb2e8f9f7 1214 */
<> 144:ef7eb2e8f9f7 1215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
<> 144:ef7eb2e8f9f7 1216 #if 1
<> 144:ef7eb2e8f9f7 1217 register uint32_t __regSCTLR;
<> 144:ef7eb2e8f9f7 1218 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
<> 144:ef7eb2e8f9f7 1219 #else
<> 144:ef7eb2e8f9f7 1220 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
<> 144:ef7eb2e8f9f7 1221 #endif
<> 144:ef7eb2e8f9f7 1222 return(__regSCTLR);
<> 144:ef7eb2e8f9f7 1223 }
<> 144:ef7eb2e8f9f7 1224
<> 144:ef7eb2e8f9f7 1225 /** \brief Enable Caches
<> 144:ef7eb2e8f9f7 1226
<> 144:ef7eb2e8f9f7 1227 Enable Caches
<> 144:ef7eb2e8f9f7 1228 */
<> 144:ef7eb2e8f9f7 1229 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
<> 144:ef7eb2e8f9f7 1230 // Set I bit 12 to enable I Cache
<> 144:ef7eb2e8f9f7 1231 // Set C bit 2 to enable D Cache
<> 144:ef7eb2e8f9f7 1232 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
<> 144:ef7eb2e8f9f7 1233 }
<> 144:ef7eb2e8f9f7 1234
<> 144:ef7eb2e8f9f7 1235 /** \brief Disable Caches
<> 144:ef7eb2e8f9f7 1236
<> 144:ef7eb2e8f9f7 1237 Disable Caches
<> 144:ef7eb2e8f9f7 1238 */
<> 144:ef7eb2e8f9f7 1239 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
<> 144:ef7eb2e8f9f7 1240 // Clear I bit 12 to disable I Cache
<> 144:ef7eb2e8f9f7 1241 // Clear C bit 2 to disable D Cache
<> 144:ef7eb2e8f9f7 1242 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
<> 144:ef7eb2e8f9f7 1243 __ISB();
<> 144:ef7eb2e8f9f7 1244 }
<> 144:ef7eb2e8f9f7 1245
<> 144:ef7eb2e8f9f7 1246 /** \brief Enable BTAC
<> 144:ef7eb2e8f9f7 1247
<> 144:ef7eb2e8f9f7 1248 Enable BTAC
<> 144:ef7eb2e8f9f7 1249 */
<> 144:ef7eb2e8f9f7 1250 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
<> 144:ef7eb2e8f9f7 1251 // Set Z bit 11 to enable branch prediction
<> 144:ef7eb2e8f9f7 1252 __set_SCTLR( __get_SCTLR() | (1 << 11));
<> 144:ef7eb2e8f9f7 1253 __ISB();
<> 144:ef7eb2e8f9f7 1254 }
<> 144:ef7eb2e8f9f7 1255
<> 144:ef7eb2e8f9f7 1256 /** \brief Disable BTAC
<> 144:ef7eb2e8f9f7 1257
<> 144:ef7eb2e8f9f7 1258 Disable BTAC
<> 144:ef7eb2e8f9f7 1259 */
<> 144:ef7eb2e8f9f7 1260 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
<> 144:ef7eb2e8f9f7 1261 // Clear Z bit 11 to disable branch prediction
<> 144:ef7eb2e8f9f7 1262 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
<> 144:ef7eb2e8f9f7 1263 }
<> 144:ef7eb2e8f9f7 1264
<> 144:ef7eb2e8f9f7 1265
<> 144:ef7eb2e8f9f7 1266 /** \brief Enable MMU
<> 144:ef7eb2e8f9f7 1267
<> 144:ef7eb2e8f9f7 1268 Enable MMU
<> 144:ef7eb2e8f9f7 1269 */
<> 144:ef7eb2e8f9f7 1270 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
<> 144:ef7eb2e8f9f7 1271 // Set M bit 0 to enable the MMU
<> 144:ef7eb2e8f9f7 1272 // Set AFE bit to enable simplified access permissions model
<> 144:ef7eb2e8f9f7 1273 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
<> 144:ef7eb2e8f9f7 1274 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
<> 144:ef7eb2e8f9f7 1275 __ISB();
<> 144:ef7eb2e8f9f7 1276 }
<> 144:ef7eb2e8f9f7 1277
<> 144:ef7eb2e8f9f7 1278 /** \brief Disable MMU
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280 Disable MMU
<> 144:ef7eb2e8f9f7 1281 */
<> 144:ef7eb2e8f9f7 1282 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
<> 144:ef7eb2e8f9f7 1283 // Clear M bit 0 to disable the MMU
<> 144:ef7eb2e8f9f7 1284 __set_SCTLR( __get_SCTLR() & ~1);
<> 144:ef7eb2e8f9f7 1285 __ISB();
<> 144:ef7eb2e8f9f7 1286 }
<> 144:ef7eb2e8f9f7 1287
<> 144:ef7eb2e8f9f7 1288 /******************************** TLB maintenance operations ************************************************/
<> 144:ef7eb2e8f9f7 1289 /** \brief Invalidate the whole tlb
<> 144:ef7eb2e8f9f7 1290
<> 144:ef7eb2e8f9f7 1291 TLBIALL. Invalidate the whole tlb
<> 144:ef7eb2e8f9f7 1292 */
<> 144:ef7eb2e8f9f7 1293
<> 144:ef7eb2e8f9f7 1294 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
<> 144:ef7eb2e8f9f7 1295 #if 1
<> 144:ef7eb2e8f9f7 1296 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
<> 144:ef7eb2e8f9f7 1297 #else
<> 144:ef7eb2e8f9f7 1298 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
<> 144:ef7eb2e8f9f7 1299 __TLBIALL = 0;
<> 144:ef7eb2e8f9f7 1300 #endif
<> 144:ef7eb2e8f9f7 1301 __DSB();
<> 144:ef7eb2e8f9f7 1302 __ISB();
<> 144:ef7eb2e8f9f7 1303 }
<> 144:ef7eb2e8f9f7 1304
<> 144:ef7eb2e8f9f7 1305 /******************************** BTB maintenance operations ************************************************/
<> 144:ef7eb2e8f9f7 1306 /** \brief Invalidate entire branch predictor array
<> 144:ef7eb2e8f9f7 1307
<> 144:ef7eb2e8f9f7 1308 BPIALL. Branch Predictor Invalidate All.
<> 144:ef7eb2e8f9f7 1309 */
<> 144:ef7eb2e8f9f7 1310
<> 144:ef7eb2e8f9f7 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
<> 144:ef7eb2e8f9f7 1312 #if 1
<> 144:ef7eb2e8f9f7 1313 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
<> 144:ef7eb2e8f9f7 1314 #else
<> 144:ef7eb2e8f9f7 1315 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
<> 144:ef7eb2e8f9f7 1316 __BPIALL = 0;
<> 144:ef7eb2e8f9f7 1317 #endif
<> 144:ef7eb2e8f9f7 1318 __DSB(); //ensure completion of the invalidation
<> 144:ef7eb2e8f9f7 1319 __ISB(); //ensure instruction fetch path sees new state
<> 144:ef7eb2e8f9f7 1320 }
<> 144:ef7eb2e8f9f7 1321
<> 144:ef7eb2e8f9f7 1322
<> 144:ef7eb2e8f9f7 1323 /******************************** L1 cache operations ******************************************************/
<> 144:ef7eb2e8f9f7 1324
<> 144:ef7eb2e8f9f7 1325 /** \brief Invalidate the whole I$
<> 144:ef7eb2e8f9f7 1326
<> 144:ef7eb2e8f9f7 1327 ICIALLU. Instruction Cache Invalidate All to PoU
<> 144:ef7eb2e8f9f7 1328 */
<> 144:ef7eb2e8f9f7 1329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
<> 144:ef7eb2e8f9f7 1330 #if 1
<> 144:ef7eb2e8f9f7 1331 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
<> 144:ef7eb2e8f9f7 1332 #else
<> 144:ef7eb2e8f9f7 1333 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
<> 144:ef7eb2e8f9f7 1334 __ICIALLU = 0;
<> 144:ef7eb2e8f9f7 1335 #endif
<> 144:ef7eb2e8f9f7 1336 __DSB(); //ensure completion of the invalidation
<> 144:ef7eb2e8f9f7 1337 __ISB(); //ensure instruction fetch path sees new I cache state
<> 144:ef7eb2e8f9f7 1338 }
<> 144:ef7eb2e8f9f7 1339
<> 144:ef7eb2e8f9f7 1340 /** \brief Clean D$ by MVA
<> 144:ef7eb2e8f9f7 1341
<> 144:ef7eb2e8f9f7 1342 DCCMVAC. Data cache clean by MVA to PoC
<> 144:ef7eb2e8f9f7 1343 */
<> 144:ef7eb2e8f9f7 1344 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
<> 144:ef7eb2e8f9f7 1345 #if 1
<> 144:ef7eb2e8f9f7 1346 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
<> 144:ef7eb2e8f9f7 1347 #else
<> 144:ef7eb2e8f9f7 1348 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
<> 144:ef7eb2e8f9f7 1349 __DCCMVAC = (uint32_t)va;
<> 144:ef7eb2e8f9f7 1350 #endif
<> 144:ef7eb2e8f9f7 1351 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
<> 144:ef7eb2e8f9f7 1352 }
<> 144:ef7eb2e8f9f7 1353
<> 144:ef7eb2e8f9f7 1354 /** \brief Invalidate D$ by MVA
<> 144:ef7eb2e8f9f7 1355
<> 144:ef7eb2e8f9f7 1356 DCIMVAC. Data cache invalidate by MVA to PoC
<> 144:ef7eb2e8f9f7 1357 */
<> 144:ef7eb2e8f9f7 1358 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
<> 144:ef7eb2e8f9f7 1359 #if 1
<> 144:ef7eb2e8f9f7 1360 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
<> 144:ef7eb2e8f9f7 1361 #else
<> 144:ef7eb2e8f9f7 1362 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
<> 144:ef7eb2e8f9f7 1363 __DCIMVAC = (uint32_t)va;
<> 144:ef7eb2e8f9f7 1364 #endif
<> 144:ef7eb2e8f9f7 1365 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
<> 144:ef7eb2e8f9f7 1366 }
<> 144:ef7eb2e8f9f7 1367
<> 144:ef7eb2e8f9f7 1368 /** \brief Clean and Invalidate D$ by MVA
<> 144:ef7eb2e8f9f7 1369
<> 144:ef7eb2e8f9f7 1370 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
<> 144:ef7eb2e8f9f7 1371 */
<> 144:ef7eb2e8f9f7 1372 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
<> 144:ef7eb2e8f9f7 1373 #if 1
<> 144:ef7eb2e8f9f7 1374 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
<> 144:ef7eb2e8f9f7 1375 #else
<> 144:ef7eb2e8f9f7 1376 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
<> 144:ef7eb2e8f9f7 1377 __DCCIMVAC = (uint32_t)va;
<> 144:ef7eb2e8f9f7 1378 #endif
<> 144:ef7eb2e8f9f7 1379 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
<> 144:ef7eb2e8f9f7 1380 }
<> 144:ef7eb2e8f9f7 1381
<> 144:ef7eb2e8f9f7 1382 /** \brief Clean and Invalidate the entire data or unified cache
<> 144:ef7eb2e8f9f7 1383
<> 144:ef7eb2e8f9f7 1384 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
<> 144:ef7eb2e8f9f7 1385 */
<> 144:ef7eb2e8f9f7 1386 extern void __v7_all_cache(uint32_t op);
<> 144:ef7eb2e8f9f7 1387
<> 144:ef7eb2e8f9f7 1388
<> 144:ef7eb2e8f9f7 1389 /** \brief Invalidate the whole D$
<> 144:ef7eb2e8f9f7 1390
<> 144:ef7eb2e8f9f7 1391 DCISW. Invalidate by Set/Way
<> 144:ef7eb2e8f9f7 1392 */
<> 144:ef7eb2e8f9f7 1393
<> 144:ef7eb2e8f9f7 1394 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
<> 144:ef7eb2e8f9f7 1395 __v7_all_cache(0);
<> 144:ef7eb2e8f9f7 1396 }
<> 144:ef7eb2e8f9f7 1397
<> 144:ef7eb2e8f9f7 1398 /** \brief Clean the whole D$
<> 144:ef7eb2e8f9f7 1399
<> 144:ef7eb2e8f9f7 1400 DCCSW. Clean by Set/Way
<> 144:ef7eb2e8f9f7 1401 */
<> 144:ef7eb2e8f9f7 1402
<> 144:ef7eb2e8f9f7 1403 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
<> 144:ef7eb2e8f9f7 1404 __v7_all_cache(1);
<> 144:ef7eb2e8f9f7 1405 }
<> 144:ef7eb2e8f9f7 1406
<> 144:ef7eb2e8f9f7 1407 /** \brief Clean and invalidate the whole D$
<> 144:ef7eb2e8f9f7 1408
<> 144:ef7eb2e8f9f7 1409 DCCISW. Clean and Invalidate by Set/Way
<> 144:ef7eb2e8f9f7 1410 */
<> 144:ef7eb2e8f9f7 1411
<> 144:ef7eb2e8f9f7 1412 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
<> 144:ef7eb2e8f9f7 1413 __v7_all_cache(2);
<> 144:ef7eb2e8f9f7 1414 }
<> 144:ef7eb2e8f9f7 1415
<> 144:ef7eb2e8f9f7 1416 #include "core_ca_mmu.h"
<> 144:ef7eb2e8f9f7 1417
<> 144:ef7eb2e8f9f7 1418 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
<> 144:ef7eb2e8f9f7 1419
<> 144:ef7eb2e8f9f7 1420 #error TASKING Compiler support not implemented for Cortex-A
<> 144:ef7eb2e8f9f7 1421
<> 144:ef7eb2e8f9f7 1422 #endif
<> 144:ef7eb2e8f9f7 1423
<> 144:ef7eb2e8f9f7 1424 /*@} end of CMSIS_Core_RegAccFunctions */
<> 144:ef7eb2e8f9f7 1425
<> 144:ef7eb2e8f9f7 1426
<> 144:ef7eb2e8f9f7 1427 #endif /* __CORE_CAFUNC_H__ */