the do / gr-peach-opencv-project

Opencv 3.1 project on GR-PEACH board

Fork of gr-peach-opencv-project by the do

GR-PEACH_video/inc/lcd_analog_rgb_ch1.h@170:54ff26da7eb6, 2017-07-04 (annotated)

Committer:
thedo
Date:
Tue Jul 04 06:23:13 2017 +0000
Revision:
170:54ff26da7eb6
Parent:
166:3a9487d57a5c 
project opencv 3.1 on GR PEACH board, no use SD card.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
thedo 166:3a9487d57a5c 1 /*******************************************************************************
thedo 166:3a9487d57a5c 2 * DISCLAIMER
thedo 166:3a9487d57a5c 3 * This software is supplied by Renesas Electronics Corporation and is only
thedo 166:3a9487d57a5c 4 * intended for use with Renesas products. No other uses are authorized. This
thedo 166:3a9487d57a5c 5 * software is owned by Renesas Electronics Corporation and is protected under
thedo 166:3a9487d57a5c 6 * all applicable laws, including copyright laws.
thedo 166:3a9487d57a5c 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
thedo 166:3a9487d57a5c 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
thedo 166:3a9487d57a5c 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
thedo 166:3a9487d57a5c 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
thedo 166:3a9487d57a5c 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
thedo 166:3a9487d57a5c 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
thedo 166:3a9487d57a5c 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
thedo 166:3a9487d57a5c 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
thedo 166:3a9487d57a5c 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
thedo 166:3a9487d57a5c 16 * Renesas reserves the right, without notice, to make changes to this software
thedo 166:3a9487d57a5c 17 * and to discontinue the availability of this software. By using this software,
thedo 166:3a9487d57a5c 18 * you agree to the additional terms and conditions found by accessing the
thedo 166:3a9487d57a5c 19 * following link:
thedo 166:3a9487d57a5c 20 * http://www.renesas.com/disclaimer
thedo 166:3a9487d57a5c 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
thedo 166:3a9487d57a5c 22 *******************************************************************************/
thedo 166:3a9487d57a5c 23 /**************************************************************************//**
thedo 166:3a9487d57a5c 24 * @file lcd_analog_rgb_ch1.h
thedo 166:3a9487d57a5c 25 * @version 1.00
thedo 166:3a9487d57a5c 26 * $Rev: 199 $
thedo 166:3a9487d57a5c 27 * $Date:: 2014-05-23 16:33:52 +0900#$
thedo 166:3a9487d57a5c 28 * @brief LCD panel for vdc5 channel 1 definition header
thedo 166:3a9487d57a5c 29 ******************************************************************************/
thedo 166:3a9487d57a5c 30
thedo 166:3a9487d57a5c 31 #ifndef LCD_ANALOG_RGB_CH1_H
thedo 166:3a9487d57a5c 32 #define LCD_ANALOG_RGB_CH1_H
thedo 166:3a9487d57a5c 33
thedo 166:3a9487d57a5c 34 #ifndef LCD_PANEL_H
thedo 166:3a9487d57a5c 35 #error Do not include this file directly!
thedo 166:3a9487d57a5c 36 #else
thedo 166:3a9487d57a5c 37 /******************************************************************************
thedo 166:3a9487d57a5c 38 Includes <System Includes> , "Project Includes"
thedo 166:3a9487d57a5c 39 ******************************************************************************/
thedo 166:3a9487d57a5c 40 #include <stdlib.h>
thedo 166:3a9487d57a5c 41
thedo 166:3a9487d57a5c 42 #include "r_typedefs.h"
thedo 166:3a9487d57a5c 43
thedo 166:3a9487d57a5c 44 #include "r_vdc5.h"
thedo 166:3a9487d57a5c 45
thedo 166:3a9487d57a5c 46 #include "lcd_analog_rgb.h"
thedo 166:3a9487d57a5c 47
thedo 166:3a9487d57a5c 48
thedo 166:3a9487d57a5c 49 /******************************************************************************
thedo 166:3a9487d57a5c 50 Macro definitions
thedo 166:3a9487d57a5c 51 ******************************************************************************/
thedo 166:3a9487d57a5c 52 /* Option board (part number: RTK7721000B00000BR)
thedo 166:3a9487d57a5c 53 ADV7123 (Video DAC), U10
thedo 166:3a9487d57a5c 54 Analog RGB D-sub15 (RGB888), J16 */
thedo 166:3a9487d57a5c 55 #define LCD_CH1_S_HSYNC (0u) /* Hsync start position */
thedo 166:3a9487d57a5c 56 #define LCD_CH1_W_HSYNC (LCD_SVGA_H_SYNC_WIDTH) /* Hsync width */
thedo 166:3a9487d57a5c 57 #define LCD_CH1_POL_HSYNC (LCD_SVGA_H_POLARITY) /* Polarity of Hsync pulse */
thedo 166:3a9487d57a5c 58 /* LCD display area size, horizontal start position */
thedo 166:3a9487d57a5c 59 #define LCD_CH1_DISP_HS (LCD_SVGA_H_SYNC_WIDTH + LCD_SVGA_H_BACK_PORCH)
thedo 166:3a9487d57a5c 60 #define LCD_CH1_DISP_HW (LCD_SVGA_H_VISIBLE_AREA) /* LCD display area size, horizontal width */
thedo 166:3a9487d57a5c 61
thedo 166:3a9487d57a5c 62 /* Vsync start position */
thedo 166:3a9487d57a5c 63 #define LCD_CH1_S_VSYNC (LCD_SVGA_V_BACK_PORCH + LCD_SVGA_V_VISIBLE_AREA + LCD_SVGA_V_FRONT_PORCH)
thedo 166:3a9487d57a5c 64 #define LCD_CH1_W_VSYNC (LCD_SVGA_V_SYNC_WIDTH) /* Vsync width */
thedo 166:3a9487d57a5c 65 #define LCD_CH1_POL_VSYNC (LCD_SVGA_V_POLARITY) /* Polarity of Vsync pulse */
thedo 166:3a9487d57a5c 66 #define LCD_CH1_DISP_VS (LCD_SVGA_V_BACK_PORCH) /* LCD display area size, vertical start position */
thedo 166:3a9487d57a5c 67 #define LCD_CH1_DISP_VW (LCD_SVGA_V_VISIBLE_AREA) /* LCD display area size, height (vertical width) */
thedo 166:3a9487d57a5c 68
thedo 166:3a9487d57a5c 69 #define LCD_CH1_SIG_FV (LCD_SVGA_V_TOTAL - 1u) /* Free-running Vsync period */
thedo 166:3a9487d57a5c 70 #define LCD_CH1_SIG_FH (LCD_SVGA_H_TOTAL - 1u) /* Hsync period */
thedo 166:3a9487d57a5c 71 /* Pixel data is latched in the rising edge of pixel clock on ADV7123.
thedo 166:3a9487d57a5c 72 Therefore, pixel data should be output from VDC5 at the falling edge of the clock. */
thedo 166:3a9487d57a5c 73 #define LCD_CH1_OUT_EDGE VDC5_EDGE_FALLING /* Output phase control of LCD_DATA[23:0] signal */
thedo 166:3a9487d57a5c 74 #define LCD_CH1_OUT_FORMAT VDC5_LCD_OUTFORMAT_RGB888 /* LCD output format select */
thedo 166:3a9487d57a5c 75
thedo 166:3a9487d57a5c 76 #define LCD_CH1_PANEL_CLK VDC5_PANEL_ICKSEL_LVDS /* Panel clock select */
thedo 166:3a9487d57a5c 77 #define LCD_CH1_PANEL_CLK_DIV VDC5_PANEL_CLKDIV_1_1 /* Panel clock frequency division ratio */
thedo 166:3a9487d57a5c 78
thedo 166:3a9487d57a5c 79 #define LCD_CH1_TCON_HALF (LCD_CH1_SIG_FH / 2u) /* TCON reference timing, 1/2fH timing */
thedo 166:3a9487d57a5c 80 #define LCD_CH1_TCON_OFFSET (0u) /* TCON reference timing, offset Hsync signal timing */
thedo 166:3a9487d57a5c 81
thedo 166:3a9487d57a5c 82
thedo 166:3a9487d57a5c 83 /******************************************************************************
thedo 166:3a9487d57a5c 84 Typedef definitions
thedo 166:3a9487d57a5c 85 ******************************************************************************/
thedo 166:3a9487d57a5c 86
thedo 166:3a9487d57a5c 87 /******************************************************************************
thedo 166:3a9487d57a5c 88 Exported global functions (to be accessed by other files)
thedo 166:3a9487d57a5c 89 ******************************************************************************/
thedo 166:3a9487d57a5c 90 void GRAPHICS_SetLcdPanel_Ch1(void);
thedo 166:3a9487d57a5c 91 void GRAPHICS_SetLcdTconSettings_Ch1(const vdc5_lcd_tcon_timing_t * * const outctrl);
thedo 166:3a9487d57a5c 92
thedo 166:3a9487d57a5c 93
thedo 166:3a9487d57a5c 94 #endif /* LCD_PANEL_H not defined */
thedo 166:3a9487d57a5c 95 #endif /* LCD_ANALOG_RGB_CH1_H */