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Opencv 3.1 project on GR-PEACH board

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GR-PEACH_video/drivers/vdec/src/r_vdec_register.c@166:3a9487d57a5c, 2017-06-29 (annotated)

Committer:
thedo
Date:
Thu Jun 29 11:00:41 2017 +0000
Revision:
166:3a9487d57a5c
This is Opencv 3.1 project on GR-PEACH board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
thedo 166:3a9487d57a5c 1 /*******************************************************************************
thedo 166:3a9487d57a5c 2 * DISCLAIMER
thedo 166:3a9487d57a5c 3 * This software is supplied by Renesas Electronics Corporation and is only
thedo 166:3a9487d57a5c 4 * intended for use with Renesas products. No other uses are authorized. This
thedo 166:3a9487d57a5c 5 * software is owned by Renesas Electronics Corporation and is protected under
thedo 166:3a9487d57a5c 6 * all applicable laws, including copyright laws.
thedo 166:3a9487d57a5c 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
thedo 166:3a9487d57a5c 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
thedo 166:3a9487d57a5c 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
thedo 166:3a9487d57a5c 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
thedo 166:3a9487d57a5c 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
thedo 166:3a9487d57a5c 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
thedo 166:3a9487d57a5c 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
thedo 166:3a9487d57a5c 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
thedo 166:3a9487d57a5c 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
thedo 166:3a9487d57a5c 16 * Renesas reserves the right, without notice, to make changes to this software
thedo 166:3a9487d57a5c 17 * and to discontinue the availability of this software. By using this software,
thedo 166:3a9487d57a5c 18 * you agree to the additional terms and conditions found by accessing the
thedo 166:3a9487d57a5c 19 * following link:
thedo 166:3a9487d57a5c 20 * http://www.renesas.com/disclaimer
thedo 166:3a9487d57a5c 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
thedo 166:3a9487d57a5c 22 *******************************************************************************/
thedo 166:3a9487d57a5c 23 /**************************************************************************//**
thedo 166:3a9487d57a5c 24 * @file r_vdec_register.c
thedo 166:3a9487d57a5c 25 * @version 1.00
thedo 166:3a9487d57a5c 26 * $Rev: 199 $
thedo 166:3a9487d57a5c 27 * $Date:: 2014-05-23 16:33:52 +0900#$
thedo 166:3a9487d57a5c 28 * @brief VDEC driver register setup processing
thedo 166:3a9487d57a5c 29 ******************************************************************************/
thedo 166:3a9487d57a5c 30
thedo 166:3a9487d57a5c 31 /******************************************************************************
thedo 166:3a9487d57a5c 32 Includes <System Includes> , "Project Includes"
thedo 166:3a9487d57a5c 33 ******************************************************************************/
thedo 166:3a9487d57a5c 34 #include "r_vdec.h"
thedo 166:3a9487d57a5c 35 #include "r_vdec_user.h"
thedo 166:3a9487d57a5c 36 #include "r_vdec_register.h"
thedo 166:3a9487d57a5c 37
thedo 166:3a9487d57a5c 38
thedo 166:3a9487d57a5c 39 /******************************************************************************
thedo 166:3a9487d57a5c 40 Macro definitions
thedo 166:3a9487d57a5c 41 ******************************************************************************/
thedo 166:3a9487d57a5c 42 /* shift value */
thedo 166:3a9487d57a5c 43 #define VEDC_REG_SHIFT_15 (15u)
thedo 166:3a9487d57a5c 44 #define VEDC_REG_SHIFT_14 (14u)
thedo 166:3a9487d57a5c 45 #define VEDC_REG_SHIFT_13 (13u)
thedo 166:3a9487d57a5c 46 #define VEDC_REG_SHIFT_12 (12u)
thedo 166:3a9487d57a5c 47 #define VEDC_REG_SHIFT_11 (11u)
thedo 166:3a9487d57a5c 48 #define VEDC_REG_SHIFT_10 (10u)
thedo 166:3a9487d57a5c 49 #define VEDC_REG_SHIFT_9 (9u)
thedo 166:3a9487d57a5c 50 #define VEDC_REG_SHIFT_8 (8u)
thedo 166:3a9487d57a5c 51 #define VEDC_REG_SHIFT_6 (6u)
thedo 166:3a9487d57a5c 52 #define VEDC_REG_SHIFT_5 (5u)
thedo 166:3a9487d57a5c 53 #define VEDC_REG_SHIFT_4 (4u)
thedo 166:3a9487d57a5c 54 #define VEDC_REG_SHIFT_2 (2u)
thedo 166:3a9487d57a5c 55 #define VEDC_REG_SHIFT_1 (1u)
thedo 166:3a9487d57a5c 56
thedo 166:3a9487d57a5c 57 /* bit set pattern */
thedo 166:3a9487d57a5c 58 #define VDEC_REG_SET_0X8000 (0x8000u)
thedo 166:3a9487d57a5c 59 #define VDEC_REG_SET_0X4000 (0x4000u)
thedo 166:3a9487d57a5c 60 #define VDEC_REG_SET_0X2000 (0x2000u)
thedo 166:3a9487d57a5c 61 #define VDEC_REG_SET_0X1000 (0x1000u)
thedo 166:3a9487d57a5c 62 #define VDEC_REG_SET_0X0800 (0x0800u)
thedo 166:3a9487d57a5c 63 #define VDEC_REG_SET_0X0100 (0x0100u)
thedo 166:3a9487d57a5c 64 #define VDEC_REG_SET_0X0080 (0x0080u)
thedo 166:3a9487d57a5c 65 #define VDEC_REG_SET_0X0020 (0x0020u)
thedo 166:3a9487d57a5c 66 #define VDEC_REG_SET_0X0010 (0x0010u)
thedo 166:3a9487d57a5c 67 #define VDEC_REG_SET_0X0008 (0x0008u)
thedo 166:3a9487d57a5c 68 #define VDEC_REG_SET_0X0004 (0x0004u)
thedo 166:3a9487d57a5c 69 #define VDEC_REG_SET_0X0002 (0x0002u)
thedo 166:3a9487d57a5c 70 #define VDEC_REG_SET_0X0001 (0x0001u)
thedo 166:3a9487d57a5c 71
thedo 166:3a9487d57a5c 72 /* bit mask pattern */
thedo 166:3a9487d57a5c 73 #define VDEC_REG_BIT_MASK_0X8000 (0x8000u)
thedo 166:3a9487d57a5c 74 #define VDEC_REG_BIT_MASK_0X4000 (0x4000u)
thedo 166:3a9487d57a5c 75 #define VDEC_REG_BIT_MASK_0X2000 (0x2000u)
thedo 166:3a9487d57a5c 76 #define VDEC_REG_BIT_MASK_0X1000 (0x1000u)
thedo 166:3a9487d57a5c 77 #define VDEC_REG_BIT_MASK_0X0800 (0x0800u)
thedo 166:3a9487d57a5c 78 #define VDEC_REG_BIT_MASK_0X0400 (0x0400u)
thedo 166:3a9487d57a5c 79 #define VDEC_REG_BIT_MASK_0X0200 (0x0200u)
thedo 166:3a9487d57a5c 80 #define VDEC_REG_BIT_MASK_0X0100 (0x0100u)
thedo 166:3a9487d57a5c 81
thedo 166:3a9487d57a5c 82 /* register mask value */
thedo 166:3a9487d57a5c 83 #define VDEC_REG_MASK_0X03FF (0x03FFu) /* mask vdec_reg->syncssr */
thedo 166:3a9487d57a5c 84 #define VDEC_REG_MASK_0XFF1F (0xFF1Fu) /* mask vdec_reg->ycscr7 */
thedo 166:3a9487d57a5c 85 #define VDEC_REG_MASK_0XF3FF (0xF3FFu) /* mask vdec_reg->hafccr1 */
thedo 166:3a9487d57a5c 86 #define VDEC_REG_MASK_0X83FF (0x83FFu) /* mask vdec_reg->dcpcr1 */
thedo 166:3a9487d57a5c 87 #define VDEC_REG_MASK_0X01FF (0x01FFu) /* mask vdec_reg->ycscr11 */
thedo 166:3a9487d57a5c 88 #define VDEC_REG_MASK_0X1C00 (0x1C00u) /* mask vdec_reg->dcpcr9 */
thedo 166:3a9487d57a5c 89 #define VDEC_REG_MASK_0X1F00 (0x1F00u) /* mask vdec_reg->pgacr */
thedo 166:3a9487d57a5c 90 #define VDEC_REG_MASK_0X3F00 (0x3F00u) /* mask vdec_reg->agccr2 */
thedo 166:3a9487d57a5c 91 #define VDEC_REG_MASK_0X0007 (0x0007u) /* mask vdec_reg->rgorcr7 */
thedo 166:3a9487d57a5c 92 #define VDEC_REG_MASK_0XF800 (0xF800u) /* mask vdec_reg->ycscr8 */
thedo 166:3a9487d57a5c 93 #define VDEC_REG_MASK_0XFC00 (0xFC00u) /* mask vdec_reg->synscr1 */
thedo 166:3a9487d57a5c 94 #define VDEC_REG_MASK_0X00FF (0x00FFu) /* mask vdec_reg->synscr1 */
thedo 166:3a9487d57a5c 95 #define VDEC_REG_MASK_0X0003 (0x0003u) /* mask vdec_reg->cromasr1 */
thedo 166:3a9487d57a5c 96
thedo 166:3a9487d57a5c 97 /******************************************************************************
thedo 166:3a9487d57a5c 98 Typedef definitions
thedo 166:3a9487d57a5c 99 ******************************************************************************/
thedo 166:3a9487d57a5c 100
thedo 166:3a9487d57a5c 101 /******************************************************************************
thedo 166:3a9487d57a5c 102 Private global variables and functions
thedo 166:3a9487d57a5c 103 ******************************************************************************/
thedo 166:3a9487d57a5c 104 static void NoiseReductionLPF(
thedo 166:3a9487d57a5c 105 const vdec_reg_address_t * const vdec_reg,
thedo 166:3a9487d57a5c 106 const vdec_noise_rd_lpf_t * const p_noise_rd_lpf);
thedo 166:3a9487d57a5c 107 static void SyncSlicer(const vdec_reg_address_t * const vdec_reg, const vdec_sync_slicer_t * const p_sync_slicer);
thedo 166:3a9487d57a5c 108 static void HorizontalAFC(
thedo 166:3a9487d57a5c 109 const vdec_reg_address_t * const vdec_reg,
thedo 166:3a9487d57a5c 110 const vdec_horizontal_afc_t * const p_horizontal_afc);
thedo 166:3a9487d57a5c 111 static void VerticalCountdown(
thedo 166:3a9487d57a5c 112 const vdec_reg_address_t * const vdec_reg,
thedo 166:3a9487d57a5c 113 const vdec_vcount_down_t * const p_vcount_down);
thedo 166:3a9487d57a5c 114 static void AgcPga(const vdec_reg_address_t * const vdec_reg, const vdec_agc_t * const p_agc);
thedo 166:3a9487d57a5c 115 static void PeakLimiterControl(
thedo 166:3a9487d57a5c 116 const vdec_reg_address_t * const vdec_reg,
thedo 166:3a9487d57a5c 117 const vdec_peak_limiter_t * const p_peak_limiter);
thedo 166:3a9487d57a5c 118 static void OverRangeControl(const vdec_reg_address_t * const vdec_reg, const vdec_over_range_t * const p_over_range);
thedo 166:3a9487d57a5c 119 static void YcSeparationControl(
thedo 166:3a9487d57a5c 120 const vdec_reg_address_t * const vdec_reg,
thedo 166:3a9487d57a5c 121 const vdec_yc_sep_ctrl_t * const p_yc_sep_ctrl);
thedo 166:3a9487d57a5c 122 static void FilterTAPsCoefficient(
thedo 166:3a9487d57a5c 123 volatile uint16_t * const * fil_reg_address,
thedo 166:3a9487d57a5c 124 const vdec_chrfil_tap_t * const fil2_2d);
thedo 166:3a9487d57a5c 125
thedo 166:3a9487d57a5c 126
thedo 166:3a9487d57a5c 127 /**************************************************************************//**
thedo 166:3a9487d57a5c 128 * @brief Sets registers for initialization
thedo 166:3a9487d57a5c 129 * @param[in] ch : Channel
thedo 166:3a9487d57a5c 130 * @param[in] vinsel : Input pin control
thedo 166:3a9487d57a5c 131 * @retval None
thedo 166:3a9487d57a5c 132 *****************************************************************************/
thedo 166:3a9487d57a5c 133 void VDEC_Initialize (const vdec_channel_t ch, const vdec_adc_vinsel_t vinsel)
thedo 166:3a9487d57a5c 134 {
thedo 166:3a9487d57a5c 135 const vdec_reg_address_t * vdec_reg;
thedo 166:3a9487d57a5c 136 uint16_t reg_data;
thedo 166:3a9487d57a5c 137
thedo 166:3a9487d57a5c 138 vdec_reg = &vdec_reg_address[ch];
thedo 166:3a9487d57a5c 139
thedo 166:3a9487d57a5c 140 /* Input pin control */
thedo 166:3a9487d57a5c 141 if (vinsel == VDEC_ADC_VINSEL_VIN1) {
thedo 166:3a9487d57a5c 142 reg_data = (uint16_t)((uint32_t)*(vdec_reg->adccr2) & (~0x0001u));
thedo 166:3a9487d57a5c 143 *(vdec_reg->adccr2) = reg_data;
thedo 166:3a9487d57a5c 144 } else {
thedo 166:3a9487d57a5c 145 reg_data = (uint16_t)((uint32_t)*(vdec_reg->adccr2) | (0x0001u));
thedo 166:3a9487d57a5c 146 *(vdec_reg->adccr2) = reg_data;
thedo 166:3a9487d57a5c 147 }
thedo 166:3a9487d57a5c 148 return;
thedo 166:3a9487d57a5c 149 } /* End of function VDEC_Initialize() */
thedo 166:3a9487d57a5c 150
thedo 166:3a9487d57a5c 151 /**************************************************************************//**
thedo 166:3a9487d57a5c 152 * @brief Sets registers for active image period
thedo 166:3a9487d57a5c 153 * @param[in] ch : Channel
thedo 166:3a9487d57a5c 154 * @param[in] param : Active image period parameter
thedo 166:3a9487d57a5c 155 * @retval None
thedo 166:3a9487d57a5c 156 *****************************************************************************/
thedo 166:3a9487d57a5c 157 void VDEC_ActivePeriod (const vdec_channel_t ch, const vdec_active_period_t * const param)
thedo 166:3a9487d57a5c 158 {
thedo 166:3a9487d57a5c 159 const vdec_reg_address_t * vdec_reg;
thedo 166:3a9487d57a5c 160
thedo 166:3a9487d57a5c 161 vdec_reg = &vdec_reg_address[ch];
thedo 166:3a9487d57a5c 162
thedo 166:3a9487d57a5c 163 /* Left end of input video signal capturing area */
thedo 166:3a9487d57a5c 164 *(vdec_reg->tgcr1) = param->srcleft;
thedo 166:3a9487d57a5c 165 /* Top end of input video signal capturing area
thedo 166:3a9487d57a5c 166 and height of input video signal capturing area */
thedo 166:3a9487d57a5c 167 *(vdec_reg->tgcr2) = (uint16_t)(((uint32_t)param->srctop << VEDC_REG_SHIFT_10) | (uint32_t)param->srcheight);
thedo 166:3a9487d57a5c 168 /* Width of input video signal capturing area */
thedo 166:3a9487d57a5c 169 *(vdec_reg->tgcr3) = param->srcwidth;
thedo 166:3a9487d57a5c 170
thedo 166:3a9487d57a5c 171 return;
thedo 166:3a9487d57a5c 172 } /* End of function VDEC_ActivePeriod() */
thedo 166:3a9487d57a5c 173
thedo 166:3a9487d57a5c 174 /**************************************************************************//**
thedo 166:3a9487d57a5c 175 * @brief Sets registers for sync separation
thedo 166:3a9487d57a5c 176 * @param[in] ch : Channel
thedo 166:3a9487d57a5c 177 * @param[in] param : Sync separation parameter
thedo 166:3a9487d57a5c 178 * @retval None
thedo 166:3a9487d57a5c 179 *****************************************************************************/
thedo 166:3a9487d57a5c 180 void VDEC_SyncSeparation (const vdec_channel_t ch, const vdec_sync_separation_t * const param)
thedo 166:3a9487d57a5c 181 {
thedo 166:3a9487d57a5c 182 const vdec_reg_address_t * vdec_reg;
thedo 166:3a9487d57a5c 183
thedo 166:3a9487d57a5c 184 vdec_reg = &vdec_reg_address[ch];
thedo 166:3a9487d57a5c 185
thedo 166:3a9487d57a5c 186 /* Noise reduction LPF */
thedo 166:3a9487d57a5c 187 NoiseReductionLPF(vdec_reg, param->noise_rd_lpf);
thedo 166:3a9487d57a5c 188 /* Auto level control sync slicer */
thedo 166:3a9487d57a5c 189 SyncSlicer(vdec_reg, param->sync_slicer);
thedo 166:3a9487d57a5c 190 /* Horizontal AFC */
thedo 166:3a9487d57a5c 191 HorizontalAFC(vdec_reg, param->horizontal_afc);
thedo 166:3a9487d57a5c 192 /* Vertical count-down */
thedo 166:3a9487d57a5c 193 VerticalCountdown(vdec_reg, param->vcount_down);
thedo 166:3a9487d57a5c 194 /* AGC/PGA */
thedo 166:3a9487d57a5c 195 AgcPga(vdec_reg, param->agc);
thedo 166:3a9487d57a5c 196 /* Peak limiter control */
thedo 166:3a9487d57a5c 197 PeakLimiterControl(vdec_reg, param->peak_limiter);
thedo 166:3a9487d57a5c 198
thedo 166:3a9487d57a5c 199 return;
thedo 166:3a9487d57a5c 200 } /* End of function VDEC_SyncSeparation() */
thedo 166:3a9487d57a5c 201
thedo 166:3a9487d57a5c 202 /**************************************************************************//**
thedo 166:3a9487d57a5c 203 * @brief Sets registers for Y/C separation
thedo 166:3a9487d57a5c 204 * @param[in] ch : Channel
thedo 166:3a9487d57a5c 205 * @param[in] param : Y/C separation parameter
thedo 166:3a9487d57a5c 206 * @retval None
thedo 166:3a9487d57a5c 207 *****************************************************************************/
thedo 166:3a9487d57a5c 208 void VDEC_YcSeparation (const vdec_channel_t ch, const vdec_yc_separation_t * const param)
thedo 166:3a9487d57a5c 209 {
thedo 166:3a9487d57a5c 210 const vdec_reg_address_t * vdec_reg;
thedo 166:3a9487d57a5c 211
thedo 166:3a9487d57a5c 212 vdec_reg = &vdec_reg_address[ch];
thedo 166:3a9487d57a5c 213
thedo 166:3a9487d57a5c 214 /* Over-range control */
thedo 166:3a9487d57a5c 215 OverRangeControl(vdec_reg, param->over_range);
thedo 166:3a9487d57a5c 216 /* Y/C separation control */
thedo 166:3a9487d57a5c 217 YcSeparationControl(vdec_reg, param->yc_sep_ctrl);
thedo 166:3a9487d57a5c 218
thedo 166:3a9487d57a5c 219 /* Two-dimensional cascade broadband (3.58/4.43/SECAM-DR)/TAKE-OFF filter TAP coefficient */
thedo 166:3a9487d57a5c 220 FilterTAPsCoefficient(vdec_filter_reg_address[ch].yctwa_f, param->fil2_2d_wa);
thedo 166:3a9487d57a5c 221 /* Two-dimensional cascade broadband (SECAM-DB) filter TAP coefficient */
thedo 166:3a9487d57a5c 222 FilterTAPsCoefficient(vdec_filter_reg_address[ch].yctwb_f, param->fil2_2d_wb);
thedo 166:3a9487d57a5c 223 /* Two-dimensional cascade narrowband (3.58/4.43/SECAM-DR) filter TAP coefficient */
thedo 166:3a9487d57a5c 224 FilterTAPsCoefficient(vdec_filter_reg_address[ch].yctna_f, param->fil2_2d_na);
thedo 166:3a9487d57a5c 225 /* Two-dimensional cascade narrowband (SECAMDB) filter TAP coefficient */
thedo 166:3a9487d57a5c 226 FilterTAPsCoefficient(vdec_filter_reg_address[ch].yctnb_f, param->fil2_2d_nb);
thedo 166:3a9487d57a5c 227
thedo 166:3a9487d57a5c 228 return;
thedo 166:3a9487d57a5c 229 } /* End of function VDEC_YcSeparation() */
thedo 166:3a9487d57a5c 230
thedo 166:3a9487d57a5c 231 /**************************************************************************//**
thedo 166:3a9487d57a5c 232 * @brief Sets registers for chroma decoding
thedo 166:3a9487d57a5c 233 * @param[in] ch : Channel
thedo 166:3a9487d57a5c 234 * @param[in] param : Chroma decoding parameter
thedo 166:3a9487d57a5c 235 * @retval None
thedo 166:3a9487d57a5c 236 *****************************************************************************/
thedo 166:3a9487d57a5c 237 void VDEC_ChromaDecoding (const vdec_channel_t ch, const vdec_chroma_decoding_t * const param)
thedo 166:3a9487d57a5c 238 {
thedo 166:3a9487d57a5c 239 const vdec_reg_address_t * vdec_reg;
thedo 166:3a9487d57a5c 240 vdec_chrmdec_ctrl_t * p_chrmdec_ctrl;
thedo 166:3a9487d57a5c 241 vdec_burst_lock_t * p_burst_lock;
thedo 166:3a9487d57a5c 242 vdec_acc_t * p_acc;
thedo 166:3a9487d57a5c 243 vdec_tint_ry_t * p_tint_ry;
thedo 166:3a9487d57a5c 244 uint32_t reg_data;
thedo 166:3a9487d57a5c 245
thedo 166:3a9487d57a5c 246 vdec_reg = &vdec_reg_address[ch];
thedo 166:3a9487d57a5c 247 p_chrmdec_ctrl = param->chrmdec_ctrl;
thedo 166:3a9487d57a5c 248 p_burst_lock = param->burst_lock;
thedo 166:3a9487d57a5c 249 p_acc = param->acc;
thedo 166:3a9487d57a5c 250 p_tint_ry = param->tint_ry;
thedo 166:3a9487d57a5c 251
thedo 166:3a9487d57a5c 252 /* Color system detection */
thedo 166:3a9487d57a5c 253 if (p_chrmdec_ctrl != NULL) {
thedo 166:3a9487d57a5c 254 reg_data = (uint32_t)*(vdec_reg->btlcr) & (uint32_t)(~VDEC_REG_MASK_0X00FF);
thedo 166:3a9487d57a5c 255 /* Default color system */
thedo 166:3a9487d57a5c 256 reg_data |= (uint32_t)p_chrmdec_ctrl->defaultsys << VEDC_REG_SHIFT_6;
thedo 166:3a9487d57a5c 257 /* NTSC-M detection control */
thedo 166:3a9487d57a5c 258 reg_data |= (p_chrmdec_ctrl->nontsc358_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0020 : (uint32_t)0x0000u;
thedo 166:3a9487d57a5c 259 /* NTSC-4.43 detection control */
thedo 166:3a9487d57a5c 260 reg_data |= (p_chrmdec_ctrl->nontsc443_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0010 : (uint32_t)0x0000u;
thedo 166:3a9487d57a5c 261 /* PAL-M detection control */
thedo 166:3a9487d57a5c 262 reg_data |= (p_chrmdec_ctrl->nopalm_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0008 : (uint32_t)0x0000u;
thedo 166:3a9487d57a5c 263 /* PAL-N detection control */
thedo 166:3a9487d57a5c 264 reg_data |= (p_chrmdec_ctrl->nopaln_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0004 : (uint32_t)0x0000u;
thedo 166:3a9487d57a5c 265 /* PAL-B, G, H, I, D detection control */
thedo 166:3a9487d57a5c 266 reg_data |= (p_chrmdec_ctrl->nopal443_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0002 : (uint32_t)0x0000u;
thedo 166:3a9487d57a5c 267 /* SECAM detection control */
thedo 166:3a9487d57a5c 268 reg_data |= (p_chrmdec_ctrl->nosecam_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0001 : (uint32_t)0x0000u;
thedo 166:3a9487d57a5c 269
thedo 166:3a9487d57a5c 270 *(vdec_reg->btlcr) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 271
thedo 166:3a9487d57a5c 272 /* Luminance signal delay adjustment */
thedo 166:3a9487d57a5c 273 reg_data = (uint32_t)p_chrmdec_ctrl->lumadelay << VEDC_REG_SHIFT_4;
thedo 166:3a9487d57a5c 274 /* LPF for demodulated chroma */
thedo 166:3a9487d57a5c 275 reg_data |= (p_chrmdec_ctrl->chromalpf == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0004;
thedo 166:3a9487d57a5c 276 /* Averaging processing for pre-demodulated line */
thedo 166:3a9487d57a5c 277 reg_data |= (uint32_t)p_chrmdec_ctrl->demodmode;
thedo 166:3a9487d57a5c 278
thedo 166:3a9487d57a5c 279 *(vdec_reg->ycdcr) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 280 }
thedo 166:3a9487d57a5c 281 /* BCO */
thedo 166:3a9487d57a5c 282 if (p_burst_lock != NULL) {
thedo 166:3a9487d57a5c 283 reg_data = (uint32_t)*(vdec_reg->btlcr) & (uint32_t)(~VDEC_REG_MASK_0XFC00);
thedo 166:3a9487d57a5c 284 /* Burst lock PLL lock range */
thedo 166:3a9487d57a5c 285 reg_data |= (uint32_t)p_burst_lock->lockrange << VEDC_REG_SHIFT_14;
thedo 166:3a9487d57a5c 286 /* Burst lock PLL loop gain */
thedo 166:3a9487d57a5c 287 reg_data |= (uint32_t)p_burst_lock->loopgain << VEDC_REG_SHIFT_12;
thedo 166:3a9487d57a5c 288 /* Level for burst lock PLL to re-search free-run frequency */
thedo 166:3a9487d57a5c 289 reg_data |= (uint32_t)p_burst_lock->locklimit << VEDC_REG_SHIFT_10;
thedo 166:3a9487d57a5c 290
thedo 166:3a9487d57a5c 291 *(vdec_reg->btlcr) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 292
thedo 166:3a9487d57a5c 293 /* burst gate pulse position check */
thedo 166:3a9487d57a5c 294 reg_data = (uint32_t)p_burst_lock->bgpcheck << VEDC_REG_SHIFT_15;
thedo 166:3a9487d57a5c 295 /* burst gate pulse width */
thedo 166:3a9487d57a5c 296 reg_data |= (uint32_t)p_burst_lock->bgpwidth << VEDC_REG_SHIFT_8;
thedo 166:3a9487d57a5c 297 /* burst gate pulse start position */
thedo 166:3a9487d57a5c 298 reg_data |= (uint32_t)p_burst_lock->bgpstart;
thedo 166:3a9487d57a5c 299
thedo 166:3a9487d57a5c 300 *(vdec_reg->btgpcr) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 301 }
thedo 166:3a9487d57a5c 302 /* ACC and color killer */
thedo 166:3a9487d57a5c 303 if (p_acc != NULL) {
thedo 166:3a9487d57a5c 304 /* ACC operating mode */
thedo 166:3a9487d57a5c 305 reg_data = (p_acc->accmode == VDEC_ACC_MD_AUTO) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0800;
thedo 166:3a9487d57a5c 306 /* Maximum ACC Gain */
thedo 166:3a9487d57a5c 307 reg_data |= (uint32_t)p_acc->accmaxgain << VEDC_REG_SHIFT_9;
thedo 166:3a9487d57a5c 308 /* ACC reference color burst amplitude */
thedo 166:3a9487d57a5c 309 reg_data |= (uint32_t)p_acc->acclevel;
thedo 166:3a9487d57a5c 310 /* Color killer offset */
thedo 166:3a9487d57a5c 311 reg_data |= (uint32_t)p_acc->killeroffset << VEDC_REG_SHIFT_12;
thedo 166:3a9487d57a5c 312
thedo 166:3a9487d57a5c 313 *(vdec_reg->acccr1) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 314
thedo 166:3a9487d57a5c 315 /* Chroma manual gain (sub) */
thedo 166:3a9487d57a5c 316 reg_data = (uint32_t)p_acc->chromasubgain << VEDC_REG_SHIFT_9;
thedo 166:3a9487d57a5c 317 /* Chroma manual gain (main) */
thedo 166:3a9487d57a5c 318 reg_data |= (uint32_t)p_acc->chromamaingain;
thedo 166:3a9487d57a5c 319
thedo 166:3a9487d57a5c 320 *(vdec_reg->acccr2) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 321
thedo 166:3a9487d57a5c 322 /* ACC response speed */
thedo 166:3a9487d57a5c 323 reg_data = (uint32_t)p_acc->accresponse << VEDC_REG_SHIFT_14;
thedo 166:3a9487d57a5c 324 /* ACC gain adjustment accuracy */
thedo 166:3a9487d57a5c 325 reg_data |= (uint32_t)p_acc->accprecis << VEDC_REG_SHIFT_8;
thedo 166:3a9487d57a5c 326 /* Forced color killer mode ON/OFF */
thedo 166:3a9487d57a5c 327 reg_data |= (p_acc->killermode == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0080;
thedo 166:3a9487d57a5c 328 /* Color killer operation start point */
thedo 166:3a9487d57a5c 329 reg_data |= (uint32_t)p_acc->killerlevel << VEDC_REG_SHIFT_1;
thedo 166:3a9487d57a5c 330
thedo 166:3a9487d57a5c 331 *(vdec_reg->acccr3) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 332 }
thedo 166:3a9487d57a5c 333 /* TINT correction/R-Y axis correction (only valid for NTSC/PAL) */
thedo 166:3a9487d57a5c 334 if (p_tint_ry != NULL) {
thedo 166:3a9487d57a5c 335 /* Fine adjustment of R-Y demodulation axis and hue adjustment level */
thedo 166:3a9487d57a5c 336 reg_data = (uint32_t)p_tint_ry->tintsub << VEDC_REG_SHIFT_10;
thedo 166:3a9487d57a5c 337 reg_data |= (uint32_t)p_tint_ry->tintmain;
thedo 166:3a9487d57a5c 338
thedo 166:3a9487d57a5c 339 *(vdec_reg->tintcr) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 340 }
thedo 166:3a9487d57a5c 341 return;
thedo 166:3a9487d57a5c 342 } /* End of function VDEC_ChromaDecoding() */
thedo 166:3a9487d57a5c 343
thedo 166:3a9487d57a5c 344 /**************************************************************************//**
thedo 166:3a9487d57a5c 345 * @brief Sets registers for digital clamp
thedo 166:3a9487d57a5c 346 * @param[in] ch : Channel
thedo 166:3a9487d57a5c 347 * @param[in] param : Digital clamp parameter
thedo 166:3a9487d57a5c 348 * @retval None
thedo 166:3a9487d57a5c 349 *****************************************************************************/
thedo 166:3a9487d57a5c 350 void VDEC_DigitalClamp (const vdec_channel_t ch, const vdec_degital_clamp_t * const param)
thedo 166:3a9487d57a5c 351 {
thedo 166:3a9487d57a5c 352 const vdec_reg_address_t * vdec_reg;
thedo 166:3a9487d57a5c 353 vdec_pedestal_clamp_t * p_pedestal_clamp;
thedo 166:3a9487d57a5c 354 vdec_center_clamp_t * p_center_clamp;
thedo 166:3a9487d57a5c 355 vdec_noise_det_t * p_noise_det;
thedo 166:3a9487d57a5c 356 uint32_t reg_data;
thedo 166:3a9487d57a5c 357
thedo 166:3a9487d57a5c 358 vdec_reg = &vdec_reg_address[ch];
thedo 166:3a9487d57a5c 359 p_pedestal_clamp = param->pedestal_clamp;
thedo 166:3a9487d57a5c 360 p_center_clamp = param->center_clamp;
thedo 166:3a9487d57a5c 361 p_noise_det = param->noise_det;
thedo 166:3a9487d57a5c 362
thedo 166:3a9487d57a5c 363 /* Digital clamp pulse position check */
thedo 166:3a9487d57a5c 364 reg_data = (uint32_t)*(vdec_reg->dcpcr1);
thedo 166:3a9487d57a5c 365 if (param->dcpcheck == VDEC_OFF) {
thedo 166:3a9487d57a5c 366 reg_data &= (uint32_t)(~VDEC_REG_SET_0X0800);
thedo 166:3a9487d57a5c 367 } else {
thedo 166:3a9487d57a5c 368 reg_data |= (uint32_t)VDEC_REG_SET_0X0800;
thedo 166:3a9487d57a5c 369 }
thedo 166:3a9487d57a5c 370 *(vdec_reg->dcpcr1) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 371
thedo 166:3a9487d57a5c 372 /* Digital clamp response speed */
thedo 166:3a9487d57a5c 373 *(vdec_reg->dcpcr3) = (uint16_t)((uint32_t)param->dcpresponse << VEDC_REG_SHIFT_12);
thedo 166:3a9487d57a5c 374 /* Digital clamp start line */
thedo 166:3a9487d57a5c 375 *(vdec_reg->dcpcr4) = (uint16_t)((uint32_t)param->dcpstart << VEDC_REG_SHIFT_10);
thedo 166:3a9487d57a5c 376 /* Digital clamp end line */
thedo 166:3a9487d57a5c 377 *(vdec_reg->dcpcr5) = (uint16_t)((uint32_t)param->dcpend << VEDC_REG_SHIFT_10);
thedo 166:3a9487d57a5c 378 /* Digital clamp pulse width */
thedo 166:3a9487d57a5c 379 *(vdec_reg->dcpcr6) = (uint16_t)((uint32_t)param->dcpwidth << VEDC_REG_SHIFT_8);
thedo 166:3a9487d57a5c 380
thedo 166:3a9487d57a5c 381 /* Pedestal clamp */
thedo 166:3a9487d57a5c 382 if (p_pedestal_clamp != NULL) {
thedo 166:3a9487d57a5c 383 reg_data = (uint32_t)*(vdec_reg->dcpcr1) & (uint32_t)(~VDEC_REG_MASK_0X83FF);
thedo 166:3a9487d57a5c 384 /* Clamp level setting mode (Y signal) */
thedo 166:3a9487d57a5c 385 reg_data |= (p_pedestal_clamp->dcpmode_y == VDEC_DCPMODE_MANUAL) ? (uint32_t)0x0000u :
thedo 166:3a9487d57a5c 386 (uint32_t)VDEC_REG_SET_0X8000;
thedo 166:3a9487d57a5c 387 /* Clamp offset level (Y signal) */
thedo 166:3a9487d57a5c 388 reg_data |= (uint32_t)p_pedestal_clamp->blanklevel_y;
thedo 166:3a9487d57a5c 389
thedo 166:3a9487d57a5c 390 *(vdec_reg->dcpcr1) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 391
thedo 166:3a9487d57a5c 392 /* Digital clamp pulse horizontal start position (Y signal) */
thedo 166:3a9487d57a5c 393 *(vdec_reg->dcpcr7) = (uint16_t)((uint32_t)p_pedestal_clamp->dcppos_y << VEDC_REG_SHIFT_8);
thedo 166:3a9487d57a5c 394 }
thedo 166:3a9487d57a5c 395 /* Center clamp */
thedo 166:3a9487d57a5c 396 if (p_center_clamp != NULL) {
thedo 166:3a9487d57a5c 397 /* Clamp level setting mode (Cb/Cr signal) */
thedo 166:3a9487d57a5c 398 reg_data = (p_center_clamp->dcpmode_c == VDEC_DCPMODE_MANUAL) ? (uint32_t)0x0000u :
thedo 166:3a9487d57a5c 399 (uint32_t)VDEC_REG_SET_0X8000;
thedo 166:3a9487d57a5c 400 /* Clamp offset level (Cb signal) */
thedo 166:3a9487d57a5c 401 reg_data |= (uint32_t)p_center_clamp->blanklevel_cb << VEDC_REG_SHIFT_6;
thedo 166:3a9487d57a5c 402 /* Clamp offset level (Cr signal) */
thedo 166:3a9487d57a5c 403 reg_data |= (uint32_t)p_center_clamp->blanklevel_cr;
thedo 166:3a9487d57a5c 404
thedo 166:3a9487d57a5c 405 *(vdec_reg->dcpcr2) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 406
thedo 166:3a9487d57a5c 407 /* Digital clamp pulse horizontal start position (Cb/Cr signal) */
thedo 166:3a9487d57a5c 408 *(vdec_reg->dcpcr8) = (uint16_t)((uint32_t)p_center_clamp->dcppos_c << VEDC_REG_SHIFT_8);
thedo 166:3a9487d57a5c 409 }
thedo 166:3a9487d57a5c 410 /* Noise detection */
thedo 166:3a9487d57a5c 411 if (p_noise_det != NULL) {
thedo 166:3a9487d57a5c 412 /* Video signal for autocorrelation function */
thedo 166:3a9487d57a5c 413 reg_data = (uint32_t)p_noise_det->acfinput << VEDC_REG_SHIFT_12;
thedo 166:3a9487d57a5c 414 /* Delay time for autocorrelation function calculation */
thedo 166:3a9487d57a5c 415 reg_data |= (uint32_t)p_noise_det->acflagtime << VEDC_REG_SHIFT_4;
thedo 166:3a9487d57a5c 416 /* Smoothing parameter of autocorrelation function data */
thedo 166:3a9487d57a5c 417 reg_data |= (uint32_t)p_noise_det->acffilter;
thedo 166:3a9487d57a5c 418
thedo 166:3a9487d57a5c 419 *(vdec_reg->nsdcr) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 420 }
thedo 166:3a9487d57a5c 421 /* Clamp data hold processing (Y, Cb, Cr) OFF */
thedo 166:3a9487d57a5c 422 reg_data = (uint32_t)*(vdec_reg->dcpcr9) & (uint32_t)(~VDEC_REG_MASK_0X1C00);
thedo 166:3a9487d57a5c 423 *(vdec_reg->dcpcr9) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 424
thedo 166:3a9487d57a5c 425 return;
thedo 166:3a9487d57a5c 426 } /* End of function VDEC_DigitalClamp() */
thedo 166:3a9487d57a5c 427
thedo 166:3a9487d57a5c 428 /**************************************************************************//**
thedo 166:3a9487d57a5c 429 * @brief Sets registers for output adjustment
thedo 166:3a9487d57a5c 430 * @param[in] ch : Channel
thedo 166:3a9487d57a5c 431 * @param[in] param : Output adjustment parameter
thedo 166:3a9487d57a5c 432 * @retval None
thedo 166:3a9487d57a5c 433 *****************************************************************************/
thedo 166:3a9487d57a5c 434 void VDEC_Output (const vdec_channel_t ch, const vdec_output_t * const param)
thedo 166:3a9487d57a5c 435 {
thedo 166:3a9487d57a5c 436 const vdec_reg_address_t * vdec_reg;
thedo 166:3a9487d57a5c 437
thedo 166:3a9487d57a5c 438 vdec_reg = &vdec_reg_address[ch];
thedo 166:3a9487d57a5c 439
thedo 166:3a9487d57a5c 440 /* Y, Cb and Cr signal gain coefficient */
thedo 166:3a9487d57a5c 441 *(vdec_reg->ygaincr) = param->y_gain2;
thedo 166:3a9487d57a5c 442 *(vdec_reg->cbgaincr) = param->cb_gain2;
thedo 166:3a9487d57a5c 443 *(vdec_reg->crgaincr) = param->cr_gain2;
thedo 166:3a9487d57a5c 444
thedo 166:3a9487d57a5c 445 return;
thedo 166:3a9487d57a5c 446 } /* End of function VDEC_Output() */
thedo 166:3a9487d57a5c 447
thedo 166:3a9487d57a5c 448 /**************************************************************************//**
thedo 166:3a9487d57a5c 449 * @brief Query VDEC parameters
thedo 166:3a9487d57a5c 450 * @param[in] ch : Channel
thedo 166:3a9487d57a5c 451 * @param[out] q_sync_sep : Sync separation parameters
thedo 166:3a9487d57a5c 452 * @param[out] q_agc : Agc parameters
thedo 166:3a9487d57a5c 453 * @param[out] q_chroma_dec : Chroma decoding parameters
thedo 166:3a9487d57a5c 454 * @param[out] q_digital_clamp : Digital clamp parameters
thedo 166:3a9487d57a5c 455 * @retval None
thedo 166:3a9487d57a5c 456 *****************************************************************************/
thedo 166:3a9487d57a5c 457 void VDEC_Query (
thedo 166:3a9487d57a5c 458 const vdec_channel_t ch,
thedo 166:3a9487d57a5c 459 vdec_q_sync_sep_t * const q_sync_sep,
thedo 166:3a9487d57a5c 460 vdec_q_agc_t * const q_agc,
thedo 166:3a9487d57a5c 461 vdec_q_chroma_dec_t * const q_chroma_dec,
thedo 166:3a9487d57a5c 462 vdec_q_digital_clamp_t * const q_digital_clamp)
thedo 166:3a9487d57a5c 463 {
thedo 166:3a9487d57a5c 464 const vdec_reg_address_t * vdec_reg;
thedo 166:3a9487d57a5c 465 uint32_t reg_value;
thedo 166:3a9487d57a5c 466
thedo 166:3a9487d57a5c 467 vdec_reg = &vdec_reg_address[ch];
thedo 166:3a9487d57a5c 468
thedo 166:3a9487d57a5c 469 /* Sync separation */
thedo 166:3a9487d57a5c 470 if (q_sync_sep != NULL) {
thedo 166:3a9487d57a5c 471 reg_value = (uint32_t)*(vdec_reg->vsyncsr);
thedo 166:3a9487d57a5c 472 /* Horizontal AFC lock detection result */
thedo 166:3a9487d57a5c 473 q_sync_sep->fhlock = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X4000) == 0u) ? VDEC_UNLOCK : VDEC_LOCK;
thedo 166:3a9487d57a5c 474 /* Detection result of low S/N signal by sync separation */
thedo 166:3a9487d57a5c 475 q_sync_sep->isnoisy = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X2000) == 0u) ? VDEC_NO : VDEC_YES;
thedo 166:3a9487d57a5c 476 /* Speed detection result */
thedo 166:3a9487d57a5c 477 q_sync_sep->fhmode = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X1000) == 0u) ? VDEC_FHMD_NORMAL :
thedo 166:3a9487d57a5c 478 VDEC_FHMD_MULTIPLIED;
thedo 166:3a9487d57a5c 479 /* No-signal detection result */
thedo 166:3a9487d57a5c 480 q_sync_sep->nosignal_ = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0800) == 0u) ? VDEC_YES : VDEC_NO;
thedo 166:3a9487d57a5c 481 /* Vertical countdown lock detection result */
thedo 166:3a9487d57a5c 482 q_sync_sep->fvlock = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0400) == 0u) ? VDEC_UNLOCK : VDEC_LOCK;
thedo 166:3a9487d57a5c 483 /* Vertical countdown oscillation mode */
thedo 166:3a9487d57a5c 484 q_sync_sep->fvmode = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0200) == 0u) ? VDEC_FVMD_50HZ :
thedo 166:3a9487d57a5c 485 VDEC_FVMD_60HZ;
thedo 166:3a9487d57a5c 486 /* Interlace detection result */
thedo 166:3a9487d57a5c 487 q_sync_sep->interlaced = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0100) == 0u) ? VDEC_NO : VDEC_YES;
thedo 166:3a9487d57a5c 488 /* Vertical cycle measurement result */
thedo 166:3a9487d57a5c 489 q_sync_sep->fvcount = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X00FF);
thedo 166:3a9487d57a5c 490 /* Horizontal AFC oscillation cycle */
thedo 166:3a9487d57a5c 491 q_sync_sep->fhcount = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X8000) == 0u) ? 0x0000u : (uint32_t)0x0001u;
thedo 166:3a9487d57a5c 492 q_sync_sep->fhcount |= (uint32_t)*(vdec_reg->hsyncsr) << VEDC_REG_SHIFT_1;
thedo 166:3a9487d57a5c 493
thedo 166:3a9487d57a5c 494 reg_value = (uint32_t)*(vdec_reg->syncssr);
thedo 166:3a9487d57a5c 495 /* Sync amplitude detection result during VBI period */
thedo 166:3a9487d57a5c 496 q_sync_sep->isreduced = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X1000) == 0u) ? VDEC_NO : VDEC_YES;
thedo 166:3a9487d57a5c 497 /* Sync pulse amplitude detection result */
thedo 166:3a9487d57a5c 498 q_sync_sep->syncdepth = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X03FF);
thedo 166:3a9487d57a5c 499 }
thedo 166:3a9487d57a5c 500 /* Agc */
thedo 166:3a9487d57a5c 501 if (q_agc != NULL) {
thedo 166:3a9487d57a5c 502 reg_value = (uint32_t)*(vdec_reg->agccsr1);
thedo 166:3a9487d57a5c 503 /* Number of pixels which have larger luminance value than peak luminance limited by peak limiter */
thedo 166:3a9487d57a5c 504 q_agc->highsamples = (uint16_t)(reg_value >> VEDC_REG_SHIFT_8);
thedo 166:3a9487d57a5c 505 /* Number of overflowing pixels */
thedo 166:3a9487d57a5c 506 q_agc->peaksamples = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X00FF);
thedo 166:3a9487d57a5c 507
thedo 166:3a9487d57a5c 508 reg_value = (uint32_t)*(vdec_reg->agccsr2);
thedo 166:3a9487d57a5c 509 /* AGC convergence detection result */
thedo 166:3a9487d57a5c 510 if ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0100) == 0u) {
thedo 166:3a9487d57a5c 511 q_agc->agcconverge = (uint16_t)0x0000u;
thedo 166:3a9487d57a5c 512 } else {
thedo 166:3a9487d57a5c 513 q_agc->agcconverge = (uint16_t)0x0001u;
thedo 166:3a9487d57a5c 514 }
thedo 166:3a9487d57a5c 515 /* Current AGC gain value */
thedo 166:3a9487d57a5c 516 q_agc->agcgain = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X00FF);
thedo 166:3a9487d57a5c 517 }
thedo 166:3a9487d57a5c 518 /* Chroma decoding */
thedo 166:3a9487d57a5c 519 if (q_chroma_dec != NULL) {
thedo 166:3a9487d57a5c 520 reg_value = (uint32_t)*(vdec_reg->cromasr1);
thedo 166:3a9487d57a5c 521 /* Color system detection result */
thedo 166:3a9487d57a5c 522 q_chroma_dec->colorsys = (vdec_color_sys_t)(reg_value >> VEDC_REG_SHIFT_14);
thedo 166:3a9487d57a5c 523 /* Color sub-carrier frequency detection result */
thedo 166:3a9487d57a5c 524 q_chroma_dec->fscmode = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X2000) == 0u) ? VDEC_FSCMD_3_58 :
thedo 166:3a9487d57a5c 525 VDEC_FSCMD_4_43;
thedo 166:3a9487d57a5c 526 /* Burst lock PLL lock state detection result */
thedo 166:3a9487d57a5c 527 q_chroma_dec->fsclock = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X1000) == 0u) ? VDEC_UNLOCK : VDEC_LOCK;
thedo 166:3a9487d57a5c 528 /* Color burst detection result */
thedo 166:3a9487d57a5c 529 q_chroma_dec->noburst_ = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0800) == 0u) ? VDEC_YES : VDEC_NO;
thedo 166:3a9487d57a5c 530 /* Current ACC gain value (sub) */
thedo 166:3a9487d57a5c 531 q_chroma_dec->accsubgain = (vdec_chrm_subgain_t)((reg_value >> VEDC_REG_SHIFT_9) &
thedo 166:3a9487d57a5c 532 (uint32_t)VDEC_REG_MASK_0X0003);
thedo 166:3a9487d57a5c 533 /* Current ACC gain value (main) */
thedo 166:3a9487d57a5c 534 q_chroma_dec->accmaingain = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X01FF);
thedo 166:3a9487d57a5c 535
thedo 166:3a9487d57a5c 536 reg_value = (uint32_t)*(vdec_reg->cromasr2);
thedo 166:3a9487d57a5c 537 /* SECAM detection result */
thedo 166:3a9487d57a5c 538 q_chroma_dec->issecam = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X1000) == 0u) ? VDEC_NO : VDEC_YES;
thedo 166:3a9487d57a5c 539 /* PAL detection result */
thedo 166:3a9487d57a5c 540 q_chroma_dec->ispal = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0800) == 0u) ? VDEC_NO : VDEC_YES;
thedo 166:3a9487d57a5c 541 /* NTSC detection result */
thedo 166:3a9487d57a5c 542 q_chroma_dec->isntsc = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0400) == 0u) ? VDEC_NO : VDEC_YES;
thedo 166:3a9487d57a5c 543 /* Low S/N signal detection result by burst lock PLL */
thedo 166:3a9487d57a5c 544 q_chroma_dec->locklevel = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X00FF);
thedo 166:3a9487d57a5c 545 }
thedo 166:3a9487d57a5c 546 /* Digital clamp */
thedo 166:3a9487d57a5c 547 if (q_digital_clamp != NULL) {
thedo 166:3a9487d57a5c 548 reg_value = (uint32_t)*(vdec_reg->dcpsr1);
thedo 166:3a9487d57a5c 549 /* Digital clamp subtraction value (Cb signal) */
thedo 166:3a9487d57a5c 550 q_digital_clamp->clamplevel_cb = (uint16_t)(reg_value >> VEDC_REG_SHIFT_10);
thedo 166:3a9487d57a5c 551 /* Digital clamp subtraction value (Y signal) */
thedo 166:3a9487d57a5c 552 q_digital_clamp->clamplevel_y = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X03FF);
thedo 166:3a9487d57a5c 553
thedo 166:3a9487d57a5c 554 /* Digital clamp subtraction value (Cr signal) */
thedo 166:3a9487d57a5c 555 q_digital_clamp->clamplevel_cr = (uint16_t)((uint32_t)*(vdec_reg->dcpsr2) >> VEDC_REG_SHIFT_10);
thedo 166:3a9487d57a5c 556
thedo 166:3a9487d57a5c 557 /* Noise autocorrelation strength at digital clamp pulse position */
thedo 166:3a9487d57a5c 558 q_digital_clamp->acfstrength = *(vdec_reg->nsdsr);
thedo 166:3a9487d57a5c 559 }
thedo 166:3a9487d57a5c 560 return;
thedo 166:3a9487d57a5c 561 } /* End of function VDEC_Query() */
thedo 166:3a9487d57a5c 562
thedo 166:3a9487d57a5c 563 /**************************************************************************//**
thedo 166:3a9487d57a5c 564 * @brief Sets registers for noise reduction LPF
thedo 166:3a9487d57a5c 565 * @param[in] vdec_reg : VDEC registers
thedo 166:3a9487d57a5c 566 * @param[in] p_noise_rd_lpf : Noise reduction LPF parameter
thedo 166:3a9487d57a5c 567 * @retval None
thedo 166:3a9487d57a5c 568 *****************************************************************************/
thedo 166:3a9487d57a5c 569 static void NoiseReductionLPF (
thedo 166:3a9487d57a5c 570 const vdec_reg_address_t * const vdec_reg,
thedo 166:3a9487d57a5c 571 const vdec_noise_rd_lpf_t * const p_noise_rd_lpf)
thedo 166:3a9487d57a5c 572 {
thedo 166:3a9487d57a5c 573 uint32_t reg_data;
thedo 166:3a9487d57a5c 574
thedo 166:3a9487d57a5c 575 /* Noise reduction LPF */
thedo 166:3a9487d57a5c 576 if (p_noise_rd_lpf != NULL) {
thedo 166:3a9487d57a5c 577 reg_data = (uint32_t)*(vdec_reg->synscr1) & (uint32_t)(~VDEC_REG_MASK_0XFC00);
thedo 166:3a9487d57a5c 578 /* LPF cutoff frequency before vertical sync separation */
thedo 166:3a9487d57a5c 579 reg_data |= (uint32_t)p_noise_rd_lpf->lpfvsync << VEDC_REG_SHIFT_13;
thedo 166:3a9487d57a5c 580 /* LPF cutoff frequency before horizontal sync separation */
thedo 166:3a9487d57a5c 581 reg_data |= (uint32_t)p_noise_rd_lpf->lpfhsync << VEDC_REG_SHIFT_10;
thedo 166:3a9487d57a5c 582
thedo 166:3a9487d57a5c 583 *(vdec_reg->synscr1) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 584 }
thedo 166:3a9487d57a5c 585 return;
thedo 166:3a9487d57a5c 586 } /* End of function NoiseReductionLPF() */
thedo 166:3a9487d57a5c 587
thedo 166:3a9487d57a5c 588 /**************************************************************************//**
thedo 166:3a9487d57a5c 589 * @brief Sets registers for auto level control sync slicer
thedo 166:3a9487d57a5c 590 * @param[in] vdec_reg : VDEC registers
thedo 166:3a9487d57a5c 591 * @param[in] p_sync_slicer : Auto level control sync slicer parameter
thedo 166:3a9487d57a5c 592 * @retval None
thedo 166:3a9487d57a5c 593 *****************************************************************************/
thedo 166:3a9487d57a5c 594 static void SyncSlicer (const vdec_reg_address_t * const vdec_reg, const vdec_sync_slicer_t * const p_sync_slicer)
thedo 166:3a9487d57a5c 595 {
thedo 166:3a9487d57a5c 596 uint32_t reg_data;
thedo 166:3a9487d57a5c 597
thedo 166:3a9487d57a5c 598 /* Auto level control sync slicer */
thedo 166:3a9487d57a5c 599 if (p_sync_slicer != NULL) {
thedo 166:3a9487d57a5c 600 reg_data = (uint32_t)*(vdec_reg->synscr1) & (uint32_t)(~VDEC_REG_MASK_0X00FF);
thedo 166:3a9487d57a5c 601 /* Reference level operation speed control for composite sync separation (for Hsync signal) */
thedo 166:3a9487d57a5c 602 reg_data |= (uint32_t)p_sync_slicer->velocityshift_h << VEDC_REG_SHIFT_4;
thedo 166:3a9487d57a5c 603 /* Auto-slice level setting for composite sync separation circuit (for Hsync signal) */
thedo 166:3a9487d57a5c 604 reg_data |= (uint32_t)p_sync_slicer->slicermode_h << VEDC_REG_SHIFT_2;
thedo 166:3a9487d57a5c 605 /* Auto-slice level setting for composite sync separation circuit (for Vsync signal) */
thedo 166:3a9487d57a5c 606 reg_data |= (uint32_t)p_sync_slicer->slicermode_v;
thedo 166:3a9487d57a5c 607
thedo 166:3a9487d57a5c 608 *(vdec_reg->synscr1) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 609
thedo 166:3a9487d57a5c 610 /* Max ratio of horizontal cycle to horizontal sync signal pulse width
thedo 166:3a9487d57a5c 611 and min ratio of horizontal cycle to horizontal sync signal pulse width (for Hsync signal) */
thedo 166:3a9487d57a5c 612 reg_data = (uint32_t)p_sync_slicer->syncmaxduty_h << VEDC_REG_SHIFT_6;
thedo 166:3a9487d57a5c 613 reg_data |= (uint32_t)p_sync_slicer->syncminduty_h;
thedo 166:3a9487d57a5c 614
thedo 166:3a9487d57a5c 615 *(vdec_reg->synscr2) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 616
thedo 166:3a9487d57a5c 617 /* Clipping level and slice level for composite sync signal separation (for Hsync signal) */
thedo 166:3a9487d57a5c 618 reg_data = (uint32_t)p_sync_slicer->ssclipsel << VEDC_REG_SHIFT_10;
thedo 166:3a9487d57a5c 619 reg_data |= (uint32_t)p_sync_slicer->csyncslice_h;
thedo 166:3a9487d57a5c 620
thedo 166:3a9487d57a5c 621 *(vdec_reg->synscr3) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 622
thedo 166:3a9487d57a5c 623 /* Max ratio of horizontal cycle to horizontal sync signal pulse width
thedo 166:3a9487d57a5c 624 and min ratio of horizontal cycle to horizontal sync signal pulse width (for Vsync signal) */
thedo 166:3a9487d57a5c 625 reg_data = (uint32_t)p_sync_slicer->syncmaxduty_v << VEDC_REG_SHIFT_6;
thedo 166:3a9487d57a5c 626 reg_data |= (uint32_t)p_sync_slicer->syncminduty_v;
thedo 166:3a9487d57a5c 627
thedo 166:3a9487d57a5c 628 *(vdec_reg->synscr4) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 629
thedo 166:3a9487d57a5c 630 /* Delays the separated vertical sync signal for 1/4 horizontal cycle */
thedo 166:3a9487d57a5c 631 reg_data = (p_sync_slicer->vsyncdelay == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X8000;
thedo 166:3a9487d57a5c 632 /* Threshold for vertical sync separation */
thedo 166:3a9487d57a5c 633 reg_data |= (uint32_t)p_sync_slicer->vsyncslice << VEDC_REG_SHIFT_10;
thedo 166:3a9487d57a5c 634 /* Slice level for composite sync signal separation (for Vsync signal) */
thedo 166:3a9487d57a5c 635 reg_data |= (uint32_t)p_sync_slicer->csyncslice_v;
thedo 166:3a9487d57a5c 636
thedo 166:3a9487d57a5c 637 *(vdec_reg->synscr5) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 638 }
thedo 166:3a9487d57a5c 639 return;
thedo 166:3a9487d57a5c 640 } /* End of function SyncSlicer() */
thedo 166:3a9487d57a5c 641
thedo 166:3a9487d57a5c 642 /**************************************************************************//**
thedo 166:3a9487d57a5c 643 * @brief Sets registers for horizontal AFC
thedo 166:3a9487d57a5c 644 * @param[in] vdec_reg : VDEC registers
thedo 166:3a9487d57a5c 645 * @param[in] p_horizontal_afc : Horizontal AFC parameter
thedo 166:3a9487d57a5c 646 * @retval None
thedo 166:3a9487d57a5c 647 *****************************************************************************/
thedo 166:3a9487d57a5c 648 static void HorizontalAFC (
thedo 166:3a9487d57a5c 649 const vdec_reg_address_t * const vdec_reg,
thedo 166:3a9487d57a5c 650 const vdec_horizontal_afc_t * const p_horizontal_afc)
thedo 166:3a9487d57a5c 651 {
thedo 166:3a9487d57a5c 652 uint32_t reg_data;
thedo 166:3a9487d57a5c 653
thedo 166:3a9487d57a5c 654 /* Horizontal AFC */
thedo 166:3a9487d57a5c 655 if (p_horizontal_afc != NULL) {
thedo 166:3a9487d57a5c 656 reg_data = (uint32_t)*(vdec_reg->hafccr1) & (uint32_t)(~VDEC_REG_MASK_0XF3FF);
thedo 166:3a9487d57a5c 657 /* Horizontal AFC loop gain */
thedo 166:3a9487d57a5c 658 reg_data |= (uint32_t)p_horizontal_afc->hafcgain << VEDC_REG_SHIFT_12;
thedo 166:3a9487d57a5c 659 /* Horizontal AFC center oscillation frequency */
thedo 166:3a9487d57a5c 660 reg_data |= (uint32_t)p_horizontal_afc->hafctyp;
thedo 166:3a9487d57a5c 661
thedo 166:3a9487d57a5c 662 *(vdec_reg->hafccr1) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 663
thedo 166:3a9487d57a5c 664 /* Start line of horizontal AFC normal operation
thedo 166:3a9487d57a5c 665 and Horizontal AFC forced double-speed oscillation (DOX2HOSC = 0, auto control) */
thedo 166:3a9487d57a5c 666 reg_data = (uint32_t)p_horizontal_afc->hafcstart << VEDC_REG_SHIFT_12;
thedo 166:3a9487d57a5c 667 /* Disable of horizontal AFC double speed detection */
thedo 166:3a9487d57a5c 668 reg_data |= (p_horizontal_afc->nox2hosc == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0800;
thedo 166:3a9487d57a5c 669 /* Maximum oscillation frequency of horizontal AFC */
thedo 166:3a9487d57a5c 670 reg_data |= (uint32_t)p_horizontal_afc->hafcmax;
thedo 166:3a9487d57a5c 671
thedo 166:3a9487d57a5c 672 *(vdec_reg->hafccr2) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 673
thedo 166:3a9487d57a5c 674 /* End line of horizontal AFC normal operation */
thedo 166:3a9487d57a5c 675 reg_data = (uint32_t)p_horizontal_afc->hafcend << VEDC_REG_SHIFT_12;
thedo 166:3a9487d57a5c 676 /* Horizontal AFC VBI period operating mode */
thedo 166:3a9487d57a5c 677 reg_data |= (uint32_t)p_horizontal_afc->hafcmode << VEDC_REG_SHIFT_10;
thedo 166:3a9487d57a5c 678 /* Min oscillation frequency of horizontal AFC */
thedo 166:3a9487d57a5c 679 reg_data |= (uint32_t)p_horizontal_afc->hafcmin;
thedo 166:3a9487d57a5c 680
thedo 166:3a9487d57a5c 681 *(vdec_reg->hafccr3) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 682
thedo 166:3a9487d57a5c 683 /* Forcible or LOWGAIN control */
thedo 166:3a9487d57a5c 684 reg_data = (p_horizontal_afc->phdet_fix == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0010;
thedo 166:3a9487d57a5c 685 /* Phase comparator feedback adjust for low sync signal lock stability */
thedo 166:3a9487d57a5c 686 reg_data |= (uint32_t)p_horizontal_afc->phdet_div;
thedo 166:3a9487d57a5c 687
thedo 166:3a9487d57a5c 688 *(vdec_reg->afcpfcr) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 689 }
thedo 166:3a9487d57a5c 690 return;
thedo 166:3a9487d57a5c 691 } /* End of function HorizontalAFC() */
thedo 166:3a9487d57a5c 692
thedo 166:3a9487d57a5c 693 /**************************************************************************//**
thedo 166:3a9487d57a5c 694 * @brief Sets registers for vertical count-down
thedo 166:3a9487d57a5c 695 * @param[in] vdec_reg : VDEC registers
thedo 166:3a9487d57a5c 696 * @param[in] p_vcount_down : Vertical count-down parameter
thedo 166:3a9487d57a5c 697 * @retval None
thedo 166:3a9487d57a5c 698 *****************************************************************************/
thedo 166:3a9487d57a5c 699 static void VerticalCountdown (
thedo 166:3a9487d57a5c 700 const vdec_reg_address_t * const vdec_reg,
thedo 166:3a9487d57a5c 701 const vdec_vcount_down_t * const p_vcount_down)
thedo 166:3a9487d57a5c 702 {
thedo 166:3a9487d57a5c 703 uint32_t reg_data;
thedo 166:3a9487d57a5c 704
thedo 166:3a9487d57a5c 705 /* Vertical count-down */
thedo 166:3a9487d57a5c 706 if (p_vcount_down != NULL) {
thedo 166:3a9487d57a5c 707 /* Vertical countdown 50-Hz oscillation mode
thedo 166:3a9487d57a5c 708 and Vertical countdown free-run oscillation mode (VCDFREERUN = OFF) */
thedo 166:3a9487d57a5c 709 reg_data = (p_vcount_down->novcd50_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X4000 : (uint32_t)0x0000u;
thedo 166:3a9487d57a5c 710 /* Vertical countdown 60-Hz (59.94-Hz) oscillation mode */
thedo 166:3a9487d57a5c 711 reg_data |= (p_vcount_down->novcd60_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X2000 : (uint32_t)0x0000u;
thedo 166:3a9487d57a5c 712 /* Vertical countdown center oscillation frequency */
thedo 166:3a9487d57a5c 713 reg_data |= (uint32_t)p_vcount_down->vcddefault << VEDC_REG_SHIFT_11;
thedo 166:3a9487d57a5c 714 /* Vertical countdown sync area */
thedo 166:3a9487d57a5c 715 reg_data |= (uint32_t)p_vcount_down->vcdwindow << VEDC_REG_SHIFT_5;
thedo 166:3a9487d57a5c 716 /* Vertical countdown minimum oscillation frequency */
thedo 166:3a9487d57a5c 717 reg_data |= (uint32_t)p_vcount_down->vcdoffset;
thedo 166:3a9487d57a5c 718
thedo 166:3a9487d57a5c 719 *(vdec_reg->vcdwcr1) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 720 }
thedo 166:3a9487d57a5c 721 return;
thedo 166:3a9487d57a5c 722 } /* End of function VerticalCountdown() */
thedo 166:3a9487d57a5c 723
thedo 166:3a9487d57a5c 724 /**************************************************************************//**
thedo 166:3a9487d57a5c 725 * @brief Sets registers for AGC/PGA
thedo 166:3a9487d57a5c 726 * @param[in] vdec_reg : VDEC registers
thedo 166:3a9487d57a5c 727 * @param[in] p_agc : AGC/PGA parameter
thedo 166:3a9487d57a5c 728 * @retval None
thedo 166:3a9487d57a5c 729 *****************************************************************************/
thedo 166:3a9487d57a5c 730 static void AgcPga (const vdec_reg_address_t * const vdec_reg, const vdec_agc_t * const p_agc)
thedo 166:3a9487d57a5c 731 {
thedo 166:3a9487d57a5c 732 uint32_t reg_data;
thedo 166:3a9487d57a5c 733
thedo 166:3a9487d57a5c 734 /* AGC/PGA */
thedo 166:3a9487d57a5c 735 if (p_agc != NULL) {
thedo 166:3a9487d57a5c 736 /* A/D converter AGC ON/OFF control & PGA switch */
thedo 166:3a9487d57a5c 737 if (p_agc->agcmode == VDEC_OFF) {
thedo 166:3a9487d57a5c 738 reg_data = (uint32_t)*(vdec_reg->pgacr) | (uint32_t)VDEC_REG_SET_0X2000;
thedo 166:3a9487d57a5c 739 *(vdec_reg->pgacr) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 740 *(vdec_reg->adccr1) = (uint16_t)0u;
thedo 166:3a9487d57a5c 741 } else {
thedo 166:3a9487d57a5c 742 *(vdec_reg->adccr1) = (uint16_t)VDEC_REG_SET_0X0100;
thedo 166:3a9487d57a5c 743 reg_data = (uint32_t)*(vdec_reg->pgacr) & (uint32_t)(~VDEC_REG_SET_0X2000);
thedo 166:3a9487d57a5c 744 *(vdec_reg->pgacr) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 745 }
thedo 166:3a9487d57a5c 746 /* PGA gain */
thedo 166:3a9487d57a5c 747 reg_data = (uint32_t)*(vdec_reg->pgacr) & (uint32_t)(~VDEC_REG_MASK_0X1F00);
thedo 166:3a9487d57a5c 748 reg_data |= (uint32_t)p_agc->pga_gain << VEDC_REG_SHIFT_8;
thedo 166:3a9487d57a5c 749
thedo 166:3a9487d57a5c 750 *(vdec_reg->pgacr) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 751
thedo 166:3a9487d57a5c 752 /* PGA register update register */
thedo 166:3a9487d57a5c 753 *(vdec_reg->pga_update) = (uint16_t)1u;
thedo 166:3a9487d57a5c 754
thedo 166:3a9487d57a5c 755 /* Manual control of sync signal amplitude detection during VBI period */
thedo 166:3a9487d57a5c 756 reg_data = (p_agc->doreduce == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X2000;
thedo 166:3a9487d57a5c 757 /* Control of sync signal amplitude detection during VBI period */
thedo 166:3a9487d57a5c 758 reg_data |= (p_agc->noreduce_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X1000 : (uint32_t)0x0000u;
thedo 166:3a9487d57a5c 759 /* AGC response speed */
thedo 166:3a9487d57a5c 760 reg_data |= (uint32_t)p_agc->agcresponse << VEDC_REG_SHIFT_9;
thedo 166:3a9487d57a5c 761 /* Sync signal reference amplitude */
thedo 166:3a9487d57a5c 762 reg_data |= (uint32_t)p_agc->agclevel;
thedo 166:3a9487d57a5c 763
thedo 166:3a9487d57a5c 764 *(vdec_reg->agccr1) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 765
thedo 166:3a9487d57a5c 766 /* AGC gain adjustment accuracy */
thedo 166:3a9487d57a5c 767 reg_data = (uint32_t)*(vdec_reg->agccr2) & (uint32_t)(~VDEC_REG_MASK_0X3F00);
thedo 166:3a9487d57a5c 768 reg_data |= (uint32_t)p_agc->agcprecis << VEDC_REG_SHIFT_8;
thedo 166:3a9487d57a5c 769
thedo 166:3a9487d57a5c 770 *(vdec_reg->agccr2) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 771 }
thedo 166:3a9487d57a5c 772 return;
thedo 166:3a9487d57a5c 773 } /* End of function AgcPga() */
thedo 166:3a9487d57a5c 774
thedo 166:3a9487d57a5c 775 /**************************************************************************//**
thedo 166:3a9487d57a5c 776 * @brief Sets registers for peak limiter control
thedo 166:3a9487d57a5c 777 * @param[in] vdec_reg : VDEC registers
thedo 166:3a9487d57a5c 778 * @param[in] p_peak_limiter : Peak limiter control parameter
thedo 166:3a9487d57a5c 779 * @retval None
thedo 166:3a9487d57a5c 780 *****************************************************************************/
thedo 166:3a9487d57a5c 781 static void PeakLimiterControl (
thedo 166:3a9487d57a5c 782 const vdec_reg_address_t * const vdec_reg,
thedo 166:3a9487d57a5c 783 const vdec_peak_limiter_t * const p_peak_limiter)
thedo 166:3a9487d57a5c 784 {
thedo 166:3a9487d57a5c 785 uint32_t reg_data;
thedo 166:3a9487d57a5c 786
thedo 166:3a9487d57a5c 787 /* Peak limiter control */
thedo 166:3a9487d57a5c 788 if (p_peak_limiter != NULL) {
thedo 166:3a9487d57a5c 789 /* Peak luminance value limited by peak limiter */
thedo 166:3a9487d57a5c 790 reg_data = (uint32_t)p_peak_limiter->peaklevel << VEDC_REG_SHIFT_14;
thedo 166:3a9487d57a5c 791 /* Response speed with peak limiter gain decreased */
thedo 166:3a9487d57a5c 792 reg_data |= (uint32_t)p_peak_limiter->peakattack << VEDC_REG_SHIFT_12;
thedo 166:3a9487d57a5c 793 /* Response speed with peak limiter gain increased */
thedo 166:3a9487d57a5c 794 reg_data |= (uint32_t)p_peak_limiter->peakrelease << VEDC_REG_SHIFT_10;
thedo 166:3a9487d57a5c 795 /* Maximum compression rate of peak limiter */
thedo 166:3a9487d57a5c 796 reg_data |= (uint32_t)p_peak_limiter->peakratio << VEDC_REG_SHIFT_8;
thedo 166:3a9487d57a5c 797 /* Allowable number of overflowing pixels */
thedo 166:3a9487d57a5c 798 reg_data |= (uint32_t)p_peak_limiter->maxpeaksamples;
thedo 166:3a9487d57a5c 799
thedo 166:3a9487d57a5c 800 *(vdec_reg->pklimitcr) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 801 }
thedo 166:3a9487d57a5c 802 return;
thedo 166:3a9487d57a5c 803 } /* End of function PeakLimiterControl() */
thedo 166:3a9487d57a5c 804
thedo 166:3a9487d57a5c 805 /**************************************************************************//**
thedo 166:3a9487d57a5c 806 * @brief Sets registers for over-range control
thedo 166:3a9487d57a5c 807 * @param[in] vdec_reg : VDEC registers
thedo 166:3a9487d57a5c 808 * @param[in] p_over_range : Over-range control parameter
thedo 166:3a9487d57a5c 809 * @retval None
thedo 166:3a9487d57a5c 810 *****************************************************************************/
thedo 166:3a9487d57a5c 811 static void OverRangeControl (const vdec_reg_address_t * const vdec_reg, const vdec_over_range_t * const p_over_range)
thedo 166:3a9487d57a5c 812 {
thedo 166:3a9487d57a5c 813 uint32_t reg_data;
thedo 166:3a9487d57a5c 814
thedo 166:3a9487d57a5c 815 /* Over-range control */
thedo 166:3a9487d57a5c 816 if (p_over_range != NULL) {
thedo 166:3a9487d57a5c 817 /* A/D over-threshold level (between levels 0 and 1) */
thedo 166:3a9487d57a5c 818 *(vdec_reg->rgorcr1) = p_over_range->radj_o_level0;
thedo 166:3a9487d57a5c 819 /* A/D under-threshold level (between levels 2 and 3) */
thedo 166:3a9487d57a5c 820 *(vdec_reg->rgorcr2) = p_over_range->radj_u_level0;
thedo 166:3a9487d57a5c 821 /* A/D over-threshold level (between levels 1 and 2) */
thedo 166:3a9487d57a5c 822 *(vdec_reg->rgorcr3) = p_over_range->radj_o_level1;
thedo 166:3a9487d57a5c 823 /* A/D under-threshold level (between levels 1 and 2) */
thedo 166:3a9487d57a5c 824 *(vdec_reg->rgorcr4) = p_over_range->radj_u_level1;
thedo 166:3a9487d57a5c 825 /* A/D over-threshold level (between levels 2 and 3) */
thedo 166:3a9487d57a5c 826 *(vdec_reg->rgorcr5) = p_over_range->radj_o_level2;
thedo 166:3a9487d57a5c 827 /* A/D under-threshold level (between levels 0 and 1) */
thedo 166:3a9487d57a5c 828 *(vdec_reg->rgorcr6) = p_over_range->radj_u_level2;
thedo 166:3a9487d57a5c 829
thedo 166:3a9487d57a5c 830 reg_data = (uint32_t)*(vdec_reg->rgorcr7) & (uint32_t)(~VDEC_REG_MASK_0X0007);
thedo 166:3a9487d57a5c 831 /* Over-range detection enable */
thedo 166:3a9487d57a5c 832 reg_data |= (p_over_range->ucmp_sw == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0004;
thedo 166:3a9487d57a5c 833 /* Under-range detection enable */
thedo 166:3a9487d57a5c 834 reg_data |= (p_over_range->dcmp_sw == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0002;
thedo 166:3a9487d57a5c 835 /* Horizontal enlargement of over/under-range level */
thedo 166:3a9487d57a5c 836 reg_data |= (p_over_range->hwide_sw == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)0x0001u;
thedo 166:3a9487d57a5c 837
thedo 166:3a9487d57a5c 838 *(vdec_reg->rgorcr7) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 839 }
thedo 166:3a9487d57a5c 840 return;
thedo 166:3a9487d57a5c 841 } /* End of function OverRangeControl() */
thedo 166:3a9487d57a5c 842
thedo 166:3a9487d57a5c 843 /**************************************************************************//**
thedo 166:3a9487d57a5c 844 * @brief Sets registers for Y/C separation control
thedo 166:3a9487d57a5c 845 * @param[in] vdec_reg : VDEC registers
thedo 166:3a9487d57a5c 846 * @param[in] p_yc_sep_ctrl : Y/C separation control parameter
thedo 166:3a9487d57a5c 847 * @retval None
thedo 166:3a9487d57a5c 848 *****************************************************************************/
thedo 166:3a9487d57a5c 849 static void YcSeparationControl (
thedo 166:3a9487d57a5c 850 const vdec_reg_address_t * const vdec_reg,
thedo 166:3a9487d57a5c 851 const vdec_yc_sep_ctrl_t * const p_yc_sep_ctrl)
thedo 166:3a9487d57a5c 852 {
thedo 166:3a9487d57a5c 853 uint32_t reg_data;
thedo 166:3a9487d57a5c 854
thedo 166:3a9487d57a5c 855 /* Y/C separation control */
thedo 166:3a9487d57a5c 856 if (p_yc_sep_ctrl != NULL) {
thedo 166:3a9487d57a5c 857 /* Two-dimensional Y/C separation filter select coefficient (K15, K13, and K11) */
thedo 166:3a9487d57a5c 858 reg_data = (uint32_t)p_yc_sep_ctrl->k15 << VEDC_REG_SHIFT_12;
thedo 166:3a9487d57a5c 859 reg_data |= (uint32_t)p_yc_sep_ctrl->k13 << VEDC_REG_SHIFT_6;
thedo 166:3a9487d57a5c 860 reg_data |= (uint32_t)p_yc_sep_ctrl->k11;
thedo 166:3a9487d57a5c 861
thedo 166:3a9487d57a5c 862 *(vdec_reg->ycscr3) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 863
thedo 166:3a9487d57a5c 864 /* Two-dimensional Y/C separation filter select coefficient (K16, K14, and K12) */
thedo 166:3a9487d57a5c 865 reg_data = (uint32_t)p_yc_sep_ctrl->k16 << VEDC_REG_SHIFT_12;
thedo 166:3a9487d57a5c 866 reg_data |= (uint32_t)p_yc_sep_ctrl->k14 << VEDC_REG_SHIFT_6;
thedo 166:3a9487d57a5c 867 reg_data |= (uint32_t)p_yc_sep_ctrl->k12;
thedo 166:3a9487d57a5c 868
thedo 166:3a9487d57a5c 869 *(vdec_reg->ycscr4) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 870
thedo 166:3a9487d57a5c 871 /* Two-dimensional Y/C separation filter select coefficient (K22A and K21A) */
thedo 166:3a9487d57a5c 872 reg_data = (uint32_t)p_yc_sep_ctrl->k22a << VEDC_REG_SHIFT_8;
thedo 166:3a9487d57a5c 873 reg_data |= (uint32_t)p_yc_sep_ctrl->k21a;
thedo 166:3a9487d57a5c 874
thedo 166:3a9487d57a5c 875 *(vdec_reg->ycscr5) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 876
thedo 166:3a9487d57a5c 877 /* Two-dimensional Y/C separation filter select coefficient (K22B and K21B) */
thedo 166:3a9487d57a5c 878 reg_data = (uint32_t)p_yc_sep_ctrl->k22b << VEDC_REG_SHIFT_8;
thedo 166:3a9487d57a5c 879 reg_data |= (uint32_t)p_yc_sep_ctrl->k21b;
thedo 166:3a9487d57a5c 880
thedo 166:3a9487d57a5c 881 *(vdec_reg->ycscr6) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 882
thedo 166:3a9487d57a5c 883 /* Two-dimensional Y/C separation filter select coefficient (K23B, K23A, and K24) */
thedo 166:3a9487d57a5c 884 reg_data = (uint32_t)*(vdec_reg->ycscr7) & (uint32_t)(~VDEC_REG_MASK_0XFF1F);
thedo 166:3a9487d57a5c 885 reg_data |= (uint32_t)p_yc_sep_ctrl->k23b << VEDC_REG_SHIFT_12;
thedo 166:3a9487d57a5c 886 reg_data |= (uint32_t)p_yc_sep_ctrl->k23a << VEDC_REG_SHIFT_8;
thedo 166:3a9487d57a5c 887 reg_data |= (uint32_t)p_yc_sep_ctrl->k24;
thedo 166:3a9487d57a5c 888
thedo 166:3a9487d57a5c 889 *(vdec_reg->ycscr7) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 890
thedo 166:3a9487d57a5c 891 reg_data = (uint32_t)*(vdec_reg->ycscr8) & (uint32_t)(~VDEC_REG_MASK_0XF800);
thedo 166:3a9487d57a5c 892 /* Latter-stage horizontal BPF select */
thedo 166:3a9487d57a5c 893 reg_data |= (p_yc_sep_ctrl->hbpf_narrow == VDEC_LSTG_BPFSEL_BYPASS) ? (uint32_t)0x0000u :
thedo 166:3a9487d57a5c 894 (uint32_t)VDEC_REG_SET_0X8000;
thedo 166:3a9487d57a5c 895 /* Latter-stage horizontal/vertical BPF select */
thedo 166:3a9487d57a5c 896 reg_data |= (p_yc_sep_ctrl->hvbpf_narrow == VDEC_LSTG_BPFSEL_BYPASS) ? (uint32_t)0x0000u :
thedo 166:3a9487d57a5c 897 (uint32_t)VDEC_REG_SET_0X4000;
thedo 166:3a9487d57a5c 898 /* Former-stage horizontal BPF select */
thedo 166:3a9487d57a5c 899 reg_data |= (p_yc_sep_ctrl->hbpf1_9tap_on == VDEC_FSTG_BPFSEL_17TAP) ? (uint32_t)0x0000u :
thedo 166:3a9487d57a5c 900 (uint32_t)VDEC_REG_SET_0X2000;
thedo 166:3a9487d57a5c 901 /* Former-stage horizontal/vertical BPF select */
thedo 166:3a9487d57a5c 902 reg_data |= (p_yc_sep_ctrl->hvbpf1_9tap_on == VDEC_FSTG_BPFSEL_17TAP) ? (uint32_t)0x0000u :
thedo 166:3a9487d57a5c 903 (uint32_t)VDEC_REG_SET_0X1000;
thedo 166:3a9487d57a5c 904 /* Horizontal filter and horizontal/vertical filter bandwidth switch signal */
thedo 166:3a9487d57a5c 905 reg_data |= (p_yc_sep_ctrl->hfil_tap_sel == VDEC_HFIL_TAP_SEL_17TAP) ? (uint32_t)0x0000u :
thedo 166:3a9487d57a5c 906 (uint32_t)VDEC_REG_SET_0X0800;
thedo 166:3a9487d57a5c 907
thedo 166:3a9487d57a5c 908 *(vdec_reg->ycscr8) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 909
thedo 166:3a9487d57a5c 910 /* Two-dimensional filter mixing select */
thedo 166:3a9487d57a5c 911 reg_data = (p_yc_sep_ctrl->det2_on == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X8000;
thedo 166:3a9487d57a5c 912 /* Mixing ratio of signal after passing horizontal filter
thedo 166:3a9487d57a5c 913 to signal after passing former-stage horizontal filter */
thedo 166:3a9487d57a5c 914 reg_data |= (uint32_t)p_yc_sep_ctrl->hsel_mix_y << VEDC_REG_SHIFT_8;
thedo 166:3a9487d57a5c 915 /* Mixing ratio of signal after passing vertical filter
thedo 166:3a9487d57a5c 916 to signal after passing former-stage horizontal/vertical filter */
thedo 166:3a9487d57a5c 917 reg_data |= (uint32_t)p_yc_sep_ctrl->vsel_mix_y << VEDC_REG_SHIFT_4;
thedo 166:3a9487d57a5c 918 /* Mixing ratio of signal after passing horizontal/vertical filter
thedo 166:3a9487d57a5c 919 to signal after passing former-stage horizontal/vertical filter */
thedo 166:3a9487d57a5c 920 reg_data |= (uint32_t)p_yc_sep_ctrl->hvsel_mix_y;
thedo 166:3a9487d57a5c 921
thedo 166:3a9487d57a5c 922 *(vdec_reg->ycscr9) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 923
thedo 166:3a9487d57a5c 924 /* Vertical luminance detection level for correlation detection filter */
thedo 166:3a9487d57a5c 925 reg_data = (uint32_t)*(vdec_reg->ycscr11) & (uint32_t)(~VDEC_REG_MASK_0X01FF);
thedo 166:3a9487d57a5c 926 reg_data |= (uint32_t)p_yc_sep_ctrl->v_y_level;
thedo 166:3a9487d57a5c 927
thedo 166:3a9487d57a5c 928 *(vdec_reg->ycscr11) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 929
thedo 166:3a9487d57a5c 930 if (p_yc_sep_ctrl->det2_on == VDEC_OFF) {
thedo 166:3a9487d57a5c 931 reg_data = ((uint32_t)VDEC_FILMIX_RATIO_0 << VEDC_REG_SHIFT_12) |
thedo 166:3a9487d57a5c 932 ((uint32_t)VDEC_FILMIX_RATIO_0 << VEDC_REG_SHIFT_8);
thedo 166:3a9487d57a5c 933 } else {
thedo 166:3a9487d57a5c 934 /* Mixing ratio of C signal after passing horizontal/vertical adaptive filter
thedo 166:3a9487d57a5c 935 to signal after passing correlation detection filter */
thedo 166:3a9487d57a5c 936 reg_data = (uint32_t)p_yc_sep_ctrl->det2_mix_c << VEDC_REG_SHIFT_12;
thedo 166:3a9487d57a5c 937 /* Mixing ratio of C signal for Y generation after passing
thedo 166:3a9487d57a5c 938 horizontal/vertical adaptive filter to signal after passing correlation */
thedo 166:3a9487d57a5c 939 reg_data |= (uint32_t)p_yc_sep_ctrl->det2_mix_y << VEDC_REG_SHIFT_8;
thedo 166:3a9487d57a5c 940 }
thedo 166:3a9487d57a5c 941 /* Two-dimensional cascade/TAKE-OFF filter mode select */
thedo 166:3a9487d57a5c 942 reg_data |= (uint32_t)p_yc_sep_ctrl->fil2_mode_2d << VEDC_REG_SHIFT_2;
thedo 166:3a9487d57a5c 943 /* Two-dimensional cascade filter select */
thedo 166:3a9487d57a5c 944 reg_data |= (p_yc_sep_ctrl->fil2_narrow_2d == VDEC_2D_FIL_SEL_BYPASS) ? (uint32_t)0x0000u :
thedo 166:3a9487d57a5c 945 (uint32_t)0x0001u;
thedo 166:3a9487d57a5c 946
thedo 166:3a9487d57a5c 947 *(vdec_reg->ycscr12) = (uint16_t)reg_data;
thedo 166:3a9487d57a5c 948 }
thedo 166:3a9487d57a5c 949 return;
thedo 166:3a9487d57a5c 950 } /* End of function YcSeparationControl() */
thedo 166:3a9487d57a5c 951
thedo 166:3a9487d57a5c 952 /**************************************************************************//**
thedo 166:3a9487d57a5c 953 * @brief Sets registers for chroma filter TAP coefficient
thedo 166:3a9487d57a5c 954 * @param[in] fil_reg_address : 2D filter TAP coefficient registers
thedo 166:3a9487d57a5c 955 * @param[in] fil2_2d : Chroma filter TAP coefficient for Y/C separation
thedo 166:3a9487d57a5c 956 * @retval None
thedo 166:3a9487d57a5c 957 *****************************************************************************/
thedo 166:3a9487d57a5c 958 static void FilterTAPsCoefficient (
thedo 166:3a9487d57a5c 959 volatile uint16_t * const * fil_reg_address,
thedo 166:3a9487d57a5c 960 const vdec_chrfil_tap_t * const fil2_2d)
thedo 166:3a9487d57a5c 961 {
thedo 166:3a9487d57a5c 962 int32_t tap_coef;
thedo 166:3a9487d57a5c 963 volatile uint16_t * fil_reg;
thedo 166:3a9487d57a5c 964 const uint16_t * taps;
thedo 166:3a9487d57a5c 965
thedo 166:3a9487d57a5c 966 if (fil2_2d != NULL) {
thedo 166:3a9487d57a5c 967 taps = fil2_2d->fil2_2d_f;
thedo 166:3a9487d57a5c 968 for (tap_coef = 0; tap_coef < VDEC_CHRFIL_TAPCOEF_NUM; tap_coef++) {
thedo 166:3a9487d57a5c 969 fil_reg = *fil_reg_address;
thedo 166:3a9487d57a5c 970 fil_reg_address++;
thedo 166:3a9487d57a5c 971 *fil_reg = *taps;
thedo 166:3a9487d57a5c 972 taps++;
thedo 166:3a9487d57a5c 973 }
thedo 166:3a9487d57a5c 974 }
thedo 166:3a9487d57a5c 975 return;
thedo 166:3a9487d57a5c 976 } /* End of function FilterTAPsCoefficient() */
thedo 166:3a9487d57a5c 977