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Opencv 3.1 project on GR-PEACH board

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GR-PEACH_video/DisplayBace.h@166:3a9487d57a5c, 2017-06-29 (annotated)

Committer:
thedo
Date:
Thu Jun 29 11:00:41 2017 +0000
Revision:
166:3a9487d57a5c
This is Opencv 3.1 project on GR-PEACH board

Who changed what in which revision?

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thedo 166:3a9487d57a5c 1 /*******************************************************************************
thedo 166:3a9487d57a5c 2 * DISCLAIMER
thedo 166:3a9487d57a5c 3 * This software is supplied by Renesas Electronics Corporation and is only
thedo 166:3a9487d57a5c 4 * intended for use with Renesas products. No other uses are authorized. This
thedo 166:3a9487d57a5c 5 * software is owned by Renesas Electronics Corporation and is protected under
thedo 166:3a9487d57a5c 6 * all applicable laws, including copyright laws.
thedo 166:3a9487d57a5c 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
thedo 166:3a9487d57a5c 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
thedo 166:3a9487d57a5c 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
thedo 166:3a9487d57a5c 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
thedo 166:3a9487d57a5c 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
thedo 166:3a9487d57a5c 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
thedo 166:3a9487d57a5c 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
thedo 166:3a9487d57a5c 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
thedo 166:3a9487d57a5c 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
thedo 166:3a9487d57a5c 16 * Renesas reserves the right, without notice, to make changes to this software
thedo 166:3a9487d57a5c 17 * and to discontinue the availability of this software. By using this software,
thedo 166:3a9487d57a5c 18 * you agree to the additional terms and conditions found by accessing the
thedo 166:3a9487d57a5c 19 * following link:
thedo 166:3a9487d57a5c 20 * http://www.renesas.com/disclaimer
thedo 166:3a9487d57a5c 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
thedo 166:3a9487d57a5c 22 *******************************************************************************/
thedo 166:3a9487d57a5c 23 /**************************************************************************//**
thedo 166:3a9487d57a5c 24 * @file DisplayBase.h
thedo 166:3a9487d57a5c 25 * @brief Display driver wrapper class for GR-PEACH
thedo 166:3a9487d57a5c 26 ******************************************************************************/
thedo 166:3a9487d57a5c 27
thedo 166:3a9487d57a5c 28 #ifndef MBED_DISPLAYBASE_H
thedo 166:3a9487d57a5c 29 #define MBED_DISPLAYBASE_H
thedo 166:3a9487d57a5c 30
thedo 166:3a9487d57a5c 31 #include "pinmap.h"
thedo 166:3a9487d57a5c 32
thedo 166:3a9487d57a5c 33 /*! @class DisplayBase
thedo 166:3a9487d57a5c 34 * @brief Display driver wrapper class for GR-PEACH
thedo 166:3a9487d57a5c 35 */
thedo 166:3a9487d57a5c 36 class DisplayBase
thedo 166:3a9487d57a5c 37 {
thedo 166:3a9487d57a5c 38
thedo 166:3a9487d57a5c 39 public:
thedo 166:3a9487d57a5c 40 /*! @enum video_input_channel_t
thedo 166:3a9487d57a5c 41 @brief Video input channel select
thedo 166:3a9487d57a5c 42 */
thedo 166:3a9487d57a5c 43 typedef enum {
thedo 166:3a9487d57a5c 44 VIDEO_INPUT_CHANNEL_0 = 0, /*!< Video input channel 0 */
thedo 166:3a9487d57a5c 45 VIDEO_INPUT_CHANNEL_1 /*!< Video input channel 1 */
thedo 166:3a9487d57a5c 46 } video_input_channel_t;
thedo 166:3a9487d57a5c 47
thedo 166:3a9487d57a5c 48 /*! @enum video_adc_vinsel_t
thedo 166:3a9487d57a5c 49 @brief Input pin control
thedo 166:3a9487d57a5c 50 */
thedo 166:3a9487d57a5c 51 typedef enum {
thedo 166:3a9487d57a5c 52 VIDEO_ADC_VINSEL_VIN1 = 0, /*!< VIN1 input */
thedo 166:3a9487d57a5c 53 VIDEO_ADC_VINSEL_VIN2 /*!< VIN2 input */
thedo 166:3a9487d57a5c 54 } video_adc_vinsel_t;
thedo 166:3a9487d57a5c 55
thedo 166:3a9487d57a5c 56 /*! @enum graphics_layer_t
thedo 166:3a9487d57a5c 57 @brief Graphics layer select
thedo 166:3a9487d57a5c 58 */
thedo 166:3a9487d57a5c 59 typedef enum {
thedo 166:3a9487d57a5c 60 GRAPHICS_LAYER_0 = 0, /*!< Graphics layer 0 */
thedo 166:3a9487d57a5c 61 GRAPHICS_LAYER_1, /*!< Graphics layer 1 */
thedo 166:3a9487d57a5c 62 GRAPHICS_LAYER_2, /*!< Graphics layer 2 */
thedo 166:3a9487d57a5c 63 GRAPHICS_LAYER_3 /*!< Graphics layer 3 */
thedo 166:3a9487d57a5c 64 } graphics_layer_t;
thedo 166:3a9487d57a5c 65
thedo 166:3a9487d57a5c 66 /*! @enum graphics_error_t
thedo 166:3a9487d57a5c 67 @brief Error codes
thedo 166:3a9487d57a5c 68 */
thedo 166:3a9487d57a5c 69 typedef enum {
thedo 166:3a9487d57a5c 70 GRAPHICS_OK = 0, /*!< Normal termination */
thedo 166:3a9487d57a5c 71 GRAPHICS_VDC5_ERR = -1, /*!< VDC5 driver error */
thedo 166:3a9487d57a5c 72 GRAPHICS_FORMA_ERR = -2, /*!< Not support format */
thedo 166:3a9487d57a5c 73 GRAPHICS_LAYER_ERR = -3, /*!< Invalid layer ID error */
thedo 166:3a9487d57a5c 74 GRAPHICS_CHANNLE_ERR = -4, /*!< Invalid channel error */
thedo 166:3a9487d57a5c 75 GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, /*!< Video write size(vw) error */
thedo 166:3a9487d57a5c 76 GRAPHICS_VIDEO_PAL_SIZE_ERR = -6, /*!< Video Write size(vw) error */
thedo 166:3a9487d57a5c 77 GRAPHICS_PARAM_RANGE_ERR = -7 /*!< Parameter range error */
thedo 166:3a9487d57a5c 78 } graphics_error_t;
thedo 166:3a9487d57a5c 79
thedo 166:3a9487d57a5c 80 /*! @enum graphics_format_t
thedo 166:3a9487d57a5c 81 @brief Graphics layer read format selects
thedo 166:3a9487d57a5c 82 */
thedo 166:3a9487d57a5c 83 typedef enum {
thedo 166:3a9487d57a5c 84 GRAPHICS_FORMAT_YCBCR422 = 0, /*!< YCbCr422 (2byte / px) */
thedo 166:3a9487d57a5c 85 GRAPHICS_FORMAT_RGB565, /*!< RGB565 (2byte / px) */
thedo 166:3a9487d57a5c 86 GRAPHICS_FORMAT_RGB888, /*!< RGB888 (4byte / px) */
thedo 166:3a9487d57a5c 87 GRAPHICS_FORMAT_ARGB8888, /*!< ARGB8888 (4byte / px) */
thedo 166:3a9487d57a5c 88 GRAPHICS_FORMAT_ARGB4444 /*!< ARGB4444 (2byte / px) */
thedo 166:3a9487d57a5c 89 } graphics_format_t;
thedo 166:3a9487d57a5c 90
thedo 166:3a9487d57a5c 91 /*! @enum video_format_t
thedo 166:3a9487d57a5c 92 @brief Video writing format selects
thedo 166:3a9487d57a5c 93 */
thedo 166:3a9487d57a5c 94 typedef enum {
thedo 166:3a9487d57a5c 95 VIDEO_FORMAT_YCBCR422 = 0, /*!< YCbCr422 (2byte / px) */
thedo 166:3a9487d57a5c 96 VIDEO_FORMAT_RGB565, /*!< RGB565 (2byte / px) */
thedo 166:3a9487d57a5c 97 VIDEO_FORMAT_RGB888 /*!< RGB888 (4byte / px) */
thedo 166:3a9487d57a5c 98 } video_format_t;
thedo 166:3a9487d57a5c 99
thedo 166:3a9487d57a5c 100 /*! @enum wr_rd_swa_t
thedo 166:3a9487d57a5c 101 @brief Frame buffer swap setting
thedo 166:3a9487d57a5c 102 */
thedo 166:3a9487d57a5c 103 typedef enum {
thedo 166:3a9487d57a5c 104 WR_RD_WRSWA_NON = 0, /*!< Not swapped: 1-2-3-4-5-6-7-8 */
thedo 166:3a9487d57a5c 105 WR_RD_WRSWA_8BIT, /*!< Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
thedo 166:3a9487d57a5c 106 WR_RD_WRSWA_16BIT, /*!< Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
thedo 166:3a9487d57a5c 107 WR_RD_WRSWA_16_8BIT, /*!< Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
thedo 166:3a9487d57a5c 108 WR_RD_WRSWA_32BIT, /*!< Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
thedo 166:3a9487d57a5c 109 WR_RD_WRSWA_32_8BIT, /*!< Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
thedo 166:3a9487d57a5c 110 WR_RD_WRSWA_32_16BIT, /*!< Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
thedo 166:3a9487d57a5c 111 WR_RD_WRSWA_32_16_8BIT, /*!< Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
thedo 166:3a9487d57a5c 112 } wr_rd_swa_t;
thedo 166:3a9487d57a5c 113
thedo 166:3a9487d57a5c 114 /*! @enum lcd_tcon_pin_t
thedo 166:3a9487d57a5c 115 @brief LCD tcon output pin selects
thedo 166:3a9487d57a5c 116 */
thedo 166:3a9487d57a5c 117 typedef enum {
thedo 166:3a9487d57a5c 118 LCD_TCON_PIN_NON = -1, /*!< Not using output */
thedo 166:3a9487d57a5c 119 LCD_TCON_PIN_0, /*!< LCD_TCON0 */
thedo 166:3a9487d57a5c 120 LCD_TCON_PIN_1, /*!< LCD_TCON1 */
thedo 166:3a9487d57a5c 121 LCD_TCON_PIN_2, /*!< LCD_TCON2 */
thedo 166:3a9487d57a5c 122 LCD_TCON_PIN_3, /*!< LCD_TCON3 */
thedo 166:3a9487d57a5c 123 LCD_TCON_PIN_4, /*!< LCD_TCON4 */
thedo 166:3a9487d57a5c 124 } lcd_tcon_pin_t;
thedo 166:3a9487d57a5c 125
thedo 166:3a9487d57a5c 126 /*! @enum lcd_outformat_t
thedo 166:3a9487d57a5c 127 @brief LCD output format selects
thedo 166:3a9487d57a5c 128 */
thedo 166:3a9487d57a5c 129 typedef enum {
thedo 166:3a9487d57a5c 130 LCD_OUTFORMAT_RGB888 = 0, /*!< RGB888 or LVDS */
thedo 166:3a9487d57a5c 131 LCD_OUTFORMAT_RGB666, /*!< RGB666 */
thedo 166:3a9487d57a5c 132 LCD_OUTFORMAT_RGB565 /*!< RGB565 */
thedo 166:3a9487d57a5c 133 } lcd_outformat_t;
thedo 166:3a9487d57a5c 134
thedo 166:3a9487d57a5c 135 /*! @enum edge_t
thedo 166:3a9487d57a5c 136 @brief Edge of a signal
thedo 166:3a9487d57a5c 137 */
thedo 166:3a9487d57a5c 138 typedef enum {
thedo 166:3a9487d57a5c 139 EDGE_RISING = 0, /*!< Rising edge */
thedo 166:3a9487d57a5c 140 EDGE_FALLING = 1 /*!< Falling edge */
thedo 166:3a9487d57a5c 141 } edge_t;
thedo 166:3a9487d57a5c 142
thedo 166:3a9487d57a5c 143 /*! @enum lcd_type_t
thedo 166:3a9487d57a5c 144 @brief LCD type
thedo 166:3a9487d57a5c 145 */
thedo 166:3a9487d57a5c 146 typedef enum {
thedo 166:3a9487d57a5c 147 LCD_TYPE_LVDS = 0, /*!< LVDS control */
thedo 166:3a9487d57a5c 148 LCD_TYPE_PARALLEL_RGB /*!< RGB parallel signal control */
thedo 166:3a9487d57a5c 149 } lcd_type_t;
thedo 166:3a9487d57a5c 150
thedo 166:3a9487d57a5c 151 /*! @enum sig_pol_t
thedo 166:3a9487d57a5c 152 @brief Polarity of a signal
thedo 166:3a9487d57a5c 153 */
thedo 166:3a9487d57a5c 154 typedef enum {
thedo 166:3a9487d57a5c 155 SIG_POL_NOT_INVERTED = 0, /*!< Not inverted */
thedo 166:3a9487d57a5c 156 SIG_POL_INVERTED /*!< Inverted */
thedo 166:3a9487d57a5c 157 } sig_pol_t;
thedo 166:3a9487d57a5c 158
thedo 166:3a9487d57a5c 159 /*! @enum int_type_t
thedo 166:3a9487d57a5c 160 @brief Interrupt type
thedo 166:3a9487d57a5c 161 */
thedo 166:3a9487d57a5c 162 typedef enum {
thedo 166:3a9487d57a5c 163 INT_TYPE_S0_VI_VSYNC = 0, /*!< Vsync signal input to scaler 0 */
thedo 166:3a9487d57a5c 164 INT_TYPE_S0_LO_VSYNC, /*!< Vsync signal output from scaler 0 */
thedo 166:3a9487d57a5c 165 INT_TYPE_S0_VSYNCERR, /*!< Missing Vsync signal for scaler 0 */
thedo 166:3a9487d57a5c 166 INT_TYPE_VLINE, /*!< Specified line signal for panel output in graphics 3 */
thedo 166:3a9487d57a5c 167 INT_TYPE_S0_VFIELD, /*!< Field end signal for recording function in scaler 0 */
thedo 166:3a9487d57a5c 168 INT_TYPE_IV1_VBUFERR, /*!< Frame buffer write overflow signal for scaler 0 */
thedo 166:3a9487d57a5c 169 INT_TYPE_IV3_VBUFERR, /*!< Frame buffer read underflow signal for graphics 0 */
thedo 166:3a9487d57a5c 170 INT_TYPE_IV5_VBUFERR, /*!< Frame buffer read underflow signal for graphics 2 */
thedo 166:3a9487d57a5c 171 INT_TYPE_IV6_VBUFERR, /*!< Frame buffer read underflow signal for graphics 3 */
thedo 166:3a9487d57a5c 172 INT_TYPE_S0_WLINE, /*!< Write specification line signal input to scaling-down control block in scaler 0 */
thedo 166:3a9487d57a5c 173 INT_TYPE_S1_VI_VSYNC, /*!< Vsync signal input to scaler 1 */
thedo 166:3a9487d57a5c 174 INT_TYPE_S1_LO_VSYNC, /*!< Vsync signal output from scaler 1 */
thedo 166:3a9487d57a5c 175 INT_TYPE_S1_VSYNCERR, /*!< Missing Vsync signal for scaler 1 */
thedo 166:3a9487d57a5c 176 INT_TYPE_S1_VFIELD, /*!< Field end signal for recording function in scaler 1 */
thedo 166:3a9487d57a5c 177 INT_TYPE_IV2_VBUFERR, /*!< Frame buffer write overflow signal for scaler 1 */
thedo 166:3a9487d57a5c 178 INT_TYPE_IV4_VBUFERR, /*!< Frame buffer read underflow signal for graphics 1 */
thedo 166:3a9487d57a5c 179 INT_TYPE_S1_WLINE, /*!< Write specification line signal input to scaling-down control block in scaler 1 */
thedo 166:3a9487d57a5c 180 INT_TYPE_OIR_VI_VSYNC, /*!< Vsync signal input to output image generator */
thedo 166:3a9487d57a5c 181 INT_TYPE_OIR_LO_VSYNC, /*!< Vsync signal output from output image generator */
thedo 166:3a9487d57a5c 182 INT_TYPE_OIR_VLINE, /*!< Specified line signal for panel output in output image generator */
thedo 166:3a9487d57a5c 183 INT_TYPE_OIR_VFIELD, /*!< Field end signal for recording function in output image generator */
thedo 166:3a9487d57a5c 184 INT_TYPE_IV7_VBUFERR, /*!< Frame buffer write overflow signal for output image generator */
thedo 166:3a9487d57a5c 185 INT_TYPE_IV8_VBUFERR, /*!< Frame buffer read underflow signal for graphics (OIR) */
thedo 166:3a9487d57a5c 186 INT_TYPE_NUM /*!< The number of VDC5 interrupt types */
thedo 166:3a9487d57a5c 187 } int_type_t;
thedo 166:3a9487d57a5c 188
thedo 166:3a9487d57a5c 189 /*! @enum graphics_video_col_sys_t
thedo 166:3a9487d57a5c 190 @brief Video color system
thedo 166:3a9487d57a5c 191 */
thedo 166:3a9487d57a5c 192 typedef enum {
thedo 166:3a9487d57a5c 193 COL_SYS_NTSC_358 = 0, /*!< NTSC-3.58 */
thedo 166:3a9487d57a5c 194 COL_SYS_NTSC_443 = 1, /*!< NTSC-4.43 */
thedo 166:3a9487d57a5c 195 COL_SYS_PAL_443 = 2, /*!< PAL-4.43 */
thedo 166:3a9487d57a5c 196 COL_SYS_PAL_M = 3, /*!< PAL-M */
thedo 166:3a9487d57a5c 197 COL_SYS_PAL_N = 4, /*!< PAL-N */
thedo 166:3a9487d57a5c 198 COL_SYS_SECAM = 5, /*!< SECAM */
thedo 166:3a9487d57a5c 199 COL_SYS_NTSC_443_60 = 6, /*!< NTSC-4.43 (60Hz) */
thedo 166:3a9487d57a5c 200 COL_SYS_PAL_60 = 7, /*!< PAL-60 */
thedo 166:3a9487d57a5c 201 } graphics_video_col_sys_t;
thedo 166:3a9487d57a5c 202
thedo 166:3a9487d57a5c 203 /*! @enum video_input_sel_t
thedo 166:3a9487d57a5c 204 @brief External Input select
thedo 166:3a9487d57a5c 205 */
thedo 166:3a9487d57a5c 206 typedef enum {
thedo 166:3a9487d57a5c 207 INPUT_SEL_VDEC = 0, /*!< Video decoder output signals */
thedo 166:3a9487d57a5c 208 INPUT_SEL_EXT = 1 /*!< Signals supplied via the external input pins */
thedo 166:3a9487d57a5c 209 } video_input_sel_t;
thedo 166:3a9487d57a5c 210
thedo 166:3a9487d57a5c 211 /*! @enum video_extin_format_t
thedo 166:3a9487d57a5c 212 @brief External input format select
thedo 166:3a9487d57a5c 213 */
thedo 166:3a9487d57a5c 214 typedef enum {
thedo 166:3a9487d57a5c 215 VIDEO_EXTIN_FORMAT_RGB888 = 0, /*!< RGB888 Not support */
thedo 166:3a9487d57a5c 216 VIDEO_EXTIN_FORMAT_RGB666, /*!< RGB666 */
thedo 166:3a9487d57a5c 217 VIDEO_EXTIN_FORMAT_RGB565, /*!< RGB565 */
thedo 166:3a9487d57a5c 218 VIDEO_EXTIN_FORMAT_BT656, /*!< BT6556 */
thedo 166:3a9487d57a5c 219 VIDEO_EXTIN_FORMAT_BT601, /*!< BT6501 */
thedo 166:3a9487d57a5c 220 VIDEO_EXTIN_FORMAT_YCBCR422, /*!< YCbCr422 */
thedo 166:3a9487d57a5c 221 VIDEO_EXTIN_FORMAT_YCBCR444, /*!< YCbCr444 Not support */
thedo 166:3a9487d57a5c 222 } video_extin_format_t;
thedo 166:3a9487d57a5c 223
thedo 166:3a9487d57a5c 224 /*! @enum onoff_t
thedo 166:3a9487d57a5c 225 @brief On/off
thedo 166:3a9487d57a5c 226 */
thedo 166:3a9487d57a5c 227 typedef enum {
thedo 166:3a9487d57a5c 228 OFF = 0, /*!< Off */
thedo 166:3a9487d57a5c 229 ON = 1 /*!< On */
thedo 166:3a9487d57a5c 230 } onoff_t;
thedo 166:3a9487d57a5c 231
thedo 166:3a9487d57a5c 232 /*! @enum extin_input_line_t
thedo 166:3a9487d57a5c 233 @brief Number of lines for BT.656 external input
thedo 166:3a9487d57a5c 234 */
thedo 166:3a9487d57a5c 235 typedef enum {
thedo 166:3a9487d57a5c 236 EXTIN_LINE_525 = 0, /*!< 525 lines */
thedo 166:3a9487d57a5c 237 EXTIN_LINE_625 = 1 /*!< 625 lines */
thedo 166:3a9487d57a5c 238 } extin_input_line_t;
thedo 166:3a9487d57a5c 239
thedo 166:3a9487d57a5c 240 /*! @enum extin_h_pos_t
thedo 166:3a9487d57a5c 241 @brief Y/Cb/Y/Cr data string start timing
thedo 166:3a9487d57a5c 242 */
thedo 166:3a9487d57a5c 243 typedef enum {
thedo 166:3a9487d57a5c 244 EXTIN_H_POS_CBYCRY = 0, /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */
thedo 166:3a9487d57a5c 245 EXTIN_H_POS_YCRYCB, /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */
thedo 166:3a9487d57a5c 246 EXTIN_H_POS_CRYCBY, /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */
thedo 166:3a9487d57a5c 247 EXTIN_H_POS_YCBYCR, /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */
thedo 166:3a9487d57a5c 248 EXTIN_H_POS_NUM
thedo 166:3a9487d57a5c 249 } extin_h_pos_t;
thedo 166:3a9487d57a5c 250
thedo 166:3a9487d57a5c 251 /*! @struct rect_t
thedo 166:3a9487d57a5c 252 @brief The relative position within the graphics display area
thedo 166:3a9487d57a5c 253 */
thedo 166:3a9487d57a5c 254 typedef struct {
thedo 166:3a9487d57a5c 255 unsigned short vs; /*!< Vertical start pos */
thedo 166:3a9487d57a5c 256 unsigned short vw; /*!< Vertical width (height) */
thedo 166:3a9487d57a5c 257 unsigned short hs; /*!< Horizontal start pos */
thedo 166:3a9487d57a5c 258 unsigned short hw; /*!< Horizontal width */
thedo 166:3a9487d57a5c 259 } rect_t;
thedo 166:3a9487d57a5c 260
thedo 166:3a9487d57a5c 261 /*! @struct lcd_config_t
thedo 166:3a9487d57a5c 262 @brief LCD configuration
thedo 166:3a9487d57a5c 263 */
thedo 166:3a9487d57a5c 264 typedef struct {
thedo 166:3a9487d57a5c 265 lcd_type_t lcd_type; /*!< LVDS or Pararel RGB */
thedo 166:3a9487d57a5c 266 double intputClock; /*!< P1 clk [MHz] ex. 66.67f */
thedo 166:3a9487d57a5c 267 double outputClock; /*!< LCD clk [MHz] ex. 33.33f */
thedo 166:3a9487d57a5c 268
thedo 166:3a9487d57a5c 269 lcd_outformat_t lcd_outformat; /*!< Output format select */
thedo 166:3a9487d57a5c 270 edge_t lcd_edge; /*!< Output phase control of LCD_DATA23 to LCD_DATA0 pin */
thedo 166:3a9487d57a5c 271
thedo 166:3a9487d57a5c 272 unsigned short h_toatal_period; /*!< Free-running Hsync period */
thedo 166:3a9487d57a5c 273 unsigned short v_toatal_period; /*!< Free-running Vsync period */
thedo 166:3a9487d57a5c 274 unsigned short h_disp_widht; /*!< LCD display area size, horizontal width */
thedo 166:3a9487d57a5c 275 unsigned short v_disp_widht; /*!< LCD display area size, vertical width */
thedo 166:3a9487d57a5c 276 unsigned short h_back_porch; /*!< LCD display horizontal back porch period */
thedo 166:3a9487d57a5c 277 unsigned short v_back_porch; /*!< LCD display vertical back porch period */
thedo 166:3a9487d57a5c 278
thedo 166:3a9487d57a5c 279 lcd_tcon_pin_t h_sync_port; /*!< TCONn or Not use(-1) */
thedo 166:3a9487d57a5c 280 sig_pol_t h_sync_port_polarity; /*!< Polarity inversion control of signal */
thedo 166:3a9487d57a5c 281 unsigned short h_sync_width; /*!< Hsync width */
thedo 166:3a9487d57a5c 282
thedo 166:3a9487d57a5c 283 lcd_tcon_pin_t v_sync_port; /*!< TCONn or Not use(-1) */
thedo 166:3a9487d57a5c 284 sig_pol_t v_sync_port_polarity; /*!< Polarity inversion control of signal */
thedo 166:3a9487d57a5c 285 unsigned short v_sync_width; /*!< Vsync width */
thedo 166:3a9487d57a5c 286
thedo 166:3a9487d57a5c 287 lcd_tcon_pin_t de_port; /*!< TCONn or Not use(-1) */
thedo 166:3a9487d57a5c 288 sig_pol_t de_port_polarity; /*!< Polarity inversion control of signal */
thedo 166:3a9487d57a5c 289 } lcd_config_t;
thedo 166:3a9487d57a5c 290
thedo 166:3a9487d57a5c 291 /*! @struct video_ext_in_config_t
thedo 166:3a9487d57a5c 292 @brief Digital Video Input configuration
thedo 166:3a9487d57a5c 293 */
thedo 166:3a9487d57a5c 294 typedef struct {
thedo 166:3a9487d57a5c 295 video_extin_format_t inp_format; /*!< External Input Format Select */
thedo 166:3a9487d57a5c 296 edge_t inp_pxd_edge; /*!< Clock Edge Select for Capturing External Input Video Image */
thedo 166:3a9487d57a5c 297 edge_t inp_vs_edge; /*!< Clock Edge Select for Capturing External Input Vsync Signal */
thedo 166:3a9487d57a5c 298 edge_t inp_hs_edge; /*!< Clock Edge Select for Capturing External Input Hsync Signal */
thedo 166:3a9487d57a5c 299 onoff_t inp_endian_on; /*!< External Input B/R Signal Swap On/Off Control */
thedo 166:3a9487d57a5c 300 onoff_t inp_swap_on; /*!< External Input Bit Endian Change On/Off Control */
thedo 166:3a9487d57a5c 301 sig_pol_t inp_vs_inv; /*!< External Input Vsync Signal DV_VSYNC Inversion Control */
thedo 166:3a9487d57a5c 302 sig_pol_t inp_hs_inv; /*!< External Input Hsync Signal DV_HSYNC Inversion Control */
thedo 166:3a9487d57a5c 303 extin_input_line_t inp_f525_625; /*!< Number of lines for BT.656 external input */
thedo 166:3a9487d57a5c 304 extin_h_pos_t inp_h_pos; /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */
thedo 166:3a9487d57a5c 305 unsigned short cap_vs_pos; /*!< Capture start position from Vsync */
thedo 166:3a9487d57a5c 306 unsigned short cap_hs_pos; /*!< Capture start position form Hsync */
thedo 166:3a9487d57a5c 307 unsigned short cap_width; /*!< Capture width */
thedo 166:3a9487d57a5c 308 unsigned short cap_height; /*!< Capture height should be a multiple of 4.*/
thedo 166:3a9487d57a5c 309 } video_ext_in_config_t;
thedo 166:3a9487d57a5c 310
thedo 166:3a9487d57a5c 311 /** Constructor method of display base object
thedo 166:3a9487d57a5c 312 */
thedo 166:3a9487d57a5c 313 DisplayBase( void );
thedo 166:3a9487d57a5c 314
thedo 166:3a9487d57a5c 315 /** Graphics initialization processing<br>
thedo 166:3a9487d57a5c 316 * If not using display, set NULL in parameter.
thedo 166:3a9487d57a5c 317 * @param[in] lcd_config : LCD configuration
thedo 166:3a9487d57a5c 318 * @retval Error code
thedo 166:3a9487d57a5c 319 */
thedo 166:3a9487d57a5c 320 graphics_error_t Graphics_init( lcd_config_t * lcd_config );
thedo 166:3a9487d57a5c 321
thedo 166:3a9487d57a5c 322 /** Graphics Video initialization processing<br>
thedo 166:3a9487d57a5c 323 * If setting INPUT_SEL_VDEC in video_input_sel parameter, set NULL in video_ext_in_config parameter.
thedo 166:3a9487d57a5c 324 * @param[in] video_input_sel : Input select
thedo 166:3a9487d57a5c 325 * @param[in] video_ext_in_config : Video configuration
thedo 166:3a9487d57a5c 326 * @retval error code
thedo 166:3a9487d57a5c 327 */
thedo 166:3a9487d57a5c 328 graphics_error_t Graphics_Video_init( video_input_sel_t video_input_sel, video_ext_in_config_t * video_ext_in_config );
thedo 166:3a9487d57a5c 329
thedo 166:3a9487d57a5c 330 /** LCD output port initialization processing
thedo 166:3a9487d57a5c 331 * @param[in] pin : Pin assign for LCD output
thedo 166:3a9487d57a5c 332 * @param[in] pin_count : Total number of pin assign
thedo 166:3a9487d57a5c 333 * @retval Error code
thedo 166:3a9487d57a5c 334 */
thedo 166:3a9487d57a5c 335 graphics_error_t Graphics_Lcd_Port_Init( PinName *pin, unsigned int pin_count );
thedo 166:3a9487d57a5c 336
thedo 166:3a9487d57a5c 337 /** LVDS output port initialization processing
thedo 166:3a9487d57a5c 338 * @param[in] pin : Pin assign for LVDS output
thedo 166:3a9487d57a5c 339 * @param[in] pin_count : Total number of pin assign
thedo 166:3a9487d57a5c 340 * @retval Error code
thedo 166:3a9487d57a5c 341 */
thedo 166:3a9487d57a5c 342 graphics_error_t Graphics_Lvds_Port_Init( PinName *pin, unsigned int pin_count );
thedo 166:3a9487d57a5c 343
thedo 166:3a9487d57a5c 344 /** Digital video input port initialization processing
thedo 166:3a9487d57a5c 345 * @param[in] pin : Pin assign for digital video input port
thedo 166:3a9487d57a5c 346 * @param[in] pin_count : Total number of pin assign
thedo 166:3a9487d57a5c 347 * @retval Error code
thedo 166:3a9487d57a5c 348 */
thedo 166:3a9487d57a5c 349 graphics_error_t Graphics_Dvinput_Port_Init( PinName *pin, unsigned int pin_count );
thedo 166:3a9487d57a5c 350
thedo 166:3a9487d57a5c 351 /** Interrupt callback setup
thedo 166:3a9487d57a5c 352 * This function performs the following processing:
thedo 166:3a9487d57a5c 353 * - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.<br>
thedo 166:3a9487d57a5c 354 * - Registers the specified interrupt callback function.<br>
thedo 166:3a9487d57a5c 355 * - Disables the interrupt when the pointer to the corresponding interrupt callback function is not specified.<br>
thedo 166:3a9487d57a5c 356 * @param[in] Graphics_Irq_Handler_Set : VDC5 interrupt type
thedo 166:3a9487d57a5c 357 * @param[in] num : Interrupt line number
thedo 166:3a9487d57a5c 358 * @param[in] callback : Interrupt callback function pointer
thedo 166:3a9487d57a5c 359 * @retval Error code
thedo 166:3a9487d57a5c 360 */
thedo 166:3a9487d57a5c 361 graphics_error_t Graphics_Irq_Handler_Set( int_type_t Graphics_Irq_Handler_Set, unsigned short num, void (* callback)(int_type_t) );
thedo 166:3a9487d57a5c 362
thedo 166:3a9487d57a5c 363 /** Start the graphics surface read process
thedo 166:3a9487d57a5c 364 * @param[in] layer_id : Graphics layer ID <br />
thedo 166:3a9487d57a5c 365 * - GRAPHICS_LAYER_0 : Layer 0
thedo 166:3a9487d57a5c 366 * - GRAPHICS_LAYER_1 : Layer 1
thedo 166:3a9487d57a5c 367 * - GRAPHICS_LAYER_2 : Layer 2
thedo 166:3a9487d57a5c 368 * - GRAPHICS_LAYER_3 : Layer 3
thedo 166:3a9487d57a5c 369 * @retval Error code
thedo 166:3a9487d57a5c 370 */
thedo 166:3a9487d57a5c 371 graphics_error_t Graphics_Start( graphics_layer_t layer_id );
thedo 166:3a9487d57a5c 372
thedo 166:3a9487d57a5c 373 /** Stop the graphics surface read process
thedo 166:3a9487d57a5c 374 * @param[in] layer_id : Graphics layer ID <br />
thedo 166:3a9487d57a5c 375 * - GRAPHICS_LAYER_0 : Layer 0
thedo 166:3a9487d57a5c 376 * - GRAPHICS_LAYER_1 : Layer 1
thedo 166:3a9487d57a5c 377 * - GRAPHICS_LAYER_2 : Layer 2
thedo 166:3a9487d57a5c 378 * - GRAPHICS_LAYER_3 : Layer 3
thedo 166:3a9487d57a5c 379 * @retval Error code
thedo 166:3a9487d57a5c 380 */
thedo 166:3a9487d57a5c 381 graphics_error_t Graphics_Stop( graphics_layer_t layer_id );
thedo 166:3a9487d57a5c 382
thedo 166:3a9487d57a5c 383 /** Start the video surface write process
thedo 166:3a9487d57a5c 384 * @param[in] video_input_channel : Video input channel <br />
thedo 166:3a9487d57a5c 385 * - VIDEO_INPUT_CHANNEL_0 : Video channel 0
thedo 166:3a9487d57a5c 386 * - VIDEO_INPUT_CHANNEL_1 : Video channel 1
thedo 166:3a9487d57a5c 387 * @retval Error code
thedo 166:3a9487d57a5c 388 */
thedo 166:3a9487d57a5c 389 graphics_error_t Video_Start ( video_input_channel_t video_input_channel );
thedo 166:3a9487d57a5c 390
thedo 166:3a9487d57a5c 391 /** Stop the video surface write process
thedo 166:3a9487d57a5c 392 * @param[in] video_input_channel : Video input channel <br />
thedo 166:3a9487d57a5c 393 * - VIDEO_INPUT_CHANNEL_0 : Video channel 0
thedo 166:3a9487d57a5c 394 * - VIDEO_INPUT_CHANNEL_1 : Video channel 1
thedo 166:3a9487d57a5c 395 * @retval Error code
thedo 166:3a9487d57a5c 396 */
thedo 166:3a9487d57a5c 397 graphics_error_t Video_Stop ( video_input_channel_t video_input_channel );
thedo 166:3a9487d57a5c 398
thedo 166:3a9487d57a5c 399 /** Graphics surface read process setting
thedo 166:3a9487d57a5c 400 * @param[in] layer_id : Graphics layer ID <br />
thedo 166:3a9487d57a5c 401 * - GRAPHICS_LAYER_0 : Layer 0
thedo 166:3a9487d57a5c 402 * - GRAPHICS_LAYER_1 : Layer 1
thedo 166:3a9487d57a5c 403 * - GRAPHICS_LAYER_2 : Layer 2
thedo 166:3a9487d57a5c 404 * - GRAPHICS_LAYER_3 : Layer 3
thedo 166:3a9487d57a5c 405 * @param[in] framebuff : Base address of the frame buffer(Not set NULL)
thedo 166:3a9487d57a5c 406 * @param[in] fb_stride : Line offset address of the frame buffer[byte] <br />
thedo 166:3a9487d57a5c 407 * Frame buffer stride should be set to a multiple of 32 or 128
thedo 166:3a9487d57a5c 408 * in accordance with the frame buffer burst transfer mode.
thedo 166:3a9487d57a5c 409 * @param[in] gr_format : Format of the frame buffer read signal <br />
thedo 166:3a9487d57a5c 410 * - VIDEO_FORMAT_YCBCR422 : YCBCR422 (2byte/px)
thedo 166:3a9487d57a5c 411 * - VIDEO_FORMAT_RGB565 : RGB565 (2byte/px)
thedo 166:3a9487d57a5c 412 * - VIDEO_FORMAT_RGB888 : RGB888 (4byte/px)
thedo 166:3a9487d57a5c 413 * - VIDEO_FORMAT_ARGB8888 : ARGB8888 (4byte/px)
thedo 166:3a9487d57a5c 414 * @param[in] wr_rd_swa : frame buffer swap setting <br />
thedo 166:3a9487d57a5c 415 * - WR_RD_WRSWA_NON : Not swapped: 1-2-3-4-5-6-7-8
thedo 166:3a9487d57a5c 416 * - WR_RD_WRSWA_8BIT : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
thedo 166:3a9487d57a5c 417 * - WR_RD_WRSWA_16BIT : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
thedo 166:3a9487d57a5c 418 * - WR_RD_WRSWA_16_8BIT : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
thedo 166:3a9487d57a5c 419 * - WR_RD_WRSWA_32BIT : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
thedo 166:3a9487d57a5c 420 * - WR_RD_WRSWA_32_8BIT : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
thedo 166:3a9487d57a5c 421 * - WR_RD_WRSWA_32_16BIT : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
thedo 166:3a9487d57a5c 422 * - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
thedo 166:3a9487d57a5c 423 * @param[in] gr_rect : Graphics display area
thedo 166:3a9487d57a5c 424 * @retval Error code
thedo 166:3a9487d57a5c 425 */
thedo 166:3a9487d57a5c 426 graphics_error_t Graphics_Read_Setting (
thedo 166:3a9487d57a5c 427 graphics_layer_t layer_id,
thedo 166:3a9487d57a5c 428 void * framebuff,
thedo 166:3a9487d57a5c 429 unsigned int fb_stride,
thedo 166:3a9487d57a5c 430 graphics_format_t gr_format,
thedo 166:3a9487d57a5c 431 wr_rd_swa_t wr_rd_swa,
thedo 166:3a9487d57a5c 432 rect_t * gr_rect );
thedo 166:3a9487d57a5c 433
thedo 166:3a9487d57a5c 434 /** Graphics surface read buffer change process
thedo 166:3a9487d57a5c 435 * @param[in] layer_id : Graphics layer ID <br />
thedo 166:3a9487d57a5c 436 * - GRAPHICS_LAYER_0 : Layer 0
thedo 166:3a9487d57a5c 437 * - GRAPHICS_LAYER_1 : Layer 1
thedo 166:3a9487d57a5c 438 * - GRAPHICS_LAYER_2 : Layer 2
thedo 166:3a9487d57a5c 439 * - GRAPHICS_LAYER_3 : Layer 3
thedo 166:3a9487d57a5c 440 * @param[in] framebuff : Base address of the frame buffer(Not set NULL)
thedo 166:3a9487d57a5c 441 * @retval Error code
thedo 166:3a9487d57a5c 442 */
thedo 166:3a9487d57a5c 443 graphics_error_t Graphics_Read_Change (
thedo 166:3a9487d57a5c 444 graphics_layer_t layer_id,
thedo 166:3a9487d57a5c 445 void * framebuff);
thedo 166:3a9487d57a5c 446
thedo 166:3a9487d57a5c 447 /** Video surface write process setting
thedo 166:3a9487d57a5c 448 * @param[in] video_input_channel : Video input channel <br />
thedo 166:3a9487d57a5c 449 * If using digital input, this parameter is not referenced. <br />
thedo 166:3a9487d57a5c 450 * - VIDEO_INPUT_CHANNEL_0 : Video channel 0
thedo 166:3a9487d57a5c 451 * - VIDEO_INPUT_CHANNEL_1 : Video channel 1
thedo 166:3a9487d57a5c 452 * @param[in] col_sys : Analog video signal color system <br />
thedo 166:3a9487d57a5c 453 * If using digital input, this parameter is not referenced. <br />
thedo 166:3a9487d57a5c 454 * - COL_SYS_NTSC_358 : NTSC-3.58
thedo 166:3a9487d57a5c 455 * - COL_SYS_NTSC_443 : NTSC-4.43
thedo 166:3a9487d57a5c 456 * - COL_SYS_PAL_443 : PAL-4.43
thedo 166:3a9487d57a5c 457 * - COL_SYS_PAL_M : PAL-M
thedo 166:3a9487d57a5c 458 * - COL_SYS_PAL_N : PAL-N
thedo 166:3a9487d57a5c 459 * - COL_SYS_SECAM : SECAM
thedo 166:3a9487d57a5c 460 * - COL_SYS_NTSC_443_60 : NTSC-4.43 (60Hz)
thedo 166:3a9487d57a5c 461 * - COL_SYS_PAL_60 : PAL-60
thedo 166:3a9487d57a5c 462 * @param[in] framebuff : Base address of the frame buffer(Not set NULL)
thedo 166:3a9487d57a5c 463 * @param[in] fb_stride : Line offset address of the frame buffer[byte] <br />
thedo 166:3a9487d57a5c 464 * Frame buffer stride should be set to a multiple of 32 or 128
thedo 166:3a9487d57a5c 465 * in accordance with the frame buffer burst transfer mode.
thedo 166:3a9487d57a5c 466 * @param[in] video_format : Frame buffer video-signal writing format <br />
thedo 166:3a9487d57a5c 467 * - VIDEO_FORMAT_YCBCR422 : YCBCR422 (2byte/px)
thedo 166:3a9487d57a5c 468 * - VIDEO_FORMAT_RGB565 : RGB565 (2byte/px)
thedo 166:3a9487d57a5c 469 * - VIDEO_FORMAT_RGB888 : RGB888 (4byte/px)
thedo 166:3a9487d57a5c 470 * @param[in] wr_rd_swa : frame buffer swap setting <br />
thedo 166:3a9487d57a5c 471 * - WR_RD_WRSWA_NON : Not swapped: 1-2-3-4-5-6-7-8
thedo 166:3a9487d57a5c 472 * - WR_RD_WRSWA_8BIT : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
thedo 166:3a9487d57a5c 473 * - WR_RD_WRSWA_16BIT : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
thedo 166:3a9487d57a5c 474 * - WR_RD_WRSWA_16_8BIT : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
thedo 166:3a9487d57a5c 475 * - WR_RD_WRSWA_32BIT : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
thedo 166:3a9487d57a5c 476 * - WR_RD_WRSWA_32_8BIT : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
thedo 166:3a9487d57a5c 477 * - WR_RD_WRSWA_32_16BIT : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
thedo 166:3a9487d57a5c 478 * - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
thedo 166:3a9487d57a5c 479 * @param[in] video_write_buff_vw : Output height[px] <br />
thedo 166:3a9487d57a5c 480 * - NTSC format : Max height is 480[px]
thedo 166:3a9487d57a5c 481 * - PAL format : Max height is 520[px]
thedo 166:3a9487d57a5c 482 * @param[in] video_write_buff_hw : Output width[px] <br />
thedo 166:3a9487d57a5c 483 * - Max width : 800[px]
thedo 166:3a9487d57a5c 484 * @param[in] video_adc_vinsel : Input pin control <br />
thedo 166:3a9487d57a5c 485 * - VIDEO_ADC_VINSEL_VIN1 : VIN1 input
thedo 166:3a9487d57a5c 486 * - VIDEO_ADC_VINSEL_VIN2 : VIN2 input
thedo 166:3a9487d57a5c 487 * @retval Error code
thedo 166:3a9487d57a5c 488 */
thedo 166:3a9487d57a5c 489 graphics_error_t Video_Write_Setting (
thedo 166:3a9487d57a5c 490 video_input_channel_t video_input_channel,
thedo 166:3a9487d57a5c 491 graphics_video_col_sys_t col_sys,
thedo 166:3a9487d57a5c 492 void * framebuff,
thedo 166:3a9487d57a5c 493 unsigned int fb_stride,
thedo 166:3a9487d57a5c 494 video_format_t video_format,
thedo 166:3a9487d57a5c 495 wr_rd_swa_t wr_rd_swa,
thedo 166:3a9487d57a5c 496 unsigned short video_write_buff_vw,
thedo 166:3a9487d57a5c 497 unsigned short video_write_buff_hw,
thedo 166:3a9487d57a5c 498 video_adc_vinsel_t video_adc_vinsel = VIDEO_ADC_VINSEL_VIN1 );
thedo 166:3a9487d57a5c 499
thedo 166:3a9487d57a5c 500 /** Video surface write buffer change process
thedo 166:3a9487d57a5c 501 * @param[in] video_input_channel : Video input channel <br />
thedo 166:3a9487d57a5c 502 * - VIDEO_INPUT_CHANNEL_0 : Video channel 0
thedo 166:3a9487d57a5c 503 * - VIDEO_INPUT_CHANNEL_1 : Video channel 1
thedo 166:3a9487d57a5c 504 * @param[in] framebuff : Base address of the frame buffer(Not set NULL)
thedo 166:3a9487d57a5c 505 * @param[in] fb_stride : Line offset address of the frame buffer <br />
thedo 166:3a9487d57a5c 506 * Frame buffer stride should be set to a multiple of 32 or 128
thedo 166:3a9487d57a5c 507 * in accordance with the frame buffer burst transfer mode.
thedo 166:3a9487d57a5c 508 * @retval Error code
thedo 166:3a9487d57a5c 509 */
thedo 166:3a9487d57a5c 510 graphics_error_t Video_Write_Change (
thedo 166:3a9487d57a5c 511 video_input_channel_t video_input_channel,
thedo 166:3a9487d57a5c 512 void * framebuff,
thedo 166:3a9487d57a5c 513 uint32_t fb_stride );
thedo 166:3a9487d57a5c 514
thedo 166:3a9487d57a5c 515 protected:
thedo 166:3a9487d57a5c 516 lcd_config_t _lcd_config;
thedo 166:3a9487d57a5c 517 video_input_sel_t _video_input_sel;
thedo 166:3a9487d57a5c 518 video_ext_in_config_t _video_ext_in_config;
thedo 166:3a9487d57a5c 519 };
thedo 166:3a9487d57a5c 520
thedo 166:3a9487d57a5c 521
thedo 166:3a9487d57a5c 522 #endif /* MBED_DISPLAYBASE_H */