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cmsis/core_cm7.h@152:9a67f0b066fc, 2016-12-15 (annotated)
- Committer:
- <>
- Date:
- Thu Dec 15 11:48:27 2016 +0000
- Revision:
- 152:9a67f0b066fc
- Parent:
- 150:02e0a0aed4ec
This updates the lib to the mbed lib v131
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /**************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 2 | * @file core_cm7.h |
<> | 144:ef7eb2e8f9f7 | 3 | * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File |
<> | 144:ef7eb2e8f9f7 | 4 | * @version V4.10 |
<> | 144:ef7eb2e8f9f7 | 5 | * @date 18. March 2015 |
<> | 144:ef7eb2e8f9f7 | 6 | * |
<> | 144:ef7eb2e8f9f7 | 7 | * @note |
<> | 144:ef7eb2e8f9f7 | 8 | * |
<> | 144:ef7eb2e8f9f7 | 9 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 10 | /* Copyright (c) 2009 - 2015 ARM LIMITED |
<> | 144:ef7eb2e8f9f7 | 11 | |
<> | 144:ef7eb2e8f9f7 | 12 | All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 13 | Redistribution and use in source and binary forms, with or without |
<> | 144:ef7eb2e8f9f7 | 14 | modification, are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 15 | - Redistributions of source code must retain the above copyright |
<> | 144:ef7eb2e8f9f7 | 16 | notice, this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 17 | - Redistributions in binary form must reproduce the above copyright |
<> | 144:ef7eb2e8f9f7 | 18 | notice, this list of conditions and the following disclaimer in the |
<> | 144:ef7eb2e8f9f7 | 19 | documentation and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 20 | - Neither the name of ARM nor the names of its contributors may be used |
<> | 144:ef7eb2e8f9f7 | 21 | to endorse or promote products derived from this software without |
<> | 144:ef7eb2e8f9f7 | 22 | specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 23 | * |
<> | 144:ef7eb2e8f9f7 | 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
<> | 144:ef7eb2e8f9f7 | 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
<> | 144:ef7eb2e8f9f7 | 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
<> | 144:ef7eb2e8f9f7 | 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
<> | 144:ef7eb2e8f9f7 | 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
<> | 144:ef7eb2e8f9f7 | 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
<> | 144:ef7eb2e8f9f7 | 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
<> | 144:ef7eb2e8f9f7 | 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
<> | 144:ef7eb2e8f9f7 | 34 | POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 35 | ---------------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 36 | |
<> | 144:ef7eb2e8f9f7 | 37 | |
<> | 144:ef7eb2e8f9f7 | 38 | #if defined ( __ICCARM__ ) |
<> | 144:ef7eb2e8f9f7 | 39 | #pragma system_include /* treat file as system include file for MISRA check */ |
<> | 144:ef7eb2e8f9f7 | 40 | #endif |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | #ifndef __CORE_CM7_H_GENERIC |
<> | 144:ef7eb2e8f9f7 | 43 | #define __CORE_CM7_H_GENERIC |
<> | 144:ef7eb2e8f9f7 | 44 | |
<> | 144:ef7eb2e8f9f7 | 45 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 46 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 47 | #endif |
<> | 144:ef7eb2e8f9f7 | 48 | |
<> | 144:ef7eb2e8f9f7 | 49 | /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
<> | 144:ef7eb2e8f9f7 | 50 | CMSIS violates the following MISRA-C:2004 rules: |
<> | 144:ef7eb2e8f9f7 | 51 | |
<> | 144:ef7eb2e8f9f7 | 52 | \li Required Rule 8.5, object/function definition in header file.<br> |
<> | 144:ef7eb2e8f9f7 | 53 | Function definitions in header files are used to allow 'inlining'. |
<> | 144:ef7eb2e8f9f7 | 54 | |
<> | 144:ef7eb2e8f9f7 | 55 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
<> | 144:ef7eb2e8f9f7 | 56 | Unions are used for effective representation of core registers. |
<> | 144:ef7eb2e8f9f7 | 57 | |
<> | 144:ef7eb2e8f9f7 | 58 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
<> | 144:ef7eb2e8f9f7 | 59 | Function-like macros are used to allow more efficient code. |
<> | 144:ef7eb2e8f9f7 | 60 | */ |
<> | 144:ef7eb2e8f9f7 | 61 | |
<> | 144:ef7eb2e8f9f7 | 62 | |
<> | 144:ef7eb2e8f9f7 | 63 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 64 | * CMSIS definitions |
<> | 144:ef7eb2e8f9f7 | 65 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 66 | /** \ingroup Cortex_M7 |
<> | 144:ef7eb2e8f9f7 | 67 | @{ |
<> | 144:ef7eb2e8f9f7 | 68 | */ |
<> | 144:ef7eb2e8f9f7 | 69 | |
<> | 144:ef7eb2e8f9f7 | 70 | /* CMSIS CM7 definitions */ |
<> | 144:ef7eb2e8f9f7 | 71 | #define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ |
<> | 144:ef7eb2e8f9f7 | 72 | #define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ |
<> | 144:ef7eb2e8f9f7 | 73 | #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ |
<> | 144:ef7eb2e8f9f7 | 74 | __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
<> | 144:ef7eb2e8f9f7 | 75 | |
<> | 144:ef7eb2e8f9f7 | 76 | #define __CORTEX_M (0x07) /*!< Cortex-M Core */ |
<> | 144:ef7eb2e8f9f7 | 77 | |
<> | 144:ef7eb2e8f9f7 | 78 | |
<> | 144:ef7eb2e8f9f7 | 79 | #if defined ( __CC_ARM ) |
<> | 144:ef7eb2e8f9f7 | 80 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
<> | 144:ef7eb2e8f9f7 | 81 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
<> | 144:ef7eb2e8f9f7 | 82 | #define __STATIC_INLINE static __inline |
<> | 144:ef7eb2e8f9f7 | 83 | |
<> | 144:ef7eb2e8f9f7 | 84 | #elif defined ( __GNUC__ ) |
<> | 144:ef7eb2e8f9f7 | 85 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
<> | 144:ef7eb2e8f9f7 | 86 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
<> | 144:ef7eb2e8f9f7 | 87 | #define __STATIC_INLINE static inline |
<> | 144:ef7eb2e8f9f7 | 88 | |
<> | 144:ef7eb2e8f9f7 | 89 | #elif defined ( __ICCARM__ ) |
<> | 144:ef7eb2e8f9f7 | 90 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
<> | 144:ef7eb2e8f9f7 | 91 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
<> | 144:ef7eb2e8f9f7 | 92 | #define __STATIC_INLINE static inline |
<> | 144:ef7eb2e8f9f7 | 93 | |
<> | 144:ef7eb2e8f9f7 | 94 | #elif defined ( __TMS470__ ) |
<> | 144:ef7eb2e8f9f7 | 95 | #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ |
<> | 144:ef7eb2e8f9f7 | 96 | #define __STATIC_INLINE static inline |
<> | 144:ef7eb2e8f9f7 | 97 | |
<> | 144:ef7eb2e8f9f7 | 98 | #elif defined ( __TASKING__ ) |
<> | 144:ef7eb2e8f9f7 | 99 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
<> | 144:ef7eb2e8f9f7 | 100 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
<> | 144:ef7eb2e8f9f7 | 101 | #define __STATIC_INLINE static inline |
<> | 144:ef7eb2e8f9f7 | 102 | |
<> | 144:ef7eb2e8f9f7 | 103 | #elif defined ( __CSMC__ ) |
<> | 144:ef7eb2e8f9f7 | 104 | #define __packed |
<> | 144:ef7eb2e8f9f7 | 105 | #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ |
<> | 144:ef7eb2e8f9f7 | 106 | #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ |
<> | 144:ef7eb2e8f9f7 | 107 | #define __STATIC_INLINE static inline |
<> | 144:ef7eb2e8f9f7 | 108 | |
<> | 144:ef7eb2e8f9f7 | 109 | #endif |
<> | 144:ef7eb2e8f9f7 | 110 | |
<> | 144:ef7eb2e8f9f7 | 111 | /** __FPU_USED indicates whether an FPU is used or not. |
<> | 144:ef7eb2e8f9f7 | 112 | For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. |
<> | 144:ef7eb2e8f9f7 | 113 | */ |
<> | 144:ef7eb2e8f9f7 | 114 | #if defined ( __CC_ARM ) |
<> | 144:ef7eb2e8f9f7 | 115 | #if defined __TARGET_FPU_VFP |
<> | 144:ef7eb2e8f9f7 | 116 | #if (__FPU_PRESENT == 1) |
<> | 144:ef7eb2e8f9f7 | 117 | #define __FPU_USED 1 |
<> | 144:ef7eb2e8f9f7 | 118 | #else |
<> | 144:ef7eb2e8f9f7 | 119 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
<> | 144:ef7eb2e8f9f7 | 120 | #define __FPU_USED 0 |
<> | 144:ef7eb2e8f9f7 | 121 | #endif |
<> | 144:ef7eb2e8f9f7 | 122 | #else |
<> | 144:ef7eb2e8f9f7 | 123 | #define __FPU_USED 0 |
<> | 144:ef7eb2e8f9f7 | 124 | #endif |
<> | 144:ef7eb2e8f9f7 | 125 | |
<> | 144:ef7eb2e8f9f7 | 126 | #elif defined ( __GNUC__ ) |
<> | 144:ef7eb2e8f9f7 | 127 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
<> | 144:ef7eb2e8f9f7 | 128 | #if (__FPU_PRESENT == 1) |
<> | 144:ef7eb2e8f9f7 | 129 | #define __FPU_USED 1 |
<> | 144:ef7eb2e8f9f7 | 130 | #else |
<> | 144:ef7eb2e8f9f7 | 131 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
<> | 144:ef7eb2e8f9f7 | 132 | #define __FPU_USED 0 |
<> | 144:ef7eb2e8f9f7 | 133 | #endif |
<> | 144:ef7eb2e8f9f7 | 134 | #else |
<> | 144:ef7eb2e8f9f7 | 135 | #define __FPU_USED 0 |
<> | 144:ef7eb2e8f9f7 | 136 | #endif |
<> | 144:ef7eb2e8f9f7 | 137 | |
<> | 144:ef7eb2e8f9f7 | 138 | #elif defined ( __ICCARM__ ) |
<> | 144:ef7eb2e8f9f7 | 139 | #if defined __ARMVFP__ |
<> | 144:ef7eb2e8f9f7 | 140 | #if (__FPU_PRESENT == 1) |
<> | 144:ef7eb2e8f9f7 | 141 | #define __FPU_USED 1 |
<> | 144:ef7eb2e8f9f7 | 142 | #else |
<> | 144:ef7eb2e8f9f7 | 143 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
<> | 144:ef7eb2e8f9f7 | 144 | #define __FPU_USED 0 |
<> | 144:ef7eb2e8f9f7 | 145 | #endif |
<> | 144:ef7eb2e8f9f7 | 146 | #else |
<> | 144:ef7eb2e8f9f7 | 147 | #define __FPU_USED 0 |
<> | 144:ef7eb2e8f9f7 | 148 | #endif |
<> | 144:ef7eb2e8f9f7 | 149 | |
<> | 144:ef7eb2e8f9f7 | 150 | #elif defined ( __TMS470__ ) |
<> | 144:ef7eb2e8f9f7 | 151 | #if defined __TI_VFP_SUPPORT__ |
<> | 144:ef7eb2e8f9f7 | 152 | #if (__FPU_PRESENT == 1) |
<> | 144:ef7eb2e8f9f7 | 153 | #define __FPU_USED 1 |
<> | 144:ef7eb2e8f9f7 | 154 | #else |
<> | 144:ef7eb2e8f9f7 | 155 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
<> | 144:ef7eb2e8f9f7 | 156 | #define __FPU_USED 0 |
<> | 144:ef7eb2e8f9f7 | 157 | #endif |
<> | 144:ef7eb2e8f9f7 | 158 | #else |
<> | 144:ef7eb2e8f9f7 | 159 | #define __FPU_USED 0 |
<> | 144:ef7eb2e8f9f7 | 160 | #endif |
<> | 144:ef7eb2e8f9f7 | 161 | |
<> | 144:ef7eb2e8f9f7 | 162 | #elif defined ( __TASKING__ ) |
<> | 144:ef7eb2e8f9f7 | 163 | #if defined __FPU_VFP__ |
<> | 144:ef7eb2e8f9f7 | 164 | #if (__FPU_PRESENT == 1) |
<> | 144:ef7eb2e8f9f7 | 165 | #define __FPU_USED 1 |
<> | 144:ef7eb2e8f9f7 | 166 | #else |
<> | 144:ef7eb2e8f9f7 | 167 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
<> | 144:ef7eb2e8f9f7 | 168 | #define __FPU_USED 0 |
<> | 144:ef7eb2e8f9f7 | 169 | #endif |
<> | 144:ef7eb2e8f9f7 | 170 | #else |
<> | 144:ef7eb2e8f9f7 | 171 | #define __FPU_USED 0 |
<> | 144:ef7eb2e8f9f7 | 172 | #endif |
<> | 144:ef7eb2e8f9f7 | 173 | |
<> | 144:ef7eb2e8f9f7 | 174 | #elif defined ( __CSMC__ ) /* Cosmic */ |
<> | 144:ef7eb2e8f9f7 | 175 | #if ( __CSMC__ & 0x400) // FPU present for parser |
<> | 144:ef7eb2e8f9f7 | 176 | #if (__FPU_PRESENT == 1) |
<> | 144:ef7eb2e8f9f7 | 177 | #define __FPU_USED 1 |
<> | 144:ef7eb2e8f9f7 | 178 | #else |
<> | 144:ef7eb2e8f9f7 | 179 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
<> | 144:ef7eb2e8f9f7 | 180 | #define __FPU_USED 0 |
<> | 144:ef7eb2e8f9f7 | 181 | #endif |
<> | 144:ef7eb2e8f9f7 | 182 | #else |
<> | 144:ef7eb2e8f9f7 | 183 | #define __FPU_USED 0 |
<> | 144:ef7eb2e8f9f7 | 184 | #endif |
<> | 144:ef7eb2e8f9f7 | 185 | #endif |
<> | 144:ef7eb2e8f9f7 | 186 | |
<> | 144:ef7eb2e8f9f7 | 187 | #include <stdint.h> /* standard types definitions */ |
<> | 144:ef7eb2e8f9f7 | 188 | #include <core_cmInstr.h> /* Core Instruction Access */ |
<> | 144:ef7eb2e8f9f7 | 189 | #include <core_cmFunc.h> /* Core Function Access */ |
<> | 144:ef7eb2e8f9f7 | 190 | #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */ |
<> | 144:ef7eb2e8f9f7 | 191 | |
<> | 144:ef7eb2e8f9f7 | 192 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 193 | } |
<> | 144:ef7eb2e8f9f7 | 194 | #endif |
<> | 144:ef7eb2e8f9f7 | 195 | |
<> | 144:ef7eb2e8f9f7 | 196 | #endif /* __CORE_CM7_H_GENERIC */ |
<> | 144:ef7eb2e8f9f7 | 197 | |
<> | 144:ef7eb2e8f9f7 | 198 | #ifndef __CMSIS_GENERIC |
<> | 144:ef7eb2e8f9f7 | 199 | |
<> | 144:ef7eb2e8f9f7 | 200 | #ifndef __CORE_CM7_H_DEPENDANT |
<> | 144:ef7eb2e8f9f7 | 201 | #define __CORE_CM7_H_DEPENDANT |
<> | 144:ef7eb2e8f9f7 | 202 | |
<> | 144:ef7eb2e8f9f7 | 203 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 204 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 205 | #endif |
<> | 144:ef7eb2e8f9f7 | 206 | |
<> | 144:ef7eb2e8f9f7 | 207 | /* check device defines and use defaults */ |
<> | 144:ef7eb2e8f9f7 | 208 | #if defined __CHECK_DEVICE_DEFINES |
<> | 144:ef7eb2e8f9f7 | 209 | #ifndef __CM7_REV |
<> | 144:ef7eb2e8f9f7 | 210 | #define __CM7_REV 0x0000 |
<> | 144:ef7eb2e8f9f7 | 211 | #warning "__CM7_REV not defined in device header file; using default!" |
<> | 144:ef7eb2e8f9f7 | 212 | #endif |
<> | 144:ef7eb2e8f9f7 | 213 | |
<> | 144:ef7eb2e8f9f7 | 214 | #ifndef __FPU_PRESENT |
<> | 144:ef7eb2e8f9f7 | 215 | #define __FPU_PRESENT 0 |
<> | 144:ef7eb2e8f9f7 | 216 | #warning "__FPU_PRESENT not defined in device header file; using default!" |
<> | 144:ef7eb2e8f9f7 | 217 | #endif |
<> | 144:ef7eb2e8f9f7 | 218 | |
<> | 144:ef7eb2e8f9f7 | 219 | #ifndef __MPU_PRESENT |
<> | 144:ef7eb2e8f9f7 | 220 | #define __MPU_PRESENT 0 |
<> | 144:ef7eb2e8f9f7 | 221 | #warning "__MPU_PRESENT not defined in device header file; using default!" |
<> | 144:ef7eb2e8f9f7 | 222 | #endif |
<> | 144:ef7eb2e8f9f7 | 223 | |
<> | 144:ef7eb2e8f9f7 | 224 | #ifndef __ICACHE_PRESENT |
<> | 144:ef7eb2e8f9f7 | 225 | #define __ICACHE_PRESENT 0 |
<> | 144:ef7eb2e8f9f7 | 226 | #warning "__ICACHE_PRESENT not defined in device header file; using default!" |
<> | 144:ef7eb2e8f9f7 | 227 | #endif |
<> | 144:ef7eb2e8f9f7 | 228 | |
<> | 144:ef7eb2e8f9f7 | 229 | #ifndef __DCACHE_PRESENT |
<> | 144:ef7eb2e8f9f7 | 230 | #define __DCACHE_PRESENT 0 |
<> | 144:ef7eb2e8f9f7 | 231 | #warning "__DCACHE_PRESENT not defined in device header file; using default!" |
<> | 144:ef7eb2e8f9f7 | 232 | #endif |
<> | 144:ef7eb2e8f9f7 | 233 | |
<> | 144:ef7eb2e8f9f7 | 234 | #ifndef __DTCM_PRESENT |
<> | 144:ef7eb2e8f9f7 | 235 | #define __DTCM_PRESENT 0 |
<> | 144:ef7eb2e8f9f7 | 236 | #warning "__DTCM_PRESENT not defined in device header file; using default!" |
<> | 144:ef7eb2e8f9f7 | 237 | #endif |
<> | 144:ef7eb2e8f9f7 | 238 | |
<> | 144:ef7eb2e8f9f7 | 239 | #ifndef __NVIC_PRIO_BITS |
<> | 144:ef7eb2e8f9f7 | 240 | #define __NVIC_PRIO_BITS 3 |
<> | 144:ef7eb2e8f9f7 | 241 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
<> | 144:ef7eb2e8f9f7 | 242 | #endif |
<> | 144:ef7eb2e8f9f7 | 243 | |
<> | 144:ef7eb2e8f9f7 | 244 | #ifndef __Vendor_SysTickConfig |
<> | 144:ef7eb2e8f9f7 | 245 | #define __Vendor_SysTickConfig 0 |
<> | 144:ef7eb2e8f9f7 | 246 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
<> | 144:ef7eb2e8f9f7 | 247 | #endif |
<> | 144:ef7eb2e8f9f7 | 248 | #endif |
<> | 144:ef7eb2e8f9f7 | 249 | |
<> | 144:ef7eb2e8f9f7 | 250 | /* IO definitions (access restrictions to peripheral registers) */ |
<> | 144:ef7eb2e8f9f7 | 251 | /** |
<> | 144:ef7eb2e8f9f7 | 252 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
<> | 144:ef7eb2e8f9f7 | 253 | |
<> | 144:ef7eb2e8f9f7 | 254 | <strong>IO Type Qualifiers</strong> are used |
<> | 144:ef7eb2e8f9f7 | 255 | \li to specify the access to peripheral variables. |
<> | 144:ef7eb2e8f9f7 | 256 | \li for automatic generation of peripheral register debug information. |
<> | 144:ef7eb2e8f9f7 | 257 | */ |
<> | 144:ef7eb2e8f9f7 | 258 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 259 | #define __I volatile /*!< Defines 'read only' permissions */ |
<> | 144:ef7eb2e8f9f7 | 260 | #else |
<> | 144:ef7eb2e8f9f7 | 261 | #define __I volatile const /*!< Defines 'read only' permissions */ |
<> | 144:ef7eb2e8f9f7 | 262 | #endif |
<> | 144:ef7eb2e8f9f7 | 263 | #define __O volatile /*!< Defines 'write only' permissions */ |
<> | 144:ef7eb2e8f9f7 | 264 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
<> | 144:ef7eb2e8f9f7 | 265 | |
<> | 150:02e0a0aed4ec | 266 | #ifdef __cplusplus |
<> | 150:02e0a0aed4ec | 267 | #define __IM volatile /*!< Defines 'read only' permissions */ |
<> | 150:02e0a0aed4ec | 268 | #else |
<> | 150:02e0a0aed4ec | 269 | #define __IM volatile const /*!< Defines 'read only' permissions */ |
<> | 150:02e0a0aed4ec | 270 | #endif |
<> | 150:02e0a0aed4ec | 271 | #define __OM volatile /*!< Defines 'write only' permissions */ |
<> | 150:02e0a0aed4ec | 272 | #define __IOM volatile /*!< Defines 'read / write' permissions */ |
<> | 150:02e0a0aed4ec | 273 | |
<> | 144:ef7eb2e8f9f7 | 274 | /*@} end of group Cortex_M7 */ |
<> | 144:ef7eb2e8f9f7 | 275 | |
<> | 144:ef7eb2e8f9f7 | 276 | |
<> | 144:ef7eb2e8f9f7 | 277 | |
<> | 144:ef7eb2e8f9f7 | 278 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 279 | * Register Abstraction |
<> | 144:ef7eb2e8f9f7 | 280 | Core Register contain: |
<> | 144:ef7eb2e8f9f7 | 281 | - Core Register |
<> | 144:ef7eb2e8f9f7 | 282 | - Core NVIC Register |
<> | 144:ef7eb2e8f9f7 | 283 | - Core SCB Register |
<> | 144:ef7eb2e8f9f7 | 284 | - Core SysTick Register |
<> | 144:ef7eb2e8f9f7 | 285 | - Core Debug Register |
<> | 144:ef7eb2e8f9f7 | 286 | - Core MPU Register |
<> | 144:ef7eb2e8f9f7 | 287 | - Core FPU Register |
<> | 144:ef7eb2e8f9f7 | 288 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 289 | /** \defgroup CMSIS_core_register Defines and Type Definitions |
<> | 144:ef7eb2e8f9f7 | 290 | \brief Type definitions and defines for Cortex-M processor based devices. |
<> | 144:ef7eb2e8f9f7 | 291 | */ |
<> | 144:ef7eb2e8f9f7 | 292 | |
<> | 144:ef7eb2e8f9f7 | 293 | /** \ingroup CMSIS_core_register |
<> | 144:ef7eb2e8f9f7 | 294 | \defgroup CMSIS_CORE Status and Control Registers |
<> | 144:ef7eb2e8f9f7 | 295 | \brief Core Register type definitions. |
<> | 144:ef7eb2e8f9f7 | 296 | @{ |
<> | 144:ef7eb2e8f9f7 | 297 | */ |
<> | 144:ef7eb2e8f9f7 | 298 | |
<> | 144:ef7eb2e8f9f7 | 299 | /** \brief Union type to access the Application Program Status Register (APSR). |
<> | 144:ef7eb2e8f9f7 | 300 | */ |
<> | 144:ef7eb2e8f9f7 | 301 | typedef union |
<> | 144:ef7eb2e8f9f7 | 302 | { |
<> | 144:ef7eb2e8f9f7 | 303 | struct |
<> | 144:ef7eb2e8f9f7 | 304 | { |
<> | 144:ef7eb2e8f9f7 | 305 | uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ |
<> | 144:ef7eb2e8f9f7 | 306 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
<> | 144:ef7eb2e8f9f7 | 307 | uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ |
<> | 144:ef7eb2e8f9f7 | 308 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
<> | 144:ef7eb2e8f9f7 | 309 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
<> | 144:ef7eb2e8f9f7 | 310 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
<> | 144:ef7eb2e8f9f7 | 311 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
<> | 144:ef7eb2e8f9f7 | 312 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
<> | 144:ef7eb2e8f9f7 | 313 | } b; /*!< Structure used for bit access */ |
<> | 144:ef7eb2e8f9f7 | 314 | uint32_t w; /*!< Type used for word access */ |
<> | 144:ef7eb2e8f9f7 | 315 | } APSR_Type; |
<> | 144:ef7eb2e8f9f7 | 316 | |
<> | 144:ef7eb2e8f9f7 | 317 | /* APSR Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 318 | #define APSR_N_Pos 31 /*!< APSR: N Position */ |
<> | 144:ef7eb2e8f9f7 | 319 | #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
<> | 144:ef7eb2e8f9f7 | 320 | |
<> | 144:ef7eb2e8f9f7 | 321 | #define APSR_Z_Pos 30 /*!< APSR: Z Position */ |
<> | 144:ef7eb2e8f9f7 | 322 | #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
<> | 144:ef7eb2e8f9f7 | 323 | |
<> | 144:ef7eb2e8f9f7 | 324 | #define APSR_C_Pos 29 /*!< APSR: C Position */ |
<> | 144:ef7eb2e8f9f7 | 325 | #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
<> | 144:ef7eb2e8f9f7 | 326 | |
<> | 144:ef7eb2e8f9f7 | 327 | #define APSR_V_Pos 28 /*!< APSR: V Position */ |
<> | 144:ef7eb2e8f9f7 | 328 | #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
<> | 144:ef7eb2e8f9f7 | 329 | |
<> | 144:ef7eb2e8f9f7 | 330 | #define APSR_Q_Pos 27 /*!< APSR: Q Position */ |
<> | 144:ef7eb2e8f9f7 | 331 | #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ |
<> | 144:ef7eb2e8f9f7 | 332 | |
<> | 144:ef7eb2e8f9f7 | 333 | #define APSR_GE_Pos 16 /*!< APSR: GE Position */ |
<> | 144:ef7eb2e8f9f7 | 334 | #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ |
<> | 144:ef7eb2e8f9f7 | 335 | |
<> | 144:ef7eb2e8f9f7 | 336 | |
<> | 144:ef7eb2e8f9f7 | 337 | /** \brief Union type to access the Interrupt Program Status Register (IPSR). |
<> | 144:ef7eb2e8f9f7 | 338 | */ |
<> | 144:ef7eb2e8f9f7 | 339 | typedef union |
<> | 144:ef7eb2e8f9f7 | 340 | { |
<> | 144:ef7eb2e8f9f7 | 341 | struct |
<> | 144:ef7eb2e8f9f7 | 342 | { |
<> | 144:ef7eb2e8f9f7 | 343 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
<> | 144:ef7eb2e8f9f7 | 344 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
<> | 144:ef7eb2e8f9f7 | 345 | } b; /*!< Structure used for bit access */ |
<> | 144:ef7eb2e8f9f7 | 346 | uint32_t w; /*!< Type used for word access */ |
<> | 144:ef7eb2e8f9f7 | 347 | } IPSR_Type; |
<> | 144:ef7eb2e8f9f7 | 348 | |
<> | 144:ef7eb2e8f9f7 | 349 | /* IPSR Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 350 | #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ |
<> | 144:ef7eb2e8f9f7 | 351 | #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
<> | 144:ef7eb2e8f9f7 | 352 | |
<> | 144:ef7eb2e8f9f7 | 353 | |
<> | 144:ef7eb2e8f9f7 | 354 | /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
<> | 144:ef7eb2e8f9f7 | 355 | */ |
<> | 144:ef7eb2e8f9f7 | 356 | typedef union |
<> | 144:ef7eb2e8f9f7 | 357 | { |
<> | 144:ef7eb2e8f9f7 | 358 | struct |
<> | 144:ef7eb2e8f9f7 | 359 | { |
<> | 144:ef7eb2e8f9f7 | 360 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
<> | 144:ef7eb2e8f9f7 | 361 | uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ |
<> | 144:ef7eb2e8f9f7 | 362 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
<> | 144:ef7eb2e8f9f7 | 363 | uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ |
<> | 144:ef7eb2e8f9f7 | 364 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
<> | 144:ef7eb2e8f9f7 | 365 | uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ |
<> | 144:ef7eb2e8f9f7 | 366 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
<> | 144:ef7eb2e8f9f7 | 367 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
<> | 144:ef7eb2e8f9f7 | 368 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
<> | 144:ef7eb2e8f9f7 | 369 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
<> | 144:ef7eb2e8f9f7 | 370 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
<> | 144:ef7eb2e8f9f7 | 371 | } b; /*!< Structure used for bit access */ |
<> | 144:ef7eb2e8f9f7 | 372 | uint32_t w; /*!< Type used for word access */ |
<> | 144:ef7eb2e8f9f7 | 373 | } xPSR_Type; |
<> | 144:ef7eb2e8f9f7 | 374 | |
<> | 144:ef7eb2e8f9f7 | 375 | /* xPSR Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 376 | #define xPSR_N_Pos 31 /*!< xPSR: N Position */ |
<> | 144:ef7eb2e8f9f7 | 377 | #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
<> | 144:ef7eb2e8f9f7 | 378 | |
<> | 144:ef7eb2e8f9f7 | 379 | #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ |
<> | 144:ef7eb2e8f9f7 | 380 | #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
<> | 144:ef7eb2e8f9f7 | 381 | |
<> | 144:ef7eb2e8f9f7 | 382 | #define xPSR_C_Pos 29 /*!< xPSR: C Position */ |
<> | 144:ef7eb2e8f9f7 | 383 | #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
<> | 144:ef7eb2e8f9f7 | 384 | |
<> | 144:ef7eb2e8f9f7 | 385 | #define xPSR_V_Pos 28 /*!< xPSR: V Position */ |
<> | 144:ef7eb2e8f9f7 | 386 | #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
<> | 144:ef7eb2e8f9f7 | 387 | |
<> | 144:ef7eb2e8f9f7 | 388 | #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ |
<> | 144:ef7eb2e8f9f7 | 389 | #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ |
<> | 144:ef7eb2e8f9f7 | 390 | |
<> | 144:ef7eb2e8f9f7 | 391 | #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ |
<> | 144:ef7eb2e8f9f7 | 392 | #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ |
<> | 144:ef7eb2e8f9f7 | 393 | |
<> | 144:ef7eb2e8f9f7 | 394 | #define xPSR_T_Pos 24 /*!< xPSR: T Position */ |
<> | 144:ef7eb2e8f9f7 | 395 | #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
<> | 144:ef7eb2e8f9f7 | 396 | |
<> | 144:ef7eb2e8f9f7 | 397 | #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */ |
<> | 144:ef7eb2e8f9f7 | 398 | #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ |
<> | 144:ef7eb2e8f9f7 | 399 | |
<> | 144:ef7eb2e8f9f7 | 400 | #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ |
<> | 144:ef7eb2e8f9f7 | 401 | #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
<> | 144:ef7eb2e8f9f7 | 402 | |
<> | 144:ef7eb2e8f9f7 | 403 | |
<> | 144:ef7eb2e8f9f7 | 404 | /** \brief Union type to access the Control Registers (CONTROL). |
<> | 144:ef7eb2e8f9f7 | 405 | */ |
<> | 144:ef7eb2e8f9f7 | 406 | typedef union |
<> | 144:ef7eb2e8f9f7 | 407 | { |
<> | 144:ef7eb2e8f9f7 | 408 | struct |
<> | 144:ef7eb2e8f9f7 | 409 | { |
<> | 144:ef7eb2e8f9f7 | 410 | uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
<> | 144:ef7eb2e8f9f7 | 411 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
<> | 144:ef7eb2e8f9f7 | 412 | uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ |
<> | 144:ef7eb2e8f9f7 | 413 | uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ |
<> | 144:ef7eb2e8f9f7 | 414 | } b; /*!< Structure used for bit access */ |
<> | 144:ef7eb2e8f9f7 | 415 | uint32_t w; /*!< Type used for word access */ |
<> | 144:ef7eb2e8f9f7 | 416 | } CONTROL_Type; |
<> | 144:ef7eb2e8f9f7 | 417 | |
<> | 144:ef7eb2e8f9f7 | 418 | /* CONTROL Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 419 | #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */ |
<> | 144:ef7eb2e8f9f7 | 420 | #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ |
<> | 144:ef7eb2e8f9f7 | 421 | |
<> | 144:ef7eb2e8f9f7 | 422 | #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ |
<> | 144:ef7eb2e8f9f7 | 423 | #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
<> | 144:ef7eb2e8f9f7 | 424 | |
<> | 144:ef7eb2e8f9f7 | 425 | #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ |
<> | 144:ef7eb2e8f9f7 | 426 | #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ |
<> | 144:ef7eb2e8f9f7 | 427 | |
<> | 144:ef7eb2e8f9f7 | 428 | /*@} end of group CMSIS_CORE */ |
<> | 144:ef7eb2e8f9f7 | 429 | |
<> | 144:ef7eb2e8f9f7 | 430 | |
<> | 144:ef7eb2e8f9f7 | 431 | /** \ingroup CMSIS_core_register |
<> | 144:ef7eb2e8f9f7 | 432 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
<> | 144:ef7eb2e8f9f7 | 433 | \brief Type definitions for the NVIC Registers |
<> | 144:ef7eb2e8f9f7 | 434 | @{ |
<> | 144:ef7eb2e8f9f7 | 435 | */ |
<> | 144:ef7eb2e8f9f7 | 436 | |
<> | 144:ef7eb2e8f9f7 | 437 | /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
<> | 144:ef7eb2e8f9f7 | 438 | */ |
<> | 144:ef7eb2e8f9f7 | 439 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 440 | { |
<> | 144:ef7eb2e8f9f7 | 441 | __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
<> | 144:ef7eb2e8f9f7 | 442 | uint32_t RESERVED0[24]; |
<> | 144:ef7eb2e8f9f7 | 443 | __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
<> | 144:ef7eb2e8f9f7 | 444 | uint32_t RSERVED1[24]; |
<> | 144:ef7eb2e8f9f7 | 445 | __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
<> | 144:ef7eb2e8f9f7 | 446 | uint32_t RESERVED2[24]; |
<> | 144:ef7eb2e8f9f7 | 447 | __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
<> | 144:ef7eb2e8f9f7 | 448 | uint32_t RESERVED3[24]; |
<> | 144:ef7eb2e8f9f7 | 449 | __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ |
<> | 144:ef7eb2e8f9f7 | 450 | uint32_t RESERVED4[56]; |
<> | 144:ef7eb2e8f9f7 | 451 | __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ |
<> | 144:ef7eb2e8f9f7 | 452 | uint32_t RESERVED5[644]; |
<> | 144:ef7eb2e8f9f7 | 453 | __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ |
<> | 144:ef7eb2e8f9f7 | 454 | } NVIC_Type; |
<> | 144:ef7eb2e8f9f7 | 455 | |
<> | 144:ef7eb2e8f9f7 | 456 | /* Software Triggered Interrupt Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 457 | #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ |
<> | 144:ef7eb2e8f9f7 | 458 | #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ |
<> | 144:ef7eb2e8f9f7 | 459 | |
<> | 144:ef7eb2e8f9f7 | 460 | /*@} end of group CMSIS_NVIC */ |
<> | 144:ef7eb2e8f9f7 | 461 | |
<> | 144:ef7eb2e8f9f7 | 462 | |
<> | 144:ef7eb2e8f9f7 | 463 | /** \ingroup CMSIS_core_register |
<> | 144:ef7eb2e8f9f7 | 464 | \defgroup CMSIS_SCB System Control Block (SCB) |
<> | 144:ef7eb2e8f9f7 | 465 | \brief Type definitions for the System Control Block Registers |
<> | 144:ef7eb2e8f9f7 | 466 | @{ |
<> | 144:ef7eb2e8f9f7 | 467 | */ |
<> | 144:ef7eb2e8f9f7 | 468 | |
<> | 144:ef7eb2e8f9f7 | 469 | /** \brief Structure type to access the System Control Block (SCB). |
<> | 144:ef7eb2e8f9f7 | 470 | */ |
<> | 144:ef7eb2e8f9f7 | 471 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 472 | { |
<> | 144:ef7eb2e8f9f7 | 473 | __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
<> | 144:ef7eb2e8f9f7 | 474 | __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
<> | 144:ef7eb2e8f9f7 | 475 | __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
<> | 144:ef7eb2e8f9f7 | 476 | __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
<> | 144:ef7eb2e8f9f7 | 477 | __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
<> | 144:ef7eb2e8f9f7 | 478 | __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
<> | 144:ef7eb2e8f9f7 | 479 | __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ |
<> | 144:ef7eb2e8f9f7 | 480 | __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
<> | 144:ef7eb2e8f9f7 | 481 | __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ |
<> | 144:ef7eb2e8f9f7 | 482 | __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ |
<> | 144:ef7eb2e8f9f7 | 483 | __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ |
<> | 144:ef7eb2e8f9f7 | 484 | __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ |
<> | 144:ef7eb2e8f9f7 | 485 | __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ |
<> | 144:ef7eb2e8f9f7 | 486 | __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ |
<> | 144:ef7eb2e8f9f7 | 487 | __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ |
<> | 144:ef7eb2e8f9f7 | 488 | __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ |
<> | 144:ef7eb2e8f9f7 | 489 | __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ |
<> | 144:ef7eb2e8f9f7 | 490 | __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ |
<> | 144:ef7eb2e8f9f7 | 491 | __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ |
<> | 144:ef7eb2e8f9f7 | 492 | uint32_t RESERVED0[1]; |
<> | 144:ef7eb2e8f9f7 | 493 | __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ |
<> | 144:ef7eb2e8f9f7 | 494 | __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ |
<> | 144:ef7eb2e8f9f7 | 495 | __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ |
<> | 144:ef7eb2e8f9f7 | 496 | __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ |
<> | 144:ef7eb2e8f9f7 | 497 | __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ |
<> | 144:ef7eb2e8f9f7 | 498 | uint32_t RESERVED3[93]; |
<> | 144:ef7eb2e8f9f7 | 499 | __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ |
<> | 144:ef7eb2e8f9f7 | 500 | uint32_t RESERVED4[15]; |
<> | 144:ef7eb2e8f9f7 | 501 | __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ |
<> | 144:ef7eb2e8f9f7 | 502 | __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ |
<> | 144:ef7eb2e8f9f7 | 503 | __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ |
<> | 144:ef7eb2e8f9f7 | 504 | uint32_t RESERVED5[1]; |
<> | 144:ef7eb2e8f9f7 | 505 | __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ |
<> | 144:ef7eb2e8f9f7 | 506 | uint32_t RESERVED6[1]; |
<> | 144:ef7eb2e8f9f7 | 507 | __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ |
<> | 144:ef7eb2e8f9f7 | 508 | __O uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ |
<> | 144:ef7eb2e8f9f7 | 509 | __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ |
<> | 144:ef7eb2e8f9f7 | 510 | __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ |
<> | 144:ef7eb2e8f9f7 | 511 | __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ |
<> | 144:ef7eb2e8f9f7 | 512 | __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ |
<> | 144:ef7eb2e8f9f7 | 513 | __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ |
<> | 144:ef7eb2e8f9f7 | 514 | __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ |
<> | 144:ef7eb2e8f9f7 | 515 | uint32_t RESERVED7[6]; |
<> | 144:ef7eb2e8f9f7 | 516 | __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ |
<> | 144:ef7eb2e8f9f7 | 517 | __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ |
<> | 144:ef7eb2e8f9f7 | 518 | __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ |
<> | 144:ef7eb2e8f9f7 | 519 | __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ |
<> | 144:ef7eb2e8f9f7 | 520 | __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ |
<> | 144:ef7eb2e8f9f7 | 521 | uint32_t RESERVED8[1]; |
<> | 144:ef7eb2e8f9f7 | 522 | __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ |
<> | 144:ef7eb2e8f9f7 | 523 | } SCB_Type; |
<> | 144:ef7eb2e8f9f7 | 524 | |
<> | 144:ef7eb2e8f9f7 | 525 | /* SCB CPUID Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 526 | #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ |
<> | 144:ef7eb2e8f9f7 | 527 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
<> | 144:ef7eb2e8f9f7 | 528 | |
<> | 144:ef7eb2e8f9f7 | 529 | #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ |
<> | 144:ef7eb2e8f9f7 | 530 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
<> | 144:ef7eb2e8f9f7 | 531 | |
<> | 144:ef7eb2e8f9f7 | 532 | #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ |
<> | 144:ef7eb2e8f9f7 | 533 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
<> | 144:ef7eb2e8f9f7 | 534 | |
<> | 144:ef7eb2e8f9f7 | 535 | #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ |
<> | 144:ef7eb2e8f9f7 | 536 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
<> | 144:ef7eb2e8f9f7 | 537 | |
<> | 144:ef7eb2e8f9f7 | 538 | #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ |
<> | 144:ef7eb2e8f9f7 | 539 | #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
<> | 144:ef7eb2e8f9f7 | 540 | |
<> | 144:ef7eb2e8f9f7 | 541 | /* SCB Interrupt Control State Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 542 | #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ |
<> | 144:ef7eb2e8f9f7 | 543 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
<> | 144:ef7eb2e8f9f7 | 544 | |
<> | 144:ef7eb2e8f9f7 | 545 | #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ |
<> | 144:ef7eb2e8f9f7 | 546 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
<> | 144:ef7eb2e8f9f7 | 547 | |
<> | 144:ef7eb2e8f9f7 | 548 | #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ |
<> | 144:ef7eb2e8f9f7 | 549 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
<> | 144:ef7eb2e8f9f7 | 550 | |
<> | 144:ef7eb2e8f9f7 | 551 | #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ |
<> | 144:ef7eb2e8f9f7 | 552 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
<> | 144:ef7eb2e8f9f7 | 553 | |
<> | 144:ef7eb2e8f9f7 | 554 | #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ |
<> | 144:ef7eb2e8f9f7 | 555 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
<> | 144:ef7eb2e8f9f7 | 556 | |
<> | 144:ef7eb2e8f9f7 | 557 | #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ |
<> | 144:ef7eb2e8f9f7 | 558 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
<> | 144:ef7eb2e8f9f7 | 559 | |
<> | 144:ef7eb2e8f9f7 | 560 | #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ |
<> | 144:ef7eb2e8f9f7 | 561 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
<> | 144:ef7eb2e8f9f7 | 562 | |
<> | 144:ef7eb2e8f9f7 | 563 | #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ |
<> | 144:ef7eb2e8f9f7 | 564 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
<> | 144:ef7eb2e8f9f7 | 565 | |
<> | 144:ef7eb2e8f9f7 | 566 | #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ |
<> | 144:ef7eb2e8f9f7 | 567 | #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ |
<> | 144:ef7eb2e8f9f7 | 568 | |
<> | 144:ef7eb2e8f9f7 | 569 | #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ |
<> | 144:ef7eb2e8f9f7 | 570 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
<> | 144:ef7eb2e8f9f7 | 571 | |
<> | 144:ef7eb2e8f9f7 | 572 | /* SCB Vector Table Offset Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 573 | #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ |
<> | 144:ef7eb2e8f9f7 | 574 | #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
<> | 144:ef7eb2e8f9f7 | 575 | |
<> | 144:ef7eb2e8f9f7 | 576 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 577 | #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ |
<> | 144:ef7eb2e8f9f7 | 578 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
<> | 144:ef7eb2e8f9f7 | 579 | |
<> | 144:ef7eb2e8f9f7 | 580 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ |
<> | 144:ef7eb2e8f9f7 | 581 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
<> | 144:ef7eb2e8f9f7 | 582 | |
<> | 144:ef7eb2e8f9f7 | 583 | #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ |
<> | 144:ef7eb2e8f9f7 | 584 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
<> | 144:ef7eb2e8f9f7 | 585 | |
<> | 144:ef7eb2e8f9f7 | 586 | #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ |
<> | 144:ef7eb2e8f9f7 | 587 | #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ |
<> | 144:ef7eb2e8f9f7 | 588 | |
<> | 144:ef7eb2e8f9f7 | 589 | #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ |
<> | 144:ef7eb2e8f9f7 | 590 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
<> | 144:ef7eb2e8f9f7 | 591 | |
<> | 144:ef7eb2e8f9f7 | 592 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
<> | 144:ef7eb2e8f9f7 | 593 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
<> | 144:ef7eb2e8f9f7 | 594 | |
<> | 144:ef7eb2e8f9f7 | 595 | #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ |
<> | 144:ef7eb2e8f9f7 | 596 | #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ |
<> | 144:ef7eb2e8f9f7 | 597 | |
<> | 144:ef7eb2e8f9f7 | 598 | /* SCB System Control Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 599 | #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ |
<> | 144:ef7eb2e8f9f7 | 600 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
<> | 144:ef7eb2e8f9f7 | 601 | |
<> | 144:ef7eb2e8f9f7 | 602 | #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ |
<> | 144:ef7eb2e8f9f7 | 603 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
<> | 144:ef7eb2e8f9f7 | 604 | |
<> | 144:ef7eb2e8f9f7 | 605 | #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ |
<> | 144:ef7eb2e8f9f7 | 606 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
<> | 144:ef7eb2e8f9f7 | 607 | |
<> | 144:ef7eb2e8f9f7 | 608 | /* SCB Configuration Control Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 609 | #define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ |
<> | 144:ef7eb2e8f9f7 | 610 | #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ |
<> | 144:ef7eb2e8f9f7 | 611 | |
<> | 144:ef7eb2e8f9f7 | 612 | #define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ |
<> | 144:ef7eb2e8f9f7 | 613 | #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ |
<> | 144:ef7eb2e8f9f7 | 614 | |
<> | 144:ef7eb2e8f9f7 | 615 | #define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ |
<> | 144:ef7eb2e8f9f7 | 616 | #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ |
<> | 144:ef7eb2e8f9f7 | 617 | |
<> | 144:ef7eb2e8f9f7 | 618 | #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ |
<> | 144:ef7eb2e8f9f7 | 619 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
<> | 144:ef7eb2e8f9f7 | 620 | |
<> | 144:ef7eb2e8f9f7 | 621 | #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ |
<> | 144:ef7eb2e8f9f7 | 622 | #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ |
<> | 144:ef7eb2e8f9f7 | 623 | |
<> | 144:ef7eb2e8f9f7 | 624 | #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ |
<> | 144:ef7eb2e8f9f7 | 625 | #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ |
<> | 144:ef7eb2e8f9f7 | 626 | |
<> | 144:ef7eb2e8f9f7 | 627 | #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ |
<> | 144:ef7eb2e8f9f7 | 628 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
<> | 144:ef7eb2e8f9f7 | 629 | |
<> | 144:ef7eb2e8f9f7 | 630 | #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ |
<> | 144:ef7eb2e8f9f7 | 631 | #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ |
<> | 144:ef7eb2e8f9f7 | 632 | |
<> | 144:ef7eb2e8f9f7 | 633 | #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ |
<> | 144:ef7eb2e8f9f7 | 634 | #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 635 | |
<> | 144:ef7eb2e8f9f7 | 636 | /* SCB System Handler Control and State Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 637 | #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ |
<> | 144:ef7eb2e8f9f7 | 638 | #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 639 | |
<> | 144:ef7eb2e8f9f7 | 640 | #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ |
<> | 144:ef7eb2e8f9f7 | 641 | #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 642 | |
<> | 144:ef7eb2e8f9f7 | 643 | #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ |
<> | 144:ef7eb2e8f9f7 | 644 | #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 645 | |
<> | 144:ef7eb2e8f9f7 | 646 | #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ |
<> | 144:ef7eb2e8f9f7 | 647 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
<> | 144:ef7eb2e8f9f7 | 648 | |
<> | 144:ef7eb2e8f9f7 | 649 | #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ |
<> | 144:ef7eb2e8f9f7 | 650 | #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ |
<> | 144:ef7eb2e8f9f7 | 651 | |
<> | 144:ef7eb2e8f9f7 | 652 | #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ |
<> | 144:ef7eb2e8f9f7 | 653 | #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ |
<> | 144:ef7eb2e8f9f7 | 654 | |
<> | 144:ef7eb2e8f9f7 | 655 | #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ |
<> | 144:ef7eb2e8f9f7 | 656 | #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ |
<> | 144:ef7eb2e8f9f7 | 657 | |
<> | 144:ef7eb2e8f9f7 | 658 | #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ |
<> | 144:ef7eb2e8f9f7 | 659 | #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ |
<> | 144:ef7eb2e8f9f7 | 660 | |
<> | 144:ef7eb2e8f9f7 | 661 | #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ |
<> | 144:ef7eb2e8f9f7 | 662 | #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ |
<> | 144:ef7eb2e8f9f7 | 663 | |
<> | 144:ef7eb2e8f9f7 | 664 | #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ |
<> | 144:ef7eb2e8f9f7 | 665 | #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ |
<> | 144:ef7eb2e8f9f7 | 666 | |
<> | 144:ef7eb2e8f9f7 | 667 | #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ |
<> | 144:ef7eb2e8f9f7 | 668 | #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ |
<> | 144:ef7eb2e8f9f7 | 669 | |
<> | 144:ef7eb2e8f9f7 | 670 | #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ |
<> | 144:ef7eb2e8f9f7 | 671 | #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ |
<> | 144:ef7eb2e8f9f7 | 672 | |
<> | 144:ef7eb2e8f9f7 | 673 | #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ |
<> | 144:ef7eb2e8f9f7 | 674 | #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ |
<> | 144:ef7eb2e8f9f7 | 675 | |
<> | 144:ef7eb2e8f9f7 | 676 | #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ |
<> | 144:ef7eb2e8f9f7 | 677 | #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ |
<> | 144:ef7eb2e8f9f7 | 678 | |
<> | 144:ef7eb2e8f9f7 | 679 | /* SCB Configurable Fault Status Registers Definitions */ |
<> | 144:ef7eb2e8f9f7 | 680 | #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ |
<> | 144:ef7eb2e8f9f7 | 681 | #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ |
<> | 144:ef7eb2e8f9f7 | 682 | |
<> | 144:ef7eb2e8f9f7 | 683 | #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ |
<> | 144:ef7eb2e8f9f7 | 684 | #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ |
<> | 144:ef7eb2e8f9f7 | 685 | |
<> | 144:ef7eb2e8f9f7 | 686 | #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ |
<> | 144:ef7eb2e8f9f7 | 687 | #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ |
<> | 144:ef7eb2e8f9f7 | 688 | |
<> | 144:ef7eb2e8f9f7 | 689 | /* SCB Hard Fault Status Registers Definitions */ |
<> | 144:ef7eb2e8f9f7 | 690 | #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ |
<> | 144:ef7eb2e8f9f7 | 691 | #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ |
<> | 144:ef7eb2e8f9f7 | 692 | |
<> | 144:ef7eb2e8f9f7 | 693 | #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ |
<> | 144:ef7eb2e8f9f7 | 694 | #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ |
<> | 144:ef7eb2e8f9f7 | 695 | |
<> | 144:ef7eb2e8f9f7 | 696 | #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ |
<> | 144:ef7eb2e8f9f7 | 697 | #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ |
<> | 144:ef7eb2e8f9f7 | 698 | |
<> | 144:ef7eb2e8f9f7 | 699 | /* SCB Debug Fault Status Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 700 | #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ |
<> | 144:ef7eb2e8f9f7 | 701 | #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ |
<> | 144:ef7eb2e8f9f7 | 702 | |
<> | 144:ef7eb2e8f9f7 | 703 | #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ |
<> | 144:ef7eb2e8f9f7 | 704 | #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ |
<> | 144:ef7eb2e8f9f7 | 705 | |
<> | 144:ef7eb2e8f9f7 | 706 | #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ |
<> | 144:ef7eb2e8f9f7 | 707 | #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ |
<> | 144:ef7eb2e8f9f7 | 708 | |
<> | 144:ef7eb2e8f9f7 | 709 | #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ |
<> | 144:ef7eb2e8f9f7 | 710 | #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ |
<> | 144:ef7eb2e8f9f7 | 711 | |
<> | 144:ef7eb2e8f9f7 | 712 | #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ |
<> | 144:ef7eb2e8f9f7 | 713 | #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ |
<> | 144:ef7eb2e8f9f7 | 714 | |
<> | 144:ef7eb2e8f9f7 | 715 | /* Cache Level ID register */ |
<> | 144:ef7eb2e8f9f7 | 716 | #define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ |
<> | 144:ef7eb2e8f9f7 | 717 | #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ |
<> | 144:ef7eb2e8f9f7 | 718 | |
<> | 144:ef7eb2e8f9f7 | 719 | #define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ |
<> | 144:ef7eb2e8f9f7 | 720 | #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ |
<> | 144:ef7eb2e8f9f7 | 721 | |
<> | 144:ef7eb2e8f9f7 | 722 | /* Cache Type register */ |
<> | 144:ef7eb2e8f9f7 | 723 | #define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ |
<> | 144:ef7eb2e8f9f7 | 724 | #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ |
<> | 144:ef7eb2e8f9f7 | 725 | |
<> | 144:ef7eb2e8f9f7 | 726 | #define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ |
<> | 144:ef7eb2e8f9f7 | 727 | #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ |
<> | 144:ef7eb2e8f9f7 | 728 | |
<> | 144:ef7eb2e8f9f7 | 729 | #define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ |
<> | 144:ef7eb2e8f9f7 | 730 | #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ |
<> | 144:ef7eb2e8f9f7 | 731 | |
<> | 144:ef7eb2e8f9f7 | 732 | #define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ |
<> | 144:ef7eb2e8f9f7 | 733 | #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ |
<> | 144:ef7eb2e8f9f7 | 734 | |
<> | 144:ef7eb2e8f9f7 | 735 | #define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ |
<> | 144:ef7eb2e8f9f7 | 736 | #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ |
<> | 144:ef7eb2e8f9f7 | 737 | |
<> | 144:ef7eb2e8f9f7 | 738 | /* Cache Size ID Register */ |
<> | 144:ef7eb2e8f9f7 | 739 | #define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ |
<> | 144:ef7eb2e8f9f7 | 740 | #define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ |
<> | 144:ef7eb2e8f9f7 | 741 | |
<> | 144:ef7eb2e8f9f7 | 742 | #define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ |
<> | 144:ef7eb2e8f9f7 | 743 | #define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ |
<> | 144:ef7eb2e8f9f7 | 744 | |
<> | 144:ef7eb2e8f9f7 | 745 | #define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ |
<> | 144:ef7eb2e8f9f7 | 746 | #define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ |
<> | 144:ef7eb2e8f9f7 | 747 | |
<> | 144:ef7eb2e8f9f7 | 748 | #define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ |
<> | 144:ef7eb2e8f9f7 | 749 | #define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ |
<> | 144:ef7eb2e8f9f7 | 750 | |
<> | 144:ef7eb2e8f9f7 | 751 | #define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ |
<> | 144:ef7eb2e8f9f7 | 752 | #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ |
<> | 144:ef7eb2e8f9f7 | 753 | |
<> | 144:ef7eb2e8f9f7 | 754 | #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ |
<> | 144:ef7eb2e8f9f7 | 755 | #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ |
<> | 144:ef7eb2e8f9f7 | 756 | |
<> | 144:ef7eb2e8f9f7 | 757 | #define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ |
<> | 144:ef7eb2e8f9f7 | 758 | #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ |
<> | 144:ef7eb2e8f9f7 | 759 | |
<> | 144:ef7eb2e8f9f7 | 760 | /* Cache Size Selection Register */ |
<> | 144:ef7eb2e8f9f7 | 761 | #define SCB_CSSELR_LEVEL_Pos 1 /*!< SCB CSSELR: Level Position */ |
<> | 144:ef7eb2e8f9f7 | 762 | #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ |
<> | 144:ef7eb2e8f9f7 | 763 | |
<> | 144:ef7eb2e8f9f7 | 764 | #define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ |
<> | 144:ef7eb2e8f9f7 | 765 | #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ |
<> | 144:ef7eb2e8f9f7 | 766 | |
<> | 144:ef7eb2e8f9f7 | 767 | /* SCB Software Triggered Interrupt Register */ |
<> | 144:ef7eb2e8f9f7 | 768 | #define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ |
<> | 144:ef7eb2e8f9f7 | 769 | #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ |
<> | 144:ef7eb2e8f9f7 | 770 | |
<> | 144:ef7eb2e8f9f7 | 771 | /* Instruction Tightly-Coupled Memory Control Register*/ |
<> | 144:ef7eb2e8f9f7 | 772 | #define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ |
<> | 144:ef7eb2e8f9f7 | 773 | #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ |
<> | 144:ef7eb2e8f9f7 | 774 | |
<> | 144:ef7eb2e8f9f7 | 775 | #define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ |
<> | 144:ef7eb2e8f9f7 | 776 | #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ |
<> | 144:ef7eb2e8f9f7 | 777 | |
<> | 144:ef7eb2e8f9f7 | 778 | #define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ |
<> | 144:ef7eb2e8f9f7 | 779 | #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ |
<> | 144:ef7eb2e8f9f7 | 780 | |
<> | 144:ef7eb2e8f9f7 | 781 | #define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ |
<> | 144:ef7eb2e8f9f7 | 782 | #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ |
<> | 144:ef7eb2e8f9f7 | 783 | |
<> | 144:ef7eb2e8f9f7 | 784 | /* Data Tightly-Coupled Memory Control Registers */ |
<> | 144:ef7eb2e8f9f7 | 785 | #define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ |
<> | 144:ef7eb2e8f9f7 | 786 | #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ |
<> | 144:ef7eb2e8f9f7 | 787 | |
<> | 144:ef7eb2e8f9f7 | 788 | #define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ |
<> | 144:ef7eb2e8f9f7 | 789 | #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ |
<> | 144:ef7eb2e8f9f7 | 790 | |
<> | 144:ef7eb2e8f9f7 | 791 | #define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ |
<> | 144:ef7eb2e8f9f7 | 792 | #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ |
<> | 144:ef7eb2e8f9f7 | 793 | |
<> | 144:ef7eb2e8f9f7 | 794 | #define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ |
<> | 144:ef7eb2e8f9f7 | 795 | #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ |
<> | 144:ef7eb2e8f9f7 | 796 | |
<> | 144:ef7eb2e8f9f7 | 797 | /* AHBP Control Register */ |
<> | 144:ef7eb2e8f9f7 | 798 | #define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ |
<> | 144:ef7eb2e8f9f7 | 799 | #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ |
<> | 144:ef7eb2e8f9f7 | 800 | |
<> | 144:ef7eb2e8f9f7 | 801 | #define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ |
<> | 144:ef7eb2e8f9f7 | 802 | #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ |
<> | 144:ef7eb2e8f9f7 | 803 | |
<> | 144:ef7eb2e8f9f7 | 804 | /* L1 Cache Control Register */ |
<> | 144:ef7eb2e8f9f7 | 805 | #define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ |
<> | 144:ef7eb2e8f9f7 | 806 | #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ |
<> | 144:ef7eb2e8f9f7 | 807 | |
<> | 144:ef7eb2e8f9f7 | 808 | #define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ |
<> | 144:ef7eb2e8f9f7 | 809 | #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ |
<> | 144:ef7eb2e8f9f7 | 810 | |
<> | 144:ef7eb2e8f9f7 | 811 | #define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ |
<> | 144:ef7eb2e8f9f7 | 812 | #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ |
<> | 144:ef7eb2e8f9f7 | 813 | |
<> | 144:ef7eb2e8f9f7 | 814 | /* AHBS control register */ |
<> | 144:ef7eb2e8f9f7 | 815 | #define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ |
<> | 144:ef7eb2e8f9f7 | 816 | #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ |
<> | 144:ef7eb2e8f9f7 | 817 | |
<> | 144:ef7eb2e8f9f7 | 818 | #define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ |
<> | 144:ef7eb2e8f9f7 | 819 | #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ |
<> | 144:ef7eb2e8f9f7 | 820 | |
<> | 144:ef7eb2e8f9f7 | 821 | #define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ |
<> | 144:ef7eb2e8f9f7 | 822 | #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ |
<> | 144:ef7eb2e8f9f7 | 823 | |
<> | 144:ef7eb2e8f9f7 | 824 | /* Auxiliary Bus Fault Status Register */ |
<> | 144:ef7eb2e8f9f7 | 825 | #define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ |
<> | 144:ef7eb2e8f9f7 | 826 | #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ |
<> | 144:ef7eb2e8f9f7 | 827 | |
<> | 144:ef7eb2e8f9f7 | 828 | #define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ |
<> | 144:ef7eb2e8f9f7 | 829 | #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ |
<> | 144:ef7eb2e8f9f7 | 830 | |
<> | 144:ef7eb2e8f9f7 | 831 | #define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ |
<> | 144:ef7eb2e8f9f7 | 832 | #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ |
<> | 144:ef7eb2e8f9f7 | 833 | |
<> | 144:ef7eb2e8f9f7 | 834 | #define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ |
<> | 144:ef7eb2e8f9f7 | 835 | #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ |
<> | 144:ef7eb2e8f9f7 | 836 | |
<> | 144:ef7eb2e8f9f7 | 837 | #define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ |
<> | 144:ef7eb2e8f9f7 | 838 | #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ |
<> | 144:ef7eb2e8f9f7 | 839 | |
<> | 144:ef7eb2e8f9f7 | 840 | #define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ |
<> | 144:ef7eb2e8f9f7 | 841 | #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ |
<> | 144:ef7eb2e8f9f7 | 842 | |
<> | 144:ef7eb2e8f9f7 | 843 | /*@} end of group CMSIS_SCB */ |
<> | 144:ef7eb2e8f9f7 | 844 | |
<> | 144:ef7eb2e8f9f7 | 845 | |
<> | 144:ef7eb2e8f9f7 | 846 | /** \ingroup CMSIS_core_register |
<> | 144:ef7eb2e8f9f7 | 847 | \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) |
<> | 144:ef7eb2e8f9f7 | 848 | \brief Type definitions for the System Control and ID Register not in the SCB |
<> | 144:ef7eb2e8f9f7 | 849 | @{ |
<> | 144:ef7eb2e8f9f7 | 850 | */ |
<> | 144:ef7eb2e8f9f7 | 851 | |
<> | 144:ef7eb2e8f9f7 | 852 | /** \brief Structure type to access the System Control and ID Register not in the SCB. |
<> | 144:ef7eb2e8f9f7 | 853 | */ |
<> | 144:ef7eb2e8f9f7 | 854 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 855 | { |
<> | 144:ef7eb2e8f9f7 | 856 | uint32_t RESERVED0[1]; |
<> | 144:ef7eb2e8f9f7 | 857 | __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ |
<> | 144:ef7eb2e8f9f7 | 858 | __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ |
<> | 144:ef7eb2e8f9f7 | 859 | } SCnSCB_Type; |
<> | 144:ef7eb2e8f9f7 | 860 | |
<> | 144:ef7eb2e8f9f7 | 861 | /* Interrupt Controller Type Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 862 | #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ |
<> | 144:ef7eb2e8f9f7 | 863 | #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ |
<> | 144:ef7eb2e8f9f7 | 864 | |
<> | 144:ef7eb2e8f9f7 | 865 | /* Auxiliary Control Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 866 | #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ |
<> | 144:ef7eb2e8f9f7 | 867 | #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ |
<> | 144:ef7eb2e8f9f7 | 868 | |
<> | 144:ef7eb2e8f9f7 | 869 | #define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ |
<> | 144:ef7eb2e8f9f7 | 870 | #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ |
<> | 144:ef7eb2e8f9f7 | 871 | |
<> | 144:ef7eb2e8f9f7 | 872 | #define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ |
<> | 144:ef7eb2e8f9f7 | 873 | #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ |
<> | 144:ef7eb2e8f9f7 | 874 | |
<> | 144:ef7eb2e8f9f7 | 875 | #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ |
<> | 144:ef7eb2e8f9f7 | 876 | #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ |
<> | 144:ef7eb2e8f9f7 | 877 | |
<> | 144:ef7eb2e8f9f7 | 878 | #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ |
<> | 144:ef7eb2e8f9f7 | 879 | #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ |
<> | 144:ef7eb2e8f9f7 | 880 | |
<> | 144:ef7eb2e8f9f7 | 881 | /*@} end of group CMSIS_SCnotSCB */ |
<> | 144:ef7eb2e8f9f7 | 882 | |
<> | 144:ef7eb2e8f9f7 | 883 | |
<> | 144:ef7eb2e8f9f7 | 884 | /** \ingroup CMSIS_core_register |
<> | 144:ef7eb2e8f9f7 | 885 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
<> | 144:ef7eb2e8f9f7 | 886 | \brief Type definitions for the System Timer Registers. |
<> | 144:ef7eb2e8f9f7 | 887 | @{ |
<> | 144:ef7eb2e8f9f7 | 888 | */ |
<> | 144:ef7eb2e8f9f7 | 889 | |
<> | 144:ef7eb2e8f9f7 | 890 | /** \brief Structure type to access the System Timer (SysTick). |
<> | 144:ef7eb2e8f9f7 | 891 | */ |
<> | 144:ef7eb2e8f9f7 | 892 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 893 | { |
<> | 144:ef7eb2e8f9f7 | 894 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
<> | 144:ef7eb2e8f9f7 | 895 | __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
<> | 144:ef7eb2e8f9f7 | 896 | __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
<> | 144:ef7eb2e8f9f7 | 897 | __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
<> | 144:ef7eb2e8f9f7 | 898 | } SysTick_Type; |
<> | 144:ef7eb2e8f9f7 | 899 | |
<> | 144:ef7eb2e8f9f7 | 900 | /* SysTick Control / Status Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 901 | #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ |
<> | 144:ef7eb2e8f9f7 | 902 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
<> | 144:ef7eb2e8f9f7 | 903 | |
<> | 144:ef7eb2e8f9f7 | 904 | #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ |
<> | 144:ef7eb2e8f9f7 | 905 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
<> | 144:ef7eb2e8f9f7 | 906 | |
<> | 144:ef7eb2e8f9f7 | 907 | #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ |
<> | 144:ef7eb2e8f9f7 | 908 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
<> | 144:ef7eb2e8f9f7 | 909 | |
<> | 144:ef7eb2e8f9f7 | 910 | #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ |
<> | 144:ef7eb2e8f9f7 | 911 | #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
<> | 144:ef7eb2e8f9f7 | 912 | |
<> | 144:ef7eb2e8f9f7 | 913 | /* SysTick Reload Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 914 | #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ |
<> | 144:ef7eb2e8f9f7 | 915 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
<> | 144:ef7eb2e8f9f7 | 916 | |
<> | 144:ef7eb2e8f9f7 | 917 | /* SysTick Current Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 918 | #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ |
<> | 144:ef7eb2e8f9f7 | 919 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
<> | 144:ef7eb2e8f9f7 | 920 | |
<> | 144:ef7eb2e8f9f7 | 921 | /* SysTick Calibration Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 922 | #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ |
<> | 144:ef7eb2e8f9f7 | 923 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
<> | 144:ef7eb2e8f9f7 | 924 | |
<> | 144:ef7eb2e8f9f7 | 925 | #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ |
<> | 144:ef7eb2e8f9f7 | 926 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
<> | 144:ef7eb2e8f9f7 | 927 | |
<> | 144:ef7eb2e8f9f7 | 928 | #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ |
<> | 144:ef7eb2e8f9f7 | 929 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
<> | 144:ef7eb2e8f9f7 | 930 | |
<> | 144:ef7eb2e8f9f7 | 931 | /*@} end of group CMSIS_SysTick */ |
<> | 144:ef7eb2e8f9f7 | 932 | |
<> | 144:ef7eb2e8f9f7 | 933 | |
<> | 144:ef7eb2e8f9f7 | 934 | /** \ingroup CMSIS_core_register |
<> | 144:ef7eb2e8f9f7 | 935 | \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) |
<> | 144:ef7eb2e8f9f7 | 936 | \brief Type definitions for the Instrumentation Trace Macrocell (ITM) |
<> | 144:ef7eb2e8f9f7 | 937 | @{ |
<> | 144:ef7eb2e8f9f7 | 938 | */ |
<> | 144:ef7eb2e8f9f7 | 939 | |
<> | 144:ef7eb2e8f9f7 | 940 | /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). |
<> | 144:ef7eb2e8f9f7 | 941 | */ |
<> | 144:ef7eb2e8f9f7 | 942 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 943 | { |
<> | 144:ef7eb2e8f9f7 | 944 | __O union |
<> | 144:ef7eb2e8f9f7 | 945 | { |
<> | 144:ef7eb2e8f9f7 | 946 | __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ |
<> | 144:ef7eb2e8f9f7 | 947 | __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ |
<> | 144:ef7eb2e8f9f7 | 948 | __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ |
<> | 144:ef7eb2e8f9f7 | 949 | } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ |
<> | 144:ef7eb2e8f9f7 | 950 | uint32_t RESERVED0[864]; |
<> | 144:ef7eb2e8f9f7 | 951 | __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ |
<> | 144:ef7eb2e8f9f7 | 952 | uint32_t RESERVED1[15]; |
<> | 144:ef7eb2e8f9f7 | 953 | __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ |
<> | 144:ef7eb2e8f9f7 | 954 | uint32_t RESERVED2[15]; |
<> | 144:ef7eb2e8f9f7 | 955 | __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ |
<> | 144:ef7eb2e8f9f7 | 956 | uint32_t RESERVED3[29]; |
<> | 144:ef7eb2e8f9f7 | 957 | __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ |
<> | 144:ef7eb2e8f9f7 | 958 | __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ |
<> | 144:ef7eb2e8f9f7 | 959 | __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ |
<> | 144:ef7eb2e8f9f7 | 960 | uint32_t RESERVED4[43]; |
<> | 144:ef7eb2e8f9f7 | 961 | __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ |
<> | 144:ef7eb2e8f9f7 | 962 | __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ |
<> | 144:ef7eb2e8f9f7 | 963 | uint32_t RESERVED5[6]; |
<> | 144:ef7eb2e8f9f7 | 964 | __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ |
<> | 144:ef7eb2e8f9f7 | 965 | __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ |
<> | 144:ef7eb2e8f9f7 | 966 | __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ |
<> | 144:ef7eb2e8f9f7 | 967 | __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ |
<> | 144:ef7eb2e8f9f7 | 968 | __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ |
<> | 144:ef7eb2e8f9f7 | 969 | __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ |
<> | 144:ef7eb2e8f9f7 | 970 | __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ |
<> | 144:ef7eb2e8f9f7 | 971 | __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ |
<> | 144:ef7eb2e8f9f7 | 972 | __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ |
<> | 144:ef7eb2e8f9f7 | 973 | __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ |
<> | 144:ef7eb2e8f9f7 | 974 | __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ |
<> | 144:ef7eb2e8f9f7 | 975 | __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ |
<> | 144:ef7eb2e8f9f7 | 976 | } ITM_Type; |
<> | 144:ef7eb2e8f9f7 | 977 | |
<> | 144:ef7eb2e8f9f7 | 978 | /* ITM Trace Privilege Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 979 | #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ |
<> | 144:ef7eb2e8f9f7 | 980 | #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ |
<> | 144:ef7eb2e8f9f7 | 981 | |
<> | 144:ef7eb2e8f9f7 | 982 | /* ITM Trace Control Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 983 | #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ |
<> | 144:ef7eb2e8f9f7 | 984 | #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ |
<> | 144:ef7eb2e8f9f7 | 985 | |
<> | 144:ef7eb2e8f9f7 | 986 | #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ |
<> | 144:ef7eb2e8f9f7 | 987 | #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ |
<> | 144:ef7eb2e8f9f7 | 988 | |
<> | 144:ef7eb2e8f9f7 | 989 | #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ |
<> | 144:ef7eb2e8f9f7 | 990 | #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ |
<> | 144:ef7eb2e8f9f7 | 991 | |
<> | 144:ef7eb2e8f9f7 | 992 | #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ |
<> | 144:ef7eb2e8f9f7 | 993 | #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ |
<> | 144:ef7eb2e8f9f7 | 994 | |
<> | 144:ef7eb2e8f9f7 | 995 | #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ |
<> | 144:ef7eb2e8f9f7 | 996 | #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 997 | |
<> | 144:ef7eb2e8f9f7 | 998 | #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ |
<> | 144:ef7eb2e8f9f7 | 999 | #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 1000 | |
<> | 144:ef7eb2e8f9f7 | 1001 | #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ |
<> | 144:ef7eb2e8f9f7 | 1002 | #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 1003 | |
<> | 144:ef7eb2e8f9f7 | 1004 | #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ |
<> | 144:ef7eb2e8f9f7 | 1005 | #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 1006 | |
<> | 144:ef7eb2e8f9f7 | 1007 | #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ |
<> | 144:ef7eb2e8f9f7 | 1008 | #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ |
<> | 144:ef7eb2e8f9f7 | 1009 | |
<> | 144:ef7eb2e8f9f7 | 1010 | /* ITM Integration Write Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1011 | #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ |
<> | 144:ef7eb2e8f9f7 | 1012 | #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ |
<> | 144:ef7eb2e8f9f7 | 1013 | |
<> | 144:ef7eb2e8f9f7 | 1014 | /* ITM Integration Read Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1015 | #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ |
<> | 144:ef7eb2e8f9f7 | 1016 | #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ |
<> | 144:ef7eb2e8f9f7 | 1017 | |
<> | 144:ef7eb2e8f9f7 | 1018 | /* ITM Integration Mode Control Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1019 | #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ |
<> | 144:ef7eb2e8f9f7 | 1020 | #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ |
<> | 144:ef7eb2e8f9f7 | 1021 | |
<> | 144:ef7eb2e8f9f7 | 1022 | /* ITM Lock Status Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1023 | #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ |
<> | 144:ef7eb2e8f9f7 | 1024 | #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ |
<> | 144:ef7eb2e8f9f7 | 1025 | |
<> | 144:ef7eb2e8f9f7 | 1026 | #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ |
<> | 144:ef7eb2e8f9f7 | 1027 | #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ |
<> | 144:ef7eb2e8f9f7 | 1028 | |
<> | 144:ef7eb2e8f9f7 | 1029 | #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ |
<> | 144:ef7eb2e8f9f7 | 1030 | #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ |
<> | 144:ef7eb2e8f9f7 | 1031 | |
<> | 144:ef7eb2e8f9f7 | 1032 | /*@}*/ /* end of group CMSIS_ITM */ |
<> | 144:ef7eb2e8f9f7 | 1033 | |
<> | 144:ef7eb2e8f9f7 | 1034 | |
<> | 144:ef7eb2e8f9f7 | 1035 | /** \ingroup CMSIS_core_register |
<> | 144:ef7eb2e8f9f7 | 1036 | \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) |
<> | 144:ef7eb2e8f9f7 | 1037 | \brief Type definitions for the Data Watchpoint and Trace (DWT) |
<> | 144:ef7eb2e8f9f7 | 1038 | @{ |
<> | 144:ef7eb2e8f9f7 | 1039 | */ |
<> | 144:ef7eb2e8f9f7 | 1040 | |
<> | 144:ef7eb2e8f9f7 | 1041 | /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). |
<> | 144:ef7eb2e8f9f7 | 1042 | */ |
<> | 144:ef7eb2e8f9f7 | 1043 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 1044 | { |
<> | 144:ef7eb2e8f9f7 | 1045 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ |
<> | 144:ef7eb2e8f9f7 | 1046 | __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ |
<> | 144:ef7eb2e8f9f7 | 1047 | __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ |
<> | 144:ef7eb2e8f9f7 | 1048 | __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ |
<> | 144:ef7eb2e8f9f7 | 1049 | __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ |
<> | 144:ef7eb2e8f9f7 | 1050 | __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ |
<> | 144:ef7eb2e8f9f7 | 1051 | __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ |
<> | 144:ef7eb2e8f9f7 | 1052 | __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ |
<> | 144:ef7eb2e8f9f7 | 1053 | __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ |
<> | 144:ef7eb2e8f9f7 | 1054 | __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ |
<> | 144:ef7eb2e8f9f7 | 1055 | __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ |
<> | 144:ef7eb2e8f9f7 | 1056 | uint32_t RESERVED0[1]; |
<> | 144:ef7eb2e8f9f7 | 1057 | __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ |
<> | 144:ef7eb2e8f9f7 | 1058 | __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ |
<> | 144:ef7eb2e8f9f7 | 1059 | __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ |
<> | 144:ef7eb2e8f9f7 | 1060 | uint32_t RESERVED1[1]; |
<> | 144:ef7eb2e8f9f7 | 1061 | __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ |
<> | 144:ef7eb2e8f9f7 | 1062 | __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ |
<> | 144:ef7eb2e8f9f7 | 1063 | __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ |
<> | 144:ef7eb2e8f9f7 | 1064 | uint32_t RESERVED2[1]; |
<> | 144:ef7eb2e8f9f7 | 1065 | __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ |
<> | 144:ef7eb2e8f9f7 | 1066 | __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ |
<> | 144:ef7eb2e8f9f7 | 1067 | __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ |
<> | 144:ef7eb2e8f9f7 | 1068 | uint32_t RESERVED3[981]; |
<> | 144:ef7eb2e8f9f7 | 1069 | __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ |
<> | 144:ef7eb2e8f9f7 | 1070 | __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ |
<> | 144:ef7eb2e8f9f7 | 1071 | } DWT_Type; |
<> | 144:ef7eb2e8f9f7 | 1072 | |
<> | 144:ef7eb2e8f9f7 | 1073 | /* DWT Control Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1074 | #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ |
<> | 144:ef7eb2e8f9f7 | 1075 | #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ |
<> | 144:ef7eb2e8f9f7 | 1076 | |
<> | 144:ef7eb2e8f9f7 | 1077 | #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ |
<> | 144:ef7eb2e8f9f7 | 1078 | #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ |
<> | 144:ef7eb2e8f9f7 | 1079 | |
<> | 144:ef7eb2e8f9f7 | 1080 | #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ |
<> | 144:ef7eb2e8f9f7 | 1081 | #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ |
<> | 144:ef7eb2e8f9f7 | 1082 | |
<> | 144:ef7eb2e8f9f7 | 1083 | #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ |
<> | 144:ef7eb2e8f9f7 | 1084 | #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ |
<> | 144:ef7eb2e8f9f7 | 1085 | |
<> | 144:ef7eb2e8f9f7 | 1086 | #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ |
<> | 144:ef7eb2e8f9f7 | 1087 | #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ |
<> | 144:ef7eb2e8f9f7 | 1088 | |
<> | 144:ef7eb2e8f9f7 | 1089 | #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ |
<> | 144:ef7eb2e8f9f7 | 1090 | #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 1091 | |
<> | 144:ef7eb2e8f9f7 | 1092 | #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ |
<> | 144:ef7eb2e8f9f7 | 1093 | #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 1094 | |
<> | 144:ef7eb2e8f9f7 | 1095 | #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ |
<> | 144:ef7eb2e8f9f7 | 1096 | #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 1097 | |
<> | 144:ef7eb2e8f9f7 | 1098 | #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ |
<> | 144:ef7eb2e8f9f7 | 1099 | #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 1100 | |
<> | 144:ef7eb2e8f9f7 | 1101 | #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ |
<> | 144:ef7eb2e8f9f7 | 1102 | #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 1103 | |
<> | 144:ef7eb2e8f9f7 | 1104 | #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ |
<> | 144:ef7eb2e8f9f7 | 1105 | #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 1106 | |
<> | 144:ef7eb2e8f9f7 | 1107 | #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ |
<> | 144:ef7eb2e8f9f7 | 1108 | #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 1109 | |
<> | 144:ef7eb2e8f9f7 | 1110 | #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ |
<> | 144:ef7eb2e8f9f7 | 1111 | #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 1112 | |
<> | 144:ef7eb2e8f9f7 | 1113 | #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ |
<> | 144:ef7eb2e8f9f7 | 1114 | #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ |
<> | 144:ef7eb2e8f9f7 | 1115 | |
<> | 144:ef7eb2e8f9f7 | 1116 | #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ |
<> | 144:ef7eb2e8f9f7 | 1117 | #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ |
<> | 144:ef7eb2e8f9f7 | 1118 | |
<> | 144:ef7eb2e8f9f7 | 1119 | #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ |
<> | 144:ef7eb2e8f9f7 | 1120 | #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ |
<> | 144:ef7eb2e8f9f7 | 1121 | |
<> | 144:ef7eb2e8f9f7 | 1122 | #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ |
<> | 144:ef7eb2e8f9f7 | 1123 | #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ |
<> | 144:ef7eb2e8f9f7 | 1124 | |
<> | 144:ef7eb2e8f9f7 | 1125 | #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ |
<> | 144:ef7eb2e8f9f7 | 1126 | #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 1127 | |
<> | 144:ef7eb2e8f9f7 | 1128 | /* DWT CPI Count Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1129 | #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ |
<> | 144:ef7eb2e8f9f7 | 1130 | #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ |
<> | 144:ef7eb2e8f9f7 | 1131 | |
<> | 144:ef7eb2e8f9f7 | 1132 | /* DWT Exception Overhead Count Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1133 | #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ |
<> | 144:ef7eb2e8f9f7 | 1134 | #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ |
<> | 144:ef7eb2e8f9f7 | 1135 | |
<> | 144:ef7eb2e8f9f7 | 1136 | /* DWT Sleep Count Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1137 | #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ |
<> | 144:ef7eb2e8f9f7 | 1138 | #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ |
<> | 144:ef7eb2e8f9f7 | 1139 | |
<> | 144:ef7eb2e8f9f7 | 1140 | /* DWT LSU Count Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1141 | #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ |
<> | 144:ef7eb2e8f9f7 | 1142 | #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ |
<> | 144:ef7eb2e8f9f7 | 1143 | |
<> | 144:ef7eb2e8f9f7 | 1144 | /* DWT Folded-instruction Count Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1145 | #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ |
<> | 144:ef7eb2e8f9f7 | 1146 | #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ |
<> | 144:ef7eb2e8f9f7 | 1147 | |
<> | 144:ef7eb2e8f9f7 | 1148 | /* DWT Comparator Mask Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1149 | #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ |
<> | 144:ef7eb2e8f9f7 | 1150 | #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ |
<> | 144:ef7eb2e8f9f7 | 1151 | |
<> | 144:ef7eb2e8f9f7 | 1152 | /* DWT Comparator Function Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1153 | #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ |
<> | 144:ef7eb2e8f9f7 | 1154 | #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ |
<> | 144:ef7eb2e8f9f7 | 1155 | |
<> | 144:ef7eb2e8f9f7 | 1156 | #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ |
<> | 144:ef7eb2e8f9f7 | 1157 | #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ |
<> | 144:ef7eb2e8f9f7 | 1158 | |
<> | 144:ef7eb2e8f9f7 | 1159 | #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ |
<> | 144:ef7eb2e8f9f7 | 1160 | #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ |
<> | 144:ef7eb2e8f9f7 | 1161 | |
<> | 144:ef7eb2e8f9f7 | 1162 | #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ |
<> | 144:ef7eb2e8f9f7 | 1163 | #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ |
<> | 144:ef7eb2e8f9f7 | 1164 | |
<> | 144:ef7eb2e8f9f7 | 1165 | #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ |
<> | 144:ef7eb2e8f9f7 | 1166 | #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 1167 | |
<> | 144:ef7eb2e8f9f7 | 1168 | #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ |
<> | 144:ef7eb2e8f9f7 | 1169 | #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ |
<> | 144:ef7eb2e8f9f7 | 1170 | |
<> | 144:ef7eb2e8f9f7 | 1171 | #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ |
<> | 144:ef7eb2e8f9f7 | 1172 | #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ |
<> | 144:ef7eb2e8f9f7 | 1173 | |
<> | 144:ef7eb2e8f9f7 | 1174 | #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ |
<> | 144:ef7eb2e8f9f7 | 1175 | #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ |
<> | 144:ef7eb2e8f9f7 | 1176 | |
<> | 144:ef7eb2e8f9f7 | 1177 | #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ |
<> | 144:ef7eb2e8f9f7 | 1178 | #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ |
<> | 144:ef7eb2e8f9f7 | 1179 | |
<> | 144:ef7eb2e8f9f7 | 1180 | /*@}*/ /* end of group CMSIS_DWT */ |
<> | 144:ef7eb2e8f9f7 | 1181 | |
<> | 144:ef7eb2e8f9f7 | 1182 | |
<> | 144:ef7eb2e8f9f7 | 1183 | /** \ingroup CMSIS_core_register |
<> | 144:ef7eb2e8f9f7 | 1184 | \defgroup CMSIS_TPI Trace Port Interface (TPI) |
<> | 144:ef7eb2e8f9f7 | 1185 | \brief Type definitions for the Trace Port Interface (TPI) |
<> | 144:ef7eb2e8f9f7 | 1186 | @{ |
<> | 144:ef7eb2e8f9f7 | 1187 | */ |
<> | 144:ef7eb2e8f9f7 | 1188 | |
<> | 144:ef7eb2e8f9f7 | 1189 | /** \brief Structure type to access the Trace Port Interface Register (TPI). |
<> | 144:ef7eb2e8f9f7 | 1190 | */ |
<> | 144:ef7eb2e8f9f7 | 1191 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 1192 | { |
<> | 144:ef7eb2e8f9f7 | 1193 | __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ |
<> | 144:ef7eb2e8f9f7 | 1194 | __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ |
<> | 144:ef7eb2e8f9f7 | 1195 | uint32_t RESERVED0[2]; |
<> | 144:ef7eb2e8f9f7 | 1196 | __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ |
<> | 144:ef7eb2e8f9f7 | 1197 | uint32_t RESERVED1[55]; |
<> | 144:ef7eb2e8f9f7 | 1198 | __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ |
<> | 144:ef7eb2e8f9f7 | 1199 | uint32_t RESERVED2[131]; |
<> | 144:ef7eb2e8f9f7 | 1200 | __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ |
<> | 144:ef7eb2e8f9f7 | 1201 | __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ |
<> | 144:ef7eb2e8f9f7 | 1202 | __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ |
<> | 144:ef7eb2e8f9f7 | 1203 | uint32_t RESERVED3[759]; |
<> | 144:ef7eb2e8f9f7 | 1204 | __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ |
<> | 144:ef7eb2e8f9f7 | 1205 | __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ |
<> | 144:ef7eb2e8f9f7 | 1206 | __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ |
<> | 144:ef7eb2e8f9f7 | 1207 | uint32_t RESERVED4[1]; |
<> | 144:ef7eb2e8f9f7 | 1208 | __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ |
<> | 144:ef7eb2e8f9f7 | 1209 | __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ |
<> | 144:ef7eb2e8f9f7 | 1210 | __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ |
<> | 144:ef7eb2e8f9f7 | 1211 | uint32_t RESERVED5[39]; |
<> | 144:ef7eb2e8f9f7 | 1212 | __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ |
<> | 144:ef7eb2e8f9f7 | 1213 | __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ |
<> | 144:ef7eb2e8f9f7 | 1214 | uint32_t RESERVED7[8]; |
<> | 144:ef7eb2e8f9f7 | 1215 | __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ |
<> | 144:ef7eb2e8f9f7 | 1216 | __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ |
<> | 144:ef7eb2e8f9f7 | 1217 | } TPI_Type; |
<> | 144:ef7eb2e8f9f7 | 1218 | |
<> | 144:ef7eb2e8f9f7 | 1219 | /* TPI Asynchronous Clock Prescaler Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1220 | #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ |
<> | 144:ef7eb2e8f9f7 | 1221 | #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ |
<> | 144:ef7eb2e8f9f7 | 1222 | |
<> | 144:ef7eb2e8f9f7 | 1223 | /* TPI Selected Pin Protocol Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1224 | #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ |
<> | 144:ef7eb2e8f9f7 | 1225 | #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ |
<> | 144:ef7eb2e8f9f7 | 1226 | |
<> | 144:ef7eb2e8f9f7 | 1227 | /* TPI Formatter and Flush Status Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1228 | #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ |
<> | 144:ef7eb2e8f9f7 | 1229 | #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ |
<> | 144:ef7eb2e8f9f7 | 1230 | |
<> | 144:ef7eb2e8f9f7 | 1231 | #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ |
<> | 144:ef7eb2e8f9f7 | 1232 | #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ |
<> | 144:ef7eb2e8f9f7 | 1233 | |
<> | 144:ef7eb2e8f9f7 | 1234 | #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ |
<> | 144:ef7eb2e8f9f7 | 1235 | #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ |
<> | 144:ef7eb2e8f9f7 | 1236 | |
<> | 144:ef7eb2e8f9f7 | 1237 | #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ |
<> | 144:ef7eb2e8f9f7 | 1238 | #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ |
<> | 144:ef7eb2e8f9f7 | 1239 | |
<> | 144:ef7eb2e8f9f7 | 1240 | /* TPI Formatter and Flush Control Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1241 | #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ |
<> | 144:ef7eb2e8f9f7 | 1242 | #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ |
<> | 144:ef7eb2e8f9f7 | 1243 | |
<> | 144:ef7eb2e8f9f7 | 1244 | #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ |
<> | 144:ef7eb2e8f9f7 | 1245 | #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ |
<> | 144:ef7eb2e8f9f7 | 1246 | |
<> | 144:ef7eb2e8f9f7 | 1247 | /* TPI TRIGGER Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1248 | #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ |
<> | 144:ef7eb2e8f9f7 | 1249 | #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ |
<> | 144:ef7eb2e8f9f7 | 1250 | |
<> | 144:ef7eb2e8f9f7 | 1251 | /* TPI Integration ETM Data Register Definitions (FIFO0) */ |
<> | 144:ef7eb2e8f9f7 | 1252 | #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ |
<> | 144:ef7eb2e8f9f7 | 1253 | #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ |
<> | 144:ef7eb2e8f9f7 | 1254 | |
<> | 144:ef7eb2e8f9f7 | 1255 | #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ |
<> | 144:ef7eb2e8f9f7 | 1256 | #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ |
<> | 144:ef7eb2e8f9f7 | 1257 | |
<> | 144:ef7eb2e8f9f7 | 1258 | #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ |
<> | 144:ef7eb2e8f9f7 | 1259 | #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ |
<> | 144:ef7eb2e8f9f7 | 1260 | |
<> | 144:ef7eb2e8f9f7 | 1261 | #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ |
<> | 144:ef7eb2e8f9f7 | 1262 | #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ |
<> | 144:ef7eb2e8f9f7 | 1263 | |
<> | 144:ef7eb2e8f9f7 | 1264 | #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ |
<> | 144:ef7eb2e8f9f7 | 1265 | #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ |
<> | 144:ef7eb2e8f9f7 | 1266 | |
<> | 144:ef7eb2e8f9f7 | 1267 | #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ |
<> | 144:ef7eb2e8f9f7 | 1268 | #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ |
<> | 144:ef7eb2e8f9f7 | 1269 | |
<> | 144:ef7eb2e8f9f7 | 1270 | #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ |
<> | 144:ef7eb2e8f9f7 | 1271 | #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ |
<> | 144:ef7eb2e8f9f7 | 1272 | |
<> | 144:ef7eb2e8f9f7 | 1273 | /* TPI ITATBCTR2 Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1274 | #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ |
<> | 144:ef7eb2e8f9f7 | 1275 | #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ |
<> | 144:ef7eb2e8f9f7 | 1276 | |
<> | 144:ef7eb2e8f9f7 | 1277 | /* TPI Integration ITM Data Register Definitions (FIFO1) */ |
<> | 144:ef7eb2e8f9f7 | 1278 | #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ |
<> | 144:ef7eb2e8f9f7 | 1279 | #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ |
<> | 144:ef7eb2e8f9f7 | 1280 | |
<> | 144:ef7eb2e8f9f7 | 1281 | #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ |
<> | 144:ef7eb2e8f9f7 | 1282 | #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ |
<> | 144:ef7eb2e8f9f7 | 1283 | |
<> | 144:ef7eb2e8f9f7 | 1284 | #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ |
<> | 144:ef7eb2e8f9f7 | 1285 | #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ |
<> | 144:ef7eb2e8f9f7 | 1286 | |
<> | 144:ef7eb2e8f9f7 | 1287 | #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ |
<> | 144:ef7eb2e8f9f7 | 1288 | #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ |
<> | 144:ef7eb2e8f9f7 | 1289 | |
<> | 144:ef7eb2e8f9f7 | 1290 | #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ |
<> | 144:ef7eb2e8f9f7 | 1291 | #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ |
<> | 144:ef7eb2e8f9f7 | 1292 | |
<> | 144:ef7eb2e8f9f7 | 1293 | #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ |
<> | 144:ef7eb2e8f9f7 | 1294 | #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ |
<> | 144:ef7eb2e8f9f7 | 1295 | |
<> | 144:ef7eb2e8f9f7 | 1296 | #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ |
<> | 144:ef7eb2e8f9f7 | 1297 | #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ |
<> | 144:ef7eb2e8f9f7 | 1298 | |
<> | 144:ef7eb2e8f9f7 | 1299 | /* TPI ITATBCTR0 Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1300 | #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ |
<> | 144:ef7eb2e8f9f7 | 1301 | #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ |
<> | 144:ef7eb2e8f9f7 | 1302 | |
<> | 144:ef7eb2e8f9f7 | 1303 | /* TPI Integration Mode Control Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1304 | #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ |
<> | 144:ef7eb2e8f9f7 | 1305 | #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ |
<> | 144:ef7eb2e8f9f7 | 1306 | |
<> | 144:ef7eb2e8f9f7 | 1307 | /* TPI DEVID Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1308 | #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ |
<> | 144:ef7eb2e8f9f7 | 1309 | #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ |
<> | 144:ef7eb2e8f9f7 | 1310 | |
<> | 144:ef7eb2e8f9f7 | 1311 | #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ |
<> | 144:ef7eb2e8f9f7 | 1312 | #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ |
<> | 144:ef7eb2e8f9f7 | 1313 | |
<> | 144:ef7eb2e8f9f7 | 1314 | #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ |
<> | 144:ef7eb2e8f9f7 | 1315 | #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ |
<> | 144:ef7eb2e8f9f7 | 1316 | |
<> | 144:ef7eb2e8f9f7 | 1317 | #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ |
<> | 144:ef7eb2e8f9f7 | 1318 | #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ |
<> | 144:ef7eb2e8f9f7 | 1319 | |
<> | 144:ef7eb2e8f9f7 | 1320 | #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ |
<> | 144:ef7eb2e8f9f7 | 1321 | #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ |
<> | 144:ef7eb2e8f9f7 | 1322 | |
<> | 144:ef7eb2e8f9f7 | 1323 | #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ |
<> | 144:ef7eb2e8f9f7 | 1324 | #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ |
<> | 144:ef7eb2e8f9f7 | 1325 | |
<> | 144:ef7eb2e8f9f7 | 1326 | /* TPI DEVTYPE Register Definitions */ |
<> | 144:ef7eb2e8f9f7 | 1327 | #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ |
<> | 144:ef7eb2e8f9f7 | 1328 | #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ |
<> | 144:ef7eb2e8f9f7 | 1329 | |
<> | 144:ef7eb2e8f9f7 | 1330 | #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ |
<> | 144:ef7eb2e8f9f7 | 1331 | #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ |
<> | 144:ef7eb2e8f9f7 | 1332 | |
<> | 144:ef7eb2e8f9f7 | 1333 | /*@}*/ /* end of group CMSIS_TPI */ |
<> | 144:ef7eb2e8f9f7 | 1334 | |
<> | 144:ef7eb2e8f9f7 | 1335 | |
<> | 144:ef7eb2e8f9f7 | 1336 | #if (__MPU_PRESENT == 1) |
<> | 144:ef7eb2e8f9f7 | 1337 | /** \ingroup CMSIS_core_register |
<> | 144:ef7eb2e8f9f7 | 1338 | \defgroup CMSIS_MPU Memory Protection Unit (MPU) |
<> | 144:ef7eb2e8f9f7 | 1339 | \brief Type definitions for the Memory Protection Unit (MPU) |
<> | 144:ef7eb2e8f9f7 | 1340 | @{ |
<> | 144:ef7eb2e8f9f7 | 1341 | */ |
<> | 144:ef7eb2e8f9f7 | 1342 | |
<> | 144:ef7eb2e8f9f7 | 1343 | /** \brief Structure type to access the Memory Protection Unit (MPU). |
<> | 144:ef7eb2e8f9f7 | 1344 | */ |
<> | 144:ef7eb2e8f9f7 | 1345 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 1346 | { |
<> | 144:ef7eb2e8f9f7 | 1347 | __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
<> | 144:ef7eb2e8f9f7 | 1348 | __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
<> | 144:ef7eb2e8f9f7 | 1349 | __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ |
<> | 144:ef7eb2e8f9f7 | 1350 | __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
<> | 144:ef7eb2e8f9f7 | 1351 | __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ |
<> | 144:ef7eb2e8f9f7 | 1352 | __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ |
<> | 144:ef7eb2e8f9f7 | 1353 | __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ |
<> | 144:ef7eb2e8f9f7 | 1354 | __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ |
<> | 144:ef7eb2e8f9f7 | 1355 | __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ |
<> | 144:ef7eb2e8f9f7 | 1356 | __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ |
<> | 144:ef7eb2e8f9f7 | 1357 | __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ |
<> | 144:ef7eb2e8f9f7 | 1358 | } MPU_Type; |
<> | 144:ef7eb2e8f9f7 | 1359 | |
<> | 144:ef7eb2e8f9f7 | 1360 | /* MPU Type Register */ |
<> | 144:ef7eb2e8f9f7 | 1361 | #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ |
<> | 144:ef7eb2e8f9f7 | 1362 | #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
<> | 144:ef7eb2e8f9f7 | 1363 | |
<> | 144:ef7eb2e8f9f7 | 1364 | #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ |
<> | 144:ef7eb2e8f9f7 | 1365 | #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
<> | 144:ef7eb2e8f9f7 | 1366 | |
<> | 144:ef7eb2e8f9f7 | 1367 | #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ |
<> | 144:ef7eb2e8f9f7 | 1368 | #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ |
<> | 144:ef7eb2e8f9f7 | 1369 | |
<> | 144:ef7eb2e8f9f7 | 1370 | /* MPU Control Register */ |
<> | 144:ef7eb2e8f9f7 | 1371 | #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ |
<> | 144:ef7eb2e8f9f7 | 1372 | #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 1373 | |
<> | 144:ef7eb2e8f9f7 | 1374 | #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ |
<> | 144:ef7eb2e8f9f7 | 1375 | #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 1376 | |
<> | 144:ef7eb2e8f9f7 | 1377 | #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ |
<> | 144:ef7eb2e8f9f7 | 1378 | #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ |
<> | 144:ef7eb2e8f9f7 | 1379 | |
<> | 144:ef7eb2e8f9f7 | 1380 | /* MPU Region Number Register */ |
<> | 144:ef7eb2e8f9f7 | 1381 | #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ |
<> | 144:ef7eb2e8f9f7 | 1382 | #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ |
<> | 144:ef7eb2e8f9f7 | 1383 | |
<> | 144:ef7eb2e8f9f7 | 1384 | /* MPU Region Base Address Register */ |
<> | 144:ef7eb2e8f9f7 | 1385 | #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ |
<> | 144:ef7eb2e8f9f7 | 1386 | #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
<> | 144:ef7eb2e8f9f7 | 1387 | |
<> | 144:ef7eb2e8f9f7 | 1388 | #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ |
<> | 144:ef7eb2e8f9f7 | 1389 | #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
<> | 144:ef7eb2e8f9f7 | 1390 | |
<> | 144:ef7eb2e8f9f7 | 1391 | #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ |
<> | 144:ef7eb2e8f9f7 | 1392 | #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ |
<> | 144:ef7eb2e8f9f7 | 1393 | |
<> | 144:ef7eb2e8f9f7 | 1394 | /* MPU Region Attribute and Size Register */ |
<> | 144:ef7eb2e8f9f7 | 1395 | #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ |
<> | 144:ef7eb2e8f9f7 | 1396 | #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ |
<> | 144:ef7eb2e8f9f7 | 1397 | |
<> | 144:ef7eb2e8f9f7 | 1398 | #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ |
<> | 144:ef7eb2e8f9f7 | 1399 | #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ |
<> | 144:ef7eb2e8f9f7 | 1400 | |
<> | 144:ef7eb2e8f9f7 | 1401 | #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ |
<> | 144:ef7eb2e8f9f7 | 1402 | #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ |
<> | 144:ef7eb2e8f9f7 | 1403 | |
<> | 144:ef7eb2e8f9f7 | 1404 | #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ |
<> | 144:ef7eb2e8f9f7 | 1405 | #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ |
<> | 144:ef7eb2e8f9f7 | 1406 | |
<> | 144:ef7eb2e8f9f7 | 1407 | #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ |
<> | 144:ef7eb2e8f9f7 | 1408 | #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ |
<> | 144:ef7eb2e8f9f7 | 1409 | |
<> | 144:ef7eb2e8f9f7 | 1410 | #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ |
<> | 144:ef7eb2e8f9f7 | 1411 | #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ |
<> | 144:ef7eb2e8f9f7 | 1412 | |
<> | 144:ef7eb2e8f9f7 | 1413 | #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ |
<> | 144:ef7eb2e8f9f7 | 1414 | #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ |
<> | 144:ef7eb2e8f9f7 | 1415 | |
<> | 144:ef7eb2e8f9f7 | 1416 | #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ |
<> | 144:ef7eb2e8f9f7 | 1417 | #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
<> | 144:ef7eb2e8f9f7 | 1418 | |
<> | 144:ef7eb2e8f9f7 | 1419 | #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ |
<> | 144:ef7eb2e8f9f7 | 1420 | #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
<> | 144:ef7eb2e8f9f7 | 1421 | |
<> | 144:ef7eb2e8f9f7 | 1422 | #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ |
<> | 144:ef7eb2e8f9f7 | 1423 | #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ |
<> | 144:ef7eb2e8f9f7 | 1424 | |
<> | 144:ef7eb2e8f9f7 | 1425 | /*@} end of group CMSIS_MPU */ |
<> | 144:ef7eb2e8f9f7 | 1426 | #endif |
<> | 144:ef7eb2e8f9f7 | 1427 | |
<> | 144:ef7eb2e8f9f7 | 1428 | |
<> | 144:ef7eb2e8f9f7 | 1429 | #if (__FPU_PRESENT == 1) |
<> | 144:ef7eb2e8f9f7 | 1430 | /** \ingroup CMSIS_core_register |
<> | 144:ef7eb2e8f9f7 | 1431 | \defgroup CMSIS_FPU Floating Point Unit (FPU) |
<> | 144:ef7eb2e8f9f7 | 1432 | \brief Type definitions for the Floating Point Unit (FPU) |
<> | 144:ef7eb2e8f9f7 | 1433 | @{ |
<> | 144:ef7eb2e8f9f7 | 1434 | */ |
<> | 144:ef7eb2e8f9f7 | 1435 | |
<> | 144:ef7eb2e8f9f7 | 1436 | /** \brief Structure type to access the Floating Point Unit (FPU). |
<> | 144:ef7eb2e8f9f7 | 1437 | */ |
<> | 144:ef7eb2e8f9f7 | 1438 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 1439 | { |
<> | 144:ef7eb2e8f9f7 | 1440 | uint32_t RESERVED0[1]; |
<> | 144:ef7eb2e8f9f7 | 1441 | __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ |
<> | 144:ef7eb2e8f9f7 | 1442 | __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ |
<> | 144:ef7eb2e8f9f7 | 1443 | __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ |
<> | 144:ef7eb2e8f9f7 | 1444 | __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ |
<> | 144:ef7eb2e8f9f7 | 1445 | __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ |
<> | 144:ef7eb2e8f9f7 | 1446 | __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ |
<> | 144:ef7eb2e8f9f7 | 1447 | } FPU_Type; |
<> | 144:ef7eb2e8f9f7 | 1448 | |
<> | 144:ef7eb2e8f9f7 | 1449 | /* Floating-Point Context Control Register */ |
<> | 144:ef7eb2e8f9f7 | 1450 | #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ |
<> | 144:ef7eb2e8f9f7 | 1451 | #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ |
<> | 144:ef7eb2e8f9f7 | 1452 | |
<> | 144:ef7eb2e8f9f7 | 1453 | #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ |
<> | 144:ef7eb2e8f9f7 | 1454 | #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ |
<> | 144:ef7eb2e8f9f7 | 1455 | |
<> | 144:ef7eb2e8f9f7 | 1456 | #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ |
<> | 144:ef7eb2e8f9f7 | 1457 | #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ |
<> | 144:ef7eb2e8f9f7 | 1458 | |
<> | 144:ef7eb2e8f9f7 | 1459 | #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ |
<> | 144:ef7eb2e8f9f7 | 1460 | #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ |
<> | 144:ef7eb2e8f9f7 | 1461 | |
<> | 144:ef7eb2e8f9f7 | 1462 | #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ |
<> | 144:ef7eb2e8f9f7 | 1463 | #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ |
<> | 144:ef7eb2e8f9f7 | 1464 | |
<> | 144:ef7eb2e8f9f7 | 1465 | #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ |
<> | 144:ef7eb2e8f9f7 | 1466 | #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ |
<> | 144:ef7eb2e8f9f7 | 1467 | |
<> | 144:ef7eb2e8f9f7 | 1468 | #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ |
<> | 144:ef7eb2e8f9f7 | 1469 | #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ |
<> | 144:ef7eb2e8f9f7 | 1470 | |
<> | 144:ef7eb2e8f9f7 | 1471 | #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ |
<> | 144:ef7eb2e8f9f7 | 1472 | #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ |
<> | 144:ef7eb2e8f9f7 | 1473 | |
<> | 144:ef7eb2e8f9f7 | 1474 | #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ |
<> | 144:ef7eb2e8f9f7 | 1475 | #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ |
<> | 144:ef7eb2e8f9f7 | 1476 | |
<> | 144:ef7eb2e8f9f7 | 1477 | /* Floating-Point Context Address Register */ |
<> | 144:ef7eb2e8f9f7 | 1478 | #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ |
<> | 144:ef7eb2e8f9f7 | 1479 | #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ |
<> | 144:ef7eb2e8f9f7 | 1480 | |
<> | 144:ef7eb2e8f9f7 | 1481 | /* Floating-Point Default Status Control Register */ |
<> | 144:ef7eb2e8f9f7 | 1482 | #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ |
<> | 144:ef7eb2e8f9f7 | 1483 | #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ |
<> | 144:ef7eb2e8f9f7 | 1484 | |
<> | 144:ef7eb2e8f9f7 | 1485 | #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ |
<> | 144:ef7eb2e8f9f7 | 1486 | #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ |
<> | 144:ef7eb2e8f9f7 | 1487 | |
<> | 144:ef7eb2e8f9f7 | 1488 | #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ |
<> | 144:ef7eb2e8f9f7 | 1489 | #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ |
<> | 144:ef7eb2e8f9f7 | 1490 | |
<> | 144:ef7eb2e8f9f7 | 1491 | #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ |
<> | 144:ef7eb2e8f9f7 | 1492 | #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ |
<> | 144:ef7eb2e8f9f7 | 1493 | |
<> | 144:ef7eb2e8f9f7 | 1494 | /* Media and FP Feature Register 0 */ |
<> | 144:ef7eb2e8f9f7 | 1495 | #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ |
<> | 144:ef7eb2e8f9f7 | 1496 | #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ |
<> | 144:ef7eb2e8f9f7 | 1497 | |
<> | 144:ef7eb2e8f9f7 | 1498 | #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ |
<> | 144:ef7eb2e8f9f7 | 1499 | #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ |
<> | 144:ef7eb2e8f9f7 | 1500 | |
<> | 144:ef7eb2e8f9f7 | 1501 | #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ |
<> | 144:ef7eb2e8f9f7 | 1502 | #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ |
<> | 144:ef7eb2e8f9f7 | 1503 | |
<> | 144:ef7eb2e8f9f7 | 1504 | #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ |
<> | 144:ef7eb2e8f9f7 | 1505 | #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ |
<> | 144:ef7eb2e8f9f7 | 1506 | |
<> | 144:ef7eb2e8f9f7 | 1507 | #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ |
<> | 144:ef7eb2e8f9f7 | 1508 | #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ |
<> | 144:ef7eb2e8f9f7 | 1509 | |
<> | 144:ef7eb2e8f9f7 | 1510 | #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ |
<> | 144:ef7eb2e8f9f7 | 1511 | #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ |
<> | 144:ef7eb2e8f9f7 | 1512 | |
<> | 144:ef7eb2e8f9f7 | 1513 | #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ |
<> | 144:ef7eb2e8f9f7 | 1514 | #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ |
<> | 144:ef7eb2e8f9f7 | 1515 | |
<> | 144:ef7eb2e8f9f7 | 1516 | #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ |
<> | 144:ef7eb2e8f9f7 | 1517 | #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ |
<> | 144:ef7eb2e8f9f7 | 1518 | |
<> | 144:ef7eb2e8f9f7 | 1519 | /* Media and FP Feature Register 1 */ |
<> | 144:ef7eb2e8f9f7 | 1520 | #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ |
<> | 144:ef7eb2e8f9f7 | 1521 | #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ |
<> | 144:ef7eb2e8f9f7 | 1522 | |
<> | 144:ef7eb2e8f9f7 | 1523 | #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ |
<> | 144:ef7eb2e8f9f7 | 1524 | #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ |
<> | 144:ef7eb2e8f9f7 | 1525 | |
<> | 144:ef7eb2e8f9f7 | 1526 | #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ |
<> | 144:ef7eb2e8f9f7 | 1527 | #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ |
<> | 144:ef7eb2e8f9f7 | 1528 | |
<> | 144:ef7eb2e8f9f7 | 1529 | #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ |
<> | 144:ef7eb2e8f9f7 | 1530 | #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ |
<> | 144:ef7eb2e8f9f7 | 1531 | |
<> | 144:ef7eb2e8f9f7 | 1532 | /* Media and FP Feature Register 2 */ |
<> | 144:ef7eb2e8f9f7 | 1533 | |
<> | 144:ef7eb2e8f9f7 | 1534 | /*@} end of group CMSIS_FPU */ |
<> | 144:ef7eb2e8f9f7 | 1535 | #endif |
<> | 144:ef7eb2e8f9f7 | 1536 | |
<> | 144:ef7eb2e8f9f7 | 1537 | |
<> | 144:ef7eb2e8f9f7 | 1538 | /** \ingroup CMSIS_core_register |
<> | 144:ef7eb2e8f9f7 | 1539 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
<> | 144:ef7eb2e8f9f7 | 1540 | \brief Type definitions for the Core Debug Registers |
<> | 144:ef7eb2e8f9f7 | 1541 | @{ |
<> | 144:ef7eb2e8f9f7 | 1542 | */ |
<> | 144:ef7eb2e8f9f7 | 1543 | |
<> | 144:ef7eb2e8f9f7 | 1544 | /** \brief Structure type to access the Core Debug Register (CoreDebug). |
<> | 144:ef7eb2e8f9f7 | 1545 | */ |
<> | 144:ef7eb2e8f9f7 | 1546 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 1547 | { |
<> | 144:ef7eb2e8f9f7 | 1548 | __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ |
<> | 144:ef7eb2e8f9f7 | 1549 | __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ |
<> | 144:ef7eb2e8f9f7 | 1550 | __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ |
<> | 144:ef7eb2e8f9f7 | 1551 | __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ |
<> | 144:ef7eb2e8f9f7 | 1552 | } CoreDebug_Type; |
<> | 144:ef7eb2e8f9f7 | 1553 | |
<> | 144:ef7eb2e8f9f7 | 1554 | /* Debug Halting Control and Status Register */ |
<> | 144:ef7eb2e8f9f7 | 1555 | #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ |
<> | 144:ef7eb2e8f9f7 | 1556 | #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ |
<> | 144:ef7eb2e8f9f7 | 1557 | |
<> | 144:ef7eb2e8f9f7 | 1558 | #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ |
<> | 144:ef7eb2e8f9f7 | 1559 | #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ |
<> | 144:ef7eb2e8f9f7 | 1560 | |
<> | 144:ef7eb2e8f9f7 | 1561 | #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ |
<> | 144:ef7eb2e8f9f7 | 1562 | #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ |
<> | 144:ef7eb2e8f9f7 | 1563 | |
<> | 144:ef7eb2e8f9f7 | 1564 | #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ |
<> | 144:ef7eb2e8f9f7 | 1565 | #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ |
<> | 144:ef7eb2e8f9f7 | 1566 | |
<> | 144:ef7eb2e8f9f7 | 1567 | #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ |
<> | 144:ef7eb2e8f9f7 | 1568 | #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ |
<> | 144:ef7eb2e8f9f7 | 1569 | |
<> | 144:ef7eb2e8f9f7 | 1570 | #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ |
<> | 144:ef7eb2e8f9f7 | 1571 | #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ |
<> | 144:ef7eb2e8f9f7 | 1572 | |
<> | 144:ef7eb2e8f9f7 | 1573 | #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ |
<> | 144:ef7eb2e8f9f7 | 1574 | #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ |
<> | 144:ef7eb2e8f9f7 | 1575 | |
<> | 144:ef7eb2e8f9f7 | 1576 | #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ |
<> | 144:ef7eb2e8f9f7 | 1577 | #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ |
<> | 144:ef7eb2e8f9f7 | 1578 | |
<> | 144:ef7eb2e8f9f7 | 1579 | #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ |
<> | 144:ef7eb2e8f9f7 | 1580 | #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ |
<> | 144:ef7eb2e8f9f7 | 1581 | |
<> | 144:ef7eb2e8f9f7 | 1582 | #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ |
<> | 144:ef7eb2e8f9f7 | 1583 | #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ |
<> | 144:ef7eb2e8f9f7 | 1584 | |
<> | 144:ef7eb2e8f9f7 | 1585 | #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ |
<> | 144:ef7eb2e8f9f7 | 1586 | #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ |
<> | 144:ef7eb2e8f9f7 | 1587 | |
<> | 144:ef7eb2e8f9f7 | 1588 | #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ |
<> | 144:ef7eb2e8f9f7 | 1589 | #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ |
<> | 144:ef7eb2e8f9f7 | 1590 | |
<> | 144:ef7eb2e8f9f7 | 1591 | /* Debug Core Register Selector Register */ |
<> | 144:ef7eb2e8f9f7 | 1592 | #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ |
<> | 144:ef7eb2e8f9f7 | 1593 | #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ |
<> | 144:ef7eb2e8f9f7 | 1594 | |
<> | 144:ef7eb2e8f9f7 | 1595 | #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ |
<> | 144:ef7eb2e8f9f7 | 1596 | #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ |
<> | 144:ef7eb2e8f9f7 | 1597 | |
<> | 144:ef7eb2e8f9f7 | 1598 | /* Debug Exception and Monitor Control Register */ |
<> | 144:ef7eb2e8f9f7 | 1599 | #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ |
<> | 144:ef7eb2e8f9f7 | 1600 | #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 1601 | |
<> | 144:ef7eb2e8f9f7 | 1602 | #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ |
<> | 144:ef7eb2e8f9f7 | 1603 | #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ |
<> | 144:ef7eb2e8f9f7 | 1604 | |
<> | 144:ef7eb2e8f9f7 | 1605 | #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ |
<> | 144:ef7eb2e8f9f7 | 1606 | #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ |
<> | 144:ef7eb2e8f9f7 | 1607 | |
<> | 144:ef7eb2e8f9f7 | 1608 | #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ |
<> | 144:ef7eb2e8f9f7 | 1609 | #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ |
<> | 144:ef7eb2e8f9f7 | 1610 | |
<> | 144:ef7eb2e8f9f7 | 1611 | #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ |
<> | 144:ef7eb2e8f9f7 | 1612 | #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ |
<> | 144:ef7eb2e8f9f7 | 1613 | |
<> | 144:ef7eb2e8f9f7 | 1614 | #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ |
<> | 144:ef7eb2e8f9f7 | 1615 | #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ |
<> | 144:ef7eb2e8f9f7 | 1616 | |
<> | 144:ef7eb2e8f9f7 | 1617 | #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ |
<> | 144:ef7eb2e8f9f7 | 1618 | #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ |
<> | 144:ef7eb2e8f9f7 | 1619 | |
<> | 144:ef7eb2e8f9f7 | 1620 | #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ |
<> | 144:ef7eb2e8f9f7 | 1621 | #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ |
<> | 144:ef7eb2e8f9f7 | 1622 | |
<> | 144:ef7eb2e8f9f7 | 1623 | #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ |
<> | 144:ef7eb2e8f9f7 | 1624 | #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ |
<> | 144:ef7eb2e8f9f7 | 1625 | |
<> | 144:ef7eb2e8f9f7 | 1626 | #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ |
<> | 144:ef7eb2e8f9f7 | 1627 | #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ |
<> | 144:ef7eb2e8f9f7 | 1628 | |
<> | 144:ef7eb2e8f9f7 | 1629 | #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ |
<> | 144:ef7eb2e8f9f7 | 1630 | #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ |
<> | 144:ef7eb2e8f9f7 | 1631 | |
<> | 144:ef7eb2e8f9f7 | 1632 | #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ |
<> | 144:ef7eb2e8f9f7 | 1633 | #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ |
<> | 144:ef7eb2e8f9f7 | 1634 | |
<> | 144:ef7eb2e8f9f7 | 1635 | #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ |
<> | 144:ef7eb2e8f9f7 | 1636 | #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ |
<> | 144:ef7eb2e8f9f7 | 1637 | |
<> | 144:ef7eb2e8f9f7 | 1638 | /*@} end of group CMSIS_CoreDebug */ |
<> | 144:ef7eb2e8f9f7 | 1639 | |
<> | 144:ef7eb2e8f9f7 | 1640 | |
<> | 144:ef7eb2e8f9f7 | 1641 | /** \ingroup CMSIS_core_register |
<> | 144:ef7eb2e8f9f7 | 1642 | \defgroup CMSIS_core_base Core Definitions |
<> | 144:ef7eb2e8f9f7 | 1643 | \brief Definitions for base addresses, unions, and structures. |
<> | 144:ef7eb2e8f9f7 | 1644 | @{ |
<> | 144:ef7eb2e8f9f7 | 1645 | */ |
<> | 144:ef7eb2e8f9f7 | 1646 | |
<> | 144:ef7eb2e8f9f7 | 1647 | /* Memory mapping of Cortex-M4 Hardware */ |
<> | 144:ef7eb2e8f9f7 | 1648 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
<> | 144:ef7eb2e8f9f7 | 1649 | #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ |
<> | 144:ef7eb2e8f9f7 | 1650 | #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ |
<> | 144:ef7eb2e8f9f7 | 1651 | #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ |
<> | 144:ef7eb2e8f9f7 | 1652 | #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ |
<> | 144:ef7eb2e8f9f7 | 1653 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
<> | 144:ef7eb2e8f9f7 | 1654 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
<> | 144:ef7eb2e8f9f7 | 1655 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
<> | 144:ef7eb2e8f9f7 | 1656 | |
<> | 144:ef7eb2e8f9f7 | 1657 | #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ |
<> | 144:ef7eb2e8f9f7 | 1658 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
<> | 144:ef7eb2e8f9f7 | 1659 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
<> | 144:ef7eb2e8f9f7 | 1660 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
<> | 144:ef7eb2e8f9f7 | 1661 | #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ |
<> | 144:ef7eb2e8f9f7 | 1662 | #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ |
<> | 144:ef7eb2e8f9f7 | 1663 | #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ |
<> | 144:ef7eb2e8f9f7 | 1664 | #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ |
<> | 144:ef7eb2e8f9f7 | 1665 | |
<> | 144:ef7eb2e8f9f7 | 1666 | #if (__MPU_PRESENT == 1) |
<> | 144:ef7eb2e8f9f7 | 1667 | #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
<> | 144:ef7eb2e8f9f7 | 1668 | #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
<> | 144:ef7eb2e8f9f7 | 1669 | #endif |
<> | 144:ef7eb2e8f9f7 | 1670 | |
<> | 144:ef7eb2e8f9f7 | 1671 | #if (__FPU_PRESENT == 1) |
<> | 144:ef7eb2e8f9f7 | 1672 | #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ |
<> | 144:ef7eb2e8f9f7 | 1673 | #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ |
<> | 144:ef7eb2e8f9f7 | 1674 | #endif |
<> | 144:ef7eb2e8f9f7 | 1675 | |
<> | 144:ef7eb2e8f9f7 | 1676 | /*@} */ |
<> | 144:ef7eb2e8f9f7 | 1677 | |
<> | 144:ef7eb2e8f9f7 | 1678 | |
<> | 144:ef7eb2e8f9f7 | 1679 | |
<> | 144:ef7eb2e8f9f7 | 1680 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 1681 | * Hardware Abstraction Layer |
<> | 144:ef7eb2e8f9f7 | 1682 | Core Function Interface contains: |
<> | 144:ef7eb2e8f9f7 | 1683 | - Core NVIC Functions |
<> | 144:ef7eb2e8f9f7 | 1684 | - Core SysTick Functions |
<> | 144:ef7eb2e8f9f7 | 1685 | - Core Debug Functions |
<> | 144:ef7eb2e8f9f7 | 1686 | - Core Register Access Functions |
<> | 144:ef7eb2e8f9f7 | 1687 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 1688 | /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
<> | 144:ef7eb2e8f9f7 | 1689 | */ |
<> | 144:ef7eb2e8f9f7 | 1690 | |
<> | 144:ef7eb2e8f9f7 | 1691 | |
<> | 144:ef7eb2e8f9f7 | 1692 | |
<> | 144:ef7eb2e8f9f7 | 1693 | /* ########################## NVIC functions #################################### */ |
<> | 144:ef7eb2e8f9f7 | 1694 | /** \ingroup CMSIS_Core_FunctionInterface |
<> | 144:ef7eb2e8f9f7 | 1695 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
<> | 144:ef7eb2e8f9f7 | 1696 | \brief Functions that manage interrupts and exceptions via the NVIC. |
<> | 144:ef7eb2e8f9f7 | 1697 | @{ |
<> | 144:ef7eb2e8f9f7 | 1698 | */ |
<> | 144:ef7eb2e8f9f7 | 1699 | |
<> | 144:ef7eb2e8f9f7 | 1700 | /** \brief Set Priority Grouping |
<> | 144:ef7eb2e8f9f7 | 1701 | |
<> | 144:ef7eb2e8f9f7 | 1702 | The function sets the priority grouping field using the required unlock sequence. |
<> | 144:ef7eb2e8f9f7 | 1703 | The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. |
<> | 144:ef7eb2e8f9f7 | 1704 | Only values from 0..7 are used. |
<> | 144:ef7eb2e8f9f7 | 1705 | In case of a conflict between priority grouping and available |
<> | 144:ef7eb2e8f9f7 | 1706 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
<> | 144:ef7eb2e8f9f7 | 1707 | |
<> | 144:ef7eb2e8f9f7 | 1708 | \param [in] PriorityGroup Priority grouping field. |
<> | 144:ef7eb2e8f9f7 | 1709 | */ |
<> | 144:ef7eb2e8f9f7 | 1710 | __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) |
<> | 144:ef7eb2e8f9f7 | 1711 | { |
<> | 144:ef7eb2e8f9f7 | 1712 | uint32_t reg_value; |
<> | 144:ef7eb2e8f9f7 | 1713 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
<> | 144:ef7eb2e8f9f7 | 1714 | |
<> | 144:ef7eb2e8f9f7 | 1715 | reg_value = SCB->AIRCR; /* read old register configuration */ |
<> | 144:ef7eb2e8f9f7 | 1716 | reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ |
<> | 144:ef7eb2e8f9f7 | 1717 | reg_value = (reg_value | |
<> | 144:ef7eb2e8f9f7 | 1718 | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
<> | 144:ef7eb2e8f9f7 | 1719 | (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ |
<> | 144:ef7eb2e8f9f7 | 1720 | SCB->AIRCR = reg_value; |
<> | 144:ef7eb2e8f9f7 | 1721 | } |
<> | 144:ef7eb2e8f9f7 | 1722 | |
<> | 144:ef7eb2e8f9f7 | 1723 | |
<> | 144:ef7eb2e8f9f7 | 1724 | /** \brief Get Priority Grouping |
<> | 144:ef7eb2e8f9f7 | 1725 | |
<> | 144:ef7eb2e8f9f7 | 1726 | The function reads the priority grouping field from the NVIC Interrupt Controller. |
<> | 144:ef7eb2e8f9f7 | 1727 | |
<> | 144:ef7eb2e8f9f7 | 1728 | \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). |
<> | 144:ef7eb2e8f9f7 | 1729 | */ |
<> | 144:ef7eb2e8f9f7 | 1730 | __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) |
<> | 144:ef7eb2e8f9f7 | 1731 | { |
<> | 144:ef7eb2e8f9f7 | 1732 | return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); |
<> | 144:ef7eb2e8f9f7 | 1733 | } |
<> | 144:ef7eb2e8f9f7 | 1734 | |
<> | 144:ef7eb2e8f9f7 | 1735 | |
<> | 144:ef7eb2e8f9f7 | 1736 | /** \brief Enable External Interrupt |
<> | 144:ef7eb2e8f9f7 | 1737 | |
<> | 144:ef7eb2e8f9f7 | 1738 | The function enables a device-specific interrupt in the NVIC interrupt controller. |
<> | 144:ef7eb2e8f9f7 | 1739 | |
<> | 144:ef7eb2e8f9f7 | 1740 | \param [in] IRQn External interrupt number. Value cannot be negative. |
<> | 144:ef7eb2e8f9f7 | 1741 | */ |
<> | 144:ef7eb2e8f9f7 | 1742 | __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
<> | 144:ef7eb2e8f9f7 | 1743 | { |
<> | 144:ef7eb2e8f9f7 | 1744 | NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
<> | 144:ef7eb2e8f9f7 | 1745 | } |
<> | 144:ef7eb2e8f9f7 | 1746 | |
<> | 144:ef7eb2e8f9f7 | 1747 | |
<> | 144:ef7eb2e8f9f7 | 1748 | /** \brief Disable External Interrupt |
<> | 144:ef7eb2e8f9f7 | 1749 | |
<> | 144:ef7eb2e8f9f7 | 1750 | The function disables a device-specific interrupt in the NVIC interrupt controller. |
<> | 144:ef7eb2e8f9f7 | 1751 | |
<> | 144:ef7eb2e8f9f7 | 1752 | \param [in] IRQn External interrupt number. Value cannot be negative. |
<> | 144:ef7eb2e8f9f7 | 1753 | */ |
<> | 144:ef7eb2e8f9f7 | 1754 | __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
<> | 144:ef7eb2e8f9f7 | 1755 | { |
<> | 144:ef7eb2e8f9f7 | 1756 | NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
<> | 152:9a67f0b066fc | 1757 | __DSB(); |
<> | 152:9a67f0b066fc | 1758 | __ISB(); |
<> | 144:ef7eb2e8f9f7 | 1759 | } |
<> | 144:ef7eb2e8f9f7 | 1760 | |
<> | 144:ef7eb2e8f9f7 | 1761 | |
<> | 144:ef7eb2e8f9f7 | 1762 | /** \brief Get Pending Interrupt |
<> | 144:ef7eb2e8f9f7 | 1763 | |
<> | 144:ef7eb2e8f9f7 | 1764 | The function reads the pending register in the NVIC and returns the pending bit |
<> | 144:ef7eb2e8f9f7 | 1765 | for the specified interrupt. |
<> | 144:ef7eb2e8f9f7 | 1766 | |
<> | 144:ef7eb2e8f9f7 | 1767 | \param [in] IRQn Interrupt number. |
<> | 144:ef7eb2e8f9f7 | 1768 | |
<> | 144:ef7eb2e8f9f7 | 1769 | \return 0 Interrupt status is not pending. |
<> | 144:ef7eb2e8f9f7 | 1770 | \return 1 Interrupt status is pending. |
<> | 144:ef7eb2e8f9f7 | 1771 | */ |
<> | 144:ef7eb2e8f9f7 | 1772 | __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
<> | 144:ef7eb2e8f9f7 | 1773 | { |
<> | 144:ef7eb2e8f9f7 | 1774 | return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
<> | 144:ef7eb2e8f9f7 | 1775 | } |
<> | 144:ef7eb2e8f9f7 | 1776 | |
<> | 144:ef7eb2e8f9f7 | 1777 | |
<> | 144:ef7eb2e8f9f7 | 1778 | /** \brief Set Pending Interrupt |
<> | 144:ef7eb2e8f9f7 | 1779 | |
<> | 144:ef7eb2e8f9f7 | 1780 | The function sets the pending bit of an external interrupt. |
<> | 144:ef7eb2e8f9f7 | 1781 | |
<> | 144:ef7eb2e8f9f7 | 1782 | \param [in] IRQn Interrupt number. Value cannot be negative. |
<> | 144:ef7eb2e8f9f7 | 1783 | */ |
<> | 144:ef7eb2e8f9f7 | 1784 | __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
<> | 144:ef7eb2e8f9f7 | 1785 | { |
<> | 144:ef7eb2e8f9f7 | 1786 | NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
<> | 144:ef7eb2e8f9f7 | 1787 | } |
<> | 144:ef7eb2e8f9f7 | 1788 | |
<> | 144:ef7eb2e8f9f7 | 1789 | |
<> | 144:ef7eb2e8f9f7 | 1790 | /** \brief Clear Pending Interrupt |
<> | 144:ef7eb2e8f9f7 | 1791 | |
<> | 144:ef7eb2e8f9f7 | 1792 | The function clears the pending bit of an external interrupt. |
<> | 144:ef7eb2e8f9f7 | 1793 | |
<> | 144:ef7eb2e8f9f7 | 1794 | \param [in] IRQn External interrupt number. Value cannot be negative. |
<> | 144:ef7eb2e8f9f7 | 1795 | */ |
<> | 144:ef7eb2e8f9f7 | 1796 | __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
<> | 144:ef7eb2e8f9f7 | 1797 | { |
<> | 144:ef7eb2e8f9f7 | 1798 | NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
<> | 144:ef7eb2e8f9f7 | 1799 | } |
<> | 144:ef7eb2e8f9f7 | 1800 | |
<> | 144:ef7eb2e8f9f7 | 1801 | |
<> | 144:ef7eb2e8f9f7 | 1802 | /** \brief Get Active Interrupt |
<> | 144:ef7eb2e8f9f7 | 1803 | |
<> | 144:ef7eb2e8f9f7 | 1804 | The function reads the active register in NVIC and returns the active bit. |
<> | 144:ef7eb2e8f9f7 | 1805 | |
<> | 144:ef7eb2e8f9f7 | 1806 | \param [in] IRQn Interrupt number. |
<> | 144:ef7eb2e8f9f7 | 1807 | |
<> | 144:ef7eb2e8f9f7 | 1808 | \return 0 Interrupt status is not active. |
<> | 144:ef7eb2e8f9f7 | 1809 | \return 1 Interrupt status is active. |
<> | 144:ef7eb2e8f9f7 | 1810 | */ |
<> | 144:ef7eb2e8f9f7 | 1811 | __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) |
<> | 144:ef7eb2e8f9f7 | 1812 | { |
<> | 144:ef7eb2e8f9f7 | 1813 | return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
<> | 144:ef7eb2e8f9f7 | 1814 | } |
<> | 144:ef7eb2e8f9f7 | 1815 | |
<> | 144:ef7eb2e8f9f7 | 1816 | |
<> | 144:ef7eb2e8f9f7 | 1817 | /** \brief Set Interrupt Priority |
<> | 144:ef7eb2e8f9f7 | 1818 | |
<> | 144:ef7eb2e8f9f7 | 1819 | The function sets the priority of an interrupt. |
<> | 144:ef7eb2e8f9f7 | 1820 | |
<> | 144:ef7eb2e8f9f7 | 1821 | \note The priority cannot be set for every core interrupt. |
<> | 144:ef7eb2e8f9f7 | 1822 | |
<> | 144:ef7eb2e8f9f7 | 1823 | \param [in] IRQn Interrupt number. |
<> | 144:ef7eb2e8f9f7 | 1824 | \param [in] priority Priority to set. |
<> | 144:ef7eb2e8f9f7 | 1825 | */ |
<> | 144:ef7eb2e8f9f7 | 1826 | __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
<> | 144:ef7eb2e8f9f7 | 1827 | { |
<> | 144:ef7eb2e8f9f7 | 1828 | if((int32_t)IRQn < 0) { |
<> | 144:ef7eb2e8f9f7 | 1829 | SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); |
<> | 144:ef7eb2e8f9f7 | 1830 | } |
<> | 144:ef7eb2e8f9f7 | 1831 | else { |
<> | 144:ef7eb2e8f9f7 | 1832 | NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); |
<> | 144:ef7eb2e8f9f7 | 1833 | } |
<> | 144:ef7eb2e8f9f7 | 1834 | } |
<> | 144:ef7eb2e8f9f7 | 1835 | |
<> | 144:ef7eb2e8f9f7 | 1836 | |
<> | 144:ef7eb2e8f9f7 | 1837 | /** \brief Get Interrupt Priority |
<> | 144:ef7eb2e8f9f7 | 1838 | |
<> | 144:ef7eb2e8f9f7 | 1839 | The function reads the priority of an interrupt. The interrupt |
<> | 144:ef7eb2e8f9f7 | 1840 | number can be positive to specify an external (device specific) |
<> | 144:ef7eb2e8f9f7 | 1841 | interrupt, or negative to specify an internal (core) interrupt. |
<> | 144:ef7eb2e8f9f7 | 1842 | |
<> | 144:ef7eb2e8f9f7 | 1843 | |
<> | 144:ef7eb2e8f9f7 | 1844 | \param [in] IRQn Interrupt number. |
<> | 144:ef7eb2e8f9f7 | 1845 | \return Interrupt Priority. Value is aligned automatically to the implemented |
<> | 144:ef7eb2e8f9f7 | 1846 | priority bits of the microcontroller. |
<> | 144:ef7eb2e8f9f7 | 1847 | */ |
<> | 144:ef7eb2e8f9f7 | 1848 | __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
<> | 144:ef7eb2e8f9f7 | 1849 | { |
<> | 144:ef7eb2e8f9f7 | 1850 | |
<> | 144:ef7eb2e8f9f7 | 1851 | if((int32_t)IRQn < 0) { |
<> | 144:ef7eb2e8f9f7 | 1852 | return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); |
<> | 144:ef7eb2e8f9f7 | 1853 | } |
<> | 144:ef7eb2e8f9f7 | 1854 | else { |
<> | 144:ef7eb2e8f9f7 | 1855 | return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); |
<> | 144:ef7eb2e8f9f7 | 1856 | } |
<> | 144:ef7eb2e8f9f7 | 1857 | } |
<> | 144:ef7eb2e8f9f7 | 1858 | |
<> | 144:ef7eb2e8f9f7 | 1859 | |
<> | 144:ef7eb2e8f9f7 | 1860 | /** \brief Encode Priority |
<> | 144:ef7eb2e8f9f7 | 1861 | |
<> | 144:ef7eb2e8f9f7 | 1862 | The function encodes the priority for an interrupt with the given priority group, |
<> | 144:ef7eb2e8f9f7 | 1863 | preemptive priority value, and subpriority value. |
<> | 144:ef7eb2e8f9f7 | 1864 | In case of a conflict between priority grouping and available |
<> | 144:ef7eb2e8f9f7 | 1865 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
<> | 144:ef7eb2e8f9f7 | 1866 | |
<> | 144:ef7eb2e8f9f7 | 1867 | \param [in] PriorityGroup Used priority group. |
<> | 144:ef7eb2e8f9f7 | 1868 | \param [in] PreemptPriority Preemptive priority value (starting from 0). |
<> | 144:ef7eb2e8f9f7 | 1869 | \param [in] SubPriority Subpriority value (starting from 0). |
<> | 144:ef7eb2e8f9f7 | 1870 | \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). |
<> | 144:ef7eb2e8f9f7 | 1871 | */ |
<> | 144:ef7eb2e8f9f7 | 1872 | __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) |
<> | 144:ef7eb2e8f9f7 | 1873 | { |
<> | 144:ef7eb2e8f9f7 | 1874 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
<> | 144:ef7eb2e8f9f7 | 1875 | uint32_t PreemptPriorityBits; |
<> | 144:ef7eb2e8f9f7 | 1876 | uint32_t SubPriorityBits; |
<> | 144:ef7eb2e8f9f7 | 1877 | |
<> | 144:ef7eb2e8f9f7 | 1878 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
<> | 144:ef7eb2e8f9f7 | 1879 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
<> | 144:ef7eb2e8f9f7 | 1880 | |
<> | 144:ef7eb2e8f9f7 | 1881 | return ( |
<> | 144:ef7eb2e8f9f7 | 1882 | ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | |
<> | 144:ef7eb2e8f9f7 | 1883 | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) |
<> | 144:ef7eb2e8f9f7 | 1884 | ); |
<> | 144:ef7eb2e8f9f7 | 1885 | } |
<> | 144:ef7eb2e8f9f7 | 1886 | |
<> | 144:ef7eb2e8f9f7 | 1887 | |
<> | 144:ef7eb2e8f9f7 | 1888 | /** \brief Decode Priority |
<> | 144:ef7eb2e8f9f7 | 1889 | |
<> | 144:ef7eb2e8f9f7 | 1890 | The function decodes an interrupt priority value with a given priority group to |
<> | 144:ef7eb2e8f9f7 | 1891 | preemptive priority value and subpriority value. |
<> | 144:ef7eb2e8f9f7 | 1892 | In case of a conflict between priority grouping and available |
<> | 144:ef7eb2e8f9f7 | 1893 | priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. |
<> | 144:ef7eb2e8f9f7 | 1894 | |
<> | 144:ef7eb2e8f9f7 | 1895 | \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). |
<> | 144:ef7eb2e8f9f7 | 1896 | \param [in] PriorityGroup Used priority group. |
<> | 144:ef7eb2e8f9f7 | 1897 | \param [out] pPreemptPriority Preemptive priority value (starting from 0). |
<> | 144:ef7eb2e8f9f7 | 1898 | \param [out] pSubPriority Subpriority value (starting from 0). |
<> | 144:ef7eb2e8f9f7 | 1899 | */ |
<> | 144:ef7eb2e8f9f7 | 1900 | __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) |
<> | 144:ef7eb2e8f9f7 | 1901 | { |
<> | 144:ef7eb2e8f9f7 | 1902 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
<> | 144:ef7eb2e8f9f7 | 1903 | uint32_t PreemptPriorityBits; |
<> | 144:ef7eb2e8f9f7 | 1904 | uint32_t SubPriorityBits; |
<> | 144:ef7eb2e8f9f7 | 1905 | |
<> | 144:ef7eb2e8f9f7 | 1906 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
<> | 144:ef7eb2e8f9f7 | 1907 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
<> | 144:ef7eb2e8f9f7 | 1908 | |
<> | 144:ef7eb2e8f9f7 | 1909 | *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); |
<> | 144:ef7eb2e8f9f7 | 1910 | *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); |
<> | 144:ef7eb2e8f9f7 | 1911 | } |
<> | 144:ef7eb2e8f9f7 | 1912 | |
<> | 144:ef7eb2e8f9f7 | 1913 | |
<> | 144:ef7eb2e8f9f7 | 1914 | /** \brief System Reset |
<> | 144:ef7eb2e8f9f7 | 1915 | |
<> | 144:ef7eb2e8f9f7 | 1916 | The function initiates a system reset request to reset the MCU. |
<> | 144:ef7eb2e8f9f7 | 1917 | */ |
<> | 144:ef7eb2e8f9f7 | 1918 | __STATIC_INLINE void NVIC_SystemReset(void) |
<> | 144:ef7eb2e8f9f7 | 1919 | { |
<> | 144:ef7eb2e8f9f7 | 1920 | __DSB(); /* Ensure all outstanding memory accesses included |
<> | 144:ef7eb2e8f9f7 | 1921 | buffered write are completed before reset */ |
<> | 144:ef7eb2e8f9f7 | 1922 | SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
<> | 144:ef7eb2e8f9f7 | 1923 | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | |
<> | 144:ef7eb2e8f9f7 | 1924 | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ |
<> | 144:ef7eb2e8f9f7 | 1925 | __DSB(); /* Ensure completion of memory access */ |
<> | 144:ef7eb2e8f9f7 | 1926 | while(1) { __NOP(); } /* wait until reset */ |
<> | 144:ef7eb2e8f9f7 | 1927 | } |
<> | 144:ef7eb2e8f9f7 | 1928 | |
<> | 144:ef7eb2e8f9f7 | 1929 | /*@} end of CMSIS_Core_NVICFunctions */ |
<> | 144:ef7eb2e8f9f7 | 1930 | |
<> | 144:ef7eb2e8f9f7 | 1931 | |
<> | 144:ef7eb2e8f9f7 | 1932 | /* ########################## FPU functions #################################### */ |
<> | 144:ef7eb2e8f9f7 | 1933 | /** \ingroup CMSIS_Core_FunctionInterface |
<> | 144:ef7eb2e8f9f7 | 1934 | \defgroup CMSIS_Core_FpuFunctions FPU Functions |
<> | 144:ef7eb2e8f9f7 | 1935 | \brief Function that provides FPU type. |
<> | 144:ef7eb2e8f9f7 | 1936 | @{ |
<> | 144:ef7eb2e8f9f7 | 1937 | */ |
<> | 144:ef7eb2e8f9f7 | 1938 | |
<> | 144:ef7eb2e8f9f7 | 1939 | /** |
<> | 144:ef7eb2e8f9f7 | 1940 | \fn uint32_t SCB_GetFPUType(void) |
<> | 144:ef7eb2e8f9f7 | 1941 | \brief get FPU type |
<> | 144:ef7eb2e8f9f7 | 1942 | \returns |
<> | 144:ef7eb2e8f9f7 | 1943 | - \b 0: No FPU |
<> | 144:ef7eb2e8f9f7 | 1944 | - \b 1: Single precision FPU |
<> | 144:ef7eb2e8f9f7 | 1945 | - \b 2: Double + Single precision FPU |
<> | 144:ef7eb2e8f9f7 | 1946 | */ |
<> | 144:ef7eb2e8f9f7 | 1947 | __STATIC_INLINE uint32_t SCB_GetFPUType(void) |
<> | 144:ef7eb2e8f9f7 | 1948 | { |
<> | 144:ef7eb2e8f9f7 | 1949 | uint32_t mvfr0; |
<> | 144:ef7eb2e8f9f7 | 1950 | |
<> | 144:ef7eb2e8f9f7 | 1951 | mvfr0 = SCB->MVFR0; |
<> | 144:ef7eb2e8f9f7 | 1952 | if ((mvfr0 & 0x00000FF0UL) == 0x220UL) { |
<> | 144:ef7eb2e8f9f7 | 1953 | return 2UL; // Double + Single precision FPU |
<> | 144:ef7eb2e8f9f7 | 1954 | } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) { |
<> | 144:ef7eb2e8f9f7 | 1955 | return 1UL; // Single precision FPU |
<> | 144:ef7eb2e8f9f7 | 1956 | } else { |
<> | 144:ef7eb2e8f9f7 | 1957 | return 0UL; // No FPU |
<> | 144:ef7eb2e8f9f7 | 1958 | } |
<> | 144:ef7eb2e8f9f7 | 1959 | } |
<> | 144:ef7eb2e8f9f7 | 1960 | |
<> | 144:ef7eb2e8f9f7 | 1961 | |
<> | 144:ef7eb2e8f9f7 | 1962 | /*@} end of CMSIS_Core_FpuFunctions */ |
<> | 144:ef7eb2e8f9f7 | 1963 | |
<> | 144:ef7eb2e8f9f7 | 1964 | |
<> | 144:ef7eb2e8f9f7 | 1965 | |
<> | 144:ef7eb2e8f9f7 | 1966 | /* ########################## Cache functions #################################### */ |
<> | 144:ef7eb2e8f9f7 | 1967 | /** \ingroup CMSIS_Core_FunctionInterface |
<> | 144:ef7eb2e8f9f7 | 1968 | \defgroup CMSIS_Core_CacheFunctions Cache Functions |
<> | 144:ef7eb2e8f9f7 | 1969 | \brief Functions that configure Instruction and Data cache. |
<> | 144:ef7eb2e8f9f7 | 1970 | @{ |
<> | 144:ef7eb2e8f9f7 | 1971 | */ |
<> | 144:ef7eb2e8f9f7 | 1972 | |
<> | 144:ef7eb2e8f9f7 | 1973 | /* Cache Size ID Register Macros */ |
<> | 144:ef7eb2e8f9f7 | 1974 | #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) |
<> | 144:ef7eb2e8f9f7 | 1975 | #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) |
<> | 144:ef7eb2e8f9f7 | 1976 | #define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ ) |
<> | 144:ef7eb2e8f9f7 | 1977 | |
<> | 144:ef7eb2e8f9f7 | 1978 | |
<> | 144:ef7eb2e8f9f7 | 1979 | /** \brief Enable I-Cache |
<> | 144:ef7eb2e8f9f7 | 1980 | |
<> | 144:ef7eb2e8f9f7 | 1981 | The function turns on I-Cache |
<> | 144:ef7eb2e8f9f7 | 1982 | */ |
<> | 144:ef7eb2e8f9f7 | 1983 | __STATIC_INLINE void SCB_EnableICache (void) |
<> | 144:ef7eb2e8f9f7 | 1984 | { |
<> | 144:ef7eb2e8f9f7 | 1985 | #if (__ICACHE_PRESENT == 1) |
<> | 144:ef7eb2e8f9f7 | 1986 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 1987 | __ISB(); |
<> | 144:ef7eb2e8f9f7 | 1988 | SCB->ICIALLU = 0UL; // invalidate I-Cache |
<> | 144:ef7eb2e8f9f7 | 1989 | SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache |
<> | 144:ef7eb2e8f9f7 | 1990 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 1991 | __ISB(); |
<> | 144:ef7eb2e8f9f7 | 1992 | #endif |
<> | 144:ef7eb2e8f9f7 | 1993 | } |
<> | 144:ef7eb2e8f9f7 | 1994 | |
<> | 144:ef7eb2e8f9f7 | 1995 | |
<> | 144:ef7eb2e8f9f7 | 1996 | /** \brief Disable I-Cache |
<> | 144:ef7eb2e8f9f7 | 1997 | |
<> | 144:ef7eb2e8f9f7 | 1998 | The function turns off I-Cache |
<> | 144:ef7eb2e8f9f7 | 1999 | */ |
<> | 144:ef7eb2e8f9f7 | 2000 | __STATIC_INLINE void SCB_DisableICache (void) |
<> | 144:ef7eb2e8f9f7 | 2001 | { |
<> | 144:ef7eb2e8f9f7 | 2002 | #if (__ICACHE_PRESENT == 1) |
<> | 144:ef7eb2e8f9f7 | 2003 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 2004 | __ISB(); |
<> | 144:ef7eb2e8f9f7 | 2005 | SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache |
<> | 144:ef7eb2e8f9f7 | 2006 | SCB->ICIALLU = 0UL; // invalidate I-Cache |
<> | 144:ef7eb2e8f9f7 | 2007 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 2008 | __ISB(); |
<> | 144:ef7eb2e8f9f7 | 2009 | #endif |
<> | 144:ef7eb2e8f9f7 | 2010 | } |
<> | 144:ef7eb2e8f9f7 | 2011 | |
<> | 144:ef7eb2e8f9f7 | 2012 | |
<> | 144:ef7eb2e8f9f7 | 2013 | /** \brief Invalidate I-Cache |
<> | 144:ef7eb2e8f9f7 | 2014 | |
<> | 144:ef7eb2e8f9f7 | 2015 | The function invalidates I-Cache |
<> | 144:ef7eb2e8f9f7 | 2016 | */ |
<> | 144:ef7eb2e8f9f7 | 2017 | __STATIC_INLINE void SCB_InvalidateICache (void) |
<> | 144:ef7eb2e8f9f7 | 2018 | { |
<> | 144:ef7eb2e8f9f7 | 2019 | #if (__ICACHE_PRESENT == 1) |
<> | 144:ef7eb2e8f9f7 | 2020 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 2021 | __ISB(); |
<> | 144:ef7eb2e8f9f7 | 2022 | SCB->ICIALLU = 0UL; |
<> | 144:ef7eb2e8f9f7 | 2023 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 2024 | __ISB(); |
<> | 144:ef7eb2e8f9f7 | 2025 | #endif |
<> | 144:ef7eb2e8f9f7 | 2026 | } |
<> | 144:ef7eb2e8f9f7 | 2027 | |
<> | 144:ef7eb2e8f9f7 | 2028 | |
<> | 144:ef7eb2e8f9f7 | 2029 | /** \brief Enable D-Cache |
<> | 144:ef7eb2e8f9f7 | 2030 | |
<> | 144:ef7eb2e8f9f7 | 2031 | The function turns on D-Cache |
<> | 144:ef7eb2e8f9f7 | 2032 | */ |
<> | 144:ef7eb2e8f9f7 | 2033 | __STATIC_INLINE void SCB_EnableDCache (void) |
<> | 144:ef7eb2e8f9f7 | 2034 | { |
<> | 144:ef7eb2e8f9f7 | 2035 | #if (__DCACHE_PRESENT == 1) |
<> | 144:ef7eb2e8f9f7 | 2036 | uint32_t ccsidr, sshift, wshift, sw; |
<> | 144:ef7eb2e8f9f7 | 2037 | uint32_t sets, ways; |
<> | 144:ef7eb2e8f9f7 | 2038 | |
<> | 144:ef7eb2e8f9f7 | 2039 | SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache |
<> | 144:ef7eb2e8f9f7 | 2040 | ccsidr = SCB->CCSIDR; |
<> | 144:ef7eb2e8f9f7 | 2041 | sets = (uint32_t)(CCSIDR_SETS(ccsidr)); |
<> | 144:ef7eb2e8f9f7 | 2042 | sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); |
<> | 144:ef7eb2e8f9f7 | 2043 | ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); |
<> | 144:ef7eb2e8f9f7 | 2044 | wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); |
<> | 144:ef7eb2e8f9f7 | 2045 | |
<> | 144:ef7eb2e8f9f7 | 2046 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 2047 | |
<> | 144:ef7eb2e8f9f7 | 2048 | do { // invalidate D-Cache |
<> | 144:ef7eb2e8f9f7 | 2049 | uint32_t tmpways = ways; |
<> | 144:ef7eb2e8f9f7 | 2050 | do { |
<> | 144:ef7eb2e8f9f7 | 2051 | sw = ((tmpways << wshift) | (sets << sshift)); |
<> | 144:ef7eb2e8f9f7 | 2052 | SCB->DCISW = sw; |
<> | 144:ef7eb2e8f9f7 | 2053 | } while(tmpways--); |
<> | 144:ef7eb2e8f9f7 | 2054 | } while(sets--); |
<> | 144:ef7eb2e8f9f7 | 2055 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 2056 | |
<> | 144:ef7eb2e8f9f7 | 2057 | SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache |
<> | 144:ef7eb2e8f9f7 | 2058 | |
<> | 144:ef7eb2e8f9f7 | 2059 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 2060 | __ISB(); |
<> | 144:ef7eb2e8f9f7 | 2061 | #endif |
<> | 144:ef7eb2e8f9f7 | 2062 | } |
<> | 144:ef7eb2e8f9f7 | 2063 | |
<> | 144:ef7eb2e8f9f7 | 2064 | |
<> | 144:ef7eb2e8f9f7 | 2065 | /** \brief Disable D-Cache |
<> | 144:ef7eb2e8f9f7 | 2066 | |
<> | 144:ef7eb2e8f9f7 | 2067 | The function turns off D-Cache |
<> | 144:ef7eb2e8f9f7 | 2068 | */ |
<> | 144:ef7eb2e8f9f7 | 2069 | __STATIC_INLINE void SCB_DisableDCache (void) |
<> | 144:ef7eb2e8f9f7 | 2070 | { |
<> | 144:ef7eb2e8f9f7 | 2071 | #if (__DCACHE_PRESENT == 1) |
<> | 144:ef7eb2e8f9f7 | 2072 | uint32_t ccsidr, sshift, wshift, sw; |
<> | 144:ef7eb2e8f9f7 | 2073 | uint32_t sets, ways; |
<> | 144:ef7eb2e8f9f7 | 2074 | |
<> | 144:ef7eb2e8f9f7 | 2075 | SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache |
<> | 144:ef7eb2e8f9f7 | 2076 | ccsidr = SCB->CCSIDR; |
<> | 144:ef7eb2e8f9f7 | 2077 | sets = (uint32_t)(CCSIDR_SETS(ccsidr)); |
<> | 144:ef7eb2e8f9f7 | 2078 | sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); |
<> | 144:ef7eb2e8f9f7 | 2079 | ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); |
<> | 144:ef7eb2e8f9f7 | 2080 | wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); |
<> | 144:ef7eb2e8f9f7 | 2081 | |
<> | 144:ef7eb2e8f9f7 | 2082 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 2083 | |
<> | 144:ef7eb2e8f9f7 | 2084 | SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache |
<> | 144:ef7eb2e8f9f7 | 2085 | |
<> | 144:ef7eb2e8f9f7 | 2086 | do { // clean & invalidate D-Cache |
<> | 144:ef7eb2e8f9f7 | 2087 | uint32_t tmpways = ways; |
<> | 144:ef7eb2e8f9f7 | 2088 | do { |
<> | 144:ef7eb2e8f9f7 | 2089 | sw = ((tmpways << wshift) | (sets << sshift)); |
<> | 144:ef7eb2e8f9f7 | 2090 | SCB->DCCISW = sw; |
<> | 144:ef7eb2e8f9f7 | 2091 | } while(tmpways--); |
<> | 144:ef7eb2e8f9f7 | 2092 | } while(sets--); |
<> | 144:ef7eb2e8f9f7 | 2093 | |
<> | 144:ef7eb2e8f9f7 | 2094 | |
<> | 144:ef7eb2e8f9f7 | 2095 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 2096 | __ISB(); |
<> | 144:ef7eb2e8f9f7 | 2097 | #endif |
<> | 144:ef7eb2e8f9f7 | 2098 | } |
<> | 144:ef7eb2e8f9f7 | 2099 | |
<> | 144:ef7eb2e8f9f7 | 2100 | |
<> | 144:ef7eb2e8f9f7 | 2101 | /** \brief Invalidate D-Cache |
<> | 144:ef7eb2e8f9f7 | 2102 | |
<> | 144:ef7eb2e8f9f7 | 2103 | The function invalidates D-Cache |
<> | 144:ef7eb2e8f9f7 | 2104 | */ |
<> | 144:ef7eb2e8f9f7 | 2105 | __STATIC_INLINE void SCB_InvalidateDCache (void) |
<> | 144:ef7eb2e8f9f7 | 2106 | { |
<> | 144:ef7eb2e8f9f7 | 2107 | #if (__DCACHE_PRESENT == 1) |
<> | 144:ef7eb2e8f9f7 | 2108 | uint32_t ccsidr, sshift, wshift, sw; |
<> | 144:ef7eb2e8f9f7 | 2109 | uint32_t sets, ways; |
<> | 144:ef7eb2e8f9f7 | 2110 | |
<> | 144:ef7eb2e8f9f7 | 2111 | SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache |
<> | 144:ef7eb2e8f9f7 | 2112 | ccsidr = SCB->CCSIDR; |
<> | 144:ef7eb2e8f9f7 | 2113 | sets = (uint32_t)(CCSIDR_SETS(ccsidr)); |
<> | 144:ef7eb2e8f9f7 | 2114 | sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); |
<> | 144:ef7eb2e8f9f7 | 2115 | ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); |
<> | 144:ef7eb2e8f9f7 | 2116 | wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); |
<> | 144:ef7eb2e8f9f7 | 2117 | |
<> | 144:ef7eb2e8f9f7 | 2118 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 2119 | |
<> | 144:ef7eb2e8f9f7 | 2120 | do { // invalidate D-Cache |
<> | 144:ef7eb2e8f9f7 | 2121 | uint32_t tmpways = ways; |
<> | 144:ef7eb2e8f9f7 | 2122 | do { |
<> | 144:ef7eb2e8f9f7 | 2123 | sw = ((tmpways << wshift) | (sets << sshift)); |
<> | 144:ef7eb2e8f9f7 | 2124 | SCB->DCISW = sw; |
<> | 144:ef7eb2e8f9f7 | 2125 | } while(tmpways--); |
<> | 144:ef7eb2e8f9f7 | 2126 | } while(sets--); |
<> | 144:ef7eb2e8f9f7 | 2127 | |
<> | 144:ef7eb2e8f9f7 | 2128 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 2129 | __ISB(); |
<> | 144:ef7eb2e8f9f7 | 2130 | #endif |
<> | 144:ef7eb2e8f9f7 | 2131 | } |
<> | 144:ef7eb2e8f9f7 | 2132 | |
<> | 144:ef7eb2e8f9f7 | 2133 | |
<> | 144:ef7eb2e8f9f7 | 2134 | /** \brief Clean D-Cache |
<> | 144:ef7eb2e8f9f7 | 2135 | |
<> | 144:ef7eb2e8f9f7 | 2136 | The function cleans D-Cache |
<> | 144:ef7eb2e8f9f7 | 2137 | */ |
<> | 144:ef7eb2e8f9f7 | 2138 | __STATIC_INLINE void SCB_CleanDCache (void) |
<> | 144:ef7eb2e8f9f7 | 2139 | { |
<> | 144:ef7eb2e8f9f7 | 2140 | #if (__DCACHE_PRESENT == 1) |
<> | 144:ef7eb2e8f9f7 | 2141 | uint32_t ccsidr, sshift, wshift, sw; |
<> | 144:ef7eb2e8f9f7 | 2142 | uint32_t sets, ways; |
<> | 144:ef7eb2e8f9f7 | 2143 | |
<> | 144:ef7eb2e8f9f7 | 2144 | SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache |
<> | 144:ef7eb2e8f9f7 | 2145 | ccsidr = SCB->CCSIDR; |
<> | 144:ef7eb2e8f9f7 | 2146 | sets = (uint32_t)(CCSIDR_SETS(ccsidr)); |
<> | 144:ef7eb2e8f9f7 | 2147 | sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); |
<> | 144:ef7eb2e8f9f7 | 2148 | ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); |
<> | 144:ef7eb2e8f9f7 | 2149 | wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); |
<> | 144:ef7eb2e8f9f7 | 2150 | |
<> | 144:ef7eb2e8f9f7 | 2151 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 2152 | |
<> | 144:ef7eb2e8f9f7 | 2153 | do { // clean D-Cache |
<> | 144:ef7eb2e8f9f7 | 2154 | uint32_t tmpways = ways; |
<> | 144:ef7eb2e8f9f7 | 2155 | do { |
<> | 144:ef7eb2e8f9f7 | 2156 | sw = ((tmpways << wshift) | (sets << sshift)); |
<> | 144:ef7eb2e8f9f7 | 2157 | SCB->DCCSW = sw; |
<> | 144:ef7eb2e8f9f7 | 2158 | } while(tmpways--); |
<> | 144:ef7eb2e8f9f7 | 2159 | } while(sets--); |
<> | 144:ef7eb2e8f9f7 | 2160 | |
<> | 144:ef7eb2e8f9f7 | 2161 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 2162 | __ISB(); |
<> | 144:ef7eb2e8f9f7 | 2163 | #endif |
<> | 144:ef7eb2e8f9f7 | 2164 | } |
<> | 144:ef7eb2e8f9f7 | 2165 | |
<> | 144:ef7eb2e8f9f7 | 2166 | |
<> | 144:ef7eb2e8f9f7 | 2167 | /** \brief Clean & Invalidate D-Cache |
<> | 144:ef7eb2e8f9f7 | 2168 | |
<> | 144:ef7eb2e8f9f7 | 2169 | The function cleans and Invalidates D-Cache |
<> | 144:ef7eb2e8f9f7 | 2170 | */ |
<> | 144:ef7eb2e8f9f7 | 2171 | __STATIC_INLINE void SCB_CleanInvalidateDCache (void) |
<> | 144:ef7eb2e8f9f7 | 2172 | { |
<> | 144:ef7eb2e8f9f7 | 2173 | #if (__DCACHE_PRESENT == 1) |
<> | 144:ef7eb2e8f9f7 | 2174 | uint32_t ccsidr, sshift, wshift, sw; |
<> | 144:ef7eb2e8f9f7 | 2175 | uint32_t sets, ways; |
<> | 144:ef7eb2e8f9f7 | 2176 | |
<> | 144:ef7eb2e8f9f7 | 2177 | SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache |
<> | 144:ef7eb2e8f9f7 | 2178 | ccsidr = SCB->CCSIDR; |
<> | 144:ef7eb2e8f9f7 | 2179 | sets = (uint32_t)(CCSIDR_SETS(ccsidr)); |
<> | 144:ef7eb2e8f9f7 | 2180 | sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); |
<> | 144:ef7eb2e8f9f7 | 2181 | ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); |
<> | 144:ef7eb2e8f9f7 | 2182 | wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); |
<> | 144:ef7eb2e8f9f7 | 2183 | |
<> | 144:ef7eb2e8f9f7 | 2184 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 2185 | |
<> | 144:ef7eb2e8f9f7 | 2186 | do { // clean & invalidate D-Cache |
<> | 144:ef7eb2e8f9f7 | 2187 | uint32_t tmpways = ways; |
<> | 144:ef7eb2e8f9f7 | 2188 | do { |
<> | 144:ef7eb2e8f9f7 | 2189 | sw = ((tmpways << wshift) | (sets << sshift)); |
<> | 144:ef7eb2e8f9f7 | 2190 | SCB->DCCISW = sw; |
<> | 144:ef7eb2e8f9f7 | 2191 | } while(tmpways--); |
<> | 144:ef7eb2e8f9f7 | 2192 | } while(sets--); |
<> | 144:ef7eb2e8f9f7 | 2193 | |
<> | 144:ef7eb2e8f9f7 | 2194 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 2195 | __ISB(); |
<> | 144:ef7eb2e8f9f7 | 2196 | #endif |
<> | 144:ef7eb2e8f9f7 | 2197 | } |
<> | 144:ef7eb2e8f9f7 | 2198 | |
<> | 144:ef7eb2e8f9f7 | 2199 | |
<> | 144:ef7eb2e8f9f7 | 2200 | /** |
<> | 144:ef7eb2e8f9f7 | 2201 | \fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize) |
<> | 144:ef7eb2e8f9f7 | 2202 | \brief D-Cache Invalidate by address |
<> | 144:ef7eb2e8f9f7 | 2203 | \param[in] addr address (aligned to 32-byte boundary) |
<> | 144:ef7eb2e8f9f7 | 2204 | \param[in] dsize size of memory block (in number of bytes) |
<> | 144:ef7eb2e8f9f7 | 2205 | */ |
<> | 144:ef7eb2e8f9f7 | 2206 | __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) |
<> | 144:ef7eb2e8f9f7 | 2207 | { |
<> | 144:ef7eb2e8f9f7 | 2208 | #if (__DCACHE_PRESENT == 1) |
<> | 144:ef7eb2e8f9f7 | 2209 | int32_t op_size = dsize; |
<> | 144:ef7eb2e8f9f7 | 2210 | uint32_t op_addr = (uint32_t)addr; |
<> | 144:ef7eb2e8f9f7 | 2211 | uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) |
<> | 144:ef7eb2e8f9f7 | 2212 | |
<> | 144:ef7eb2e8f9f7 | 2213 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 2214 | |
<> | 144:ef7eb2e8f9f7 | 2215 | while (op_size > 0) { |
<> | 144:ef7eb2e8f9f7 | 2216 | SCB->DCIMVAC = op_addr; |
<> | 144:ef7eb2e8f9f7 | 2217 | op_addr += linesize; |
<> | 144:ef7eb2e8f9f7 | 2218 | op_size -= (int32_t)linesize; |
<> | 144:ef7eb2e8f9f7 | 2219 | } |
<> | 144:ef7eb2e8f9f7 | 2220 | |
<> | 144:ef7eb2e8f9f7 | 2221 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 2222 | __ISB(); |
<> | 144:ef7eb2e8f9f7 | 2223 | #endif |
<> | 144:ef7eb2e8f9f7 | 2224 | } |
<> | 144:ef7eb2e8f9f7 | 2225 | |
<> | 144:ef7eb2e8f9f7 | 2226 | |
<> | 144:ef7eb2e8f9f7 | 2227 | /** |
<> | 144:ef7eb2e8f9f7 | 2228 | \fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize) |
<> | 144:ef7eb2e8f9f7 | 2229 | \brief D-Cache Clean by address |
<> | 144:ef7eb2e8f9f7 | 2230 | \param[in] addr address (aligned to 32-byte boundary) |
<> | 144:ef7eb2e8f9f7 | 2231 | \param[in] dsize size of memory block (in number of bytes) |
<> | 144:ef7eb2e8f9f7 | 2232 | */ |
<> | 144:ef7eb2e8f9f7 | 2233 | __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) |
<> | 144:ef7eb2e8f9f7 | 2234 | { |
<> | 144:ef7eb2e8f9f7 | 2235 | #if (__DCACHE_PRESENT == 1) |
<> | 144:ef7eb2e8f9f7 | 2236 | int32_t op_size = dsize; |
<> | 144:ef7eb2e8f9f7 | 2237 | uint32_t op_addr = (uint32_t) addr; |
<> | 144:ef7eb2e8f9f7 | 2238 | uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) |
<> | 144:ef7eb2e8f9f7 | 2239 | |
<> | 144:ef7eb2e8f9f7 | 2240 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 2241 | |
<> | 144:ef7eb2e8f9f7 | 2242 | while (op_size > 0) { |
<> | 144:ef7eb2e8f9f7 | 2243 | SCB->DCCMVAC = op_addr; |
<> | 144:ef7eb2e8f9f7 | 2244 | op_addr += linesize; |
<> | 144:ef7eb2e8f9f7 | 2245 | op_size -= (int32_t)linesize; |
<> | 144:ef7eb2e8f9f7 | 2246 | } |
<> | 144:ef7eb2e8f9f7 | 2247 | |
<> | 144:ef7eb2e8f9f7 | 2248 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 2249 | __ISB(); |
<> | 144:ef7eb2e8f9f7 | 2250 | #endif |
<> | 144:ef7eb2e8f9f7 | 2251 | } |
<> | 144:ef7eb2e8f9f7 | 2252 | |
<> | 144:ef7eb2e8f9f7 | 2253 | |
<> | 144:ef7eb2e8f9f7 | 2254 | /** |
<> | 144:ef7eb2e8f9f7 | 2255 | \fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize) |
<> | 144:ef7eb2e8f9f7 | 2256 | \brief D-Cache Clean and Invalidate by address |
<> | 144:ef7eb2e8f9f7 | 2257 | \param[in] addr address (aligned to 32-byte boundary) |
<> | 144:ef7eb2e8f9f7 | 2258 | \param[in] dsize size of memory block (in number of bytes) |
<> | 144:ef7eb2e8f9f7 | 2259 | */ |
<> | 144:ef7eb2e8f9f7 | 2260 | __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) |
<> | 144:ef7eb2e8f9f7 | 2261 | { |
<> | 144:ef7eb2e8f9f7 | 2262 | #if (__DCACHE_PRESENT == 1) |
<> | 144:ef7eb2e8f9f7 | 2263 | int32_t op_size = dsize; |
<> | 144:ef7eb2e8f9f7 | 2264 | uint32_t op_addr = (uint32_t) addr; |
<> | 144:ef7eb2e8f9f7 | 2265 | uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) |
<> | 144:ef7eb2e8f9f7 | 2266 | |
<> | 144:ef7eb2e8f9f7 | 2267 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 2268 | |
<> | 144:ef7eb2e8f9f7 | 2269 | while (op_size > 0) { |
<> | 144:ef7eb2e8f9f7 | 2270 | SCB->DCCIMVAC = op_addr; |
<> | 144:ef7eb2e8f9f7 | 2271 | op_addr += linesize; |
<> | 144:ef7eb2e8f9f7 | 2272 | op_size -= (int32_t)linesize; |
<> | 144:ef7eb2e8f9f7 | 2273 | } |
<> | 144:ef7eb2e8f9f7 | 2274 | |
<> | 144:ef7eb2e8f9f7 | 2275 | __DSB(); |
<> | 144:ef7eb2e8f9f7 | 2276 | __ISB(); |
<> | 144:ef7eb2e8f9f7 | 2277 | #endif |
<> | 144:ef7eb2e8f9f7 | 2278 | } |
<> | 144:ef7eb2e8f9f7 | 2279 | |
<> | 144:ef7eb2e8f9f7 | 2280 | |
<> | 144:ef7eb2e8f9f7 | 2281 | /*@} end of CMSIS_Core_CacheFunctions */ |
<> | 144:ef7eb2e8f9f7 | 2282 | |
<> | 144:ef7eb2e8f9f7 | 2283 | |
<> | 144:ef7eb2e8f9f7 | 2284 | |
<> | 144:ef7eb2e8f9f7 | 2285 | /* ################################## SysTick function ############################################ */ |
<> | 144:ef7eb2e8f9f7 | 2286 | /** \ingroup CMSIS_Core_FunctionInterface |
<> | 144:ef7eb2e8f9f7 | 2287 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
<> | 144:ef7eb2e8f9f7 | 2288 | \brief Functions that configure the System. |
<> | 144:ef7eb2e8f9f7 | 2289 | @{ |
<> | 144:ef7eb2e8f9f7 | 2290 | */ |
<> | 144:ef7eb2e8f9f7 | 2291 | |
<> | 144:ef7eb2e8f9f7 | 2292 | #if (__Vendor_SysTickConfig == 0) |
<> | 144:ef7eb2e8f9f7 | 2293 | |
<> | 144:ef7eb2e8f9f7 | 2294 | /** \brief System Tick Configuration |
<> | 144:ef7eb2e8f9f7 | 2295 | |
<> | 144:ef7eb2e8f9f7 | 2296 | The function initializes the System Timer and its interrupt, and starts the System Tick Timer. |
<> | 144:ef7eb2e8f9f7 | 2297 | Counter is in free running mode to generate periodic interrupts. |
<> | 144:ef7eb2e8f9f7 | 2298 | |
<> | 144:ef7eb2e8f9f7 | 2299 | \param [in] ticks Number of ticks between two interrupts. |
<> | 144:ef7eb2e8f9f7 | 2300 | |
<> | 144:ef7eb2e8f9f7 | 2301 | \return 0 Function succeeded. |
<> | 144:ef7eb2e8f9f7 | 2302 | \return 1 Function failed. |
<> | 144:ef7eb2e8f9f7 | 2303 | |
<> | 144:ef7eb2e8f9f7 | 2304 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
<> | 144:ef7eb2e8f9f7 | 2305 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
<> | 144:ef7eb2e8f9f7 | 2306 | must contain a vendor-specific implementation of this function. |
<> | 144:ef7eb2e8f9f7 | 2307 | |
<> | 144:ef7eb2e8f9f7 | 2308 | */ |
<> | 144:ef7eb2e8f9f7 | 2309 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
<> | 144:ef7eb2e8f9f7 | 2310 | { |
<> | 144:ef7eb2e8f9f7 | 2311 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ |
<> | 144:ef7eb2e8f9f7 | 2312 | |
<> | 144:ef7eb2e8f9f7 | 2313 | SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
<> | 144:ef7eb2e8f9f7 | 2314 | NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2315 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
<> | 144:ef7eb2e8f9f7 | 2316 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
<> | 144:ef7eb2e8f9f7 | 2317 | SysTick_CTRL_TICKINT_Msk | |
<> | 144:ef7eb2e8f9f7 | 2318 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
<> | 144:ef7eb2e8f9f7 | 2319 | return (0UL); /* Function successful */ |
<> | 144:ef7eb2e8f9f7 | 2320 | } |
<> | 144:ef7eb2e8f9f7 | 2321 | |
<> | 144:ef7eb2e8f9f7 | 2322 | #endif |
<> | 144:ef7eb2e8f9f7 | 2323 | |
<> | 144:ef7eb2e8f9f7 | 2324 | /*@} end of CMSIS_Core_SysTickFunctions */ |
<> | 144:ef7eb2e8f9f7 | 2325 | |
<> | 144:ef7eb2e8f9f7 | 2326 | |
<> | 144:ef7eb2e8f9f7 | 2327 | |
<> | 144:ef7eb2e8f9f7 | 2328 | /* ##################################### Debug In/Output function ########################################### */ |
<> | 144:ef7eb2e8f9f7 | 2329 | /** \ingroup CMSIS_Core_FunctionInterface |
<> | 144:ef7eb2e8f9f7 | 2330 | \defgroup CMSIS_core_DebugFunctions ITM Functions |
<> | 144:ef7eb2e8f9f7 | 2331 | \brief Functions that access the ITM debug interface. |
<> | 144:ef7eb2e8f9f7 | 2332 | @{ |
<> | 144:ef7eb2e8f9f7 | 2333 | */ |
<> | 144:ef7eb2e8f9f7 | 2334 | |
<> | 144:ef7eb2e8f9f7 | 2335 | extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ |
<> | 144:ef7eb2e8f9f7 | 2336 | #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ |
<> | 144:ef7eb2e8f9f7 | 2337 | |
<> | 144:ef7eb2e8f9f7 | 2338 | |
<> | 144:ef7eb2e8f9f7 | 2339 | /** \brief ITM Send Character |
<> | 144:ef7eb2e8f9f7 | 2340 | |
<> | 144:ef7eb2e8f9f7 | 2341 | The function transmits a character via the ITM channel 0, and |
<> | 144:ef7eb2e8f9f7 | 2342 | \li Just returns when no debugger is connected that has booked the output. |
<> | 144:ef7eb2e8f9f7 | 2343 | \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. |
<> | 144:ef7eb2e8f9f7 | 2344 | |
<> | 144:ef7eb2e8f9f7 | 2345 | \param [in] ch Character to transmit. |
<> | 144:ef7eb2e8f9f7 | 2346 | |
<> | 144:ef7eb2e8f9f7 | 2347 | \returns Character to transmit. |
<> | 144:ef7eb2e8f9f7 | 2348 | */ |
<> | 144:ef7eb2e8f9f7 | 2349 | __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) |
<> | 144:ef7eb2e8f9f7 | 2350 | { |
<> | 144:ef7eb2e8f9f7 | 2351 | if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ |
<> | 144:ef7eb2e8f9f7 | 2352 | ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ |
<> | 144:ef7eb2e8f9f7 | 2353 | { |
<> | 144:ef7eb2e8f9f7 | 2354 | while (ITM->PORT[0].u32 == 0UL) { __NOP(); } |
<> | 144:ef7eb2e8f9f7 | 2355 | ITM->PORT[0].u8 = (uint8_t)ch; |
<> | 144:ef7eb2e8f9f7 | 2356 | } |
<> | 144:ef7eb2e8f9f7 | 2357 | return (ch); |
<> | 144:ef7eb2e8f9f7 | 2358 | } |
<> | 144:ef7eb2e8f9f7 | 2359 | |
<> | 144:ef7eb2e8f9f7 | 2360 | |
<> | 144:ef7eb2e8f9f7 | 2361 | /** \brief ITM Receive Character |
<> | 144:ef7eb2e8f9f7 | 2362 | |
<> | 144:ef7eb2e8f9f7 | 2363 | The function inputs a character via the external variable \ref ITM_RxBuffer. |
<> | 144:ef7eb2e8f9f7 | 2364 | |
<> | 144:ef7eb2e8f9f7 | 2365 | \return Received character. |
<> | 144:ef7eb2e8f9f7 | 2366 | \return -1 No character pending. |
<> | 144:ef7eb2e8f9f7 | 2367 | */ |
<> | 144:ef7eb2e8f9f7 | 2368 | __STATIC_INLINE int32_t ITM_ReceiveChar (void) { |
<> | 144:ef7eb2e8f9f7 | 2369 | int32_t ch = -1; /* no character available */ |
<> | 144:ef7eb2e8f9f7 | 2370 | |
<> | 144:ef7eb2e8f9f7 | 2371 | if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { |
<> | 144:ef7eb2e8f9f7 | 2372 | ch = ITM_RxBuffer; |
<> | 144:ef7eb2e8f9f7 | 2373 | ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ |
<> | 144:ef7eb2e8f9f7 | 2374 | } |
<> | 144:ef7eb2e8f9f7 | 2375 | |
<> | 144:ef7eb2e8f9f7 | 2376 | return (ch); |
<> | 144:ef7eb2e8f9f7 | 2377 | } |
<> | 144:ef7eb2e8f9f7 | 2378 | |
<> | 144:ef7eb2e8f9f7 | 2379 | |
<> | 144:ef7eb2e8f9f7 | 2380 | /** \brief ITM Check Character |
<> | 144:ef7eb2e8f9f7 | 2381 | |
<> | 144:ef7eb2e8f9f7 | 2382 | The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. |
<> | 144:ef7eb2e8f9f7 | 2383 | |
<> | 144:ef7eb2e8f9f7 | 2384 | \return 0 No character available. |
<> | 144:ef7eb2e8f9f7 | 2385 | \return 1 Character available. |
<> | 144:ef7eb2e8f9f7 | 2386 | */ |
<> | 144:ef7eb2e8f9f7 | 2387 | __STATIC_INLINE int32_t ITM_CheckChar (void) { |
<> | 144:ef7eb2e8f9f7 | 2388 | |
<> | 144:ef7eb2e8f9f7 | 2389 | if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { |
<> | 144:ef7eb2e8f9f7 | 2390 | return (0); /* no character available */ |
<> | 144:ef7eb2e8f9f7 | 2391 | } else { |
<> | 144:ef7eb2e8f9f7 | 2392 | return (1); /* character available */ |
<> | 144:ef7eb2e8f9f7 | 2393 | } |
<> | 144:ef7eb2e8f9f7 | 2394 | } |
<> | 144:ef7eb2e8f9f7 | 2395 | |
<> | 144:ef7eb2e8f9f7 | 2396 | /*@} end of CMSIS_core_DebugFunctions */ |
<> | 144:ef7eb2e8f9f7 | 2397 | |
<> | 144:ef7eb2e8f9f7 | 2398 | |
<> | 144:ef7eb2e8f9f7 | 2399 | |
<> | 144:ef7eb2e8f9f7 | 2400 | |
<> | 144:ef7eb2e8f9f7 | 2401 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 2402 | } |
<> | 144:ef7eb2e8f9f7 | 2403 | #endif |
<> | 144:ef7eb2e8f9f7 | 2404 | |
<> | 144:ef7eb2e8f9f7 | 2405 | #endif /* __CORE_CM7_H_DEPENDANT */ |
<> | 144:ef7eb2e8f9f7 | 2406 | |
<> | 144:ef7eb2e8f9f7 | 2407 | #endif /* __CMSIS_GENERIC */ |