the do / gr-peach-opencv-project

Opencv 3.1 project on GR-PEACH board

Fork of gr-peach-opencv-project by the do

GR-PEACH_video/gr_peach_vdc5.c@170:54ff26da7eb6, 2017-07-04 (annotated)

Committer:
thedo
Date:
Tue Jul 04 06:23:13 2017 +0000
Revision:
170:54ff26da7eb6
Parent:
166:3a9487d57a5c 
project opencv 3.1 on GR PEACH board, no use SD card.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
thedo 166:3a9487d57a5c 1 /*******************************************************************************
thedo 166:3a9487d57a5c 2 * DISCLAIMER
thedo 166:3a9487d57a5c 3 * This software is supplied by Renesas Electronics Corporation and is only
thedo 166:3a9487d57a5c 4 * intended for use with Renesas products. No other uses are authorized. This
thedo 166:3a9487d57a5c 5 * software is owned by Renesas Electronics Corporation and is protected under
thedo 166:3a9487d57a5c 6 * all applicable laws, including copyright laws.
thedo 166:3a9487d57a5c 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
thedo 166:3a9487d57a5c 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
thedo 166:3a9487d57a5c 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
thedo 166:3a9487d57a5c 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
thedo 166:3a9487d57a5c 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
thedo 166:3a9487d57a5c 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
thedo 166:3a9487d57a5c 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
thedo 166:3a9487d57a5c 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
thedo 166:3a9487d57a5c 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
thedo 166:3a9487d57a5c 16 * Renesas reserves the right, without notice, to make changes to this software
thedo 166:3a9487d57a5c 17 * and to discontinue the availability of this software. By using this software,
thedo 166:3a9487d57a5c 18 * you agree to the additional terms and conditions found by accessing the
thedo 166:3a9487d57a5c 19 * following link:
thedo 166:3a9487d57a5c 20 * http://www.renesas.com/disclaimer
thedo 166:3a9487d57a5c 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
thedo 166:3a9487d57a5c 22 *******************************************************************************/
thedo 166:3a9487d57a5c 23 /**************************************************************************//**
thedo 166:3a9487d57a5c 24 * @file gr_peach_vdc5.c
thedo 166:3a9487d57a5c 25 * @version
thedo 166:3a9487d57a5c 26 * $Rev:
thedo 166:3a9487d57a5c 27 * $Date::
thedo 166:3a9487d57a5c 28 * @brief VDC5 driver API wrapper function in C interface
thedo 166:3a9487d57a5c 29 ******************************************************************************/
thedo 166:3a9487d57a5c 30
thedo 166:3a9487d57a5c 31 /******************************************************************************
thedo 166:3a9487d57a5c 32 Includes <System Includes> , "Project Includes"
thedo 166:3a9487d57a5c 33 ******************************************************************************/
thedo 166:3a9487d57a5c 34 #include <stdio.h>
thedo 166:3a9487d57a5c 35 #include <string.h>
thedo 166:3a9487d57a5c 36
thedo 166:3a9487d57a5c 37 #include "r_typedefs.h"
thedo 166:3a9487d57a5c 38 #include "r_vdc5.h"
thedo 166:3a9487d57a5c 39 #include "video_decoder.h"
thedo 166:3a9487d57a5c 40 #include "lvds_pll_calc.h"
thedo 166:3a9487d57a5c 41 #include "gr_peach_vdc5.h"
thedo 166:3a9487d57a5c 42
thedo 166:3a9487d57a5c 43 #include "mbed_assert.h"
thedo 166:3a9487d57a5c 44 #include "pinmap.h"
thedo 166:3a9487d57a5c 45
thedo 166:3a9487d57a5c 46 /******************************************************************************
thedo 166:3a9487d57a5c 47 Macro definitions
thedo 166:3a9487d57a5c 48 ******************************************************************************/
thedo 166:3a9487d57a5c 49 #define STP91_BIT (0x02u)
thedo 166:3a9487d57a5c 50 #define STP90_BIT (0x01u)
thedo 166:3a9487d57a5c 51 #define STBRQ25_BIT (0x20u)
thedo 166:3a9487d57a5c 52 #define STBAK25_BIT (0x20u)
thedo 166:3a9487d57a5c 53 #define STBRQ24_BIT (0x10u)
thedo 166:3a9487d57a5c 54 #define STBAK24_BIT (0x10u)
thedo 166:3a9487d57a5c 55
thedo 166:3a9487d57a5c 56 /******************************************************************************
thedo 166:3a9487d57a5c 57 Typedef definitions
thedo 166:3a9487d57a5c 58 ******************************************************************************/
thedo 166:3a9487d57a5c 59 typedef enum {
thedo 166:3a9487d57a5c 60 VDC5_CH0,
thedo 166:3a9487d57a5c 61 VDC5_CH1,
thedo 166:3a9487d57a5c 62 } VDC5Name;
thedo 166:3a9487d57a5c 63
thedo 166:3a9487d57a5c 64 /******************************************************************************
thedo 166:3a9487d57a5c 65 Imported global variables and functions (from other files)
thedo 166:3a9487d57a5c 66 ******************************************************************************/
thedo 166:3a9487d57a5c 67
thedo 166:3a9487d57a5c 68 /******************************************************************************
thedo 166:3a9487d57a5c 69 Exported global variables (to be accessed by other files)
thedo 166:3a9487d57a5c 70 ******************************************************************************/
thedo 166:3a9487d57a5c 71 static const PinMap PinMap_DV_INPUT_PIN[] = {
thedo 166:3a9487d57a5c 72 {P8_11 , VDC5_CH0, 8}, /* DV0_CLK */
thedo 166:3a9487d57a5c 73 {P10_0 , VDC5_CH0, 1}, /* DV0_CLK */
thedo 166:3a9487d57a5c 74 {P1_12 , VDC5_CH0, 2}, /* DV0_VSYNC */
thedo 166:3a9487d57a5c 75 {P1_13 , VDC5_CH0, 2}, /* DV0_HSYNC */
thedo 166:3a9487d57a5c 76 {P1_1 , VDC5_CH0, 6}, /* DV0_HSYNC */
thedo 166:3a9487d57a5c 77 {P1_0 , VDC5_CH0, 6}, /* DV0_VSYNC */
thedo 166:3a9487d57a5c 78 {P1_9 , VDC5_CH0, 6}, /* DV0_DATA15 */
thedo 166:3a9487d57a5c 79 {P2_15 , VDC5_CH0, 3}, /* DV0_DATA15 */
thedo 166:3a9487d57a5c 80 {P4_7 , VDC5_CH0, 7}, /* DV0_DATA15 */
thedo 166:3a9487d57a5c 81 {P5_7 , VDC5_CH0, 4}, /* DV0_DATA15 */
thedo 166:3a9487d57a5c 82 {P1_8 , VDC5_CH0, 6}, /* DV0_DATA14 */
thedo 166:3a9487d57a5c 83 {P2_14 , VDC5_CH0, 3}, /* DV0_DATA14 */
thedo 166:3a9487d57a5c 84 {P4_6 , VDC5_CH0, 7}, /* DV0_DATA14 */
thedo 166:3a9487d57a5c 85 {P5_6 , VDC5_CH0, 4}, /* DV0_DATA14 */
thedo 166:3a9487d57a5c 86 {P1_7 , VDC5_CH0, 6}, /* DV0_DATA13 */
thedo 166:3a9487d57a5c 87 {P2_13 , VDC5_CH0, 3}, /* DV0_DATA13 */
thedo 166:3a9487d57a5c 88 {P4_5 , VDC5_CH0, 7}, /* DV0_DATA13 */
thedo 166:3a9487d57a5c 89 {P5_5 , VDC5_CH0, 4}, /* DV0_DATA13 */
thedo 166:3a9487d57a5c 90 {P1_6 , VDC5_CH0, 6}, /* DV0_DATA12 */
thedo 166:3a9487d57a5c 91 {P4_4 , VDC5_CH0, 7}, /* DV0_DATA12 */
thedo 166:3a9487d57a5c 92 {P5_4 , VDC5_CH0, 4}, /* DV0_DATA12 */
thedo 166:3a9487d57a5c 93 {P10_5 , VDC5_CH0, 1}, /* DV0_DATA11 */
thedo 166:3a9487d57a5c 94 {P2_10 , VDC5_CH0, 3}, /* DV0_DATA10 */
thedo 166:3a9487d57a5c 95 {P10_14, VDC5_CH0, 1}, /* DV0_DATA10 */
thedo 166:3a9487d57a5c 96 {P2_9 , VDC5_CH0, 3}, /* DV0_DATA9 */
thedo 166:3a9487d57a5c 97 {P10_13, VDC5_CH0, 1}, /* DV0_DATA9 */
thedo 166:3a9487d57a5c 98 {P10_12, VDC5_CH0, 1}, /* DV0_DATA8 */
thedo 166:3a9487d57a5c 99 {P2_7 , VDC5_CH0, 3}, /* DV0_DATA7 */
thedo 166:3a9487d57a5c 100 {P2_6 , VDC5_CH0, 3}, /* DV0_DATA6 */
thedo 166:3a9487d57a5c 101 {P2_5 , VDC5_CH0, 3}, /* DV0_DATA5 */
thedo 166:3a9487d57a5c 102 {P2_4 , VDC5_CH0, 3}, /* DV0_DATA4 */
thedo 166:3a9487d57a5c 103 {P2_3 , VDC5_CH0, 3}, /* DV0_DATA3 */
thedo 166:3a9487d57a5c 104 {P2_2 , VDC5_CH0, 3}, /* DV0_DATA2 */
thedo 166:3a9487d57a5c 105 {P2_1 , VDC5_CH0, 3}, /* DV0_DATA1 */
thedo 166:3a9487d57a5c 106 {P2_0 , VDC5_CH0, 3}, /* DV0_DATA0 */
thedo 166:3a9487d57a5c 107 {NC , NC , 0}
thedo 166:3a9487d57a5c 108 };
thedo 166:3a9487d57a5c 109
thedo 166:3a9487d57a5c 110 static const PinMap PinMap_LCD_DISP_PIN[] = {
thedo 166:3a9487d57a5c 111 {P2_7 , VDC5_CH0, 8}, /* LCD0_DATA23 */
thedo 166:3a9487d57a5c 112 {P5_7 , VDC5_CH0, 3}, /* LCD0_DATA23 */
thedo 166:3a9487d57a5c 113 {P10_0 , VDC5_CH0, 5}, /* LCD0_DATA23 */
thedo 166:3a9487d57a5c 114 {P2_6 , VDC5_CH0, 8}, /* LCD0_DATA22 */
thedo 166:3a9487d57a5c 115 {P5_6 , VDC5_CH0, 3}, /* LCD0_DATA22 */
thedo 166:3a9487d57a5c 116 {P10_1 , VDC5_CH0, 5}, /* LCD0_DATA22 */
thedo 166:3a9487d57a5c 117 {P2_5 , VDC5_CH0, 8}, /* LCD0_DATA21 */
thedo 166:3a9487d57a5c 118 {P5_5 , VDC5_CH0, 3}, /* LCD0_DATA21 */
thedo 166:3a9487d57a5c 119 {P10_2 , VDC5_CH0, 5}, /* LCD0_DATA21 */
thedo 166:3a9487d57a5c 120 {P2_4 , VDC5_CH0, 8}, /* LCD0_DATA20 */
thedo 166:3a9487d57a5c 121 {P5_4 , VDC5_CH0, 3}, /* LCD0_DATA20 */
thedo 166:3a9487d57a5c 122 {P10_3 , VDC5_CH0, 5}, /* LCD0_DATA20 */
thedo 166:3a9487d57a5c 123 {P2_3 , VDC5_CH0, 8}, /* LCD0_DATA19 */
thedo 166:3a9487d57a5c 124 {P5_3 , VDC5_CH0, 3}, /* LCD0_DATA19 */
thedo 166:3a9487d57a5c 125 {P10_4 , VDC5_CH0, 5}, /* LCD0_DATA19 */
thedo 166:3a9487d57a5c 126 {P2_2 , VDC5_CH0, 8}, /* LCD0_DATA18 */
thedo 166:3a9487d57a5c 127 {P5_2 , VDC5_CH0, 3}, /* LCD0_DATA18 */
thedo 166:3a9487d57a5c 128 {P10_5 , VDC5_CH0, 5}, /* LCD0_DATA18 */
thedo 166:3a9487d57a5c 129 {P2_1 , VDC5_CH0, 8}, /* LCD0_DATA17 */
thedo 166:3a9487d57a5c 130 {P5_1 , VDC5_CH0, 3}, /* LCD0_DATA17 */
thedo 166:3a9487d57a5c 131 {P10_7 , VDC5_CH0, 5}, /* LCD0_DATA17 */
thedo 166:3a9487d57a5c 132 {P2_0 , VDC5_CH0, 8}, /* LCD0_DATA16 */
thedo 166:3a9487d57a5c 133 {P5_0 , VDC5_CH0, 3}, /* LCD0_DATA16 */
thedo 166:3a9487d57a5c 134 {P10_6 , VDC5_CH0, 5}, /* LCD0_DATA16 */
thedo 166:3a9487d57a5c 135 {P4_7 , VDC5_CH0, 1}, /* LCD0_DATA15 */
thedo 166:3a9487d57a5c 136 {P10_8 , VDC5_CH0, 5}, /* LCD0_DATA15 */
thedo 166:3a9487d57a5c 137 {P4_6 , VDC5_CH0, 1}, /* LCD0_DATA14 */
thedo 166:3a9487d57a5c 138 {P10_9 , VDC5_CH0, 5}, /* LCD0_DATA14 */
thedo 166:3a9487d57a5c 139 {P4_5 , VDC5_CH0, 1}, /* LCD0_DATA13 */
thedo 166:3a9487d57a5c 140 {P10_10, VDC5_CH0, 5}, /* LCD0_DATA13 */
thedo 166:3a9487d57a5c 141 {P4_4 , VDC5_CH0, 1}, /* LCD0_DATA12 */
thedo 166:3a9487d57a5c 142 {P10_11, VDC5_CH0, 5}, /* LCD0_DATA12 */
thedo 166:3a9487d57a5c 143 {P10_12, VDC5_CH0, 5}, /* LCD0_DATA11 */
thedo 166:3a9487d57a5c 144 {P10_13, VDC5_CH0, 5}, /* LCD0_DATA10 */
thedo 166:3a9487d57a5c 145 {P10_14, VDC5_CH0, 5}, /* LCD0_DATA9 */
thedo 166:3a9487d57a5c 146 {P4_0 , VDC5_CH0, 1}, /* LCD0_DATA8 */
thedo 166:3a9487d57a5c 147 {P10_15, VDC5_CH0, 5}, /* LCD0_DATA8 */
thedo 166:3a9487d57a5c 148 {P3_15 , VDC5_CH0, 1}, /* LCD0_DATA7 */
thedo 166:3a9487d57a5c 149 {P11_0 , VDC5_CH0, 5}, /* LCD0_DATA7 */
thedo 166:3a9487d57a5c 150 {P3_14 , VDC5_CH0, 1}, /* LCD0_DATA6 */
thedo 166:3a9487d57a5c 151 {P11_1 , VDC5_CH0, 5}, /* LCD0_DATA6 */
thedo 166:3a9487d57a5c 152 {P3_13 , VDC5_CH0, 1}, /* LCD0_DATA5 */
thedo 166:3a9487d57a5c 153 {P11_2 , VDC5_CH0, 5}, /* LCD0_DATA5 */
thedo 166:3a9487d57a5c 154 {P3_12 , VDC5_CH0, 1}, /* LCD0_DATA4 */
thedo 166:3a9487d57a5c 155 {P11_3 , VDC5_CH0, 5}, /* LCD0_DATA4 */
thedo 166:3a9487d57a5c 156 {P3_11 , VDC5_CH0, 1}, /* LCD0_DATA3 */
thedo 166:3a9487d57a5c 157 {P11_4 , VDC5_CH0, 5}, /* LCD0_DATA3 */
thedo 166:3a9487d57a5c 158 {P3_10 , VDC5_CH0, 1}, /* LCD0_DATA2 */
thedo 166:3a9487d57a5c 159 {P11_5 , VDC5_CH0, 5}, /* LCD0_DATA2 */
thedo 166:3a9487d57a5c 160 {P3_9 , VDC5_CH0, 1}, /* LCD0_DATA1 */
thedo 166:3a9487d57a5c 161 {P11_6 , VDC5_CH0, 5}, /* LCD0_DATA1 */
thedo 166:3a9487d57a5c 162 {P3_8 , VDC5_CH0, 1}, /* LCD0_DATA0 */
thedo 166:3a9487d57a5c 163 {P11_7 , VDC5_CH0, 5}, /* LCD0_DATA0 */
thedo 166:3a9487d57a5c 164 {P11_10, VDC5_CH0, 5}, /* LCD0_TCON4 */
thedo 166:3a9487d57a5c 165 {P11_11, VDC5_CH0, 5}, /* LCD0_TCON3 */
thedo 166:3a9487d57a5c 166 {P11_12, VDC5_CH0, 5}, /* LCD0_TCON2 */
thedo 166:3a9487d57a5c 167 {P3_2 , VDC5_CH0, 1}, /* LCD0_TCON1 */
thedo 166:3a9487d57a5c 168 {P11_13, VDC5_CH0, 5}, /* LCD0_TCON1 */
thedo 166:3a9487d57a5c 169 {P11_14, VDC5_CH0, 5}, /* LCD0_TCON0 */
thedo 166:3a9487d57a5c 170 {P11_15, VDC5_CH0, 5}, /* LCD0_CLK */
thedo 166:3a9487d57a5c 171 {NC , NC , 0}
thedo 166:3a9487d57a5c 172 };
thedo 166:3a9487d57a5c 173
thedo 166:3a9487d57a5c 174 static const PinMap PinMap_LVDS_DISP_PIN[] = {
thedo 166:3a9487d57a5c 175 {P5_7 , VDC5_CH0, 1}, /* TXOUT0M */
thedo 166:3a9487d57a5c 176 {P5_6 , VDC5_CH0, 1}, /* TXOUT0P */
thedo 166:3a9487d57a5c 177 {P5_5 , VDC5_CH0, 1}, /* TXOUT1M */
thedo 166:3a9487d57a5c 178 {P5_4 , VDC5_CH0, 1}, /* TXOUT1P */
thedo 166:3a9487d57a5c 179 {P5_3 , VDC5_CH0, 1}, /* TXOUT2M */
thedo 166:3a9487d57a5c 180 {P5_2 , VDC5_CH0, 1}, /* TXOUT2P */
thedo 166:3a9487d57a5c 181 {P5_1 , VDC5_CH0, 1}, /* TXCLKOUTM */
thedo 166:3a9487d57a5c 182 {P5_0 , VDC5_CH0, 1}, /* TXCLKOUTP */
thedo 166:3a9487d57a5c 183 {NC , NC , 0}
thedo 166:3a9487d57a5c 184 };
thedo 166:3a9487d57a5c 185
thedo 166:3a9487d57a5c 186 static const IRQn_Type vdc5_irq_set_tbl[] = {
thedo 166:3a9487d57a5c 187 S0_VI_VSYNC0_IRQn,
thedo 166:3a9487d57a5c 188 S0_LO_VSYNC0_IRQn,
thedo 166:3a9487d57a5c 189 S0_VSYNCERR0_IRQn,
thedo 166:3a9487d57a5c 190 GR3_VLINE0_IRQn,
thedo 166:3a9487d57a5c 191 S0_VFIELD0_IRQn,
thedo 166:3a9487d57a5c 192 IV1_VBUFERR0_IRQn,
thedo 166:3a9487d57a5c 193 IV3_VBUFERR0_IRQn,
thedo 166:3a9487d57a5c 194 IV5_VBUFERR0_IRQn,
thedo 166:3a9487d57a5c 195 IV6_VBUFERR0_IRQn,
thedo 166:3a9487d57a5c 196 S0_WLINE0_IRQn,
thedo 166:3a9487d57a5c 197 S1_VI_VSYNC0_IRQn,
thedo 166:3a9487d57a5c 198 S1_LO_VSYNC0_IRQn,
thedo 166:3a9487d57a5c 199 S1_VSYNCERR0_IRQn,
thedo 166:3a9487d57a5c 200 S1_VFIELD0_IRQn,
thedo 166:3a9487d57a5c 201 IV2_VBUFERR0_IRQn,
thedo 166:3a9487d57a5c 202 IV4_VBUFERR0_IRQn,
thedo 166:3a9487d57a5c 203 S1_WLINE0_IRQn,
thedo 166:3a9487d57a5c 204 OIR_VI_VSYNC0_IRQn,
thedo 166:3a9487d57a5c 205 OIR_LO_VSYNC0_IRQn,
thedo 166:3a9487d57a5c 206 OIR_VSYNCERR0_IRQn,
thedo 166:3a9487d57a5c 207 OIR_VFIELD0_IRQn,
thedo 166:3a9487d57a5c 208 IV7_VBUFERR0_IRQn,
thedo 166:3a9487d57a5c 209 IV8_VBUFERR0_IRQn
thedo 166:3a9487d57a5c 210 };
thedo 166:3a9487d57a5c 211
thedo 166:3a9487d57a5c 212 /******************************************************************************
thedo 166:3a9487d57a5c 213 Private global variables and functions
thedo 166:3a9487d57a5c 214 ******************************************************************************/
thedo 166:3a9487d57a5c 215 static void init_func (const uint32_t user_num);
thedo 166:3a9487d57a5c 216 static void DRV_Graphics_Irq_Set(vdc5_int_type_t irq, uint32_t enable);
thedo 166:3a9487d57a5c 217
thedo 166:3a9487d57a5c 218 /**************************************************************************//**
thedo 166:3a9487d57a5c 219 * @brief User-defined function within R_VDC5_Initialize
thedo 166:3a9487d57a5c 220 * @param[in] user_num : VDC5 channel
thedo 166:3a9487d57a5c 221 * @retval None
thedo 166:3a9487d57a5c 222 ******************************************************************************/
thedo 166:3a9487d57a5c 223 static void init_func (const uint32_t user_num)
thedo 166:3a9487d57a5c 224 {
thedo 166:3a9487d57a5c 225 uint32_t reg_data;
thedo 166:3a9487d57a5c 226 volatile uint8_t dummy_read;
thedo 166:3a9487d57a5c 227
thedo 166:3a9487d57a5c 228 if ((vdc5_channel_t)user_num == VDC5_CHANNEL_0) {
thedo 166:3a9487d57a5c 229
thedo 166:3a9487d57a5c 230 /* Standby control register 9 (STBCR9)
thedo 166:3a9487d57a5c 231 b1 ------0-; MSTP91 : 0 : Video display controller channel 0 & LVDS enable */
thedo 166:3a9487d57a5c 232 reg_data = (uint32_t)CPG.STBCR9 & (uint32_t)~STP91_BIT;
thedo 166:3a9487d57a5c 233 CPG.STBCR9 = (uint8_t)reg_data;
thedo 166:3a9487d57a5c 234 /* In order to reflect the change, a dummy read should be done. */
thedo 166:3a9487d57a5c 235 dummy_read = CPG.STBCR9;
thedo 166:3a9487d57a5c 236
thedo 166:3a9487d57a5c 237 /* Standby Request Register 2 (STBREQ2)
thedo 166:3a9487d57a5c 238 b5 --0-----; STBRQ25 : The standby request to VDC5 channel 0 is invalid. */
thedo 166:3a9487d57a5c 239 reg_data = (uint32_t)CPG.STBREQ2 & (uint32_t)~STBRQ25_BIT;
thedo 166:3a9487d57a5c 240 CPG.STBREQ2 = (uint8_t)reg_data;
thedo 166:3a9487d57a5c 241 /* Standby Acknowledge Register 2 (STBACK2)
thedo 166:3a9487d57a5c 242 b5 --*-----; STBAK25 : Standby acknowledgement from VDC5 channel 0. */
thedo 166:3a9487d57a5c 243 while (((uint32_t)CPG.STBACK2 & (uint32_t)STBAK25_BIT) != 0u) {
thedo 166:3a9487d57a5c 244 /* Wait for the STBAK25 to be cleared to 0. */
thedo 166:3a9487d57a5c 245 }
thedo 166:3a9487d57a5c 246
thedo 166:3a9487d57a5c 247 /* Standby control register 9 (STBCR9)
thedo 166:3a9487d57a5c 248 b0 -------0; MSTP90 : 0 : Video display controller channel 1 enable */
thedo 166:3a9487d57a5c 249 reg_data = (uint32_t)CPG.STBCR9 & (uint32_t)~(STP91_BIT|STP90_BIT);
thedo 166:3a9487d57a5c 250 CPG.STBCR9 = (uint8_t)reg_data;
thedo 166:3a9487d57a5c 251 /* In order to reflect the change, a dummy read should be done. */
thedo 166:3a9487d57a5c 252 dummy_read = CPG.STBCR9;
thedo 166:3a9487d57a5c 253
thedo 166:3a9487d57a5c 254 /* Standby Request Register 2 (STBREQ2)
thedo 166:3a9487d57a5c 255 b4 ---0----; STBRQ24 : The standby request to VDC5 channel 1 is invalid. */
thedo 166:3a9487d57a5c 256 reg_data = (uint32_t)CPG.STBREQ2 & (uint32_t)~STBRQ24_BIT;
thedo 166:3a9487d57a5c 257 CPG.STBREQ2 = (uint8_t)reg_data;
thedo 166:3a9487d57a5c 258 /* Standby Acknowledge Register 2 (STBACK2)
thedo 166:3a9487d57a5c 259 b4 ---*----; STBAK24 : Standby acknowledgement from VDC5 channel 1. */
thedo 166:3a9487d57a5c 260 while (((uint32_t)CPG.STBACK2 & (uint32_t)STBAK24_BIT) != 0u) {
thedo 166:3a9487d57a5c 261 /* Wait for the STBAK24 to be cleared to 0. */
thedo 166:3a9487d57a5c 262 }
thedo 166:3a9487d57a5c 263 }
thedo 166:3a9487d57a5c 264 } /* End of function init_func() */
thedo 166:3a9487d57a5c 265
thedo 166:3a9487d57a5c 266 /**************************************************************************//**
thedo 166:3a9487d57a5c 267 * @brief Interrupt service routine acquisition processing
thedo 166:3a9487d57a5c 268 *
thedo 166:3a9487d57a5c 269 * Description:<br>
thedo 166:3a9487d57a5c 270 * This function returns the function pointer to the specified interrupt service routine.
thedo 166:3a9487d57a5c 271 * @param[in] irq : VDC5 interrupt type
thedo 166:3a9487d57a5c 272 * @param[in] enable : VDC5 interrupt enable
thedo 166:3a9487d57a5c 273 * @retval None
thedo 166:3a9487d57a5c 274 ******************************************************************************/
thedo 166:3a9487d57a5c 275 static void DRV_Graphics_Irq_Set(vdc5_int_type_t irq, uint32_t enable)
thedo 166:3a9487d57a5c 276 {
thedo 166:3a9487d57a5c 277 vdc5_channel_t ch = VDC5_CHANNEL_0;
thedo 166:3a9487d57a5c 278 IRQn_Type IRQn;
thedo 166:3a9487d57a5c 279 IRQHandler handler;
thedo 166:3a9487d57a5c 280
thedo 166:3a9487d57a5c 281 IRQn = vdc5_irq_set_tbl[irq];
thedo 166:3a9487d57a5c 282 handler = R_VDC5_GetISR(ch, irq);
thedo 166:3a9487d57a5c 283
thedo 166:3a9487d57a5c 284 if (enable) {
thedo 166:3a9487d57a5c 285 InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler);
thedo 166:3a9487d57a5c 286 GIC_SetPriority(IRQn, 5);
thedo 166:3a9487d57a5c 287 GIC_EnableIRQ(IRQn);
thedo 166:3a9487d57a5c 288 } else {
thedo 166:3a9487d57a5c 289 GIC_DisableIRQ(IRQn);
thedo 166:3a9487d57a5c 290 }
thedo 166:3a9487d57a5c 291 } /* End of function DRV_Graphics_Irq_Set() */
thedo 166:3a9487d57a5c 292
thedo 166:3a9487d57a5c 293 /**************************************************************************//**
thedo 166:3a9487d57a5c 294 * @brief Interrupt callback setup
thedo 166:3a9487d57a5c 295 * This function performs the following processing:
thedo 166:3a9487d57a5c 296 * - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.
thedo 166:3a9487d57a5c 297 * - Registers the specified interrupt callback function.
thedo 166:3a9487d57a5c 298 * - Disables the interrupt when the pointer to the corresponding interrupt callback function is not
thedo 166:3a9487d57a5c 299 * specified.
thedo 166:3a9487d57a5c 300 * @param[in] irq : VDC5 interrupt type
thedo 166:3a9487d57a5c 301 * @param[in] num : Interrupt line number
thedo 166:3a9487d57a5c 302 * @param[in] * callback : Interrupt callback function pointer
thedo 166:3a9487d57a5c 303 * @retval Error code
thedo 166:3a9487d57a5c 304 ******************************************************************************/
thedo 166:3a9487d57a5c 305 drv_graphics_error_t DRV_Graphics_Irq_Handler_Set(
thedo 166:3a9487d57a5c 306 vdc5_int_type_t irq,
thedo 166:3a9487d57a5c 307 uint16_t num,
thedo 166:3a9487d57a5c 308 void (* callback)(vdc5_int_type_t) )
thedo 166:3a9487d57a5c 309 {
thedo 166:3a9487d57a5c 310 vdc5_channel_t ch = VDC5_CHANNEL_0;
thedo 166:3a9487d57a5c 311 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
thedo 166:3a9487d57a5c 312 vdc5_error_t error;
thedo 166:3a9487d57a5c 313 vdc5_int_t interrupt;
thedo 166:3a9487d57a5c 314
thedo 166:3a9487d57a5c 315 if( callback == NULL ) {
thedo 166:3a9487d57a5c 316 DRV_Graphics_Irq_Set( irq, 0 );
thedo 166:3a9487d57a5c 317 } else {
thedo 166:3a9487d57a5c 318 DRV_Graphics_Irq_Set( irq, 1 );
thedo 166:3a9487d57a5c 319 }
thedo 166:3a9487d57a5c 320
thedo 166:3a9487d57a5c 321 /* Interrupt parameter */
thedo 166:3a9487d57a5c 322 interrupt.type = irq; /* Interrupt type */
thedo 166:3a9487d57a5c 323 interrupt.line_num = num ; /* Line number */
thedo 166:3a9487d57a5c 324
thedo 166:3a9487d57a5c 325 /* Interrupt parameter */
thedo 166:3a9487d57a5c 326 interrupt.callback = callback; /* Callback function pointer */
thedo 166:3a9487d57a5c 327 /* Set interrupt service routine */
thedo 166:3a9487d57a5c 328 error = R_VDC5_CallbackISR(ch, &interrupt);
thedo 166:3a9487d57a5c 329 if (error != VDC5_OK) {
thedo 166:3a9487d57a5c 330 drv_error = DRV_GRAPHICS_VDC5_ERR;
thedo 166:3a9487d57a5c 331 }
thedo 166:3a9487d57a5c 332 return drv_error ;
thedo 166:3a9487d57a5c 333 } /* End of function DRV_Graphics_Irq_Handler_Set() */
thedo 166:3a9487d57a5c 334
thedo 166:3a9487d57a5c 335 /**************************************************************************//**
thedo 166:3a9487d57a5c 336 * @brief LCD output port initialization processing
thedo 166:3a9487d57a5c 337 * @param[in] pin : Pin assign for LCD output
thedo 166:3a9487d57a5c 338 * @param[in] pin_count : Total number of pin assign
thedo 166:3a9487d57a5c 339 * @retval Error code
thedo 166:3a9487d57a5c 340 ******************************************************************************/
thedo 166:3a9487d57a5c 341 drv_graphics_error_t DRV_Graphics_Lcd_Port_Init( PinName *pin, uint32_t pin_count )
thedo 166:3a9487d57a5c 342 {
thedo 166:3a9487d57a5c 343 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
thedo 166:3a9487d57a5c 344 uint32_t count;
thedo 166:3a9487d57a5c 345
thedo 166:3a9487d57a5c 346 for( count = 0 ; count < pin_count ; count++ ) {
thedo 166:3a9487d57a5c 347 pinmap_peripheral(pin[count], PinMap_LCD_DISP_PIN);
thedo 166:3a9487d57a5c 348 pinmap_pinout(pin[count], PinMap_LCD_DISP_PIN);
thedo 166:3a9487d57a5c 349 }
thedo 166:3a9487d57a5c 350 return drv_error;
thedo 166:3a9487d57a5c 351 } /* End of function DRV_Graphics_Lcd_Port_Init() */
thedo 166:3a9487d57a5c 352
thedo 166:3a9487d57a5c 353 /**************************************************************************//**
thedo 166:3a9487d57a5c 354 * @brief LVDS output port initialization processing
thedo 166:3a9487d57a5c 355 * @param[in] pin : Pin assign for LVDS output
thedo 166:3a9487d57a5c 356 * @param[in] pin_count : Total number of pin assign
thedo 166:3a9487d57a5c 357 * @retval Error code
thedo 166:3a9487d57a5c 358 ******************************************************************************/
thedo 166:3a9487d57a5c 359 drv_graphics_error_t DRV_Graphics_Lvds_Port_Init( PinName *pin, uint32_t pin_count )
thedo 166:3a9487d57a5c 360 {
thedo 166:3a9487d57a5c 361 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
thedo 166:3a9487d57a5c 362 uint32_t count;
thedo 166:3a9487d57a5c 363
thedo 166:3a9487d57a5c 364 for( count = 0 ; count < pin_count ; count++ ) {
thedo 166:3a9487d57a5c 365 pinmap_peripheral(pin[count], PinMap_LVDS_DISP_PIN);
thedo 166:3a9487d57a5c 366 pinmap_pinout(pin[count], PinMap_LVDS_DISP_PIN);
thedo 166:3a9487d57a5c 367 }
thedo 166:3a9487d57a5c 368 return drv_error;
thedo 166:3a9487d57a5c 369 } /* End of function DRV_Graphics_Lvds_Port_Init() */
thedo 166:3a9487d57a5c 370
thedo 166:3a9487d57a5c 371 /**************************************************************************//**
thedo 166:3a9487d57a5c 372 * @brief Digital video inpout port initialization processing
thedo 166:3a9487d57a5c 373 * @param[in] pin : Pin assign for digital video input port
thedo 166:3a9487d57a5c 374 * @param[in] pin_count : Total number of pin assign
thedo 166:3a9487d57a5c 375 * @retval Error code
thedo 166:3a9487d57a5c 376 ******************************************************************************/
thedo 166:3a9487d57a5c 377 drv_graphics_error_t DRV_Graphics_Dvinput_Port_Init( PinName *pin, uint32_t pin_count )
thedo 166:3a9487d57a5c 378 {
thedo 166:3a9487d57a5c 379 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
thedo 166:3a9487d57a5c 380 uint32_t count;
thedo 166:3a9487d57a5c 381
thedo 166:3a9487d57a5c 382 for( count = 0 ; count < pin_count ; count++ ) {
thedo 166:3a9487d57a5c 383 pinmap_peripheral(pin[count], PinMap_DV_INPUT_PIN);
thedo 166:3a9487d57a5c 384 pinmap_pinout(pin[count], PinMap_DV_INPUT_PIN);
thedo 166:3a9487d57a5c 385 }
thedo 166:3a9487d57a5c 386 return drv_error;
thedo 166:3a9487d57a5c 387 } /* End of function DRV_Graphics_Dvinput_Port_Init() */
thedo 166:3a9487d57a5c 388
thedo 166:3a9487d57a5c 389 /**************************************************************************//**
thedo 166:3a9487d57a5c 390 * @brief Graphics initialization processing
thedo 166:3a9487d57a5c 391 * @param[in] drv_lcd_config : LCD configuration
thedo 166:3a9487d57a5c 392 * @retval Error code
thedo 166:3a9487d57a5c 393 ******************************************************************************/
thedo 166:3a9487d57a5c 394 drv_graphics_error_t DRV_Graphics_Init( drv_lcd_config_t * drv_lcd_config )
thedo 166:3a9487d57a5c 395 {
thedo 166:3a9487d57a5c 396 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
thedo 166:3a9487d57a5c 397 vdc5_channel_t ch = VDC5_CHANNEL_0;
thedo 166:3a9487d57a5c 398 vdc5_error_t error;
thedo 166:3a9487d57a5c 399 vdc5_init_t init;
thedo 166:3a9487d57a5c 400 vdc5_lvds_t vdc5_lvds;
thedo 166:3a9487d57a5c 401 pll_parameter_t pll_parameter;
thedo 166:3a9487d57a5c 402 double InputClock = DEFAULT_INPUT_CLOCK;
thedo 166:3a9487d57a5c 403 double OutputClock = DEFAULT_OUTPUT_CLOCK;
thedo 166:3a9487d57a5c 404 uint32_t LvdsUsed = LVDS_IF_USE;
thedo 166:3a9487d57a5c 405
thedo 166:3a9487d57a5c 406 /* Initialization parameter */
thedo 166:3a9487d57a5c 407 init.panel_icksel = VDC5_PANEL_ICKSEL_LVDS; /* Panel clock select */
thedo 166:3a9487d57a5c 408 init.panel_dcdr = VDC5_PANEL_CLKDIV_1_1; /* Panel clock frequency division ratio */
thedo 166:3a9487d57a5c 409
thedo 166:3a9487d57a5c 410 if( drv_lcd_config != NULL ) {
thedo 166:3a9487d57a5c 411 InputClock = drv_lcd_config->intputClock;
thedo 166:3a9487d57a5c 412 OutputClock = drv_lcd_config->outputClock;
thedo 166:3a9487d57a5c 413
thedo 166:3a9487d57a5c 414 /* LVDS PLL Setting Calculation */
thedo 166:3a9487d57a5c 415 if( drv_lcd_config->lcd_type == DRV_LCD_TYPE_LVDS ) {
thedo 166:3a9487d57a5c 416 LvdsUsed = LVDS_IF_USE;
thedo 166:3a9487d57a5c 417 init.panel_icksel = VDC5_PANEL_ICKSEL_LVDS_DIV7; /* Panel clock select */
thedo 166:3a9487d57a5c 418 } else {
thedo 166:3a9487d57a5c 419 LvdsUsed = LVDS_IF_NOT_USE;
thedo 166:3a9487d57a5c 420 }
thedo 166:3a9487d57a5c 421 }
thedo 166:3a9487d57a5c 422 lvds_pll_calc( InputClock, OutputClock, LvdsUsed, &pll_parameter );
thedo 166:3a9487d57a5c 423
thedo 166:3a9487d57a5c 424 vdc5_lvds.lvds_in_clk_sel = VDC5_LVDS_INCLK_SEL_PERI; /* P1 */
thedo 166:3a9487d57a5c 425 vdc5_lvds.lvds_idiv_set = (vdc5_lvds_ndiv_t)pll_parameter.nidiv;
thedo 166:3a9487d57a5c 426 vdc5_lvds.lvdspll_tst = 16u;
thedo 166:3a9487d57a5c 427 vdc5_lvds.lvds_odiv_set = (vdc5_lvds_ndiv_t)pll_parameter.nodiv;
thedo 166:3a9487d57a5c 428 vdc5_lvds.lvdspll_tst = 16u;
thedo 166:3a9487d57a5c 429 vdc5_lvds.lvds_vdc_sel = ch;
thedo 166:3a9487d57a5c 430 vdc5_lvds.lvdspll_fd = pll_parameter.nfd;
thedo 166:3a9487d57a5c 431 vdc5_lvds.lvdspll_rd = pll_parameter.nrd;
thedo 166:3a9487d57a5c 432 vdc5_lvds.lvdspll_od = (vdc5_lvds_pll_nod_t)pll_parameter.nod;
thedo 166:3a9487d57a5c 433 init.lvds = &vdc5_lvds; /* LVDS parameter */
thedo 166:3a9487d57a5c 434
thedo 166:3a9487d57a5c 435 /* Initialize (Set module clock to VDC5) */
thedo 166:3a9487d57a5c 436 error = R_VDC5_Initialize( ch, &init, &init_func, (uint32_t)ch );
thedo 166:3a9487d57a5c 437 if (error != VDC5_OK) {
thedo 166:3a9487d57a5c 438 drv_error = DRV_GRAPHICS_VDC5_ERR;
thedo 166:3a9487d57a5c 439 }
thedo 166:3a9487d57a5c 440
thedo 166:3a9487d57a5c 441 if ( drv_error == DRV_GRAPHICS_OK ) {
thedo 166:3a9487d57a5c 442 vdc5_sync_ctrl_t sync_ctrl;
thedo 166:3a9487d57a5c 443
thedo 166:3a9487d57a5c 444 /* Sync signal control */
thedo 166:3a9487d57a5c 445 sync_ctrl.res_vs_sel = VDC5_ON; /* Vsync signal output select (free-running Vsync on/off control) */
thedo 166:3a9487d57a5c 446 /* Sync signal output and full-screen enable signal select */
thedo 166:3a9487d57a5c 447 sync_ctrl.res_vs_in_sel = VDC5_RES_VS_IN_SEL_SC0;
thedo 166:3a9487d57a5c 448 sync_ctrl.res_fv = drv_lcd_config->v_toatal_period-1; /* Free-running Vsync period setting */
thedo 166:3a9487d57a5c 449 sync_ctrl.res_fh = drv_lcd_config->h_toatal_period-1; /* Hsync period setting */
thedo 166:3a9487d57a5c 450 sync_ctrl.res_vsdly = (uint16_t)0u; /* Vsync signal delay control */
thedo 166:3a9487d57a5c 451 /* Full-screen enable control */
thedo 166:3a9487d57a5c 452 sync_ctrl.res_f.vs = (drv_lcd_config->v_back_porch);
thedo 166:3a9487d57a5c 453 sync_ctrl.res_f.vw = (drv_lcd_config->v_disp_widht);
thedo 166:3a9487d57a5c 454 sync_ctrl.res_f.hs = (drv_lcd_config->h_back_porch);
thedo 166:3a9487d57a5c 455 sync_ctrl.res_f.hw = (drv_lcd_config->h_disp_widht);
thedo 166:3a9487d57a5c 456 sync_ctrl.vsync_cpmpe = NULL; /* Vsync signal compensation */
thedo 166:3a9487d57a5c 457 /* Sync control */
thedo 166:3a9487d57a5c 458 error = R_VDC5_SyncControl( ch, &sync_ctrl );
thedo 166:3a9487d57a5c 459 if (error != VDC5_OK) {
thedo 166:3a9487d57a5c 460 drv_error = DRV_GRAPHICS_VDC5_ERR;
thedo 166:3a9487d57a5c 461 }
thedo 166:3a9487d57a5c 462 }
thedo 166:3a9487d57a5c 463
thedo 166:3a9487d57a5c 464 if ( drv_error == DRV_GRAPHICS_OK ) {
thedo 166:3a9487d57a5c 465 vdc5_output_t output;
thedo 166:3a9487d57a5c 466 vdc5_lcd_tcon_timing_t lcd_tcon_timing_VS;
thedo 166:3a9487d57a5c 467 vdc5_lcd_tcon_timing_t lcd_tcon_timing_VE;
thedo 166:3a9487d57a5c 468 vdc5_lcd_tcon_timing_t lcd_tcon_timing_HS;
thedo 166:3a9487d57a5c 469 vdc5_lcd_tcon_timing_t lcd_tcon_timing_HE;
thedo 166:3a9487d57a5c 470 vdc5_lcd_tcon_timing_t lcd_tcon_timing_DE;
thedo 166:3a9487d57a5c 471
thedo 166:3a9487d57a5c 472 /* Output parameter */
thedo 166:3a9487d57a5c 473 output.tcon_half = (drv_lcd_config->h_toatal_period-1)/2; /* TCON reference timing, 1/2fH timing */
thedo 166:3a9487d57a5c 474 output.tcon_offset = 0; /* TCON reference timing, offset Hsync signal timing */
thedo 166:3a9487d57a5c 475
thedo 166:3a9487d57a5c 476 /* LCD TCON timing setting */
thedo 166:3a9487d57a5c 477 if( drv_lcd_config->v_sync_port != DRV_LCD_TCON_PIN_NON ) {
thedo 166:3a9487d57a5c 478 lcd_tcon_timing_VS.tcon_hsvs = 0u;
thedo 166:3a9487d57a5c 479 lcd_tcon_timing_VS.tcon_hwvw = (drv_lcd_config->v_sync_width * 2u);
thedo 166:3a9487d57a5c 480 lcd_tcon_timing_VS.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
thedo 166:3a9487d57a5c 481 lcd_tcon_timing_VS.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
thedo 166:3a9487d57a5c 482 lcd_tcon_timing_VS.tcon_inv = (vdc5_sig_pol_t)drv_lcd_config->v_sync_port_polarity;
thedo 166:3a9487d57a5c 483 lcd_tcon_timing_VS.tcon_pin = (vdc5_lcd_tcon_pin_t)drv_lcd_config->v_sync_port;
thedo 166:3a9487d57a5c 484 lcd_tcon_timing_VS.outcnt_edge = VDC5_EDGE_FALLING;
thedo 166:3a9487d57a5c 485 output.outctrl[VDC5_LCD_TCONSIG_STVA_VS] = &lcd_tcon_timing_VS; /* STVA/VS: Vsync */
thedo 166:3a9487d57a5c 486 } else {
thedo 166:3a9487d57a5c 487 output.outctrl[VDC5_LCD_TCONSIG_STVA_VS] = NULL; /* STVA/VS: Vsync */
thedo 166:3a9487d57a5c 488 }
thedo 166:3a9487d57a5c 489
thedo 166:3a9487d57a5c 490 if( drv_lcd_config->h_sync_port != DRV_LCD_TCON_PIN_NON ) {
thedo 166:3a9487d57a5c 491 lcd_tcon_timing_HS.tcon_hsvs = 0u;
thedo 166:3a9487d57a5c 492 lcd_tcon_timing_HS.tcon_hwvw = drv_lcd_config->h_sync_width;
thedo 166:3a9487d57a5c 493 lcd_tcon_timing_HS.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
thedo 166:3a9487d57a5c 494 lcd_tcon_timing_HS.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
thedo 166:3a9487d57a5c 495 lcd_tcon_timing_HS.tcon_inv = (vdc5_sig_pol_t)drv_lcd_config->h_sync_port_polarity;
thedo 166:3a9487d57a5c 496 lcd_tcon_timing_HS.tcon_pin = (vdc5_lcd_tcon_pin_t)drv_lcd_config->h_sync_port;
thedo 166:3a9487d57a5c 497 lcd_tcon_timing_HS.outcnt_edge = VDC5_EDGE_FALLING;
thedo 166:3a9487d57a5c 498 output.outctrl[VDC5_LCD_TCONSIG_STH_SP_HS] = &lcd_tcon_timing_HS; /* STH/SP/HS: Hsync */
thedo 166:3a9487d57a5c 499 } else {
thedo 166:3a9487d57a5c 500 output.outctrl[VDC5_LCD_TCONSIG_STH_SP_HS] = NULL; /* STH/SP/HS: Hsync */
thedo 166:3a9487d57a5c 501 }
thedo 166:3a9487d57a5c 502
thedo 166:3a9487d57a5c 503 if( drv_lcd_config->de_port != DRV_LCD_TCON_PIN_NON ) {
thedo 166:3a9487d57a5c 504 lcd_tcon_timing_VE.tcon_hsvs = (drv_lcd_config->v_back_porch * 2u);
thedo 166:3a9487d57a5c 505 lcd_tcon_timing_VE.tcon_hwvw = (drv_lcd_config->v_disp_widht * 2u);
thedo 166:3a9487d57a5c 506 lcd_tcon_timing_VE.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
thedo 166:3a9487d57a5c 507 lcd_tcon_timing_VE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
thedo 166:3a9487d57a5c 508 lcd_tcon_timing_VE.tcon_inv = (vdc5_sig_pol_t)drv_lcd_config->de_port_polarity;
thedo 166:3a9487d57a5c 509 lcd_tcon_timing_VE.tcon_pin = VDC5_LCD_TCON_PIN_NON;
thedo 166:3a9487d57a5c 510 lcd_tcon_timing_VE.outcnt_edge = VDC5_EDGE_FALLING;
thedo 166:3a9487d57a5c 511 output.outctrl[VDC5_LCD_TCONSIG_STVB_VE] = &lcd_tcon_timing_VE; /* STVB/VE: Not used */
thedo 166:3a9487d57a5c 512
thedo 166:3a9487d57a5c 513 lcd_tcon_timing_HE.tcon_hsvs = drv_lcd_config->h_back_porch;
thedo 166:3a9487d57a5c 514 lcd_tcon_timing_HE.tcon_hwvw = drv_lcd_config->h_disp_widht;
thedo 166:3a9487d57a5c 515 lcd_tcon_timing_HE.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
thedo 166:3a9487d57a5c 516 lcd_tcon_timing_HE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
thedo 166:3a9487d57a5c 517 lcd_tcon_timing_HE.tcon_inv = (vdc5_sig_pol_t)drv_lcd_config->de_port_polarity;
thedo 166:3a9487d57a5c 518 lcd_tcon_timing_HE.tcon_pin = VDC5_LCD_TCON_PIN_NON;
thedo 166:3a9487d57a5c 519 lcd_tcon_timing_HE.outcnt_edge = VDC5_EDGE_FALLING;
thedo 166:3a9487d57a5c 520 output.outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = &lcd_tcon_timing_HE; /* STB/LP/HE: Not used */
thedo 166:3a9487d57a5c 521
thedo 166:3a9487d57a5c 522 lcd_tcon_timing_DE.tcon_hsvs = 0u;
thedo 166:3a9487d57a5c 523 lcd_tcon_timing_DE.tcon_hwvw = 0u;
thedo 166:3a9487d57a5c 524 lcd_tcon_timing_DE.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
thedo 166:3a9487d57a5c 525 lcd_tcon_timing_DE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
thedo 166:3a9487d57a5c 526 lcd_tcon_timing_DE.tcon_inv = (vdc5_sig_pol_t)drv_lcd_config->de_port_polarity;
thedo 166:3a9487d57a5c 527 lcd_tcon_timing_DE.tcon_pin = (vdc5_lcd_tcon_pin_t)drv_lcd_config->de_port;
thedo 166:3a9487d57a5c 528 lcd_tcon_timing_DE.outcnt_edge = VDC5_EDGE_FALLING;
thedo 166:3a9487d57a5c 529 output.outctrl[VDC5_LCD_TCONSIG_DE] = &lcd_tcon_timing_DE; /* DE */
thedo 166:3a9487d57a5c 530 } else {
thedo 166:3a9487d57a5c 531 output.outctrl[VDC5_LCD_TCONSIG_STVB_VE] = NULL; /* STVB/VE: Not used */
thedo 166:3a9487d57a5c 532 output.outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = NULL; /* STB/LP/HE: Not used */
thedo 166:3a9487d57a5c 533 output.outctrl[VDC5_LCD_TCONSIG_DE] = NULL; /* DE */
thedo 166:3a9487d57a5c 534 }
thedo 166:3a9487d57a5c 535
thedo 166:3a9487d57a5c 536 output.outctrl[VDC5_LCD_TCONSIG_CPV_GCK] = NULL;
thedo 166:3a9487d57a5c 537 output.outctrl[VDC5_LCD_TCONSIG_POLA] = NULL;
thedo 166:3a9487d57a5c 538 output.outctrl[VDC5_LCD_TCONSIG_POLB] = NULL;
thedo 166:3a9487d57a5c 539
thedo 166:3a9487d57a5c 540 output.outcnt_lcd_edge = (vdc5_edge_t)drv_lcd_config->lcd_edge; /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
thedo 166:3a9487d57a5c 541 output.out_endian_on = VDC5_OFF; /* Bit endian change on/off control */
thedo 166:3a9487d57a5c 542 output.out_swap_on = VDC5_OFF; /* B/R signal swap on/off control */
thedo 166:3a9487d57a5c 543 output.out_format = (vdc5_lcd_outformat_t)drv_lcd_config->lcd_outformat; /* Output format select */
thedo 166:3a9487d57a5c 544 output.out_frq_sel = VDC5_LCD_PARALLEL_CLKFRQ_1; /* Clock frequency control */
thedo 166:3a9487d57a5c 545 output.out_dir_sel = VDC5_LCD_SERIAL_SCAN_FORWARD; /* Scan direction select */
thedo 166:3a9487d57a5c 546 output.out_phase = VDC5_LCD_SERIAL_CLKPHASE_0; /* Clock phase adjustment */
thedo 166:3a9487d57a5c 547 output.bg_color = (uint32_t)0x00000000u; /* Background color in 24-bit RGB color format */
thedo 166:3a9487d57a5c 548 /* Display output */
thedo 166:3a9487d57a5c 549 error = R_VDC5_DisplayOutput( ch, &output );
thedo 166:3a9487d57a5c 550 if (error != VDC5_OK) {
thedo 166:3a9487d57a5c 551 drv_error = DRV_GRAPHICS_VDC5_ERR;
thedo 166:3a9487d57a5c 552 }
thedo 166:3a9487d57a5c 553 }
thedo 166:3a9487d57a5c 554 return drv_error;
thedo 166:3a9487d57a5c 555 } /* End of function DRV_Graphics_Init() */
thedo 166:3a9487d57a5c 556
thedo 166:3a9487d57a5c 557 /**************************************************************************//**
thedo 166:3a9487d57a5c 558 * @brief Video initialization processing
thedo 166:3a9487d57a5c 559 * @param[in] drv_video_ext_in_config : Video configuration
thedo 166:3a9487d57a5c 560 * @retval Error code
thedo 166:3a9487d57a5c 561 ******************************************************************************/
thedo 166:3a9487d57a5c 562 drv_graphics_error_t DRV_Graphics_Video_init( drv_video_input_sel_t drv_video_input_sel, drv_video_ext_in_config_t * drv_video_ext_in_config )
thedo 166:3a9487d57a5c 563 {
thedo 166:3a9487d57a5c 564 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
thedo 166:3a9487d57a5c 565 vdc5_error_t error;
thedo 166:3a9487d57a5c 566 vdc5_input_t input;
thedo 166:3a9487d57a5c 567 vdc5_ext_in_sig_t ext_in_sig;
thedo 166:3a9487d57a5c 568 vdc5_sync_delay_t sync_delay;
thedo 166:3a9487d57a5c 569
thedo 166:3a9487d57a5c 570 input.inp_sel = (vdc5_input_sel_t)drv_video_input_sel; /* Input select */
thedo 166:3a9487d57a5c 571 input.inp_fh50 = (uint16_t)VSYNC_1_2_FH_TIMING; /* Vsync signal 1/2fH phase timing */
thedo 166:3a9487d57a5c 572 input.inp_fh25 = (uint16_t)VSYNC_1_4_FH_TIMING; /* Vsync signal 1/4fH phase timing */
thedo 166:3a9487d57a5c 573
thedo 166:3a9487d57a5c 574 if( drv_video_input_sel == DRV_INPUT_SEL_VDEC ) {
thedo 166:3a9487d57a5c 575 input.dly = NULL; /* Sync signal delay adjustment */
thedo 166:3a9487d57a5c 576 input.ext_sig = NULL; /* External input signal */
thedo 166:3a9487d57a5c 577 } else {
thedo 166:3a9487d57a5c 578 ext_in_sig.inp_format = (vdc5_extin_format_t)drv_video_ext_in_config->inp_format;
thedo 166:3a9487d57a5c 579 ext_in_sig.inp_pxd_edge = (vdc5_edge_t)drv_video_ext_in_config->inp_pxd_edge;
thedo 166:3a9487d57a5c 580 ext_in_sig.inp_vs_edge = (vdc5_edge_t)drv_video_ext_in_config->inp_vs_edge;
thedo 166:3a9487d57a5c 581 ext_in_sig.inp_hs_edge = (vdc5_edge_t)drv_video_ext_in_config->inp_hs_edge;
thedo 166:3a9487d57a5c 582 ext_in_sig.inp_endian_on = (vdc5_onoff_t)drv_video_ext_in_config->inp_endian_on;
thedo 166:3a9487d57a5c 583 ext_in_sig.inp_swap_on = (vdc5_onoff_t)drv_video_ext_in_config->inp_swap_on;
thedo 166:3a9487d57a5c 584 ext_in_sig.inp_vs_inv = (vdc5_sig_pol_t)drv_video_ext_in_config->inp_vs_inv;
thedo 166:3a9487d57a5c 585 ext_in_sig.inp_hs_inv = (vdc5_sig_pol_t)drv_video_ext_in_config->inp_hs_inv;
thedo 166:3a9487d57a5c 586 ext_in_sig.inp_h_edge_sel = (vdc5_extin_ref_hsync_t)drv_video_ext_in_config->inp_hs_edge;
thedo 166:3a9487d57a5c 587 ext_in_sig.inp_f525_625 = (vdc5_extin_input_line_t)drv_video_ext_in_config->inp_f525_625;
thedo 166:3a9487d57a5c 588 ext_in_sig.inp_h_pos = (vdc5_extin_h_pos_t)drv_video_ext_in_config->inp_h_pos;
thedo 166:3a9487d57a5c 589
thedo 166:3a9487d57a5c 590 sync_delay.inp_vs_dly_l = 0u;
thedo 166:3a9487d57a5c 591 sync_delay.inp_vs_dly = 16u;
thedo 166:3a9487d57a5c 592 sync_delay.inp_hs_dly = 16u;
thedo 166:3a9487d57a5c 593 sync_delay.inp_fld_dly = 16u;
thedo 166:3a9487d57a5c 594
thedo 166:3a9487d57a5c 595 input.dly = &sync_delay; /* Sync signal delay adjustment */
thedo 166:3a9487d57a5c 596 input.ext_sig = &ext_in_sig; /* External input signal */
thedo 166:3a9487d57a5c 597 }
thedo 166:3a9487d57a5c 598 /* Video input 0ch */
thedo 166:3a9487d57a5c 599 error = R_VDC5_VideoInput( VDC5_CHANNEL_0, &input );
thedo 166:3a9487d57a5c 600 if (error != VDC5_OK) {
thedo 166:3a9487d57a5c 601 drv_error = DRV_GRAPHICS_VDC5_ERR;
thedo 166:3a9487d57a5c 602 }
thedo 166:3a9487d57a5c 603
thedo 166:3a9487d57a5c 604 if( drv_video_input_sel == DRV_INPUT_SEL_VDEC ) {
thedo 166:3a9487d57a5c 605 if ( drv_error == DRV_GRAPHICS_OK ) {
thedo 166:3a9487d57a5c 606 /* Video input 1ch */
thedo 166:3a9487d57a5c 607 error = R_VDC5_VideoInput( VDC5_CHANNEL_1, &input );
thedo 166:3a9487d57a5c 608 if (error != VDC5_OK) {
thedo 166:3a9487d57a5c 609 drv_error = DRV_GRAPHICS_VDC5_ERR;
thedo 166:3a9487d57a5c 610 }
thedo 166:3a9487d57a5c 611 }
thedo 166:3a9487d57a5c 612 }
thedo 166:3a9487d57a5c 613 return drv_error;
thedo 166:3a9487d57a5c 614 } /* End of function DRV_Video_Init() */
thedo 166:3a9487d57a5c 615
thedo 166:3a9487d57a5c 616 /**************************************************************************//**
thedo 166:3a9487d57a5c 617 * @brief Start the graphics surface read process
thedo 166:3a9487d57a5c 618 * @param[in] layer_id : Graphics layer ID
thedo 166:3a9487d57a5c 619 * @retval drv_graphics_error_t
thedo 166:3a9487d57a5c 620 ******************************************************************************/
thedo 166:3a9487d57a5c 621 drv_graphics_error_t DRV_Graphics_Start ( drv_graphics_layer_t layer_id )
thedo 166:3a9487d57a5c 622 {
thedo 166:3a9487d57a5c 623 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
thedo 166:3a9487d57a5c 624 vdc5_channel_t ch = VDC5_CHANNEL_0;
thedo 166:3a9487d57a5c 625 vdc5_error_t error;
thedo 166:3a9487d57a5c 626 vdc5_start_t start;
thedo 166:3a9487d57a5c 627 vdc5_gr_disp_sel_t gr_disp_sel;
thedo 166:3a9487d57a5c 628 vdc5_layer_id_t vdc5_layer_id;
thedo 166:3a9487d57a5c 629
thedo 166:3a9487d57a5c 630 switch( layer_id ) {
thedo 166:3a9487d57a5c 631 case DRV_GRAPHICS_LAYER_0:
thedo 166:3a9487d57a5c 632 vdc5_layer_id = VDC5_LAYER_ID_0_RD;
thedo 166:3a9487d57a5c 633 gr_disp_sel = VDC5_DISPSEL_CURRENT;
thedo 166:3a9487d57a5c 634 break;
thedo 166:3a9487d57a5c 635 case DRV_GRAPHICS_LAYER_1:
thedo 166:3a9487d57a5c 636 vdc5_layer_id = VDC5_LAYER_ID_1_RD;
thedo 166:3a9487d57a5c 637 gr_disp_sel = VDC5_DISPSEL_BLEND;
thedo 166:3a9487d57a5c 638 break;
thedo 166:3a9487d57a5c 639 case DRV_GRAPHICS_LAYER_2:
thedo 166:3a9487d57a5c 640 vdc5_layer_id = VDC5_LAYER_ID_2_RD;
thedo 166:3a9487d57a5c 641 gr_disp_sel = VDC5_DISPSEL_BLEND;
thedo 166:3a9487d57a5c 642 break;
thedo 166:3a9487d57a5c 643 case DRV_GRAPHICS_LAYER_3:
thedo 166:3a9487d57a5c 644 vdc5_layer_id = VDC5_LAYER_ID_3_RD;
thedo 166:3a9487d57a5c 645 gr_disp_sel = VDC5_DISPSEL_BLEND;
thedo 166:3a9487d57a5c 646 break;
thedo 166:3a9487d57a5c 647 default:
thedo 166:3a9487d57a5c 648 drv_error = DRV_GRAPHICS_LAYER_ERR;
thedo 166:3a9487d57a5c 649 break;
thedo 166:3a9487d57a5c 650 }
thedo 166:3a9487d57a5c 651
thedo 166:3a9487d57a5c 652 if( drv_error == DRV_GRAPHICS_OK ) {
thedo 166:3a9487d57a5c 653 /* Start process */
thedo 166:3a9487d57a5c 654 start.gr_disp_sel = &gr_disp_sel;
thedo 166:3a9487d57a5c 655 error = R_VDC5_StartProcess( ch, vdc5_layer_id, &start );
thedo 166:3a9487d57a5c 656 if (error != VDC5_OK) {
thedo 166:3a9487d57a5c 657 drv_error = DRV_GRAPHICS_VDC5_ERR;
thedo 166:3a9487d57a5c 658 }
thedo 166:3a9487d57a5c 659 }
thedo 166:3a9487d57a5c 660 return drv_error;
thedo 166:3a9487d57a5c 661 } /* End of function DRV_Graphics_Start() */
thedo 166:3a9487d57a5c 662
thedo 166:3a9487d57a5c 663 /**************************************************************************//**
thedo 166:3a9487d57a5c 664 * @brief Stop the graphics surface read process
thedo 166:3a9487d57a5c 665 * @param[in] layer_id : Graphics layer ID
thedo 166:3a9487d57a5c 666 * @retval Error code
thedo 166:3a9487d57a5c 667 ******************************************************************************/
thedo 166:3a9487d57a5c 668 drv_graphics_error_t DRV_Graphics_Stop ( drv_graphics_layer_t layer_id )
thedo 166:3a9487d57a5c 669 {
thedo 166:3a9487d57a5c 670 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
thedo 166:3a9487d57a5c 671 vdc5_channel_t ch = VDC5_CHANNEL_0;
thedo 166:3a9487d57a5c 672 vdc5_error_t error;
thedo 166:3a9487d57a5c 673 vdc5_layer_id_t vdc5_layer_id;
thedo 166:3a9487d57a5c 674
thedo 166:3a9487d57a5c 675 switch( layer_id ) {
thedo 166:3a9487d57a5c 676 case DRV_GRAPHICS_LAYER_0:
thedo 166:3a9487d57a5c 677 vdc5_layer_id = VDC5_LAYER_ID_0_RD;
thedo 166:3a9487d57a5c 678 break;
thedo 166:3a9487d57a5c 679 case DRV_GRAPHICS_LAYER_1:
thedo 166:3a9487d57a5c 680 vdc5_layer_id = VDC5_LAYER_ID_1_RD;
thedo 166:3a9487d57a5c 681 break;
thedo 166:3a9487d57a5c 682 case DRV_GRAPHICS_LAYER_2:
thedo 166:3a9487d57a5c 683 vdc5_layer_id = VDC5_LAYER_ID_2_RD;
thedo 166:3a9487d57a5c 684 break;
thedo 166:3a9487d57a5c 685 case DRV_GRAPHICS_LAYER_3:
thedo 166:3a9487d57a5c 686 vdc5_layer_id = VDC5_LAYER_ID_3_RD;
thedo 166:3a9487d57a5c 687 break;
thedo 166:3a9487d57a5c 688 default:
thedo 166:3a9487d57a5c 689 drv_error = DRV_GRAPHICS_LAYER_ERR;
thedo 166:3a9487d57a5c 690 break;
thedo 166:3a9487d57a5c 691 }
thedo 166:3a9487d57a5c 692
thedo 166:3a9487d57a5c 693 if( drv_error == DRV_GRAPHICS_OK ) {
thedo 166:3a9487d57a5c 694 /* Stop process */
thedo 166:3a9487d57a5c 695 error = R_VDC5_StopProcess ( ch, vdc5_layer_id );
thedo 166:3a9487d57a5c 696 if (error != VDC5_OK) {
thedo 166:3a9487d57a5c 697 drv_error = DRV_GRAPHICS_VDC5_ERR;
thedo 166:3a9487d57a5c 698 }
thedo 166:3a9487d57a5c 699 }
thedo 166:3a9487d57a5c 700 return drv_error;
thedo 166:3a9487d57a5c 701 } /* End of function DRV_Graphics_Stop() */
thedo 166:3a9487d57a5c 702
thedo 166:3a9487d57a5c 703 /**************************************************************************//**
thedo 166:3a9487d57a5c 704 * @brief Start the video surface write process
thedo 166:3a9487d57a5c 705 * @param[in] video_input_ch : Video input channel
thedo 166:3a9487d57a5c 706 * @retval Error code
thedo 166:3a9487d57a5c 707 ******************************************************************************/
thedo 166:3a9487d57a5c 708 drv_graphics_error_t DRV_Video_Start ( drv_video_input_channel_t video_input_ch )
thedo 166:3a9487d57a5c 709 {
thedo 166:3a9487d57a5c 710 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
thedo 166:3a9487d57a5c 711 vdc5_channel_t ch = VDC5_CHANNEL_0;
thedo 166:3a9487d57a5c 712 vdc5_error_t error;
thedo 166:3a9487d57a5c 713 vdc5_start_t start;
thedo 166:3a9487d57a5c 714 vdc5_gr_disp_sel_t gr_disp_sel;
thedo 166:3a9487d57a5c 715 vdc5_layer_id_t vdc5_layer_id;
thedo 166:3a9487d57a5c 716
thedo 166:3a9487d57a5c 717 if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) {
thedo 166:3a9487d57a5c 718 vdc5_layer_id = VDC5_LAYER_ID_0_WR;
thedo 166:3a9487d57a5c 719 } else if ( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1 ) {
thedo 166:3a9487d57a5c 720 vdc5_layer_id = VDC5_LAYER_ID_1_WR;
thedo 166:3a9487d57a5c 721 } else {
thedo 166:3a9487d57a5c 722 drv_error = DRV_GRAPHICS_LAYER_ERR;
thedo 166:3a9487d57a5c 723 }
thedo 166:3a9487d57a5c 724
thedo 166:3a9487d57a5c 725 if( drv_error == DRV_GRAPHICS_OK ) {
thedo 166:3a9487d57a5c 726 /* Start process */
thedo 166:3a9487d57a5c 727 gr_disp_sel = VDC5_DISPSEL_CURRENT; /* CURRENT fixed for weave input mode */
thedo 166:3a9487d57a5c 728 start.gr_disp_sel = &gr_disp_sel;
thedo 166:3a9487d57a5c 729 error = R_VDC5_StartProcess( ch, vdc5_layer_id, &start );
thedo 166:3a9487d57a5c 730 if (error != VDC5_OK) {
thedo 166:3a9487d57a5c 731 drv_error = DRV_GRAPHICS_VDC5_ERR;
thedo 166:3a9487d57a5c 732 }
thedo 166:3a9487d57a5c 733 }
thedo 166:3a9487d57a5c 734 return drv_error;
thedo 166:3a9487d57a5c 735 } /* End of function DRV_Video_Start() */
thedo 166:3a9487d57a5c 736
thedo 166:3a9487d57a5c 737 /**************************************************************************//**
thedo 166:3a9487d57a5c 738 * @brief Stop the video surface write process
thedo 166:3a9487d57a5c 739 * @param[in] video_input_ch : Video input channel
thedo 166:3a9487d57a5c 740 * @retval Error code
thedo 166:3a9487d57a5c 741 ******************************************************************************/
thedo 166:3a9487d57a5c 742 drv_graphics_error_t DRV_Video_Stop ( drv_video_input_channel_t video_input_ch )
thedo 166:3a9487d57a5c 743 {
thedo 166:3a9487d57a5c 744 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
thedo 166:3a9487d57a5c 745 vdc5_channel_t ch = VDC5_CHANNEL_0;
thedo 166:3a9487d57a5c 746 vdc5_error_t error;
thedo 166:3a9487d57a5c 747 vdc5_layer_id_t vdc5_layer_id;
thedo 166:3a9487d57a5c 748
thedo 166:3a9487d57a5c 749 switch (video_input_ch) {
thedo 166:3a9487d57a5c 750 case DRV_VIDEO_INPUT_CHANNEL_0:
thedo 166:3a9487d57a5c 751 vdc5_layer_id = VDC5_LAYER_ID_0_WR;
thedo 166:3a9487d57a5c 752 break;
thedo 166:3a9487d57a5c 753 case DRV_VIDEO_INPUT_CHANNEL_1:
thedo 166:3a9487d57a5c 754 vdc5_layer_id = VDC5_LAYER_ID_1_WR;
thedo 166:3a9487d57a5c 755 break;
thedo 166:3a9487d57a5c 756 default:
thedo 166:3a9487d57a5c 757 drv_error = DRV_GRAPHICS_LAYER_ERR;
thedo 166:3a9487d57a5c 758 break;
thedo 166:3a9487d57a5c 759 }
thedo 166:3a9487d57a5c 760
thedo 166:3a9487d57a5c 761 if( drv_error == DRV_GRAPHICS_OK ) {
thedo 166:3a9487d57a5c 762 /* Stop process */
thedo 166:3a9487d57a5c 763 error = R_VDC5_StopProcess ( ch, vdc5_layer_id );
thedo 166:3a9487d57a5c 764 if (error != VDC5_OK) {
thedo 166:3a9487d57a5c 765 drv_error = DRV_GRAPHICS_VDC5_ERR;
thedo 166:3a9487d57a5c 766 }
thedo 166:3a9487d57a5c 767 }
thedo 166:3a9487d57a5c 768 return drv_error;
thedo 166:3a9487d57a5c 769 } /* End of function DRV_Video_Stop() */
thedo 166:3a9487d57a5c 770
thedo 166:3a9487d57a5c 771 /**************************************************************************//**
thedo 166:3a9487d57a5c 772 * @brief Graphics surface read process setting
thedo 166:3a9487d57a5c 773 *
thedo 166:3a9487d57a5c 774 * Description:<br>
thedo 166:3a9487d57a5c 775 * This function supports the following 4 image format.
thedo 166:3a9487d57a5c 776 * YCbCr422, RGB565, RGB888, ARGB8888
thedo 166:3a9487d57a5c 777 * @param[in] layer_id : Graphics layer ID
thedo 166:3a9487d57a5c 778 * @param[in] framebuff : Base address of the frame buffer
thedo 166:3a9487d57a5c 779 * @param[in] fb_stride : Line offset address of the frame buffer
thedo 166:3a9487d57a5c 780 * @param[in] gr_format : Format of the frame buffer read signal
thedo 166:3a9487d57a5c 781 * @param[in] gr_rect : Graphics display area
thedo 166:3a9487d57a5c 782 * @retval Error code
thedo 166:3a9487d57a5c 783 ******************************************************************************/
thedo 166:3a9487d57a5c 784 drv_graphics_error_t DRV_Graphics_Read_Setting (
thedo 166:3a9487d57a5c 785 drv_graphics_layer_t layer_id,
thedo 166:3a9487d57a5c 786 void * framebuff,
thedo 166:3a9487d57a5c 787 uint32_t fb_stride,
thedo 166:3a9487d57a5c 788 drv_graphics_format_t gr_format,
thedo 166:3a9487d57a5c 789 drv_wr_rd_swa_t wr_rd_swa,
thedo 166:3a9487d57a5c 790 drv_rect_t * gr_rect )
thedo 166:3a9487d57a5c 791 {
thedo 166:3a9487d57a5c 792 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
thedo 166:3a9487d57a5c 793 vdc5_channel_t ch = VDC5_CHANNEL_0;
thedo 166:3a9487d57a5c 794 vdc5_error_t error;
thedo 166:3a9487d57a5c 795 vdc5_layer_id_t vdc5_layer_id;
thedo 166:3a9487d57a5c 796 vdc5_gr_format_t vdc5_gr_format;
thedo 166:3a9487d57a5c 797 vdc5_read_t read;
thedo 166:3a9487d57a5c 798
thedo 166:3a9487d57a5c 799 switch(layer_id) {
thedo 166:3a9487d57a5c 800 case DRV_GRAPHICS_LAYER_0:
thedo 166:3a9487d57a5c 801 vdc5_layer_id = VDC5_LAYER_ID_0_RD;
thedo 166:3a9487d57a5c 802 break;
thedo 166:3a9487d57a5c 803 case DRV_GRAPHICS_LAYER_1:
thedo 166:3a9487d57a5c 804 vdc5_layer_id = VDC5_LAYER_ID_1_RD;
thedo 166:3a9487d57a5c 805 break;
thedo 166:3a9487d57a5c 806 case DRV_GRAPHICS_LAYER_2:
thedo 166:3a9487d57a5c 807 vdc5_layer_id = VDC5_LAYER_ID_2_RD;
thedo 166:3a9487d57a5c 808 break;
thedo 166:3a9487d57a5c 809 case DRV_GRAPHICS_LAYER_3:
thedo 166:3a9487d57a5c 810 vdc5_layer_id = VDC5_LAYER_ID_3_RD;
thedo 166:3a9487d57a5c 811 break;
thedo 166:3a9487d57a5c 812 default:
thedo 166:3a9487d57a5c 813 drv_error = DRV_GRAPHICS_LAYER_ERR;
thedo 166:3a9487d57a5c 814 break;
thedo 166:3a9487d57a5c 815 }
thedo 166:3a9487d57a5c 816
thedo 166:3a9487d57a5c 817 if( drv_error == DRV_GRAPHICS_OK ) {
thedo 166:3a9487d57a5c 818 switch( gr_format ) {
thedo 166:3a9487d57a5c 819 case DRV_GRAPHICS_FORMAT_YCBCR422:
thedo 166:3a9487d57a5c 820 vdc5_gr_format = VDC5_GR_FORMAT_YCBCR422;
thedo 166:3a9487d57a5c 821 break;
thedo 166:3a9487d57a5c 822 case DRV_GRAPHICS_FORMAT_RGB565:
thedo 166:3a9487d57a5c 823 vdc5_gr_format = VDC5_GR_FORMAT_RGB565;
thedo 166:3a9487d57a5c 824 break;
thedo 166:3a9487d57a5c 825 case DRV_GRAPHICS_FORMAT_RGB888:
thedo 166:3a9487d57a5c 826 vdc5_gr_format = VDC5_GR_FORMAT_RGB888;
thedo 166:3a9487d57a5c 827 break;
thedo 166:3a9487d57a5c 828 case DRV_GRAPHICS_FORMAT_ARGB8888:
thedo 166:3a9487d57a5c 829 vdc5_gr_format = VDC5_GR_FORMAT_ARGB8888;
thedo 166:3a9487d57a5c 830 break;
thedo 166:3a9487d57a5c 831 case DRV_GRAPHICS_FORMAT_ARGB4444:
thedo 166:3a9487d57a5c 832 vdc5_gr_format = VDC5_GR_FORMAT_ARGB4444;
thedo 166:3a9487d57a5c 833 break;
thedo 166:3a9487d57a5c 834 default:
thedo 166:3a9487d57a5c 835 drv_error = DRV_GRAPHICS_FORMAT_ERR;
thedo 166:3a9487d57a5c 836 break;
thedo 166:3a9487d57a5c 837 }
thedo 166:3a9487d57a5c 838 }
thedo 166:3a9487d57a5c 839
thedo 166:3a9487d57a5c 840 if( drv_error == DRV_GRAPHICS_OK ) {
thedo 166:3a9487d57a5c 841 /* Read data parameter */
thedo 166:3a9487d57a5c 842 read.gr_ln_off_dir = VDC5_GR_LN_OFF_DIR_INC; /* Line offset address direction of the frame buffer */
thedo 166:3a9487d57a5c 843 read.gr_flm_sel = VDC5_GR_FLM_SEL_FLM_NUM; /* Selects a frame buffer address setting signal */
thedo 166:3a9487d57a5c 844 read.gr_imr_flm_inv = VDC5_OFF; /* Frame buffer number for distortion correction */
thedo 166:3a9487d57a5c 845 read.gr_bst_md = VDC5_BST_MD_32BYTE; /* Frame buffer burst transfer mode */
thedo 166:3a9487d57a5c 846 read.gr_base = framebuff; /* Frame buffer base address */
thedo 166:3a9487d57a5c 847 read.gr_ln_off = fb_stride; /* Frame buffer line offset address */
thedo 166:3a9487d57a5c 848
thedo 166:3a9487d57a5c 849 read.width_read_fb = NULL; /* Width of the image read from frame buffer */
thedo 166:3a9487d57a5c 850
thedo 166:3a9487d57a5c 851 read.adj_sel = VDC5_OFF; /* Measures to decrease the influence
thedo 166:3a9487d57a5c 852 by folding pixels/lines (on/off) */
thedo 166:3a9487d57a5c 853 read.gr_format = vdc5_gr_format; /* Format of the frame buffer read signal */
thedo 166:3a9487d57a5c 854 read.gr_ycc_swap = VDC5_GR_YCCSWAP_CBY0CRY1; /* Controls swapping of data read from buffer
thedo 166:3a9487d57a5c 855 in the YCbCr422 format */
thedo 166:3a9487d57a5c 856 read.gr_rdswa = (vdc5_wr_rd_swa_t)wr_rd_swa; /* Frame buffer swap setting */
thedo 166:3a9487d57a5c 857 /* Display area */
thedo 166:3a9487d57a5c 858 read.gr_grc.vs = gr_rect->vs;
thedo 166:3a9487d57a5c 859 read.gr_grc.vw = gr_rect->vw;
thedo 166:3a9487d57a5c 860 read.gr_grc.hs = gr_rect->hs;
thedo 166:3a9487d57a5c 861 read.gr_grc.hw = gr_rect->hw;
thedo 166:3a9487d57a5c 862
thedo 166:3a9487d57a5c 863 /* Read data control */
thedo 166:3a9487d57a5c 864 error = R_VDC5_ReadDataControl( ch, vdc5_layer_id, &read );
thedo 166:3a9487d57a5c 865 if (error != VDC5_OK) {
thedo 166:3a9487d57a5c 866 drv_error = DRV_GRAPHICS_VDC5_ERR;
thedo 166:3a9487d57a5c 867 }
thedo 166:3a9487d57a5c 868 }
thedo 166:3a9487d57a5c 869 return drv_error;
thedo 166:3a9487d57a5c 870 } /* End of function DRV_Graphics_Read_Setting() */
thedo 166:3a9487d57a5c 871
thedo 166:3a9487d57a5c 872 /**************************************************************************//**
thedo 166:3a9487d57a5c 873 * @brief Graphics surface read buffer change process
thedo 166:3a9487d57a5c 874 * @param[in] layer_id : Graphics layer ID
thedo 166:3a9487d57a5c 875 * @param[in] framebuff : Base address of the frame buffer
thedo 166:3a9487d57a5c 876 * @retval Error code
thedo 166:3a9487d57a5c 877 ******************************************************************************/
thedo 166:3a9487d57a5c 878 drv_graphics_error_t DRV_Graphics_Read_Change (
thedo 166:3a9487d57a5c 879 drv_graphics_layer_t layer_id,
thedo 166:3a9487d57a5c 880 void * framebuff)
thedo 166:3a9487d57a5c 881 {
thedo 166:3a9487d57a5c 882 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
thedo 166:3a9487d57a5c 883 vdc5_channel_t ch = VDC5_CHANNEL_0;
thedo 166:3a9487d57a5c 884 vdc5_error_t error;
thedo 166:3a9487d57a5c 885 vdc5_layer_id_t vdc5_layer_id;
thedo 166:3a9487d57a5c 886 vdc5_read_chg_t read_chg;
thedo 166:3a9487d57a5c 887
thedo 166:3a9487d57a5c 888 switch(layer_id) {
thedo 166:3a9487d57a5c 889 case DRV_GRAPHICS_LAYER_0:
thedo 166:3a9487d57a5c 890 vdc5_layer_id = VDC5_LAYER_ID_0_RD;
thedo 166:3a9487d57a5c 891 break;
thedo 166:3a9487d57a5c 892 case DRV_GRAPHICS_LAYER_1:
thedo 166:3a9487d57a5c 893 vdc5_layer_id = VDC5_LAYER_ID_1_RD;
thedo 166:3a9487d57a5c 894 break;
thedo 166:3a9487d57a5c 895 case DRV_GRAPHICS_LAYER_2:
thedo 166:3a9487d57a5c 896 vdc5_layer_id = VDC5_LAYER_ID_2_RD;
thedo 166:3a9487d57a5c 897 break;
thedo 166:3a9487d57a5c 898 case DRV_GRAPHICS_LAYER_3:
thedo 166:3a9487d57a5c 899 vdc5_layer_id = VDC5_LAYER_ID_3_RD;
thedo 166:3a9487d57a5c 900 break;
thedo 166:3a9487d57a5c 901 default:
thedo 166:3a9487d57a5c 902 drv_error = DRV_GRAPHICS_LAYER_ERR;
thedo 166:3a9487d57a5c 903 break;
thedo 166:3a9487d57a5c 904 }
thedo 166:3a9487d57a5c 905
thedo 166:3a9487d57a5c 906 if( drv_error == DRV_GRAPHICS_OK ) {
thedo 166:3a9487d57a5c 907 /* Read data parameter */
thedo 166:3a9487d57a5c 908 read_chg.width_read_fb = NULL; /* Width of the image read from frame buffer */
thedo 166:3a9487d57a5c 909 read_chg.gr_grc = NULL; /* Display area */
thedo 166:3a9487d57a5c 910 read_chg.gr_disp_sel = NULL; /* Graphics display mode */
thedo 166:3a9487d57a5c 911 read_chg.gr_base = framebuff; /* Frame buffer base address */
thedo 166:3a9487d57a5c 912
thedo 166:3a9487d57a5c 913 /* Change read process */
thedo 166:3a9487d57a5c 914 error = R_VDC5_ChangeReadProcess( ch, vdc5_layer_id, &read_chg );
thedo 166:3a9487d57a5c 915 if (error != VDC5_OK) {
thedo 166:3a9487d57a5c 916 drv_error = DRV_GRAPHICS_VDC5_ERR;
thedo 166:3a9487d57a5c 917 }
thedo 166:3a9487d57a5c 918 }
thedo 166:3a9487d57a5c 919 return drv_error;
thedo 166:3a9487d57a5c 920 } /* End of function DRV_Graphics_Read_Change() */
thedo 166:3a9487d57a5c 921
thedo 166:3a9487d57a5c 922 /**************************************************************************//**
thedo 166:3a9487d57a5c 923 * @brief Video surface write process setting
thedo 166:3a9487d57a5c 924 *
thedo 166:3a9487d57a5c 925 * Description:<br>
thedo 166:3a9487d57a5c 926 * This function set the video write process. Input form is weave
thedo 166:3a9487d57a5c 927 * (progressive) mode fixed.
thedo 166:3a9487d57a5c 928 * This function supports the following 3 image format.
thedo 166:3a9487d57a5c 929 * YCbCr422, RGB565, RGB888
thedo 166:3a9487d57a5c 930 * @param[in] video_input_ch : Video input channel
thedo 166:3a9487d57a5c 931 * @param[in] col_sys : Analog video signal color system
thedo 166:3a9487d57a5c 932 * @param[in] adc_vinsel : Video input pin
thedo 166:3a9487d57a5c 933 * @param[in] framebuff : Base address of the frame buffer
thedo 166:3a9487d57a5c 934 * @param[in] fb_stride [byte] : Line offset address of the frame buffer
thedo 166:3a9487d57a5c 935 * @param[in] video_format : Frame buffer video-signal writing format
thedo 166:3a9487d57a5c 936 * @param[in] wr_rd_swa : Frame buffer swap setting
thedo 166:3a9487d57a5c 937 * @param[in] video_write_size_vw [px]: output height
thedo 166:3a9487d57a5c 938 * @param[in] video_write_size_hw [px]: output width
thedo 166:3a9487d57a5c 939 * @param[in] video_adc_vinsel : Input pin control
thedo 166:3a9487d57a5c 940 * @retval Error code
thedo 166:3a9487d57a5c 941 ******************************************************************************/
thedo 166:3a9487d57a5c 942 drv_graphics_error_t DRV_Video_Write_Setting (
thedo 166:3a9487d57a5c 943 drv_video_input_channel_t video_input_ch,
thedo 166:3a9487d57a5c 944 drv_graphics_video_col_sys_t col_sys,
thedo 166:3a9487d57a5c 945 void * framebuff,
thedo 166:3a9487d57a5c 946 uint32_t fb_stride,
thedo 166:3a9487d57a5c 947 drv_video_format_t video_format,
thedo 166:3a9487d57a5c 948 drv_wr_rd_swa_t wr_rd_swa,
thedo 166:3a9487d57a5c 949 uint16_t video_write_buff_vw,
thedo 166:3a9487d57a5c 950 uint16_t video_write_buff_hw,
thedo 166:3a9487d57a5c 951 drv_video_adc_vinsel_t video_adc_vinsel )
thedo 166:3a9487d57a5c 952 {
thedo 166:3a9487d57a5c 953 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
thedo 166:3a9487d57a5c 954 vdc5_channel_t ch = VDC5_CHANNEL_0;
thedo 166:3a9487d57a5c 955 vdc5_error_t error;
thedo 166:3a9487d57a5c 956 vdc5_layer_id_t vdc5_layer_id;
thedo 166:3a9487d57a5c 957 vdc5_write_t write;
thedo 166:3a9487d57a5c 958 vdc5_scalingdown_rot_t * scldw_rot;
thedo 166:3a9487d57a5c 959 vdc5_res_md_t res_md;
thedo 166:3a9487d57a5c 960 drv_rect_t video_in_rect;
thedo 166:3a9487d57a5c 961 uint8_t * framebuffer_t;
thedo 166:3a9487d57a5c 962 uint8_t * framebuffer_b;
thedo 166:3a9487d57a5c 963
thedo 166:3a9487d57a5c 964 if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) {
thedo 166:3a9487d57a5c 965 GRAPHICS_VideoDecoderInit( (vdec_adc_vinsel_t)video_adc_vinsel, VDEC_CHANNEL_0, (graphics_col_sys_t)col_sys );
thedo 166:3a9487d57a5c 966 } else if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1 ) {
thedo 166:3a9487d57a5c 967 GRAPHICS_VideoDecoderInit( (vdec_adc_vinsel_t)video_adc_vinsel, VDEC_CHANNEL_1, (graphics_col_sys_t)col_sys );
thedo 166:3a9487d57a5c 968 } else {
thedo 166:3a9487d57a5c 969 drv_error = DRV_GRAPHICS_CHANNEL_ERR;
thedo 166:3a9487d57a5c 970 }
thedo 166:3a9487d57a5c 971
thedo 166:3a9487d57a5c 972 if( drv_error == DRV_GRAPHICS_OK ) {
thedo 166:3a9487d57a5c 973 if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) {
thedo 166:3a9487d57a5c 974 vdc5_layer_id = VDC5_LAYER_ID_0_WR;
thedo 166:3a9487d57a5c 975 } else if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1 ) {
thedo 166:3a9487d57a5c 976 vdc5_layer_id = VDC5_LAYER_ID_1_WR;
thedo 166:3a9487d57a5c 977 } else {
thedo 166:3a9487d57a5c 978 drv_error = DRV_GRAPHICS_CHANNEL_ERR;
thedo 166:3a9487d57a5c 979 }
thedo 166:3a9487d57a5c 980 }
thedo 166:3a9487d57a5c 981
thedo 166:3a9487d57a5c 982 if( drv_error == DRV_GRAPHICS_OK ) {
thedo 166:3a9487d57a5c 983 if( video_format == DRV_VIDEO_FORMAT_YCBCR422 ) {
thedo 166:3a9487d57a5c 984 res_md = VDC5_RES_MD_YCBCR422;
thedo 166:3a9487d57a5c 985 } else if( video_format == DRV_VIDEO_FORMAT_RGB888 ) {
thedo 166:3a9487d57a5c 986 res_md = VDC5_RES_MD_RGB888;
thedo 166:3a9487d57a5c 987 } else if( video_format == DRV_VIDEO_FORMAT_RGB565 ) {
thedo 166:3a9487d57a5c 988 res_md = VDC5_RES_MD_RGB565;
thedo 166:3a9487d57a5c 989 } else {
thedo 166:3a9487d57a5c 990 drv_error = DRV_GRAPHICS_FORMAT_ERR;
thedo 166:3a9487d57a5c 991 }
thedo 166:3a9487d57a5c 992 }
thedo 166:3a9487d57a5c 993
thedo 166:3a9487d57a5c 994 if( col_sys == DRV_COL_SYS_NTSC_358 || col_sys == DVV_COL_SYS_NTSC_443 || col_sys == DRV_COL_SYS_NTSC_443_60 ) {
thedo 166:3a9487d57a5c 995 video_in_rect.hs = IMGCAP_SIZE_NTSC_HS * 2;
thedo 166:3a9487d57a5c 996 video_in_rect.hw = IMGCAP_SIZE_NTSC_HW * 2;
thedo 166:3a9487d57a5c 997 video_in_rect.vs = IMGCAP_SIZE_NTSC_VS;
thedo 166:3a9487d57a5c 998 video_in_rect.vw = IMGCAP_SIZE_NTSC_VW;
thedo 166:3a9487d57a5c 999 } else {
thedo 166:3a9487d57a5c 1000 video_in_rect.hs = IMGCAP_SIZE_PAL_HS * 2;
thedo 166:3a9487d57a5c 1001 video_in_rect.hw = IMGCAP_SIZE_PAL_HW * 2;
thedo 166:3a9487d57a5c 1002 video_in_rect.vs = IMGCAP_SIZE_PAL_VS;
thedo 166:3a9487d57a5c 1003 video_in_rect.vw = IMGCAP_SIZE_PAL_VW;
thedo 166:3a9487d57a5c 1004 }
thedo 166:3a9487d57a5c 1005
thedo 166:3a9487d57a5c 1006 if( drv_error == DRV_GRAPHICS_OK ) {
thedo 166:3a9487d57a5c 1007 if( col_sys == DRV_COL_SYS_NTSC_358 || col_sys == DVV_COL_SYS_NTSC_443 || col_sys == DRV_COL_SYS_NTSC_443_60 ) {
thedo 166:3a9487d57a5c 1008 if( (video_write_buff_vw / 2u) > video_in_rect.vw ) {
thedo 166:3a9487d57a5c 1009 drv_error = DRV_GRAPHICS_VIDEO_NTSC_SIZE_ERR;
thedo 166:3a9487d57a5c 1010 }
thedo 166:3a9487d57a5c 1011 } else {
thedo 166:3a9487d57a5c 1012 if( (video_write_buff_vw / 2u) > video_in_rect.vw ) {
thedo 166:3a9487d57a5c 1013 drv_error = DRV_GRAPHICS_VIDEO_PAL_SIZE_ERR;
thedo 166:3a9487d57a5c 1014 }
thedo 166:3a9487d57a5c 1015 }
thedo 166:3a9487d57a5c 1016 }
thedo 166:3a9487d57a5c 1017
thedo 166:3a9487d57a5c 1018 if( drv_error == DRV_GRAPHICS_OK ) {
thedo 166:3a9487d57a5c 1019 if( video_write_buff_hw > 800 ) {
thedo 166:3a9487d57a5c 1020 drv_error = DRV_GRAPHICS_PARAM_RANGE_ERR;
thedo 166:3a9487d57a5c 1021 }
thedo 166:3a9487d57a5c 1022 }
thedo 166:3a9487d57a5c 1023
thedo 166:3a9487d57a5c 1024 if( drv_error == DRV_GRAPHICS_OK ) {
thedo 166:3a9487d57a5c 1025 /* Scaling-down and rotation parameter */
thedo 166:3a9487d57a5c 1026 scldw_rot = &write.scalingdown_rot;
thedo 166:3a9487d57a5c 1027 /* Image area to be captured */
thedo 166:3a9487d57a5c 1028 scldw_rot->res.vs = (uint16_t)((uint32_t)video_in_rect.vs - 1u);
thedo 166:3a9487d57a5c 1029 scldw_rot->res.vw = video_in_rect.vw;
thedo 166:3a9487d57a5c 1030 scldw_rot->res.hs = video_in_rect.hs;
thedo 166:3a9487d57a5c 1031 scldw_rot->res.hw = video_in_rect.hw;
thedo 166:3a9487d57a5c 1032
thedo 166:3a9487d57a5c 1033 /* Write data parameter */
thedo 166:3a9487d57a5c 1034 framebuffer_t = framebuff;
thedo 166:3a9487d57a5c 1035 framebuffer_b = &framebuffer_t[fb_stride];
thedo 166:3a9487d57a5c 1036 scldw_rot->res_pfil_sel = VDC5_ON; /* Prefilter mode select for brightness signals (on/off) */
thedo 166:3a9487d57a5c 1037 scldw_rot->res_out_vw = video_write_buff_vw / 2u; /* Number of valid lines in vertical direction
thedo 166:3a9487d57a5c 1038 output by scaling-down control block */
thedo 166:3a9487d57a5c 1039 scldw_rot->res_out_hw = video_write_buff_hw; /* Number of valid horizontal pixels
thedo 166:3a9487d57a5c 1040 output by scaling-down control block */
thedo 166:3a9487d57a5c 1041 scldw_rot->adj_sel = VDC5_ON; /* Measures to decrease the influence
thedo 166:3a9487d57a5c 1042 by lack of last-input line (on/off) */
thedo 166:3a9487d57a5c 1043 scldw_rot->res_ds_wr_md = VDC5_WR_MD_NORMAL; /* Frame buffer writing mode */
thedo 166:3a9487d57a5c 1044 write.res_wrswa = (vdc5_wr_rd_swa_t)wr_rd_swa; /* Frame buffer swap setting */
thedo 166:3a9487d57a5c 1045 write.res_md = res_md; /* Frame buffer video-signal writing format */
thedo 166:3a9487d57a5c 1046 write.res_bst_md = VDC5_BST_MD_32BYTE; /* Transfer burst length for frame buffer */
thedo 166:3a9487d57a5c 1047 write.res_inter = VDC5_RES_INTER_PROGRESSIVE; /* Field operating mode select */
thedo 166:3a9487d57a5c 1048 write.res_fs_rate = VDC5_RES_FS_RATE_PER1; /* Writing rate */
thedo 166:3a9487d57a5c 1049 write.res_fld_sel = VDC5_RES_FLD_SEL_TOP; /* Write field select */
thedo 166:3a9487d57a5c 1050 write.res_dth_on = VDC5_ON; /* Dither correction on/off */
thedo 166:3a9487d57a5c 1051 write.base = framebuff; /* Frame buffer base address */
thedo 166:3a9487d57a5c 1052 write.ln_off = fb_stride * 2u; /* Frame buffer line offset address [byte] */
thedo 166:3a9487d57a5c 1053 write.flm_num = (uint32_t)(1u - 1u); /* Number of frames of buffer (res_flm_num + 1) */
thedo 166:3a9487d57a5c 1054 /* Frame buffer frame offset address */
thedo 166:3a9487d57a5c 1055 write.flm_off = fb_stride * 2u * (uint32_t)scldw_rot->res_out_vw;
thedo 166:3a9487d57a5c 1056 write.btm_base = framebuffer_b; /* Frame buffer base address for bottom */
thedo 166:3a9487d57a5c 1057
thedo 166:3a9487d57a5c 1058 /* Write data control */
thedo 166:3a9487d57a5c 1059 error = R_VDC5_WriteDataControl( ch, vdc5_layer_id, &write );
thedo 166:3a9487d57a5c 1060 if (error != VDC5_OK) {
thedo 166:3a9487d57a5c 1061 drv_error = DRV_GRAPHICS_VDC5_ERR;
thedo 166:3a9487d57a5c 1062 }
thedo 166:3a9487d57a5c 1063 }
thedo 166:3a9487d57a5c 1064 return drv_error;
thedo 166:3a9487d57a5c 1065 } /* End of function DRV_Video_Write_Setting() */
thedo 166:3a9487d57a5c 1066
thedo 166:3a9487d57a5c 1067 /**************************************************************************//**
thedo 166:3a9487d57a5c 1068 * @brief Video surface write process setting for digital input
thedo 166:3a9487d57a5c 1069 *
thedo 166:3a9487d57a5c 1070 * Description:<br>
thedo 166:3a9487d57a5c 1071 * This function set the video write process for digital input.
thedo 166:3a9487d57a5c 1072 * This function supports the following 3 image format.
thedo 166:3a9487d57a5c 1073 * YCbCr422, RGB565, RGB888
thedo 166:3a9487d57a5c 1074 * @param[in] framebuff : Base address of the frame buffer
thedo 166:3a9487d57a5c 1075 * @param[in] fb_stride [byte] : Line offset address of the frame buffer
thedo 166:3a9487d57a5c 1076 * @param[in] video_format : Frame buffer video-signal writing format
thedo 166:3a9487d57a5c 1077 * @param[in] wr_rd_swa : Frame buffer swap setting
thedo 166:3a9487d57a5c 1078 * @param[in] video_write_size_vw [px]: output height
thedo 166:3a9487d57a5c 1079 * @param[in] video_write_size_hw [px]: output width
thedo 166:3a9487d57a5c 1080 * @param[in] cap_area : Capture area
thedo 166:3a9487d57a5c 1081 * @retval Error code
thedo 166:3a9487d57a5c 1082 ******************************************************************************/
thedo 166:3a9487d57a5c 1083 drv_graphics_error_t DRV_Video_Write_Setting_Digital (
thedo 166:3a9487d57a5c 1084 void * framebuff,
thedo 166:3a9487d57a5c 1085 uint32_t fb_stride,
thedo 166:3a9487d57a5c 1086 drv_video_format_t video_format,
thedo 166:3a9487d57a5c 1087 drv_wr_rd_swa_t wr_rd_swa,
thedo 166:3a9487d57a5c 1088 uint16_t video_write_buff_vw,
thedo 166:3a9487d57a5c 1089 uint16_t video_write_buff_hw,
thedo 166:3a9487d57a5c 1090 drv_rect_t * cap_area )
thedo 166:3a9487d57a5c 1091 {
thedo 166:3a9487d57a5c 1092 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
thedo 166:3a9487d57a5c 1093 vdc5_channel_t ch = VDC5_CHANNEL_0;
thedo 166:3a9487d57a5c 1094 vdc5_error_t error;
thedo 166:3a9487d57a5c 1095 vdc5_layer_id_t vdc5_layer_id;
thedo 166:3a9487d57a5c 1096 vdc5_write_t write;
thedo 166:3a9487d57a5c 1097 vdc5_scalingdown_rot_t * scldw_rot;
thedo 166:3a9487d57a5c 1098 vdc5_res_md_t res_md;
thedo 166:3a9487d57a5c 1099
thedo 166:3a9487d57a5c 1100 vdc5_layer_id = VDC5_LAYER_ID_0_WR;
thedo 166:3a9487d57a5c 1101
thedo 166:3a9487d57a5c 1102 if( drv_error == DRV_GRAPHICS_OK ) {
thedo 166:3a9487d57a5c 1103 if( video_format == DRV_VIDEO_FORMAT_YCBCR422 ) {
thedo 166:3a9487d57a5c 1104 res_md = VDC5_RES_MD_YCBCR422;
thedo 166:3a9487d57a5c 1105 } else if( video_format == DRV_VIDEO_FORMAT_RGB888 ) {
thedo 166:3a9487d57a5c 1106 res_md = VDC5_RES_MD_RGB888;
thedo 166:3a9487d57a5c 1107 } else if( video_format == DRV_VIDEO_FORMAT_RGB565 ) {
thedo 166:3a9487d57a5c 1108 res_md = VDC5_RES_MD_RGB565;
thedo 166:3a9487d57a5c 1109 } else {
thedo 166:3a9487d57a5c 1110 drv_error = DRV_GRAPHICS_FORMAT_ERR;
thedo 166:3a9487d57a5c 1111 }
thedo 166:3a9487d57a5c 1112 }
thedo 166:3a9487d57a5c 1113
thedo 166:3a9487d57a5c 1114 if( drv_error == DRV_GRAPHICS_OK ) {
thedo 166:3a9487d57a5c 1115 /* Scaling-down and rotation parameter */
thedo 166:3a9487d57a5c 1116 scldw_rot = &write.scalingdown_rot;
thedo 166:3a9487d57a5c 1117 /* Image area to be captured */
thedo 166:3a9487d57a5c 1118 scldw_rot->res.vs = (uint16_t)((uint32_t)cap_area->vs - 1u);
thedo 166:3a9487d57a5c 1119 scldw_rot->res.vw = cap_area->vw;
thedo 166:3a9487d57a5c 1120 scldw_rot->res.hs = cap_area->hs;
thedo 166:3a9487d57a5c 1121 scldw_rot->res.hw = cap_area->hw;
thedo 166:3a9487d57a5c 1122
thedo 166:3a9487d57a5c 1123 /* Write data parameter */
thedo 166:3a9487d57a5c 1124 scldw_rot->res_pfil_sel = VDC5_ON; /* Prefilter mode select for brightness signals (on/off) */
thedo 166:3a9487d57a5c 1125 scldw_rot->res_out_vw = video_write_buff_vw ; /* Number of valid lines in vertical direction
thedo 166:3a9487d57a5c 1126 output by scaling-down control block */
thedo 166:3a9487d57a5c 1127 scldw_rot->res_out_hw = video_write_buff_hw; /* Number of valid horizontal pixels
thedo 166:3a9487d57a5c 1128 output by scaling-down control block */
thedo 166:3a9487d57a5c 1129 scldw_rot->adj_sel = VDC5_ON; /* Measures to decrease the influence
thedo 166:3a9487d57a5c 1130 by lack of last-input line (on/off) */
thedo 166:3a9487d57a5c 1131 scldw_rot->res_ds_wr_md = VDC5_WR_MD_NORMAL; /* Frame buffer writing mode */
thedo 166:3a9487d57a5c 1132 write.res_wrswa = (vdc5_wr_rd_swa_t)wr_rd_swa; /* Frame buffer swap setting */
thedo 166:3a9487d57a5c 1133 write.res_md = res_md; /* Frame buffer video-signal writing format */
thedo 166:3a9487d57a5c 1134 write.res_bst_md = VDC5_BST_MD_32BYTE; /* Transfer burst length for frame buffer */
thedo 166:3a9487d57a5c 1135 write.res_inter = VDC5_RES_INTER_PROGRESSIVE; /* Field operating mode select */
thedo 166:3a9487d57a5c 1136 write.res_fs_rate = VDC5_RES_FS_RATE_PER1; /* Writing rate */
thedo 166:3a9487d57a5c 1137 write.res_fld_sel = VDC5_RES_FLD_SEL_TOP; /* Write field select */
thedo 166:3a9487d57a5c 1138 write.res_dth_on = VDC5_ON; /* Dither correction on/off */
thedo 166:3a9487d57a5c 1139 write.base = framebuff; /* Frame buffer base address */
thedo 166:3a9487d57a5c 1140 write.ln_off = fb_stride;
thedo 166:3a9487d57a5c 1141 /* Frame buffer line offset address [byte] */
thedo 166:3a9487d57a5c 1142 write.flm_num = (uint32_t)(1u - 1u); /* Number of frames of buffer (res_flm_num + 1) */
thedo 166:3a9487d57a5c 1143 /* Frame buffer frame offset address */
thedo 166:3a9487d57a5c 1144 write.flm_off = fb_stride * (uint32_t)scldw_rot->res_out_vw;
thedo 166:3a9487d57a5c 1145 write.btm_base = NULL; /* Frame buffer base address for bottom */
thedo 166:3a9487d57a5c 1146
thedo 166:3a9487d57a5c 1147 /* Write data control */
thedo 166:3a9487d57a5c 1148 error = R_VDC5_WriteDataControl( ch, vdc5_layer_id, &write );
thedo 166:3a9487d57a5c 1149 if (error != VDC5_OK) {
thedo 166:3a9487d57a5c 1150 drv_error = DRV_GRAPHICS_VDC5_ERR;
thedo 166:3a9487d57a5c 1151 }
thedo 166:3a9487d57a5c 1152 }
thedo 166:3a9487d57a5c 1153 return drv_error;
thedo 166:3a9487d57a5c 1154 } /* End of function DRV_Video_Write_Setting_Digital() */
thedo 166:3a9487d57a5c 1155
thedo 166:3a9487d57a5c 1156 /**************************************************************************//**
thedo 166:3a9487d57a5c 1157 * @brief Video surface write buffer change process
thedo 166:3a9487d57a5c 1158 * @param[in] video_input_ch : Video input channle
thedo 166:3a9487d57a5c 1159 * @param[in] framebuff : Base address of the frame buffer
thedo 166:3a9487d57a5c 1160 * @param[in] fb_stride : Line offset address of the frame buffer
thedo 166:3a9487d57a5c 1161 * @retval Error code
thedo 166:3a9487d57a5c 1162 ******************************************************************************/
thedo 166:3a9487d57a5c 1163 drv_graphics_error_t DRV_Video_Write_Change (
thedo 166:3a9487d57a5c 1164 drv_video_input_channel_t video_input_ch,
thedo 166:3a9487d57a5c 1165 void * framebuff,
thedo 166:3a9487d57a5c 1166 uint32_t fb_stride )
thedo 166:3a9487d57a5c 1167 {
thedo 166:3a9487d57a5c 1168 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
thedo 166:3a9487d57a5c 1169 uint8_t * framebuffer_t;
thedo 166:3a9487d57a5c 1170 uint8_t * framebuffer_b;
thedo 166:3a9487d57a5c 1171
thedo 166:3a9487d57a5c 1172 framebuffer_t = (uint8_t *)((uint32_t)framebuff & ~0x1F);
thedo 166:3a9487d57a5c 1173 framebuffer_b = &framebuffer_t[fb_stride];
thedo 166:3a9487d57a5c 1174
thedo 166:3a9487d57a5c 1175 if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) {
thedo 166:3a9487d57a5c 1176 VDC50.SC0_SCL1_WR2 = (uint32_t)framebuffer_t;
thedo 166:3a9487d57a5c 1177 VDC50.SC0_SCL1_WR8 = (uint32_t)framebuffer_b;
thedo 166:3a9487d57a5c 1178 VDC50.SC0_SCL1_UPDATE = 0x10;
thedo 166:3a9487d57a5c 1179 } else if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1 ) {
thedo 166:3a9487d57a5c 1180 VDC50.SC1_SCL1_WR2 = (uint32_t)framebuffer_t;
thedo 166:3a9487d57a5c 1181 VDC50.SC1_SCL1_WR8 = (uint32_t)framebuffer_b;
thedo 166:3a9487d57a5c 1182 VDC50.SC1_SCL1_UPDATE = 0x10;
thedo 166:3a9487d57a5c 1183 } else {
thedo 166:3a9487d57a5c 1184 drv_error = DRV_GRAPHICS_CHANNEL_ERR;
thedo 166:3a9487d57a5c 1185 }
thedo 166:3a9487d57a5c 1186 return drv_error;
thedo 166:3a9487d57a5c 1187 } /* End of function DRV_Video_Write_Change() */
thedo 166:3a9487d57a5c 1188
thedo 166:3a9487d57a5c 1189 /* End of file */