the do / gr-peach-opencv-project

Opencv 3.1 project on GR-PEACH board

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GR-PEACH_video/inc/lcd_analog_rgb.h@166:3a9487d57a5c, 2017-06-29 (annotated)

Committer:
thedo
Date:
Thu Jun 29 11:00:41 2017 +0000
Revision:
166:3a9487d57a5c
This is Opencv 3.1 project on GR-PEACH board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
thedo 166:3a9487d57a5c 1 /*******************************************************************************
thedo 166:3a9487d57a5c 2 * DISCLAIMER
thedo 166:3a9487d57a5c 3 * This software is supplied by Renesas Electronics Corporation and is only
thedo 166:3a9487d57a5c 4 * intended for use with Renesas products. No other uses are authorized. This
thedo 166:3a9487d57a5c 5 * software is owned by Renesas Electronics Corporation and is protected under
thedo 166:3a9487d57a5c 6 * all applicable laws, including copyright laws.
thedo 166:3a9487d57a5c 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
thedo 166:3a9487d57a5c 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
thedo 166:3a9487d57a5c 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
thedo 166:3a9487d57a5c 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
thedo 166:3a9487d57a5c 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
thedo 166:3a9487d57a5c 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
thedo 166:3a9487d57a5c 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
thedo 166:3a9487d57a5c 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
thedo 166:3a9487d57a5c 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
thedo 166:3a9487d57a5c 16 * Renesas reserves the right, without notice, to make changes to this software
thedo 166:3a9487d57a5c 17 * and to discontinue the availability of this software. By using this software,
thedo 166:3a9487d57a5c 18 * you agree to the additional terms and conditions found by accessing the
thedo 166:3a9487d57a5c 19 * following link:
thedo 166:3a9487d57a5c 20 * http://www.renesas.com/disclaimer
thedo 166:3a9487d57a5c 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
thedo 166:3a9487d57a5c 22 *******************************************************************************/
thedo 166:3a9487d57a5c 23 /**************************************************************************//**
thedo 166:3a9487d57a5c 24 * @file lcd_analog_rgb.h
thedo 166:3a9487d57a5c 25 * @version 1.00
thedo 166:3a9487d57a5c 26 * $Rev: 199 $
thedo 166:3a9487d57a5c 27 * $Date:: 2014-05-23 16:33:52 +0900#$
thedo 166:3a9487d57a5c 28 * @brief LCD panel definition header
thedo 166:3a9487d57a5c 29 ******************************************************************************/
thedo 166:3a9487d57a5c 30
thedo 166:3a9487d57a5c 31 #ifndef LCD_ANALOG_RGB_H
thedo 166:3a9487d57a5c 32 #define LCD_ANALOG_RGB_H
thedo 166:3a9487d57a5c 33
thedo 166:3a9487d57a5c 34 /******************************************************************************
thedo 166:3a9487d57a5c 35 Includes <System Includes> , "Project Includes"
thedo 166:3a9487d57a5c 36 ******************************************************************************/
thedo 166:3a9487d57a5c 37 #include <stdlib.h>
thedo 166:3a9487d57a5c 38
thedo 166:3a9487d57a5c 39 #include "r_typedefs.h"
thedo 166:3a9487d57a5c 40
thedo 166:3a9487d57a5c 41 #include "r_vdc5.h"
thedo 166:3a9487d57a5c 42
thedo 166:3a9487d57a5c 43
thedo 166:3a9487d57a5c 44 /******************************************************************************
thedo 166:3a9487d57a5c 45 Macro definitions
thedo 166:3a9487d57a5c 46 ******************************************************************************/
thedo 166:3a9487d57a5c 47 /* SVGA signal 800x600
thedo 166:3a9487d57a5c 48 Pixel clock frequency: 40.0 MHz
thedo 166:3a9487d57a5c 49 Refresh rate: 60.3 Hz
thedo 166:3a9487d57a5c 50 Polarity of horizontal sync pulse: Positive
thedo 166:3a9487d57a5c 51 Polarity of vertical sync pulse: Positive
thedo 166:3a9487d57a5c 52 */
thedo 166:3a9487d57a5c 53 #define LCD_SVGA_H_VISIBLE_AREA (800u) /* Horizontal visible area [pixel] */
thedo 166:3a9487d57a5c 54 #define LCD_SVGA_H_FRONT_PORCH (40u) /* Horizontal front porch [pixel] */
thedo 166:3a9487d57a5c 55 #define LCD_SVGA_H_SYNC_WIDTH (128u) /* Horizontal sync pulse width [pixel] */
thedo 166:3a9487d57a5c 56 #define LCD_SVGA_H_BACK_PORCH (88u) /* Horizontal back porch [pixel] */
thedo 166:3a9487d57a5c 57 /* Horizontal total (one line) [pixel] */
thedo 166:3a9487d57a5c 58 #define LCD_SVGA_H_TOTAL (LCD_SVGA_H_VISIBLE_AREA +\
thedo 166:3a9487d57a5c 59 LCD_SVGA_H_FRONT_PORCH +\
thedo 166:3a9487d57a5c 60 LCD_SVGA_H_SYNC_WIDTH +\
thedo 166:3a9487d57a5c 61 LCD_SVGA_H_BACK_PORCH)
thedo 166:3a9487d57a5c 62 #define LCD_SVGA_H_POLARITY (VDC5_SIG_POL_NOT_INVERTED) /* Polarity of horizontal sync pulse */
thedo 166:3a9487d57a5c 63
thedo 166:3a9487d57a5c 64 #define LCD_SVGA_V_VISIBLE_AREA (600u) /* Vertical visible area [line] */
thedo 166:3a9487d57a5c 65 #define LCD_SVGA_V_FRONT_PORCH (1u) /* Vertical front porch [line] */
thedo 166:3a9487d57a5c 66 #define LCD_SVGA_V_SYNC_WIDTH (4u) /* Vertical sync pulse width [line] */
thedo 166:3a9487d57a5c 67 #define LCD_SVGA_V_BACK_PORCH (23u) /* Vertical back porch [line] */
thedo 166:3a9487d57a5c 68 /* Vertical total (one frame) [line] */
thedo 166:3a9487d57a5c 69 #define LCD_SVGA_V_TOTAL (LCD_SVGA_V_VISIBLE_AREA +\
thedo 166:3a9487d57a5c 70 LCD_SVGA_V_FRONT_PORCH +\
thedo 166:3a9487d57a5c 71 LCD_SVGA_V_SYNC_WIDTH +\
thedo 166:3a9487d57a5c 72 LCD_SVGA_V_BACK_PORCH)
thedo 166:3a9487d57a5c 73 #define LCD_SVGA_V_POLARITY (VDC5_SIG_POL_NOT_INVERTED) /* Polarity of vertical sync pulse */
thedo 166:3a9487d57a5c 74
thedo 166:3a9487d57a5c 75
thedo 166:3a9487d57a5c 76 /* XGA signal 1024x768
thedo 166:3a9487d57a5c 77 Pixel clock frequency: 65.0 MHz
thedo 166:3a9487d57a5c 78 Refresh rate: 60.0 Hz
thedo 166:3a9487d57a5c 79 Polarity of horizontal sync pulse: Negative
thedo 166:3a9487d57a5c 80 Polarity of vertical sync pulse: Negative
thedo 166:3a9487d57a5c 81 */
thedo 166:3a9487d57a5c 82 #define LCD_XGA_H_VISIBLE_AREA (1024u) /* Horizontal visible area [pixel] */
thedo 166:3a9487d57a5c 83 #define LCD_XGA_H_FRONT_PORCH (24u) /* Horizontal front porch [pixel] */
thedo 166:3a9487d57a5c 84 #define LCD_XGA_H_SYNC_WIDTH (136u) /* Horizontal sync pulse width [pixel] */
thedo 166:3a9487d57a5c 85 #define LCD_XGA_H_BACK_PORCH (160u) /* Horizontal back porch [pixel] */
thedo 166:3a9487d57a5c 86 /* Horizontal total (one line) [pixel] */
thedo 166:3a9487d57a5c 87 #define LCD_XGA_H_TOTAL (LCD_XGA_H_VISIBLE_AREA +\
thedo 166:3a9487d57a5c 88 LCD_XGA_H_FRONT_PORCH +\
thedo 166:3a9487d57a5c 89 LCD_XGA_H_SYNC_WIDTH +\
thedo 166:3a9487d57a5c 90 LCD_XGA_H_BACK_PORCH)
thedo 166:3a9487d57a5c 91 #define LCD_XGA_H_POLARITY (VDC5_SIG_POL_INVERTED) /* Polarity of horizontal sync pulse */
thedo 166:3a9487d57a5c 92
thedo 166:3a9487d57a5c 93 #define LCD_XGA_V_VISIBLE_AREA (768u) /* Vertical visible area [line] */
thedo 166:3a9487d57a5c 94 #define LCD_XGA_V_FRONT_PORCH (3u) /* Vertical front porch [line] */
thedo 166:3a9487d57a5c 95 #define LCD_XGA_V_SYNC_WIDTH (6u) /* Vertical sync pulse width [line] */
thedo 166:3a9487d57a5c 96 #define LCD_XGA_V_BACK_PORCH (29u) /* Vertical back porch [line] */
thedo 166:3a9487d57a5c 97 /* Vertical total (one frame) [line] */
thedo 166:3a9487d57a5c 98 #define LCD_XGA_V_TOTAL (LCD_XGA_V_VISIBLE_AREA +\
thedo 166:3a9487d57a5c 99 LCD_XGA_V_FRONT_PORCH +\
thedo 166:3a9487d57a5c 100 LCD_XGA_V_SYNC_WIDTH +\
thedo 166:3a9487d57a5c 101 LCD_XGA_V_BACK_PORCH)
thedo 166:3a9487d57a5c 102 #define LCD_XGA_V_POLARITY (VDC5_SIG_POL_INVERTED) /* Polarity of vertical sync pulse */
thedo 166:3a9487d57a5c 103
thedo 166:3a9487d57a5c 104
thedo 166:3a9487d57a5c 105 /* VGA signal 640x480
thedo 166:3a9487d57a5c 106 Pixel clock frequency: 25.175 MHz
thedo 166:3a9487d57a5c 107 Refresh rate: 59.94 Hz
thedo 166:3a9487d57a5c 108 Polarity of horizontal sync pulse: Negative
thedo 166:3a9487d57a5c 109 Polarity of vertical sync pulse: Negative
thedo 166:3a9487d57a5c 110 */
thedo 166:3a9487d57a5c 111 #define LCD_VGA_H_VISIBLE_AREA (640u) /* Horizontal visible area [pixel] */
thedo 166:3a9487d57a5c 112 #define LCD_VGA_H_FRONT_PORCH (16u) /* Horizontal front porch [pixel] */
thedo 166:3a9487d57a5c 113 #define LCD_VGA_H_SYNC_WIDTH (96u) /* Horizontal sync pulse width [pixel] */
thedo 166:3a9487d57a5c 114 #define LCD_VGA_H_BACK_PORCH (48u) /* Horizontal back porch [pixel] */
thedo 166:3a9487d57a5c 115 /* Horizontal total (one line) [pixel] */
thedo 166:3a9487d57a5c 116 #define LCD_VGA_H_TOTAL (LCD_VGA_H_VISIBLE_AREA +\
thedo 166:3a9487d57a5c 117 LCD_VGA_H_FRONT_PORCH +\
thedo 166:3a9487d57a5c 118 LCD_VGA_H_SYNC_WIDTH +\
thedo 166:3a9487d57a5c 119 LCD_VGA_H_BACK_PORCH)
thedo 166:3a9487d57a5c 120 #define LCD_VGA_H_POLARITY (VDC5_SIG_POL_INVERTED) /* Polarity of horizontal sync pulse */
thedo 166:3a9487d57a5c 121
thedo 166:3a9487d57a5c 122 #define LCD_VGA_V_VISIBLE_AREA (480u) /* Vertical visible area [line] */
thedo 166:3a9487d57a5c 123 #define LCD_VGA_V_FRONT_PORCH (10u) /* Vertical front porch [line] */
thedo 166:3a9487d57a5c 124 #define LCD_VGA_V_SYNC_WIDTH (2u) /* Vertical sync pulse width [line] */
thedo 166:3a9487d57a5c 125 #define LCD_VGA_V_BACK_PORCH (33u) /* Vertical back porch [line] */
thedo 166:3a9487d57a5c 126 /* Vertical total (one frame) [line] */
thedo 166:3a9487d57a5c 127 #define LCD_VGA_V_TOTAL (LCD_VGA_V_VISIBLE_AREA +\
thedo 166:3a9487d57a5c 128 LCD_VGA_V_FRONT_PORCH +\
thedo 166:3a9487d57a5c 129 LCD_VGA_V_SYNC_WIDTH +\
thedo 166:3a9487d57a5c 130 LCD_VGA_V_BACK_PORCH)
thedo 166:3a9487d57a5c 131 #define LCD_VGA_V_POLARITY (VDC5_SIG_POL_INVERTED) /* Polarity of vertical sync pulse */
thedo 166:3a9487d57a5c 132
thedo 166:3a9487d57a5c 133
thedo 166:3a9487d57a5c 134 #endif /* LCD_ANALOG_RGB_H */