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Opencv 3.1 project on GR-PEACH board

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GR-PEACH_video/gr_peach_vdc5.h@166:3a9487d57a5c, 2017-06-29 (annotated)

Committer:
thedo
Date:
Thu Jun 29 11:00:41 2017 +0000
Revision:
166:3a9487d57a5c
This is Opencv 3.1 project on GR-PEACH board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
thedo 166:3a9487d57a5c 1 /*******************************************************************************
thedo 166:3a9487d57a5c 2 * DISCLAIMER
thedo 166:3a9487d57a5c 3 * This software is supplied by Renesas Electronics Corporation and is only
thedo 166:3a9487d57a5c 4 * intended for use with Renesas products. No other uses are authorized. This
thedo 166:3a9487d57a5c 5 * software is owned by Renesas Electronics Corporation and is protected under
thedo 166:3a9487d57a5c 6 * all applicable laws, including copyright laws.
thedo 166:3a9487d57a5c 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
thedo 166:3a9487d57a5c 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
thedo 166:3a9487d57a5c 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
thedo 166:3a9487d57a5c 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
thedo 166:3a9487d57a5c 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
thedo 166:3a9487d57a5c 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
thedo 166:3a9487d57a5c 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
thedo 166:3a9487d57a5c 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
thedo 166:3a9487d57a5c 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
thedo 166:3a9487d57a5c 16 * Renesas reserves the right, without notice, to make changes to this software
thedo 166:3a9487d57a5c 17 * and to discontinue the availability of this software. By using this software,
thedo 166:3a9487d57a5c 18 * you agree to the additional terms and conditions found by accessing the
thedo 166:3a9487d57a5c 19 * following link:
thedo 166:3a9487d57a5c 20 * http://www.renesas.com/disclaimer
thedo 166:3a9487d57a5c 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
thedo 166:3a9487d57a5c 22 *******************************************************************************/
thedo 166:3a9487d57a5c 23 /**************************************************************************//**
thedo 166:3a9487d57a5c 24 * @file gr_peach_vdc5.h
thedo 166:3a9487d57a5c 25 * @version 1.00
thedo 166:3a9487d57a5c 26 * $Rev: 199 $
thedo 166:3a9487d57a5c 27 * $Date:: 2014-05-23 16:33:52 +0900#$
thedo 166:3a9487d57a5c 28 * @brief Graphics driver wrapper function definitions in C
thedo 166:3a9487d57a5c 29 ******************************************************************************/
thedo 166:3a9487d57a5c 30
thedo 166:3a9487d57a5c 31 #ifndef GR_PEACH_VDC5_H
thedo 166:3a9487d57a5c 32 #define GR_PEACH_VDC5_H
thedo 166:3a9487d57a5c 33
thedo 166:3a9487d57a5c 34 /******************************************************************************
thedo 166:3a9487d57a5c 35 Includes <System Includes> , "Project Includes"
thedo 166:3a9487d57a5c 36 ******************************************************************************/
thedo 166:3a9487d57a5c 37 #include <stdlib.h>
thedo 166:3a9487d57a5c 38
thedo 166:3a9487d57a5c 39 #include "r_typedefs.h"
thedo 166:3a9487d57a5c 40 #include "r_vdc5.h"
thedo 166:3a9487d57a5c 41 #include "pinmap.h"
thedo 166:3a9487d57a5c 42
thedo 166:3a9487d57a5c 43 #ifdef __cplusplus
thedo 166:3a9487d57a5c 44 extern "C"
thedo 166:3a9487d57a5c 45 {
thedo 166:3a9487d57a5c 46 #endif /* __cplusplus */
thedo 166:3a9487d57a5c 47
thedo 166:3a9487d57a5c 48 /******************************************************************************
thedo 166:3a9487d57a5c 49 Macro definitions
thedo 166:3a9487d57a5c 50 ******************************************************************************/
thedo 166:3a9487d57a5c 51
thedo 166:3a9487d57a5c 52 #define VSYNC_1_2_FH_TIMING (858u) /* Vsync signal 1/2fH phase timing */
thedo 166:3a9487d57a5c 53 #define VSYNC_1_4_FH_TIMING (429u) /* Vsync signal 1/4fH phase timing */
thedo 166:3a9487d57a5c 54 #define DEFAULT_INPUT_CLOCK (66.67) /* P1 clock VDC5 */
thedo 166:3a9487d57a5c 55 #define DEFAULT_OUTPUT_CLOCK (66.67) /* LVDS output clock */
thedo 166:3a9487d57a5c 56
thedo 166:3a9487d57a5c 57 #define IMGCAP_SIZE_NTSC_HS (122u)
thedo 166:3a9487d57a5c 58 #define IMGCAP_SIZE_NTSC_HW (720u)
thedo 166:3a9487d57a5c 59 #define IMGCAP_SIZE_NTSC_VS (16u)
thedo 166:3a9487d57a5c 60 #define IMGCAP_SIZE_NTSC_VW (240u)
thedo 166:3a9487d57a5c 61
thedo 166:3a9487d57a5c 62 #define IMGCAP_SIZE_PAL_HS (132u)
thedo 166:3a9487d57a5c 63 #define IMGCAP_SIZE_PAL_HW (720u)
thedo 166:3a9487d57a5c 64 #define IMGCAP_SIZE_PAL_VS (19u)
thedo 166:3a9487d57a5c 65 #define IMGCAP_SIZE_PAL_VW (280u)
thedo 166:3a9487d57a5c 66
thedo 166:3a9487d57a5c 67 typedef void (*vdc5_irq_handler)(uint32_t int_sense);
thedo 166:3a9487d57a5c 68
thedo 166:3a9487d57a5c 69 /* video channel select */
thedo 166:3a9487d57a5c 70 typedef enum {
thedo 166:3a9487d57a5c 71 DRV_VIDEO_INPUT_CHANNEL_0 = 0, /* video input channel 0 */
thedo 166:3a9487d57a5c 72 DRV_VIDEO_INPUT_CHANNEL_1 /* video input channel 1 */
thedo 166:3a9487d57a5c 73 } drv_video_input_channel_t;
thedo 166:3a9487d57a5c 74
thedo 166:3a9487d57a5c 75 /* input pin control */
thedo 166:3a9487d57a5c 76 typedef enum {
thedo 166:3a9487d57a5c 77 DRV_VIDEO_ADC_VINSEL_VIN1 = 0, /* VIN1 input */
thedo 166:3a9487d57a5c 78 DRV_VIDEO_ADC_VINSEL_VIN2 /* VIN2 input */
thedo 166:3a9487d57a5c 79 } drv_video_adc_vinsel_t;
thedo 166:3a9487d57a5c 80
thedo 166:3a9487d57a5c 81 /* graphics layer select */
thedo 166:3a9487d57a5c 82 typedef enum {
thedo 166:3a9487d57a5c 83 DRV_GRAPHICS_LAYER_0 = 0, /* graphics layer 0 */
thedo 166:3a9487d57a5c 84 DRV_GRAPHICS_LAYER_1, /* graphics layer 1 */
thedo 166:3a9487d57a5c 85 DRV_GRAPHICS_LAYER_2, /* graphics layer 2 */
thedo 166:3a9487d57a5c 86 DRV_GRAPHICS_LAYER_3 /* graphics layer 3 */
thedo 166:3a9487d57a5c 87 } drv_graphics_layer_t;
thedo 166:3a9487d57a5c 88
thedo 166:3a9487d57a5c 89 /* error codes */
thedo 166:3a9487d57a5c 90 typedef enum {
thedo 166:3a9487d57a5c 91 DRV_GRAPHICS_OK = 0, /* Normal termination */
thedo 166:3a9487d57a5c 92 DRV_GRAPHICS_VDC5_ERR = -1, /* VDC5 error */
thedo 166:3a9487d57a5c 93 DRV_GRAPHICS_FORMAT_ERR = -2, /* Not support format */
thedo 166:3a9487d57a5c 94 DRV_GRAPHICS_LAYER_ERR = -3, /* Invalid layer ID error */
thedo 166:3a9487d57a5c 95 DRV_GRAPHICS_CHANNEL_ERR = -4, /* Invalid channel error */
thedo 166:3a9487d57a5c 96 DRV_GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, /* Video Write */
thedo 166:3a9487d57a5c 97 DRV_GRAPHICS_VIDEO_PAL_SIZE_ERR = -6, /* Video Write */
thedo 166:3a9487d57a5c 98 DRV_GRAPHICS_PARAM_RANGE_ERR = -7 /* Parameter range error */
thedo 166:3a9487d57a5c 99 } drv_graphics_error_t;
thedo 166:3a9487d57a5c 100
thedo 166:3a9487d57a5c 101 /* graphics layer format select */
thedo 166:3a9487d57a5c 102 typedef enum {
thedo 166:3a9487d57a5c 103 DRV_GRAPHICS_FORMAT_YCBCR422 = 0, /* YCbCr422 */
thedo 166:3a9487d57a5c 104 DRV_GRAPHICS_FORMAT_RGB565, /* RGB565 */
thedo 166:3a9487d57a5c 105 DRV_GRAPHICS_FORMAT_RGB888, /* RGB888 */
thedo 166:3a9487d57a5c 106 DRV_GRAPHICS_FORMAT_ARGB8888, /* ARGB8888 */
thedo 166:3a9487d57a5c 107 DRV_GRAPHICS_FORMAT_ARGB4444 /* ARGB4444 */
thedo 166:3a9487d57a5c 108 } drv_graphics_format_t;
thedo 166:3a9487d57a5c 109
thedo 166:3a9487d57a5c 110 /* video writing format select */
thedo 166:3a9487d57a5c 111 typedef enum {
thedo 166:3a9487d57a5c 112 DRV_VIDEO_FORMAT_YCBCR422 = 0, /* YCbCr422 */
thedo 166:3a9487d57a5c 113 DRV_VIDEO_FORMAT_RGB565, /* RGB565 */
thedo 166:3a9487d57a5c 114 DRV_VIDEO_FORMAT_RGB888 /* RGB888 */
thedo 166:3a9487d57a5c 115 } drv_video_format_t;
thedo 166:3a9487d57a5c 116
thedo 166:3a9487d57a5c 117
thedo 166:3a9487d57a5c 118 /* lcd tcon output pin select */
thedo 166:3a9487d57a5c 119 typedef enum {
thedo 166:3a9487d57a5c 120 DRV_LCD_TCON_PIN_NON = -1, /* Not using output */
thedo 166:3a9487d57a5c 121 DRV_LCD_TCON_PIN_0, /* LCD_TCON0 */
thedo 166:3a9487d57a5c 122 DRV_LCD_TCON_PIN_1, /* LCD_TCON1 */
thedo 166:3a9487d57a5c 123 DRV_LCD_TCON_PIN_2 /* LCD_TCON2 */
thedo 166:3a9487d57a5c 124 } drv_lcd_tcon_pin_t;
thedo 166:3a9487d57a5c 125
thedo 166:3a9487d57a5c 126 /* lcd output format select */
thedo 166:3a9487d57a5c 127 typedef enum {
thedo 166:3a9487d57a5c 128 DRV_LCD_OUTFORMAT_RGB888 = 0, /* RGB888 or LVDS */
thedo 166:3a9487d57a5c 129 DRV_LCD_OUTFORMAT_RGB666, /* RGB666 */
thedo 166:3a9487d57a5c 130 DRV_LCD_OUTFORMAT_RGB565 /* RGB565 */
thedo 166:3a9487d57a5c 131 } drv_lcd_outformat_t;
thedo 166:3a9487d57a5c 132
thedo 166:3a9487d57a5c 133 /* frame buffer swap setting */
thedo 166:3a9487d57a5c 134 typedef enum {
thedo 166:3a9487d57a5c 135 DRV_WR_RD_WRSWA_NON = 0, /* Not swapped: 1-2-3-4-5-6-7-8 */
thedo 166:3a9487d57a5c 136 DRV_WR_RD_WRSWA_8BIT, /* Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
thedo 166:3a9487d57a5c 137 DRV_WR_RD_WRSWA_16BIT, /* Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
thedo 166:3a9487d57a5c 138 DRV_WR_RD_WRSWA_16_8BIT, /* Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
thedo 166:3a9487d57a5c 139 DRV_WR_RD_WRSWA_32BIT, /* Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
thedo 166:3a9487d57a5c 140 DRV_WR_RD_WRSWA_32_8BIT, /* Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
thedo 166:3a9487d57a5c 141 DRV_WR_RD_WRSWA_32_16BIT, /* Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
thedo 166:3a9487d57a5c 142 DRV_WR_RD_WRSWA_32_16_8BIT, /* Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
thedo 166:3a9487d57a5c 143 } drv_wr_rd_swa_t;
thedo 166:3a9487d57a5c 144
thedo 166:3a9487d57a5c 145 /* edge of a signal */
thedo 166:3a9487d57a5c 146 typedef enum {
thedo 166:3a9487d57a5c 147 DRV_EDGE_RISING = 0, /* Rising edge */
thedo 166:3a9487d57a5c 148 DRV_EDGE_FALLING = 1 /* Falling edge */
thedo 166:3a9487d57a5c 149 } drv_edge_t;
thedo 166:3a9487d57a5c 150
thedo 166:3a9487d57a5c 151 /* lcd type */
thedo 166:3a9487d57a5c 152 typedef enum {
thedo 166:3a9487d57a5c 153 DRV_LCD_TYPE_LVDS = 0, /* LVDS signal control */
thedo 166:3a9487d57a5c 154 DRV_LCD_TYPE_PARALLEL_RGB /* RGB parallel signal control */
thedo 166:3a9487d57a5c 155 } drv_lcd_type_t;
thedo 166:3a9487d57a5c 156
thedo 166:3a9487d57a5c 157 /* Polarity of a signal */
thedo 166:3a9487d57a5c 158 typedef enum {
thedo 166:3a9487d57a5c 159 DRV_SIG_POL_NOT_INVERTED = 0, /* Not inverted */
thedo 166:3a9487d57a5c 160 DRV_SIG_POL_INVERTED /* Inverted */
thedo 166:3a9487d57a5c 161 } drv_sig_pol_t;
thedo 166:3a9487d57a5c 162
thedo 166:3a9487d57a5c 163 /* Video color system */
thedo 166:3a9487d57a5c 164 typedef enum {
thedo 166:3a9487d57a5c 165 DRV_COL_SYS_NTSC_358 = 0, /* NTSC-3.58 */
thedo 166:3a9487d57a5c 166 DVV_COL_SYS_NTSC_443 = 1, /* NTSC-4.43 */
thedo 166:3a9487d57a5c 167 DRV_COL_SYS_PAL_443 = 2, /* PAL-4.43 */
thedo 166:3a9487d57a5c 168 DRV_COL_SYS_PAL_M = 3, /* PAL-M */
thedo 166:3a9487d57a5c 169 DRV_COL_SYS_PAL_N = 4, /* PAL-N */
thedo 166:3a9487d57a5c 170 DRV_COL_SYS_SECAM = 5, /* SECAM */
thedo 166:3a9487d57a5c 171 DRV_COL_SYS_NTSC_443_60 = 6, /* NTSC-4.43 (60Hz) */
thedo 166:3a9487d57a5c 172 DRV_COL_SYS_PAL_60 = 7, /* PAL-60 */
thedo 166:3a9487d57a5c 173 } drv_graphics_video_col_sys_t;
thedo 166:3a9487d57a5c 174
thedo 166:3a9487d57a5c 175 /* External Input select */
thedo 166:3a9487d57a5c 176 typedef enum {
thedo 166:3a9487d57a5c 177 DRV_INPUT_SEL_VDEC = 0, /*!< Video decoder output signals */
thedo 166:3a9487d57a5c 178 DRV_INPUT_SEL_EXT = 1 /*!< Signals supplied via the external input pins */
thedo 166:3a9487d57a5c 179 } drv_video_input_sel_t;
thedo 166:3a9487d57a5c 180
thedo 166:3a9487d57a5c 181 /* External input format select */
thedo 166:3a9487d57a5c 182 typedef enum {
thedo 166:3a9487d57a5c 183 DRV_VIDEO_EXTIN_FORMAT_RGB888 = 0, /*!< RGB888 Not support */
thedo 166:3a9487d57a5c 184 DRV_VIDEO_EXTIN_FORMAT_RGB666, /*!< RGB666 */
thedo 166:3a9487d57a5c 185 DRV_VIDEO_EXTIN_FORMAT_RGB565, /*!< RGB565 */
thedo 166:3a9487d57a5c 186 DRV_VIDEO_EXTIN_FORMAT_BT656, /*!< BT6556 */
thedo 166:3a9487d57a5c 187 DRV_VIDEO_EXTIN_FORMAT_BT601, /*!< BT6501 */
thedo 166:3a9487d57a5c 188 DRV_VIDEO_EXTIN_FORMAT_YCBCR422, /*!< YCbCr422 */
thedo 166:3a9487d57a5c 189 DRV_VIDEO_EXTIN_FORMAT_YCBCR444, /*!< YCbCr444 Not support */
thedo 166:3a9487d57a5c 190 } drv_video_extin_format_t;
thedo 166:3a9487d57a5c 191
thedo 166:3a9487d57a5c 192 /* On/off */
thedo 166:3a9487d57a5c 193 typedef enum {
thedo 166:3a9487d57a5c 194 DRV_OFF = 0, /*!< Off */
thedo 166:3a9487d57a5c 195 DRV_ON = 1 /*!< On */
thedo 166:3a9487d57a5c 196 } drv_onoff_t;
thedo 166:3a9487d57a5c 197
thedo 166:3a9487d57a5c 198 /* Number of lines for BT.656 external input */
thedo 166:3a9487d57a5c 199 typedef enum {
thedo 166:3a9487d57a5c 200 DRV_EXTIN_LINE_525 = 0, /*!< 525 lines */
thedo 166:3a9487d57a5c 201 DRV_EXTIN_LINE_625 = 1 /*!< 625 lines */
thedo 166:3a9487d57a5c 202 } drv_extin_input_line_t;
thedo 166:3a9487d57a5c 203
thedo 166:3a9487d57a5c 204 /* Y/Cb/Y/Cr data string start timing */
thedo 166:3a9487d57a5c 205 typedef enum {
thedo 166:3a9487d57a5c 206 DRV_EXTIN_H_POS_CBYCRY = 0, /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */
thedo 166:3a9487d57a5c 207 DRV_EXTIN_H_POS_YCRYCB, /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */
thedo 166:3a9487d57a5c 208 DRV_EXTIN_H_POS_CRYCBY, /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */
thedo 166:3a9487d57a5c 209 DRV_EXTIN_H_POS_YCBYCR, /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */
thedo 166:3a9487d57a5c 210 } drv_extin_h_pos_t;
thedo 166:3a9487d57a5c 211
thedo 166:3a9487d57a5c 212 /* The relative position within the graphics display area */
thedo 166:3a9487d57a5c 213 typedef struct {
thedo 166:3a9487d57a5c 214 uint16_t vs; /* Vertical start pos */
thedo 166:3a9487d57a5c 215 uint16_t vw; /* Vertical width (height) */
thedo 166:3a9487d57a5c 216 uint16_t hs; /* Horizontal start pos */
thedo 166:3a9487d57a5c 217 uint16_t hw; /* Horizontal width */
thedo 166:3a9487d57a5c 218 } drv_rect_t;
thedo 166:3a9487d57a5c 219
thedo 166:3a9487d57a5c 220 /* lcd configuration */
thedo 166:3a9487d57a5c 221 typedef struct {
thedo 166:3a9487d57a5c 222 drv_lcd_type_t lcd_type; /* LVDS or Pararel RGB */
thedo 166:3a9487d57a5c 223 double intputClock; /* P1 clk [MHz] ex. 66.67 */
thedo 166:3a9487d57a5c 224 double outputClock; /* LCD clk [MHz] ex. 33.33 */
thedo 166:3a9487d57a5c 225
thedo 166:3a9487d57a5c 226 drv_lcd_outformat_t lcd_outformat; /* Output format select */
thedo 166:3a9487d57a5c 227 drv_edge_t lcd_edge; /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
thedo 166:3a9487d57a5c 228
thedo 166:3a9487d57a5c 229 uint16_t h_toatal_period; /* Free-running Hsync period */
thedo 166:3a9487d57a5c 230 uint16_t v_toatal_period; /* Free-running Vsync period */
thedo 166:3a9487d57a5c 231 uint16_t h_disp_widht; /* LCD display area size, horizontal width */
thedo 166:3a9487d57a5c 232 uint16_t v_disp_widht; /* LCD display area size, vertical width */
thedo 166:3a9487d57a5c 233 uint16_t h_back_porch; /* LCD display horizontal back porch period */
thedo 166:3a9487d57a5c 234 uint16_t v_back_porch; /* LCD display vertical back porch period */
thedo 166:3a9487d57a5c 235
thedo 166:3a9487d57a5c 236 drv_lcd_tcon_pin_t h_sync_port; /* TCONn or Not use(-1) */
thedo 166:3a9487d57a5c 237 drv_sig_pol_t h_sync_port_polarity; /* Polarity inversion control of signal */
thedo 166:3a9487d57a5c 238 uint16_t h_sync_width; /* Hsync width */
thedo 166:3a9487d57a5c 239
thedo 166:3a9487d57a5c 240 drv_lcd_tcon_pin_t v_sync_port; /* TCONn or Not use(-1) */
thedo 166:3a9487d57a5c 241 drv_sig_pol_t v_sync_port_polarity; /* Polarity inversion control of signal */
thedo 166:3a9487d57a5c 242 uint16_t v_sync_width; /* Vsync width */
thedo 166:3a9487d57a5c 243
thedo 166:3a9487d57a5c 244 drv_lcd_tcon_pin_t de_port; /* TCONn or Not use(-1) */
thedo 166:3a9487d57a5c 245 drv_sig_pol_t de_port_polarity; /* Polarity inversion control of signal */
thedo 166:3a9487d57a5c 246
thedo 166:3a9487d57a5c 247 } drv_lcd_config_t;
thedo 166:3a9487d57a5c 248
thedo 166:3a9487d57a5c 249 /* Digital video input configuration */
thedo 166:3a9487d57a5c 250 typedef struct {
thedo 166:3a9487d57a5c 251 drv_video_extin_format_t inp_format; /*!< External Input Format Select */
thedo 166:3a9487d57a5c 252 drv_edge_t inp_pxd_edge; /*!< Clock Edge Select for Capturing External Input Video Image */
thedo 166:3a9487d57a5c 253 drv_edge_t inp_vs_edge; /*!< Clock Edge Select for Capturing External Input Vsync Signal */
thedo 166:3a9487d57a5c 254 drv_edge_t inp_hs_edge; /*!< Clock Edge Select for Capturing External Input Hsync Signal */
thedo 166:3a9487d57a5c 255 drv_onoff_t inp_endian_on; /*!< External Input B/R Signal Swap On/Off Control */
thedo 166:3a9487d57a5c 256 drv_onoff_t inp_swap_on; /*!< External Input Bit Endian Change On/Off Control */
thedo 166:3a9487d57a5c 257 drv_sig_pol_t inp_vs_inv; /*!< External Input Vsync Signal DV_VSYNC Inversion Control */
thedo 166:3a9487d57a5c 258 drv_sig_pol_t inp_hs_inv; /*!< External Input Hsync Signal DV_HSYNC Inversion Control */
thedo 166:3a9487d57a5c 259 drv_extin_input_line_t inp_f525_625; /*!< Number of lines for BT.656 external input */
thedo 166:3a9487d57a5c 260 drv_extin_h_pos_t inp_h_pos; /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */
thedo 166:3a9487d57a5c 261 } drv_video_ext_in_config_t;
thedo 166:3a9487d57a5c 262
thedo 166:3a9487d57a5c 263 /******************************************************************************
thedo 166:3a9487d57a5c 264 Typedef definitions
thedo 166:3a9487d57a5c 265 ******************************************************************************/
thedo 166:3a9487d57a5c 266
thedo 166:3a9487d57a5c 267 /******************************************************************************
thedo 166:3a9487d57a5c 268 Exported global functions (to be accessed by other files)
thedo 166:3a9487d57a5c 269 ******************************************************************************/
thedo 166:3a9487d57a5c 270 drv_graphics_error_t DRV_Graphics_Init( drv_lcd_config_t * drv_lcd_config );
thedo 166:3a9487d57a5c 271 drv_graphics_error_t DRV_Graphics_Video_init( drv_video_input_sel_t drv_video_input_sel, drv_video_ext_in_config_t * drv_video_ext_in_config );
thedo 166:3a9487d57a5c 272
thedo 166:3a9487d57a5c 273 drv_graphics_error_t DRV_Graphics_Lcd_Port_Init( PinName *pin, uint32_t pin_count );
thedo 166:3a9487d57a5c 274 drv_graphics_error_t DRV_Graphics_Lvds_Port_Init( PinName *pin, uint32_t pin_count );
thedo 166:3a9487d57a5c 275 drv_graphics_error_t DRV_Graphics_Dvinput_Port_Init( PinName *pin, uint32_t pin_count );
thedo 166:3a9487d57a5c 276
thedo 166:3a9487d57a5c 277 drv_graphics_error_t DRV_Graphics_Irq_Handler_Set( vdc5_int_type_t irq, uint16_t num, void (* callback)(vdc5_int_type_t) );
thedo 166:3a9487d57a5c 278
thedo 166:3a9487d57a5c 279 drv_graphics_error_t DRV_Graphics_Start ( drv_graphics_layer_t layer_id );
thedo 166:3a9487d57a5c 280 drv_graphics_error_t DRV_Graphics_Stop ( drv_graphics_layer_t layer_id );
thedo 166:3a9487d57a5c 281 drv_graphics_error_t DRV_Video_Start ( drv_video_input_channel_t video_input_ch );
thedo 166:3a9487d57a5c 282 drv_graphics_error_t DRV_Video_Stop ( drv_video_input_channel_t video_input_ch );
thedo 166:3a9487d57a5c 283
thedo 166:3a9487d57a5c 284 drv_graphics_error_t DRV_Graphics_Read_Setting (
thedo 166:3a9487d57a5c 285 drv_graphics_layer_t layer_id,
thedo 166:3a9487d57a5c 286 void * framebuff,
thedo 166:3a9487d57a5c 287 uint32_t fb_stride,
thedo 166:3a9487d57a5c 288 drv_graphics_format_t gr_format,
thedo 166:3a9487d57a5c 289 drv_wr_rd_swa_t wr_rd_swa,
thedo 166:3a9487d57a5c 290 drv_rect_t * gr_rect );
thedo 166:3a9487d57a5c 291
thedo 166:3a9487d57a5c 292 drv_graphics_error_t DRV_Graphics_Read_Change (
thedo 166:3a9487d57a5c 293 drv_graphics_layer_t layer_id,
thedo 166:3a9487d57a5c 294 void * framebuff);
thedo 166:3a9487d57a5c 295
thedo 166:3a9487d57a5c 296 drv_graphics_error_t DRV_Video_Write_Setting (
thedo 166:3a9487d57a5c 297 drv_video_input_channel_t video_input_ch,
thedo 166:3a9487d57a5c 298 drv_graphics_video_col_sys_t col_sys,
thedo 166:3a9487d57a5c 299 void * framebuff,
thedo 166:3a9487d57a5c 300 uint32_t fb_stride,
thedo 166:3a9487d57a5c 301 drv_video_format_t video_format,
thedo 166:3a9487d57a5c 302 drv_wr_rd_swa_t wr_rd_swa,
thedo 166:3a9487d57a5c 303 uint16_t video_write_buff_vw,
thedo 166:3a9487d57a5c 304 uint16_t video_write_buff_hw,
thedo 166:3a9487d57a5c 305 drv_video_adc_vinsel_t video_adc_vinsel );
thedo 166:3a9487d57a5c 306
thedo 166:3a9487d57a5c 307 drv_graphics_error_t DRV_Video_Write_Setting_Digital (
thedo 166:3a9487d57a5c 308 void * framebuff,
thedo 166:3a9487d57a5c 309 uint32_t fb_stride,
thedo 166:3a9487d57a5c 310 drv_video_format_t video_format,
thedo 166:3a9487d57a5c 311 drv_wr_rd_swa_t wr_rd_swa,
thedo 166:3a9487d57a5c 312 uint16_t video_write_buff_vw,
thedo 166:3a9487d57a5c 313 uint16_t video_write_buff_hw,
thedo 166:3a9487d57a5c 314 drv_rect_t * cap_area );
thedo 166:3a9487d57a5c 315
thedo 166:3a9487d57a5c 316 drv_graphics_error_t DRV_Video_Write_Change (
thedo 166:3a9487d57a5c 317 drv_video_input_channel_t video_input_ch,
thedo 166:3a9487d57a5c 318 void * framebuff,
thedo 166:3a9487d57a5c 319 uint32_t fb_stride );
thedo 166:3a9487d57a5c 320
thedo 166:3a9487d57a5c 321 #ifdef __cplusplus
thedo 166:3a9487d57a5c 322 }
thedo 166:3a9487d57a5c 323 #endif /* __cplusplus */
thedo 166:3a9487d57a5c 324
thedo 166:3a9487d57a5c 325 #endif /* GR_PEACH_VDC5_H */