Diff: tools/export/codered_lpc1114_cproject.tmpl

Revision:

0:5c4d7b2438d3

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/export/codered_lpc1114_cproject.tmpl	Fri Nov 11 20:59:50 2016 +0000
@@ -0,0 +1,48 @@
+{% extends "codered_cproject_cortexm0_common.tmpl" %}
+
+{% block startup_file %}cr_startup_lpc11xx.c{% endblock %}
+
+{% block cpu_config %}<?xml version="1.0" encoding="UTF-8"?>
+<TargetConfig>
+<Properties property_0="" property_2="LPC11_12_13_32K_4K.cfx" property_3="NXP" property_4="LPC1114FN/102" property_count="5" version="60100"/>
+<infoList vendor="NXP">
+<info chip="LPC1114FN/102" flash_driver="LPC11_12_13_32K_4K.cfx" match_id="0x0A40902B,0x1A40902B" name="LPC1114FN/102" stub="crt_emu_lpc11_13_nxp">
+<chip>
+<name>LPC1114FN/102</name>
+<family>LPC11xx</family>
+<vendor>NXP (formerly Philips)</vendor>
+<reset board="None" core="Real" sys="Real"/>
+<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/>
+<memory can_program="true" id="Flash" is_ro="true" type="Flash"/>
+<memory id="RAM" type="RAM"/>
+<memory id="Periph" is_volatile="true" type="Peripheral"/>
+<memoryInstance derived_from="Flash" id="MFlash32" location="0x0" size="0x8000"/>
+<memoryInstance derived_from="RAM" id="RamLoc4" location="0x10000000" size="0x1000"/>
+<peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/>
+<peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/>
+<peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/>
+<peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/>
+<peripheralInstance derived_from="UART" determined="infoFile" id="UART" location="0x40008000"/>
+<peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/>
+<peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/>
+<peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/>
+<peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/>
+<peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/>
+<peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/>
+<peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/>
+<peripheralInstance derived_from="SPI0" determined="infoFile" id="SPI0" location="0x40040000"/>
+<peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/>
+<peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/>
+<peripheralInstance derived_from="GPIO0" determined="infoFile" id="GPIO0" location="0x50000000"/>
+<peripheralInstance derived_from="GPIO1" determined="infoFile" id="GPIO1" location="0x50010000"/>
+<peripheralInstance derived_from="GPIO2" determined="infoFile" id="GPIO2" location="0x50020000"/>
+<peripheralInstance derived_from="GPIO3" determined="infoFile" id="GPIO3" location="0x50030000"/>
+</chip>
+<processor>
+<name gcc_name="cortex-m0">Cortex-M0</name>
+<family>Cortex-M</family>
+</processor>
+<link href="LPC11xx_peripheral.xme" show="embed" type="simple"/>
+</info>
+</infoList>
+</TargetConfig>{% endblock %}