dev01 Brautlecht / mbed-STM32F030F4

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   STM32F031_Blink_Aug17

Fork of mbed-STM32F030F4 by Nothing Special

targets/cmsis/core_cmFunc.h@0:38ccae254a29, 2014-10-18 (annotated)

Committer:
mega64
Date:
Sat Oct 18 02:40:17 2014 +0000
Revision:
0:38ccae254a29
only for STM32F030F4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mega64 0:38ccae254a29 1 /**************************************************************************//**
mega64 0:38ccae254a29 2 * @file core_cmFunc.h
mega64 0:38ccae254a29 3 * @brief CMSIS Cortex-M Core Function Access Header File
mega64 0:38ccae254a29 4 * @version V3.20
mega64 0:38ccae254a29 5 * @date 25. February 2013
mega64 0:38ccae254a29 6 *
mega64 0:38ccae254a29 7 * @note
mega64 0:38ccae254a29 8 *
mega64 0:38ccae254a29 9 ******************************************************************************/
mega64 0:38ccae254a29 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
mega64 0:38ccae254a29 11
mega64 0:38ccae254a29 12 All rights reserved.
mega64 0:38ccae254a29 13 Redistribution and use in source and binary forms, with or without
mega64 0:38ccae254a29 14 modification, are permitted provided that the following conditions are met:
mega64 0:38ccae254a29 15 - Redistributions of source code must retain the above copyright
mega64 0:38ccae254a29 16 notice, this list of conditions and the following disclaimer.
mega64 0:38ccae254a29 17 - Redistributions in binary form must reproduce the above copyright
mega64 0:38ccae254a29 18 notice, this list of conditions and the following disclaimer in the
mega64 0:38ccae254a29 19 documentation and/or other materials provided with the distribution.
mega64 0:38ccae254a29 20 - Neither the name of ARM nor the names of its contributors may be used
mega64 0:38ccae254a29 21 to endorse or promote products derived from this software without
mega64 0:38ccae254a29 22 specific prior written permission.
mega64 0:38ccae254a29 23 *
mega64 0:38ccae254a29 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mega64 0:38ccae254a29 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mega64 0:38ccae254a29 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mega64 0:38ccae254a29 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mega64 0:38ccae254a29 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mega64 0:38ccae254a29 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mega64 0:38ccae254a29 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mega64 0:38ccae254a29 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mega64 0:38ccae254a29 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mega64 0:38ccae254a29 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mega64 0:38ccae254a29 34 POSSIBILITY OF SUCH DAMAGE.
mega64 0:38ccae254a29 35 ---------------------------------------------------------------------------*/
mega64 0:38ccae254a29 36
mega64 0:38ccae254a29 37
mega64 0:38ccae254a29 38 #ifndef __CORE_CMFUNC_H
mega64 0:38ccae254a29 39 #define __CORE_CMFUNC_H
mega64 0:38ccae254a29 40
mega64 0:38ccae254a29 41
mega64 0:38ccae254a29 42 /* ########################### Core Function Access ########################### */
mega64 0:38ccae254a29 43 /** \ingroup CMSIS_Core_FunctionInterface
mega64 0:38ccae254a29 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
mega64 0:38ccae254a29 45 @{
mega64 0:38ccae254a29 46 */
mega64 0:38ccae254a29 47
mega64 0:38ccae254a29 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
mega64 0:38ccae254a29 49 /* ARM armcc specific functions */
mega64 0:38ccae254a29 50
mega64 0:38ccae254a29 51 #if (__ARMCC_VERSION < 400677)
mega64 0:38ccae254a29 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
mega64 0:38ccae254a29 53 #endif
mega64 0:38ccae254a29 54
mega64 0:38ccae254a29 55 /* intrinsic void __enable_irq(); */
mega64 0:38ccae254a29 56 /* intrinsic void __disable_irq(); */
mega64 0:38ccae254a29 57
mega64 0:38ccae254a29 58 /** \brief Get Control Register
mega64 0:38ccae254a29 59
mega64 0:38ccae254a29 60 This function returns the content of the Control Register.
mega64 0:38ccae254a29 61
mega64 0:38ccae254a29 62 \return Control Register value
mega64 0:38ccae254a29 63 */
mega64 0:38ccae254a29 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
mega64 0:38ccae254a29 65 {
mega64 0:38ccae254a29 66 register uint32_t __regControl __ASM("control");
mega64 0:38ccae254a29 67 return(__regControl);
mega64 0:38ccae254a29 68 }
mega64 0:38ccae254a29 69
mega64 0:38ccae254a29 70
mega64 0:38ccae254a29 71 /** \brief Set Control Register
mega64 0:38ccae254a29 72
mega64 0:38ccae254a29 73 This function writes the given value to the Control Register.
mega64 0:38ccae254a29 74
mega64 0:38ccae254a29 75 \param [in] control Control Register value to set
mega64 0:38ccae254a29 76 */
mega64 0:38ccae254a29 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
mega64 0:38ccae254a29 78 {
mega64 0:38ccae254a29 79 register uint32_t __regControl __ASM("control");
mega64 0:38ccae254a29 80 __regControl = control;
mega64 0:38ccae254a29 81 }
mega64 0:38ccae254a29 82
mega64 0:38ccae254a29 83
mega64 0:38ccae254a29 84 /** \brief Get IPSR Register
mega64 0:38ccae254a29 85
mega64 0:38ccae254a29 86 This function returns the content of the IPSR Register.
mega64 0:38ccae254a29 87
mega64 0:38ccae254a29 88 \return IPSR Register value
mega64 0:38ccae254a29 89 */
mega64 0:38ccae254a29 90 __STATIC_INLINE uint32_t __get_IPSR(void)
mega64 0:38ccae254a29 91 {
mega64 0:38ccae254a29 92 register uint32_t __regIPSR __ASM("ipsr");
mega64 0:38ccae254a29 93 return(__regIPSR);
mega64 0:38ccae254a29 94 }
mega64 0:38ccae254a29 95
mega64 0:38ccae254a29 96
mega64 0:38ccae254a29 97 /** \brief Get APSR Register
mega64 0:38ccae254a29 98
mega64 0:38ccae254a29 99 This function returns the content of the APSR Register.
mega64 0:38ccae254a29 100
mega64 0:38ccae254a29 101 \return APSR Register value
mega64 0:38ccae254a29 102 */
mega64 0:38ccae254a29 103 __STATIC_INLINE uint32_t __get_APSR(void)
mega64 0:38ccae254a29 104 {
mega64 0:38ccae254a29 105 register uint32_t __regAPSR __ASM("apsr");
mega64 0:38ccae254a29 106 return(__regAPSR);
mega64 0:38ccae254a29 107 }
mega64 0:38ccae254a29 108
mega64 0:38ccae254a29 109
mega64 0:38ccae254a29 110 /** \brief Get xPSR Register
mega64 0:38ccae254a29 111
mega64 0:38ccae254a29 112 This function returns the content of the xPSR Register.
mega64 0:38ccae254a29 113
mega64 0:38ccae254a29 114 \return xPSR Register value
mega64 0:38ccae254a29 115 */
mega64 0:38ccae254a29 116 __STATIC_INLINE uint32_t __get_xPSR(void)
mega64 0:38ccae254a29 117 {
mega64 0:38ccae254a29 118 register uint32_t __regXPSR __ASM("xpsr");
mega64 0:38ccae254a29 119 return(__regXPSR);
mega64 0:38ccae254a29 120 }
mega64 0:38ccae254a29 121
mega64 0:38ccae254a29 122
mega64 0:38ccae254a29 123 /** \brief Get Process Stack Pointer
mega64 0:38ccae254a29 124
mega64 0:38ccae254a29 125 This function returns the current value of the Process Stack Pointer (PSP).
mega64 0:38ccae254a29 126
mega64 0:38ccae254a29 127 \return PSP Register value
mega64 0:38ccae254a29 128 */
mega64 0:38ccae254a29 129 __STATIC_INLINE uint32_t __get_PSP(void)
mega64 0:38ccae254a29 130 {
mega64 0:38ccae254a29 131 register uint32_t __regProcessStackPointer __ASM("psp");
mega64 0:38ccae254a29 132 return(__regProcessStackPointer);
mega64 0:38ccae254a29 133 }
mega64 0:38ccae254a29 134
mega64 0:38ccae254a29 135
mega64 0:38ccae254a29 136 /** \brief Set Process Stack Pointer
mega64 0:38ccae254a29 137
mega64 0:38ccae254a29 138 This function assigns the given value to the Process Stack Pointer (PSP).
mega64 0:38ccae254a29 139
mega64 0:38ccae254a29 140 \param [in] topOfProcStack Process Stack Pointer value to set
mega64 0:38ccae254a29 141 */
mega64 0:38ccae254a29 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
mega64 0:38ccae254a29 143 {
mega64 0:38ccae254a29 144 register uint32_t __regProcessStackPointer __ASM("psp");
mega64 0:38ccae254a29 145 __regProcessStackPointer = topOfProcStack;
mega64 0:38ccae254a29 146 }
mega64 0:38ccae254a29 147
mega64 0:38ccae254a29 148
mega64 0:38ccae254a29 149 /** \brief Get Main Stack Pointer
mega64 0:38ccae254a29 150
mega64 0:38ccae254a29 151 This function returns the current value of the Main Stack Pointer (MSP).
mega64 0:38ccae254a29 152
mega64 0:38ccae254a29 153 \return MSP Register value
mega64 0:38ccae254a29 154 */
mega64 0:38ccae254a29 155 __STATIC_INLINE uint32_t __get_MSP(void)
mega64 0:38ccae254a29 156 {
mega64 0:38ccae254a29 157 register uint32_t __regMainStackPointer __ASM("msp");
mega64 0:38ccae254a29 158 return(__regMainStackPointer);
mega64 0:38ccae254a29 159 }
mega64 0:38ccae254a29 160
mega64 0:38ccae254a29 161
mega64 0:38ccae254a29 162 /** \brief Set Main Stack Pointer
mega64 0:38ccae254a29 163
mega64 0:38ccae254a29 164 This function assigns the given value to the Main Stack Pointer (MSP).
mega64 0:38ccae254a29 165
mega64 0:38ccae254a29 166 \param [in] topOfMainStack Main Stack Pointer value to set
mega64 0:38ccae254a29 167 */
mega64 0:38ccae254a29 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
mega64 0:38ccae254a29 169 {
mega64 0:38ccae254a29 170 register uint32_t __regMainStackPointer __ASM("msp");
mega64 0:38ccae254a29 171 __regMainStackPointer = topOfMainStack;
mega64 0:38ccae254a29 172 }
mega64 0:38ccae254a29 173
mega64 0:38ccae254a29 174
mega64 0:38ccae254a29 175 /** \brief Get Priority Mask
mega64 0:38ccae254a29 176
mega64 0:38ccae254a29 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
mega64 0:38ccae254a29 178
mega64 0:38ccae254a29 179 \return Priority Mask value
mega64 0:38ccae254a29 180 */
mega64 0:38ccae254a29 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
mega64 0:38ccae254a29 182 {
mega64 0:38ccae254a29 183 register uint32_t __regPriMask __ASM("primask");
mega64 0:38ccae254a29 184 return(__regPriMask);
mega64 0:38ccae254a29 185 }
mega64 0:38ccae254a29 186
mega64 0:38ccae254a29 187
mega64 0:38ccae254a29 188 /** \brief Set Priority Mask
mega64 0:38ccae254a29 189
mega64 0:38ccae254a29 190 This function assigns the given value to the Priority Mask Register.
mega64 0:38ccae254a29 191
mega64 0:38ccae254a29 192 \param [in] priMask Priority Mask
mega64 0:38ccae254a29 193 */
mega64 0:38ccae254a29 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
mega64 0:38ccae254a29 195 {
mega64 0:38ccae254a29 196 register uint32_t __regPriMask __ASM("primask");
mega64 0:38ccae254a29 197 __regPriMask = (priMask);
mega64 0:38ccae254a29 198 }
mega64 0:38ccae254a29 199
mega64 0:38ccae254a29 200
mega64 0:38ccae254a29 201 #if (__CORTEX_M >= 0x03)
mega64 0:38ccae254a29 202
mega64 0:38ccae254a29 203 /** \brief Enable FIQ
mega64 0:38ccae254a29 204
mega64 0:38ccae254a29 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
mega64 0:38ccae254a29 206 Can only be executed in Privileged modes.
mega64 0:38ccae254a29 207 */
mega64 0:38ccae254a29 208 #define __enable_fault_irq __enable_fiq
mega64 0:38ccae254a29 209
mega64 0:38ccae254a29 210
mega64 0:38ccae254a29 211 /** \brief Disable FIQ
mega64 0:38ccae254a29 212
mega64 0:38ccae254a29 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
mega64 0:38ccae254a29 214 Can only be executed in Privileged modes.
mega64 0:38ccae254a29 215 */
mega64 0:38ccae254a29 216 #define __disable_fault_irq __disable_fiq
mega64 0:38ccae254a29 217
mega64 0:38ccae254a29 218
mega64 0:38ccae254a29 219 /** \brief Get Base Priority
mega64 0:38ccae254a29 220
mega64 0:38ccae254a29 221 This function returns the current value of the Base Priority register.
mega64 0:38ccae254a29 222
mega64 0:38ccae254a29 223 \return Base Priority register value
mega64 0:38ccae254a29 224 */
mega64 0:38ccae254a29 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
mega64 0:38ccae254a29 226 {
mega64 0:38ccae254a29 227 register uint32_t __regBasePri __ASM("basepri");
mega64 0:38ccae254a29 228 return(__regBasePri);
mega64 0:38ccae254a29 229 }
mega64 0:38ccae254a29 230
mega64 0:38ccae254a29 231
mega64 0:38ccae254a29 232 /** \brief Set Base Priority
mega64 0:38ccae254a29 233
mega64 0:38ccae254a29 234 This function assigns the given value to the Base Priority register.
mega64 0:38ccae254a29 235
mega64 0:38ccae254a29 236 \param [in] basePri Base Priority value to set
mega64 0:38ccae254a29 237 */
mega64 0:38ccae254a29 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
mega64 0:38ccae254a29 239 {
mega64 0:38ccae254a29 240 register uint32_t __regBasePri __ASM("basepri");
mega64 0:38ccae254a29 241 __regBasePri = (basePri & 0xff);
mega64 0:38ccae254a29 242 }
mega64 0:38ccae254a29 243
mega64 0:38ccae254a29 244
mega64 0:38ccae254a29 245 /** \brief Get Fault Mask
mega64 0:38ccae254a29 246
mega64 0:38ccae254a29 247 This function returns the current value of the Fault Mask register.
mega64 0:38ccae254a29 248
mega64 0:38ccae254a29 249 \return Fault Mask register value
mega64 0:38ccae254a29 250 */
mega64 0:38ccae254a29 251 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
mega64 0:38ccae254a29 252 {
mega64 0:38ccae254a29 253 register uint32_t __regFaultMask __ASM("faultmask");
mega64 0:38ccae254a29 254 return(__regFaultMask);
mega64 0:38ccae254a29 255 }
mega64 0:38ccae254a29 256
mega64 0:38ccae254a29 257
mega64 0:38ccae254a29 258 /** \brief Set Fault Mask
mega64 0:38ccae254a29 259
mega64 0:38ccae254a29 260 This function assigns the given value to the Fault Mask register.
mega64 0:38ccae254a29 261
mega64 0:38ccae254a29 262 \param [in] faultMask Fault Mask value to set
mega64 0:38ccae254a29 263 */
mega64 0:38ccae254a29 264 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
mega64 0:38ccae254a29 265 {
mega64 0:38ccae254a29 266 register uint32_t __regFaultMask __ASM("faultmask");
mega64 0:38ccae254a29 267 __regFaultMask = (faultMask & (uint32_t)1);
mega64 0:38ccae254a29 268 }
mega64 0:38ccae254a29 269
mega64 0:38ccae254a29 270 #endif /* (__CORTEX_M >= 0x03) */
mega64 0:38ccae254a29 271
mega64 0:38ccae254a29 272
mega64 0:38ccae254a29 273 #if (__CORTEX_M == 0x04)
mega64 0:38ccae254a29 274
mega64 0:38ccae254a29 275 /** \brief Get FPSCR
mega64 0:38ccae254a29 276
mega64 0:38ccae254a29 277 This function returns the current value of the Floating Point Status/Control register.
mega64 0:38ccae254a29 278
mega64 0:38ccae254a29 279 \return Floating Point Status/Control register value
mega64 0:38ccae254a29 280 */
mega64 0:38ccae254a29 281 __STATIC_INLINE uint32_t __get_FPSCR(void)
mega64 0:38ccae254a29 282 {
mega64 0:38ccae254a29 283 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mega64 0:38ccae254a29 284 register uint32_t __regfpscr __ASM("fpscr");
mega64 0:38ccae254a29 285 return(__regfpscr);
mega64 0:38ccae254a29 286 #else
mega64 0:38ccae254a29 287 return(0);
mega64 0:38ccae254a29 288 #endif
mega64 0:38ccae254a29 289 }
mega64 0:38ccae254a29 290
mega64 0:38ccae254a29 291
mega64 0:38ccae254a29 292 /** \brief Set FPSCR
mega64 0:38ccae254a29 293
mega64 0:38ccae254a29 294 This function assigns the given value to the Floating Point Status/Control register.
mega64 0:38ccae254a29 295
mega64 0:38ccae254a29 296 \param [in] fpscr Floating Point Status/Control value to set
mega64 0:38ccae254a29 297 */
mega64 0:38ccae254a29 298 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
mega64 0:38ccae254a29 299 {
mega64 0:38ccae254a29 300 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mega64 0:38ccae254a29 301 register uint32_t __regfpscr __ASM("fpscr");
mega64 0:38ccae254a29 302 __regfpscr = (fpscr);
mega64 0:38ccae254a29 303 #endif
mega64 0:38ccae254a29 304 }
mega64 0:38ccae254a29 305
mega64 0:38ccae254a29 306 #endif /* (__CORTEX_M == 0x04) */
mega64 0:38ccae254a29 307
mega64 0:38ccae254a29 308
mega64 0:38ccae254a29 309 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
mega64 0:38ccae254a29 310 /* IAR iccarm specific functions */
mega64 0:38ccae254a29 311
mega64 0:38ccae254a29 312 #include <cmsis_iar.h>
mega64 0:38ccae254a29 313
mega64 0:38ccae254a29 314
mega64 0:38ccae254a29 315 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
mega64 0:38ccae254a29 316 /* TI CCS specific functions */
mega64 0:38ccae254a29 317
mega64 0:38ccae254a29 318 #include <cmsis_ccs.h>
mega64 0:38ccae254a29 319
mega64 0:38ccae254a29 320
mega64 0:38ccae254a29 321 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
mega64 0:38ccae254a29 322 /* GNU gcc specific functions */
mega64 0:38ccae254a29 323
mega64 0:38ccae254a29 324 /** \brief Enable IRQ Interrupts
mega64 0:38ccae254a29 325
mega64 0:38ccae254a29 326 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
mega64 0:38ccae254a29 327 Can only be executed in Privileged modes.
mega64 0:38ccae254a29 328 */
mega64 0:38ccae254a29 329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
mega64 0:38ccae254a29 330 {
mega64 0:38ccae254a29 331 __ASM volatile ("cpsie i" : : : "memory");
mega64 0:38ccae254a29 332 }
mega64 0:38ccae254a29 333
mega64 0:38ccae254a29 334
mega64 0:38ccae254a29 335 /** \brief Disable IRQ Interrupts
mega64 0:38ccae254a29 336
mega64 0:38ccae254a29 337 This function disables IRQ interrupts by setting the I-bit in the CPSR.
mega64 0:38ccae254a29 338 Can only be executed in Privileged modes.
mega64 0:38ccae254a29 339 */
mega64 0:38ccae254a29 340 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
mega64 0:38ccae254a29 341 {
mega64 0:38ccae254a29 342 __ASM volatile ("cpsid i" : : : "memory");
mega64 0:38ccae254a29 343 }
mega64 0:38ccae254a29 344
mega64 0:38ccae254a29 345
mega64 0:38ccae254a29 346 /** \brief Get Control Register
mega64 0:38ccae254a29 347
mega64 0:38ccae254a29 348 This function returns the content of the Control Register.
mega64 0:38ccae254a29 349
mega64 0:38ccae254a29 350 \return Control Register value
mega64 0:38ccae254a29 351 */
mega64 0:38ccae254a29 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
mega64 0:38ccae254a29 353 {
mega64 0:38ccae254a29 354 uint32_t result;
mega64 0:38ccae254a29 355
mega64 0:38ccae254a29 356 __ASM volatile ("MRS %0, control" : "=r" (result) );
mega64 0:38ccae254a29 357 return(result);
mega64 0:38ccae254a29 358 }
mega64 0:38ccae254a29 359
mega64 0:38ccae254a29 360
mega64 0:38ccae254a29 361 /** \brief Set Control Register
mega64 0:38ccae254a29 362
mega64 0:38ccae254a29 363 This function writes the given value to the Control Register.
mega64 0:38ccae254a29 364
mega64 0:38ccae254a29 365 \param [in] control Control Register value to set
mega64 0:38ccae254a29 366 */
mega64 0:38ccae254a29 367 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
mega64 0:38ccae254a29 368 {
mega64 0:38ccae254a29 369 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
mega64 0:38ccae254a29 370 }
mega64 0:38ccae254a29 371
mega64 0:38ccae254a29 372
mega64 0:38ccae254a29 373 /** \brief Get IPSR Register
mega64 0:38ccae254a29 374
mega64 0:38ccae254a29 375 This function returns the content of the IPSR Register.
mega64 0:38ccae254a29 376
mega64 0:38ccae254a29 377 \return IPSR Register value
mega64 0:38ccae254a29 378 */
mega64 0:38ccae254a29 379 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
mega64 0:38ccae254a29 380 {
mega64 0:38ccae254a29 381 uint32_t result;
mega64 0:38ccae254a29 382
mega64 0:38ccae254a29 383 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
mega64 0:38ccae254a29 384 return(result);
mega64 0:38ccae254a29 385 }
mega64 0:38ccae254a29 386
mega64 0:38ccae254a29 387
mega64 0:38ccae254a29 388 /** \brief Get APSR Register
mega64 0:38ccae254a29 389
mega64 0:38ccae254a29 390 This function returns the content of the APSR Register.
mega64 0:38ccae254a29 391
mega64 0:38ccae254a29 392 \return APSR Register value
mega64 0:38ccae254a29 393 */
mega64 0:38ccae254a29 394 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
mega64 0:38ccae254a29 395 {
mega64 0:38ccae254a29 396 uint32_t result;
mega64 0:38ccae254a29 397
mega64 0:38ccae254a29 398 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
mega64 0:38ccae254a29 399 return(result);
mega64 0:38ccae254a29 400 }
mega64 0:38ccae254a29 401
mega64 0:38ccae254a29 402
mega64 0:38ccae254a29 403 /** \brief Get xPSR Register
mega64 0:38ccae254a29 404
mega64 0:38ccae254a29 405 This function returns the content of the xPSR Register.
mega64 0:38ccae254a29 406
mega64 0:38ccae254a29 407 \return xPSR Register value
mega64 0:38ccae254a29 408 */
mega64 0:38ccae254a29 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
mega64 0:38ccae254a29 410 {
mega64 0:38ccae254a29 411 uint32_t result;
mega64 0:38ccae254a29 412
mega64 0:38ccae254a29 413 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
mega64 0:38ccae254a29 414 return(result);
mega64 0:38ccae254a29 415 }
mega64 0:38ccae254a29 416
mega64 0:38ccae254a29 417
mega64 0:38ccae254a29 418 /** \brief Get Process Stack Pointer
mega64 0:38ccae254a29 419
mega64 0:38ccae254a29 420 This function returns the current value of the Process Stack Pointer (PSP).
mega64 0:38ccae254a29 421
mega64 0:38ccae254a29 422 \return PSP Register value
mega64 0:38ccae254a29 423 */
mega64 0:38ccae254a29 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
mega64 0:38ccae254a29 425 {
mega64 0:38ccae254a29 426 register uint32_t result;
mega64 0:38ccae254a29 427
mega64 0:38ccae254a29 428 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
mega64 0:38ccae254a29 429 return(result);
mega64 0:38ccae254a29 430 }
mega64 0:38ccae254a29 431
mega64 0:38ccae254a29 432
mega64 0:38ccae254a29 433 /** \brief Set Process Stack Pointer
mega64 0:38ccae254a29 434
mega64 0:38ccae254a29 435 This function assigns the given value to the Process Stack Pointer (PSP).
mega64 0:38ccae254a29 436
mega64 0:38ccae254a29 437 \param [in] topOfProcStack Process Stack Pointer value to set
mega64 0:38ccae254a29 438 */
mega64 0:38ccae254a29 439 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
mega64 0:38ccae254a29 440 {
mega64 0:38ccae254a29 441 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
mega64 0:38ccae254a29 442 }
mega64 0:38ccae254a29 443
mega64 0:38ccae254a29 444
mega64 0:38ccae254a29 445 /** \brief Get Main Stack Pointer
mega64 0:38ccae254a29 446
mega64 0:38ccae254a29 447 This function returns the current value of the Main Stack Pointer (MSP).
mega64 0:38ccae254a29 448
mega64 0:38ccae254a29 449 \return MSP Register value
mega64 0:38ccae254a29 450 */
mega64 0:38ccae254a29 451 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
mega64 0:38ccae254a29 452 {
mega64 0:38ccae254a29 453 register uint32_t result;
mega64 0:38ccae254a29 454
mega64 0:38ccae254a29 455 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
mega64 0:38ccae254a29 456 return(result);
mega64 0:38ccae254a29 457 }
mega64 0:38ccae254a29 458
mega64 0:38ccae254a29 459
mega64 0:38ccae254a29 460 /** \brief Set Main Stack Pointer
mega64 0:38ccae254a29 461
mega64 0:38ccae254a29 462 This function assigns the given value to the Main Stack Pointer (MSP).
mega64 0:38ccae254a29 463
mega64 0:38ccae254a29 464 \param [in] topOfMainStack Main Stack Pointer value to set
mega64 0:38ccae254a29 465 */
mega64 0:38ccae254a29 466 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
mega64 0:38ccae254a29 467 {
mega64 0:38ccae254a29 468 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
mega64 0:38ccae254a29 469 }
mega64 0:38ccae254a29 470
mega64 0:38ccae254a29 471
mega64 0:38ccae254a29 472 /** \brief Get Priority Mask
mega64 0:38ccae254a29 473
mega64 0:38ccae254a29 474 This function returns the current state of the priority mask bit from the Priority Mask Register.
mega64 0:38ccae254a29 475
mega64 0:38ccae254a29 476 \return Priority Mask value
mega64 0:38ccae254a29 477 */
mega64 0:38ccae254a29 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
mega64 0:38ccae254a29 479 {
mega64 0:38ccae254a29 480 uint32_t result;
mega64 0:38ccae254a29 481
mega64 0:38ccae254a29 482 __ASM volatile ("MRS %0, primask" : "=r" (result) );
mega64 0:38ccae254a29 483 return(result);
mega64 0:38ccae254a29 484 }
mega64 0:38ccae254a29 485
mega64 0:38ccae254a29 486
mega64 0:38ccae254a29 487 /** \brief Set Priority Mask
mega64 0:38ccae254a29 488
mega64 0:38ccae254a29 489 This function assigns the given value to the Priority Mask Register.
mega64 0:38ccae254a29 490
mega64 0:38ccae254a29 491 \param [in] priMask Priority Mask
mega64 0:38ccae254a29 492 */
mega64 0:38ccae254a29 493 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
mega64 0:38ccae254a29 494 {
mega64 0:38ccae254a29 495 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
mega64 0:38ccae254a29 496 }
mega64 0:38ccae254a29 497
mega64 0:38ccae254a29 498
mega64 0:38ccae254a29 499 #if (__CORTEX_M >= 0x03)
mega64 0:38ccae254a29 500
mega64 0:38ccae254a29 501 /** \brief Enable FIQ
mega64 0:38ccae254a29 502
mega64 0:38ccae254a29 503 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
mega64 0:38ccae254a29 504 Can only be executed in Privileged modes.
mega64 0:38ccae254a29 505 */
mega64 0:38ccae254a29 506 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
mega64 0:38ccae254a29 507 {
mega64 0:38ccae254a29 508 __ASM volatile ("cpsie f" : : : "memory");
mega64 0:38ccae254a29 509 }
mega64 0:38ccae254a29 510
mega64 0:38ccae254a29 511
mega64 0:38ccae254a29 512 /** \brief Disable FIQ
mega64 0:38ccae254a29 513
mega64 0:38ccae254a29 514 This function disables FIQ interrupts by setting the F-bit in the CPSR.
mega64 0:38ccae254a29 515 Can only be executed in Privileged modes.
mega64 0:38ccae254a29 516 */
mega64 0:38ccae254a29 517 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
mega64 0:38ccae254a29 518 {
mega64 0:38ccae254a29 519 __ASM volatile ("cpsid f" : : : "memory");
mega64 0:38ccae254a29 520 }
mega64 0:38ccae254a29 521
mega64 0:38ccae254a29 522
mega64 0:38ccae254a29 523 /** \brief Get Base Priority
mega64 0:38ccae254a29 524
mega64 0:38ccae254a29 525 This function returns the current value of the Base Priority register.
mega64 0:38ccae254a29 526
mega64 0:38ccae254a29 527 \return Base Priority register value
mega64 0:38ccae254a29 528 */
mega64 0:38ccae254a29 529 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
mega64 0:38ccae254a29 530 {
mega64 0:38ccae254a29 531 uint32_t result;
mega64 0:38ccae254a29 532
mega64 0:38ccae254a29 533 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
mega64 0:38ccae254a29 534 return(result);
mega64 0:38ccae254a29 535 }
mega64 0:38ccae254a29 536
mega64 0:38ccae254a29 537
mega64 0:38ccae254a29 538 /** \brief Set Base Priority
mega64 0:38ccae254a29 539
mega64 0:38ccae254a29 540 This function assigns the given value to the Base Priority register.
mega64 0:38ccae254a29 541
mega64 0:38ccae254a29 542 \param [in] basePri Base Priority value to set
mega64 0:38ccae254a29 543 */
mega64 0:38ccae254a29 544 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
mega64 0:38ccae254a29 545 {
mega64 0:38ccae254a29 546 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
mega64 0:38ccae254a29 547 }
mega64 0:38ccae254a29 548
mega64 0:38ccae254a29 549
mega64 0:38ccae254a29 550 /** \brief Get Fault Mask
mega64 0:38ccae254a29 551
mega64 0:38ccae254a29 552 This function returns the current value of the Fault Mask register.
mega64 0:38ccae254a29 553
mega64 0:38ccae254a29 554 \return Fault Mask register value
mega64 0:38ccae254a29 555 */
mega64 0:38ccae254a29 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
mega64 0:38ccae254a29 557 {
mega64 0:38ccae254a29 558 uint32_t result;
mega64 0:38ccae254a29 559
mega64 0:38ccae254a29 560 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
mega64 0:38ccae254a29 561 return(result);
mega64 0:38ccae254a29 562 }
mega64 0:38ccae254a29 563
mega64 0:38ccae254a29 564
mega64 0:38ccae254a29 565 /** \brief Set Fault Mask
mega64 0:38ccae254a29 566
mega64 0:38ccae254a29 567 This function assigns the given value to the Fault Mask register.
mega64 0:38ccae254a29 568
mega64 0:38ccae254a29 569 \param [in] faultMask Fault Mask value to set
mega64 0:38ccae254a29 570 */
mega64 0:38ccae254a29 571 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
mega64 0:38ccae254a29 572 {
mega64 0:38ccae254a29 573 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
mega64 0:38ccae254a29 574 }
mega64 0:38ccae254a29 575
mega64 0:38ccae254a29 576 #endif /* (__CORTEX_M >= 0x03) */
mega64 0:38ccae254a29 577
mega64 0:38ccae254a29 578
mega64 0:38ccae254a29 579 #if (__CORTEX_M == 0x04)
mega64 0:38ccae254a29 580
mega64 0:38ccae254a29 581 /** \brief Get FPSCR
mega64 0:38ccae254a29 582
mega64 0:38ccae254a29 583 This function returns the current value of the Floating Point Status/Control register.
mega64 0:38ccae254a29 584
mega64 0:38ccae254a29 585 \return Floating Point Status/Control register value
mega64 0:38ccae254a29 586 */
mega64 0:38ccae254a29 587 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
mega64 0:38ccae254a29 588 {
mega64 0:38ccae254a29 589 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mega64 0:38ccae254a29 590 uint32_t result;
mega64 0:38ccae254a29 591
mega64 0:38ccae254a29 592 /* Empty asm statement works as a scheduling barrier */
mega64 0:38ccae254a29 593 __ASM volatile ("");
mega64 0:38ccae254a29 594 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
mega64 0:38ccae254a29 595 __ASM volatile ("");
mega64 0:38ccae254a29 596 return(result);
mega64 0:38ccae254a29 597 #else
mega64 0:38ccae254a29 598 return(0);
mega64 0:38ccae254a29 599 #endif
mega64 0:38ccae254a29 600 }
mega64 0:38ccae254a29 601
mega64 0:38ccae254a29 602
mega64 0:38ccae254a29 603 /** \brief Set FPSCR
mega64 0:38ccae254a29 604
mega64 0:38ccae254a29 605 This function assigns the given value to the Floating Point Status/Control register.
mega64 0:38ccae254a29 606
mega64 0:38ccae254a29 607 \param [in] fpscr Floating Point Status/Control value to set
mega64 0:38ccae254a29 608 */
mega64 0:38ccae254a29 609 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
mega64 0:38ccae254a29 610 {
mega64 0:38ccae254a29 611 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mega64 0:38ccae254a29 612 /* Empty asm statement works as a scheduling barrier */
mega64 0:38ccae254a29 613 __ASM volatile ("");
mega64 0:38ccae254a29 614 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
mega64 0:38ccae254a29 615 __ASM volatile ("");
mega64 0:38ccae254a29 616 #endif
mega64 0:38ccae254a29 617 }
mega64 0:38ccae254a29 618
mega64 0:38ccae254a29 619 #endif /* (__CORTEX_M == 0x04) */
mega64 0:38ccae254a29 620
mega64 0:38ccae254a29 621
mega64 0:38ccae254a29 622 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
mega64 0:38ccae254a29 623 /* TASKING carm specific functions */
mega64 0:38ccae254a29 624
mega64 0:38ccae254a29 625 /*
mega64 0:38ccae254a29 626 * The CMSIS functions have been implemented as intrinsics in the compiler.
mega64 0:38ccae254a29 627 * Please use "carm -?i" to get an up to date list of all instrinsics,
mega64 0:38ccae254a29 628 * Including the CMSIS ones.
mega64 0:38ccae254a29 629 */
mega64 0:38ccae254a29 630
mega64 0:38ccae254a29 631 #endif
mega64 0:38ccae254a29 632
mega64 0:38ccae254a29 633 /*@} end of CMSIS_Core_RegAccFunctions */
mega64 0:38ccae254a29 634
mega64 0:38ccae254a29 635
mega64 0:38ccae254a29 636 #endif /* __CORE_CMFUNC_H */