Steven Osborn / SX1276GenericLib

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sx1276/sx1276-hal.cpp@21:2e496deb7858, 2015-11-26 (annotated)

Committer:
mluis
Date:
Thu Nov 26 10:39:03 2015 +0000
Revision:
21:2e496deb7858
Parent:
20:e05596ba4166
Child:
22:7f3aab69cca9
Made radio driver API compatible with GitHub radio driver

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
GregCr 8:0fe3e0e8007b 7 ( C )2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: -
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276-hal.h"
GregCr 0:e6ceb13d2d05 16
GregCr 0:e6ceb13d2d05 17 const RadioRegisters_t SX1276MB1xAS::RadioRegsInit[] =
GregCr 0:e6ceb13d2d05 18 {
GregCr 0:e6ceb13d2d05 19 { MODEM_FSK , REG_LNA , 0x23 },
GregCr 0:e6ceb13d2d05 20 { MODEM_FSK , REG_RXCONFIG , 0x1E },
GregCr 0:e6ceb13d2d05 21 { MODEM_FSK , REG_RSSICONFIG , 0xD2 },
GregCr 0:e6ceb13d2d05 22 { MODEM_FSK , REG_PREAMBLEDETECT , 0xAA },
GregCr 0:e6ceb13d2d05 23 { MODEM_FSK , REG_OSC , 0x07 },
GregCr 0:e6ceb13d2d05 24 { MODEM_FSK , REG_SYNCCONFIG , 0x12 },
GregCr 0:e6ceb13d2d05 25 { MODEM_FSK , REG_SYNCVALUE1 , 0xC1 },
GregCr 0:e6ceb13d2d05 26 { MODEM_FSK , REG_SYNCVALUE2 , 0x94 },
GregCr 0:e6ceb13d2d05 27 { MODEM_FSK , REG_SYNCVALUE3 , 0xC1 },
mluis 15:04374b1c33fa 28 { MODEM_FSK , REG_PACKETCONFIG1 , 0xD8 },
GregCr 0:e6ceb13d2d05 29 { MODEM_FSK , REG_FIFOTHRESH , 0x8F },
GregCr 0:e6ceb13d2d05 30 { MODEM_FSK , REG_IMAGECAL , 0x02 },
GregCr 0:e6ceb13d2d05 31 { MODEM_FSK , REG_DIOMAPPING1 , 0x00 },
GregCr 0:e6ceb13d2d05 32 { MODEM_FSK , REG_DIOMAPPING2 , 0x30 },
GregCr 0:e6ceb13d2d05 33 { MODEM_LORA, REG_LR_PAYLOADMAXLENGTH, 0x40 },
GregCr 0:e6ceb13d2d05 34 };
GregCr 0:e6ceb13d2d05 35
mluis 21:2e496deb7858 36 SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events,
GregCr 0:e6ceb13d2d05 37 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
GregCr 0:e6ceb13d2d05 38 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5,
GregCr 0:e6ceb13d2d05 39 PinName antSwitch )
mluis 21:2e496deb7858 40 : SX1276( events, mosi, miso, sclk, nss, reset, dio0, dio1, dio2, dio3, dio4, dio5 ),
GregCr 0:e6ceb13d2d05 41 antSwitch( antSwitch ),
GregCr 12:aa5b3bf7fdf4 42 #if( defined ( TARGET_NUCLEO_L152RE ) )
GregCr 12:aa5b3bf7fdf4 43 fake( D8 )
GregCr 12:aa5b3bf7fdf4 44 #else
GregCr 0:e6ceb13d2d05 45 fake( A3 )
GregCr 0:e6ceb13d2d05 46 #endif
GregCr 0:e6ceb13d2d05 47 {
mluis 21:2e496deb7858 48 this->RadioEvents = events;
mluis 21:2e496deb7858 49
GregCr 0:e6ceb13d2d05 50 Reset( );
GregCr 0:e6ceb13d2d05 51
GregCr 0:e6ceb13d2d05 52 RxChainCalibration( );
GregCr 0:e6ceb13d2d05 53
GregCr 0:e6ceb13d2d05 54 IoInit( );
GregCr 0:e6ceb13d2d05 55
GregCr 0:e6ceb13d2d05 56 SetOpMode( RF_OPMODE_SLEEP );
GregCr 0:e6ceb13d2d05 57
GregCr 0:e6ceb13d2d05 58 IoIrqInit( dioIrq );
GregCr 0:e6ceb13d2d05 59
GregCr 0:e6ceb13d2d05 60 RadioRegistersInit( );
GregCr 0:e6ceb13d2d05 61
GregCr 0:e6ceb13d2d05 62 SetModem( MODEM_FSK );
GregCr 0:e6ceb13d2d05 63
mluis 21:2e496deb7858 64 this->settings.State = RF_IDLE ;
GregCr 0:e6ceb13d2d05 65 }
GregCr 0:e6ceb13d2d05 66
mluis 21:2e496deb7858 67 SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events )
GregCr 12:aa5b3bf7fdf4 68 #if defined ( TARGET_NUCLEO_L152RE )
mluis 21:2e496deb7858 69 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, A3, D9 ), // For NUCLEO L152RE dio4 is on port A3
GregCr 0:e6ceb13d2d05 70 antSwitch( A4 ),
GregCr 0:e6ceb13d2d05 71 fake( D8 )
mluis 20:e05596ba4166 72 #elif defined( TARGET_LPC11U6X )
mluis 21:2e496deb7858 73 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
mluis 20:e05596ba4166 74 antSwitch( P0_23 ),
mluis 20:e05596ba4166 75 fake( A3 )
GregCr 0:e6ceb13d2d05 76 #else
mluis 21:2e496deb7858 77 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
GregCr 12:aa5b3bf7fdf4 78 antSwitch( A4 ),
GregCr 12:aa5b3bf7fdf4 79 fake( A3 )
GregCr 0:e6ceb13d2d05 80 #endif
GregCr 0:e6ceb13d2d05 81 {
mluis 21:2e496deb7858 82 this->RadioEvents = events;
mluis 21:2e496deb7858 83
GregCr 0:e6ceb13d2d05 84 Reset( );
GregCr 0:e6ceb13d2d05 85
GregCr 5:11ec8a6ba4f0 86 boardConnected = UNKNOWN;
GregCr 5:11ec8a6ba4f0 87
GregCr 1:f979673946c0 88 DetectBoardType( );
GregCr 1:f979673946c0 89
GregCr 0:e6ceb13d2d05 90 RxChainCalibration( );
GregCr 0:e6ceb13d2d05 91
GregCr 0:e6ceb13d2d05 92 IoInit( );
GregCr 0:e6ceb13d2d05 93
GregCr 0:e6ceb13d2d05 94 SetOpMode( RF_OPMODE_SLEEP );
GregCr 0:e6ceb13d2d05 95 IoIrqInit( dioIrq );
GregCr 0:e6ceb13d2d05 96
GregCr 0:e6ceb13d2d05 97 RadioRegistersInit( );
GregCr 0:e6ceb13d2d05 98
GregCr 0:e6ceb13d2d05 99 SetModem( MODEM_FSK );
GregCr 0:e6ceb13d2d05 100
mluis 21:2e496deb7858 101 this->settings.State = RF_IDLE ;
GregCr 0:e6ceb13d2d05 102 }
GregCr 0:e6ceb13d2d05 103
GregCr 0:e6ceb13d2d05 104 //-------------------------------------------------------------------------
GregCr 0:e6ceb13d2d05 105 // Board relative functions
GregCr 0:e6ceb13d2d05 106 //-------------------------------------------------------------------------
GregCr 2:5eb3066446dd 107 uint8_t SX1276MB1xAS::DetectBoardType( void )
GregCr 1:f979673946c0 108 {
GregCr 5:11ec8a6ba4f0 109 if( boardConnected == UNKNOWN )
GregCr 1:f979673946c0 110 {
GregCr 5:11ec8a6ba4f0 111 antSwitch.input( );
GregCr 5:11ec8a6ba4f0 112 wait_ms( 1 );
GregCr 5:11ec8a6ba4f0 113 if( antSwitch == 1 )
GregCr 5:11ec8a6ba4f0 114 {
GregCr 5:11ec8a6ba4f0 115 boardConnected = SX1276MB1LAS;
GregCr 5:11ec8a6ba4f0 116 }
GregCr 5:11ec8a6ba4f0 117 else
GregCr 5:11ec8a6ba4f0 118 {
GregCr 5:11ec8a6ba4f0 119 boardConnected = SX1276MB1MAS;
GregCr 5:11ec8a6ba4f0 120 }
GregCr 5:11ec8a6ba4f0 121 antSwitch.output( );
GregCr 5:11ec8a6ba4f0 122 wait_ms( 1 );
GregCr 1:f979673946c0 123 }
GregCr 2:5eb3066446dd 124 return ( boardConnected );
GregCr 1:f979673946c0 125 }
GregCr 0:e6ceb13d2d05 126
GregCr 0:e6ceb13d2d05 127 void SX1276MB1xAS::IoInit( void )
GregCr 0:e6ceb13d2d05 128 {
GregCr 0:e6ceb13d2d05 129 AntSwInit( );
GregCr 0:e6ceb13d2d05 130 SpiInit( );
GregCr 0:e6ceb13d2d05 131 }
GregCr 0:e6ceb13d2d05 132
GregCr 0:e6ceb13d2d05 133 void SX1276MB1xAS::RadioRegistersInit( ){
GregCr 0:e6ceb13d2d05 134 uint8_t i = 0;
GregCr 0:e6ceb13d2d05 135 for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
GregCr 0:e6ceb13d2d05 136 {
GregCr 0:e6ceb13d2d05 137 SetModem( RadioRegsInit[i].Modem );
GregCr 0:e6ceb13d2d05 138 Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
GregCr 0:e6ceb13d2d05 139 }
GregCr 0:e6ceb13d2d05 140 }
GregCr 0:e6ceb13d2d05 141
GregCr 0:e6ceb13d2d05 142 void SX1276MB1xAS::SpiInit( void )
GregCr 0:e6ceb13d2d05 143 {
GregCr 0:e6ceb13d2d05 144 nss = 1;
GregCr 0:e6ceb13d2d05 145 spi.format( 8,0 );
GregCr 0:e6ceb13d2d05 146 uint32_t frequencyToSet = 8000000;
GregCr 0:e6ceb13d2d05 147 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) )
GregCr 0:e6ceb13d2d05 148 spi.frequency( frequencyToSet );
GregCr 0:e6ceb13d2d05 149 #elif( defined ( TARGET_KL25Z ) ) //busclock frequency is halved -> double the spi frequency to compensate
GregCr 0:e6ceb13d2d05 150 spi.frequency( frequencyToSet * 2 );
GregCr 0:e6ceb13d2d05 151 #else
GregCr 0:e6ceb13d2d05 152 #warning "Check the board's SPI frequency"
GregCr 0:e6ceb13d2d05 153 #endif
GregCr 0:e6ceb13d2d05 154 wait(0.1);
GregCr 0:e6ceb13d2d05 155 }
GregCr 0:e6ceb13d2d05 156
GregCr 0:e6ceb13d2d05 157 void SX1276MB1xAS::IoIrqInit( DioIrqHandler *irqHandlers )
GregCr 0:e6ceb13d2d05 158 {
GregCr 0:e6ceb13d2d05 159 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) )
GregCr 0:e6ceb13d2d05 160 dio0.mode(PullDown);
GregCr 0:e6ceb13d2d05 161 dio1.mode(PullDown);
GregCr 0:e6ceb13d2d05 162 dio2.mode(PullDown);
GregCr 0:e6ceb13d2d05 163 dio3.mode(PullDown);
GregCr 0:e6ceb13d2d05 164 dio4.mode(PullDown);
GregCr 0:e6ceb13d2d05 165 #endif
GregCr 0:e6ceb13d2d05 166 dio0.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[0] ) );
GregCr 0:e6ceb13d2d05 167 dio1.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[1] ) );
GregCr 0:e6ceb13d2d05 168 dio2.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[2] ) );
GregCr 0:e6ceb13d2d05 169 dio3.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[3] ) );
GregCr 0:e6ceb13d2d05 170 dio4.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[4] ) );
GregCr 0:e6ceb13d2d05 171 }
GregCr 0:e6ceb13d2d05 172
GregCr 0:e6ceb13d2d05 173 void SX1276MB1xAS::IoDeInit( void )
GregCr 0:e6ceb13d2d05 174 {
GregCr 0:e6ceb13d2d05 175 //nothing
GregCr 0:e6ceb13d2d05 176 }
GregCr 0:e6ceb13d2d05 177
GregCr 0:e6ceb13d2d05 178 uint8_t SX1276MB1xAS::GetPaSelect( uint32_t channel )
GregCr 0:e6ceb13d2d05 179 {
GregCr 0:e6ceb13d2d05 180 if( channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 181 {
GregCr 3:ca84be1f3fac 182 if( boardConnected == SX1276MB1LAS )
GregCr 1:f979673946c0 183 {
GregCr 1:f979673946c0 184 return RF_PACONFIG_PASELECT_PABOOST;
GregCr 1:f979673946c0 185 }
GregCr 1:f979673946c0 186 else
GregCr 1:f979673946c0 187 {
GregCr 1:f979673946c0 188 return RF_PACONFIG_PASELECT_RFO;
GregCr 1:f979673946c0 189 }
GregCr 0:e6ceb13d2d05 190 }
GregCr 0:e6ceb13d2d05 191 else
GregCr 0:e6ceb13d2d05 192 {
GregCr 0:e6ceb13d2d05 193 return RF_PACONFIG_PASELECT_RFO;
GregCr 0:e6ceb13d2d05 194 }
GregCr 0:e6ceb13d2d05 195 }
GregCr 0:e6ceb13d2d05 196
GregCr 0:e6ceb13d2d05 197 void SX1276MB1xAS::SetAntSwLowPower( bool status )
GregCr 0:e6ceb13d2d05 198 {
GregCr 0:e6ceb13d2d05 199 if( isRadioActive != status )
GregCr 0:e6ceb13d2d05 200 {
GregCr 0:e6ceb13d2d05 201 isRadioActive = status;
GregCr 0:e6ceb13d2d05 202
GregCr 0:e6ceb13d2d05 203 if( status == false )
GregCr 0:e6ceb13d2d05 204 {
GregCr 0:e6ceb13d2d05 205 AntSwInit( );
GregCr 0:e6ceb13d2d05 206 }
GregCr 0:e6ceb13d2d05 207 else
GregCr 0:e6ceb13d2d05 208 {
GregCr 0:e6ceb13d2d05 209 AntSwDeInit( );
GregCr 0:e6ceb13d2d05 210 }
GregCr 0:e6ceb13d2d05 211 }
GregCr 0:e6ceb13d2d05 212 }
GregCr 0:e6ceb13d2d05 213
GregCr 0:e6ceb13d2d05 214 void SX1276MB1xAS::AntSwInit( void )
GregCr 0:e6ceb13d2d05 215 {
GregCr 0:e6ceb13d2d05 216 antSwitch = 0;
GregCr 0:e6ceb13d2d05 217 }
GregCr 0:e6ceb13d2d05 218
GregCr 0:e6ceb13d2d05 219 void SX1276MB1xAS::AntSwDeInit( void )
GregCr 0:e6ceb13d2d05 220 {
GregCr 0:e6ceb13d2d05 221 antSwitch = 0;
GregCr 0:e6ceb13d2d05 222 }
GregCr 0:e6ceb13d2d05 223
GregCr 0:e6ceb13d2d05 224 void SX1276MB1xAS::SetAntSw( uint8_t rxTx )
GregCr 0:e6ceb13d2d05 225 {
GregCr 0:e6ceb13d2d05 226 if( this->rxTx == rxTx )
GregCr 0:e6ceb13d2d05 227 {
GregCr 0:e6ceb13d2d05 228 //no need to go further
GregCr 0:e6ceb13d2d05 229 return;
GregCr 0:e6ceb13d2d05 230 }
GregCr 0:e6ceb13d2d05 231
GregCr 0:e6ceb13d2d05 232 this->rxTx = rxTx;
GregCr 0:e6ceb13d2d05 233
GregCr 0:e6ceb13d2d05 234 if( rxTx != 0 )
GregCr 0:e6ceb13d2d05 235 {
GregCr 0:e6ceb13d2d05 236 antSwitch = 1;
GregCr 0:e6ceb13d2d05 237 }
GregCr 0:e6ceb13d2d05 238 else
GregCr 0:e6ceb13d2d05 239 {
GregCr 0:e6ceb13d2d05 240 antSwitch = 0;
GregCr 0:e6ceb13d2d05 241 }
GregCr 0:e6ceb13d2d05 242 }
GregCr 0:e6ceb13d2d05 243
GregCr 0:e6ceb13d2d05 244 bool SX1276MB1xAS::CheckRfFrequency( uint32_t frequency )
GregCr 0:e6ceb13d2d05 245 {
GregCr 0:e6ceb13d2d05 246 //TODO: Implement check, currently all frequencies are supported
GregCr 0:e6ceb13d2d05 247 return true;
GregCr 0:e6ceb13d2d05 248 }
GregCr 0:e6ceb13d2d05 249
GregCr 0:e6ceb13d2d05 250
GregCr 0:e6ceb13d2d05 251 void SX1276MB1xAS::Reset( void )
GregCr 0:e6ceb13d2d05 252 {
GregCr 4:f0ce52e94d3f 253 reset.output();
GregCr 0:e6ceb13d2d05 254 reset = 0;
GregCr 0:e6ceb13d2d05 255 wait_ms( 1 );
GregCr 4:f0ce52e94d3f 256 reset.input();
GregCr 0:e6ceb13d2d05 257 wait_ms( 6 );
GregCr 0:e6ceb13d2d05 258 }
GregCr 0:e6ceb13d2d05 259
GregCr 0:e6ceb13d2d05 260 void SX1276MB1xAS::Write( uint8_t addr, uint8_t data )
GregCr 0:e6ceb13d2d05 261 {
GregCr 0:e6ceb13d2d05 262 Write( addr, &data, 1 );
GregCr 0:e6ceb13d2d05 263 }
GregCr 0:e6ceb13d2d05 264
GregCr 0:e6ceb13d2d05 265 uint8_t SX1276MB1xAS::Read( uint8_t addr )
GregCr 0:e6ceb13d2d05 266 {
GregCr 0:e6ceb13d2d05 267 uint8_t data;
GregCr 0:e6ceb13d2d05 268 Read( addr, &data, 1 );
GregCr 0:e6ceb13d2d05 269 return data;
GregCr 0:e6ceb13d2d05 270 }
GregCr 0:e6ceb13d2d05 271
GregCr 0:e6ceb13d2d05 272 void SX1276MB1xAS::Write( uint8_t addr, uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 273 {
GregCr 0:e6ceb13d2d05 274 uint8_t i;
GregCr 0:e6ceb13d2d05 275
GregCr 0:e6ceb13d2d05 276 nss = 0;
GregCr 0:e6ceb13d2d05 277 spi.write( addr | 0x80 );
GregCr 0:e6ceb13d2d05 278 for( i = 0; i < size; i++ )
GregCr 0:e6ceb13d2d05 279 {
GregCr 0:e6ceb13d2d05 280 spi.write( buffer[i] );
GregCr 0:e6ceb13d2d05 281 }
GregCr 0:e6ceb13d2d05 282 nss = 1;
GregCr 0:e6ceb13d2d05 283 }
GregCr 0:e6ceb13d2d05 284
GregCr 0:e6ceb13d2d05 285 void SX1276MB1xAS::Read( uint8_t addr, uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 286 {
GregCr 0:e6ceb13d2d05 287 uint8_t i;
GregCr 0:e6ceb13d2d05 288
GregCr 0:e6ceb13d2d05 289 nss = 0;
GregCr 0:e6ceb13d2d05 290 spi.write( addr & 0x7F );
GregCr 0:e6ceb13d2d05 291 for( i = 0; i < size; i++ )
GregCr 0:e6ceb13d2d05 292 {
GregCr 0:e6ceb13d2d05 293 buffer[i] = spi.write( 0 );
GregCr 0:e6ceb13d2d05 294 }
GregCr 0:e6ceb13d2d05 295 nss = 1;
GregCr 0:e6ceb13d2d05 296 }
GregCr 0:e6ceb13d2d05 297
GregCr 0:e6ceb13d2d05 298 void SX1276MB1xAS::WriteFifo( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 299 {
GregCr 0:e6ceb13d2d05 300 Write( 0, buffer, size );
GregCr 0:e6ceb13d2d05 301 }
GregCr 0:e6ceb13d2d05 302
GregCr 0:e6ceb13d2d05 303 void SX1276MB1xAS::ReadFifo( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 304 {
GregCr 0:e6ceb13d2d05 305 Read( 0, buffer, size );
GregCr 0:e6ceb13d2d05 306 }