steven niu / Mbed 2 deprecated LP1768-lowpower_test

a test code to implement and test LP1768 power control mode

Dependencies:   mbed

This code implemented some LP1768 power mode : Sleep(), DeepSleep(), PowerDown(), DeepPowerDown(), BOGD_PowerDown(). It also has a test code to test these power modes and wakeup using watch dog. The wakeup part is based on Erik's code but add implementation for LP1768. As LP1768 has debug enabled in default, it cannot be waked up in DeepSleep mode. Therefore this code use WDC reset to wake up the chips from deep sleep. The test code also allow test the power under two clock frequency (96 MHz and 48MHz). Inspired by Paul and Michael Wang, I also tested the power reduction by power off PHY. The analysis could be found in http://mbed.org/users/steniu01/notebook/lp1768-power-mode-implementation-and-measurement-/#

PowerControl/PowerControl.h@0:5c4169623549, 2014-07-21 (annotated)

Committer:
steniu01
Date:
Mon Jul 21 13:46:49 2014 +0000
Revision:
0:5c4169623549
the first workrable version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
steniu01 0:5c4169623549 1 /* mbed PowerControl Library
steniu01 0:5c4169623549 2 * Copyright (c) 2010 Michael Wei
steniu01 0:5c4169623549 3 */
steniu01 0:5c4169623549 4
steniu01 0:5c4169623549 5 #ifndef MBED_POWERCONTROL_H
steniu01 0:5c4169623549 6 #define MBED_POWERCONTROL_H
steniu01 0:5c4169623549 7
steniu01 0:5c4169623549 8 //shouldn't have to include, but fixes weird problems with defines
steniu01 0:5c4169623549 9 //#include "LPC1768/LPC17xx.h"
steniu01 0:5c4169623549 10
steniu01 0:5c4169623549 11 //System Control Register
steniu01 0:5c4169623549 12 // bit 0: Reserved
steniu01 0:5c4169623549 13 // bit 1: Sleep on Exit
steniu01 0:5c4169623549 14 #define LPC1768_SCR_SLEEPONEXIT 0x2
steniu01 0:5c4169623549 15 // bit 2: Deep Sleep
steniu01 0:5c4169623549 16 #define LPC1768_SCR_SLEEPDEEP 0x4
steniu01 0:5c4169623549 17 // bit 3: Resereved
steniu01 0:5c4169623549 18 // bit 4: Send on Pending
steniu01 0:5c4169623549 19 #define LPC1768_SCR_SEVONPEND 0x10
steniu01 0:5c4169623549 20 // bit 5-31: Reserved
steniu01 0:5c4169623549 21
steniu01 0:5c4169623549 22 //Power Control Register
steniu01 0:5c4169623549 23 // bit 0: Power mode control bit 0 (power-down mode)
steniu01 0:5c4169623549 24 #define LPC1768_PCON_PM0 0x1
steniu01 0:5c4169623549 25 // bit 1: Power mode control bit 1 (deep power-down mode)
steniu01 0:5c4169623549 26 #define LPC1768_PCON_PM1 0x2
steniu01 0:5c4169623549 27 // bit 2: Brown-out reduced power mode
steniu01 0:5c4169623549 28 #define LPC1768_PCON_BODRPM 0x4
steniu01 0:5c4169623549 29 // bit 3: Brown-out global disable
steniu01 0:5c4169623549 30 #define LPC1768_PCON_BOGD 0x8
steniu01 0:5c4169623549 31 // bit 4: Brown-out reset disable
steniu01 0:5c4169623549 32 #define LPC1768_PCON_BORD 0x10
steniu01 0:5c4169623549 33 // bit 5-7 : Reserved
steniu01 0:5c4169623549 34 // bit 8: Sleep Mode Entry Flag
steniu01 0:5c4169623549 35 #define LPC1768_PCON_SMFLAG 0x100
steniu01 0:5c4169623549 36 // bit 9: Deep Sleep Entry Flag
steniu01 0:5c4169623549 37 #define LPC1768_PCON_DSFLAG 0x200
steniu01 0:5c4169623549 38 // bit 10: Power Down Entry Flag
steniu01 0:5c4169623549 39 #define LPC1768_PCON_PDFLAG 0x400
steniu01 0:5c4169623549 40 // bit 11: Deep Power Down Entry Flag
steniu01 0:5c4169623549 41 #define LPC1768_PCON_DPDFLAG 0x800
steniu01 0:5c4169623549 42 // bit 12-31: Reserved
steniu01 0:5c4169623549 43
steniu01 0:5c4169623549 44 //"Sleep Mode" (WFI).
steniu01 0:5c4169623549 45 inline void Sleep(void)
steniu01 0:5c4169623549 46 {
steniu01 0:5c4169623549 47 __WFI();
steniu01 0:5c4169623549 48 }
steniu01 0:5c4169623549 49
steniu01 0:5c4169623549 50 //"Deep Sleep" Mode
steniu01 0:5c4169623549 51 inline void DeepSleep(void)
steniu01 0:5c4169623549 52 {
steniu01 0:5c4169623549 53 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
steniu01 0:5c4169623549 54 __WFI();
steniu01 0:5c4169623549 55 }
steniu01 0:5c4169623549 56
steniu01 0:5c4169623549 57 //"Power-Down" Mode
steniu01 0:5c4169623549 58 inline void PowerDown(void)
steniu01 0:5c4169623549 59 {
steniu01 0:5c4169623549 60 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
steniu01 0:5c4169623549 61 LPC_SC->PCON &= ~LPC1768_PCON_PM1;
steniu01 0:5c4169623549 62 LPC_SC->PCON |= LPC1768_PCON_PM0;
steniu01 0:5c4169623549 63 __WFI();
steniu01 0:5c4169623549 64 //reset back to normal
steniu01 0:5c4169623549 65 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
steniu01 0:5c4169623549 66 }
steniu01 0:5c4169623549 67
steniu01 0:5c4169623549 68 //"Deep Power-Down" Mode
steniu01 0:5c4169623549 69 inline void DeepPowerDown(void)
steniu01 0:5c4169623549 70 {
steniu01 0:5c4169623549 71 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
steniu01 0:5c4169623549 72 LPC_SC->PCON |= LPC1768_PCON_PM1 | LPC1768_PCON_PM0;
steniu01 0:5c4169623549 73 __WFI();
steniu01 0:5c4169623549 74 //reset back to normal
steniu01 0:5c4169623549 75 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
steniu01 0:5c4169623549 76 }
steniu01 0:5c4169623549 77
steniu01 0:5c4169623549 78 //shut down BOD during power-down/deep sleep
steniu01 0:5c4169623549 79 inline void BrownOut_ReducedPowerMode_Enable(void)
steniu01 0:5c4169623549 80 {
steniu01 0:5c4169623549 81 LPC_SC->PCON |= LPC1768_PCON_BODRPM;
steniu01 0:5c4169623549 82 }
steniu01 0:5c4169623549 83
steniu01 0:5c4169623549 84 //turn on BOD during power-down/deep sleep
steniu01 0:5c4169623549 85 inline void BrownOut_ReducedPowerMode_Disable(void)
steniu01 0:5c4169623549 86 {
steniu01 0:5c4169623549 87 LPC_SC->PCON &= ~LPC1768_PCON_BODRPM;
steniu01 0:5c4169623549 88 }
steniu01 0:5c4169623549 89
steniu01 0:5c4169623549 90 //turn off brown out circutry
steniu01 0:5c4169623549 91 inline void BrownOut_Global_Disable(void)
steniu01 0:5c4169623549 92 {
steniu01 0:5c4169623549 93 LPC_SC->PCON |= LPC1768_PCON_BOGD;
steniu01 0:5c4169623549 94 }
steniu01 0:5c4169623549 95
steniu01 0:5c4169623549 96 //turn on brown out circutry
steniu01 0:5c4169623549 97 inline void BrownOut_Global_Enable(void)
steniu01 0:5c4169623549 98 {
steniu01 0:5c4169623549 99 LPC_SC->PCON &= !LPC1768_PCON_BOGD;
steniu01 0:5c4169623549 100 }
steniu01 0:5c4169623549 101
steniu01 0:5c4169623549 102 //turn off brown out reset circutry
steniu01 0:5c4169623549 103 inline void BrownOut_Reset_Disable(void)
steniu01 0:5c4169623549 104 {
steniu01 0:5c4169623549 105 LPC_SC->PCON |= LPC1768_PCON_BORD;
steniu01 0:5c4169623549 106 }
steniu01 0:5c4169623549 107
steniu01 0:5c4169623549 108 //turn on brown outreset circutry
steniu01 0:5c4169623549 109 inline void BrownOut_Reset_Enable(void)
steniu01 0:5c4169623549 110 {
steniu01 0:5c4169623549 111 LPC_SC->PCON &= ~LPC1768_PCON_BORD;
steniu01 0:5c4169623549 112 }
steniu01 0:5c4169623549 113 //Peripheral Control Register
steniu01 0:5c4169623549 114 // bit 0: Reserved
steniu01 0:5c4169623549 115 // bit 1: PCTIM0: Timer/Counter 0 power/clock enable
steniu01 0:5c4169623549 116 #define LPC1768_PCONP_PCTIM0 0x2
steniu01 0:5c4169623549 117 // bit 2: PCTIM1: Timer/Counter 1 power/clock enable
steniu01 0:5c4169623549 118 #define LPC1768_PCONP_PCTIM1 0x4
steniu01 0:5c4169623549 119 // bit 3: PCUART0: UART 0 power/clock enable
steniu01 0:5c4169623549 120 #define LPC1768_PCONP_PCUART0 0x8
steniu01 0:5c4169623549 121 // bit 4: PCUART1: UART 1 power/clock enable
steniu01 0:5c4169623549 122 #define LPC1768_PCONP_PCUART1 0x10
steniu01 0:5c4169623549 123 // bit 5: Reserved
steniu01 0:5c4169623549 124 // bit 6: PCPWM1: PWM 1 power/clock enable
steniu01 0:5c4169623549 125 #define LPC1768_PCONP_PCPWM1 0x40
steniu01 0:5c4169623549 126 // bit 7: PCI2C0: I2C interface 0 power/clock enable
steniu01 0:5c4169623549 127 #define LPC1768_PCONP_PCI2C0 0x80
steniu01 0:5c4169623549 128 // bit 8: PCSPI: SPI interface power/clock enable
steniu01 0:5c4169623549 129 #define LPC1768_PCONP_PCSPI 0x100
steniu01 0:5c4169623549 130 // bit 9: PCRTC: RTC power/clock enable
steniu01 0:5c4169623549 131 #define LPC1768_PCONP_PCRTC 0x200
steniu01 0:5c4169623549 132 // bit 10: PCSSP1: SSP interface 1 power/clock enable
steniu01 0:5c4169623549 133 #define LPC1768_PCONP_PCSSP1 0x400
steniu01 0:5c4169623549 134 // bit 11: Reserved
steniu01 0:5c4169623549 135 // bit 12: PCADC: A/D converter power/clock enable
steniu01 0:5c4169623549 136 #define LPC1768_PCONP_PCADC 0x1000
steniu01 0:5c4169623549 137 // bit 13: PCCAN1: CAN controller 1 power/clock enable
steniu01 0:5c4169623549 138 #define LPC1768_PCONP_PCCAN1 0x2000
steniu01 0:5c4169623549 139 // bit 14: PCCAN2: CAN controller 2 power/clock enable
steniu01 0:5c4169623549 140 #define LPC1768_PCONP_PCCAN2 0x4000
steniu01 0:5c4169623549 141 // bit 15: PCGPIO: GPIOs power/clock enable
steniu01 0:5c4169623549 142 #define LPC1768_PCONP_PCGPIO 0x8000
steniu01 0:5c4169623549 143 // bit 16: PCRIT: Repetitive interrupt timer power/clock enable
steniu01 0:5c4169623549 144 #define LPC1768_PCONP_PCRIT 0x10000
steniu01 0:5c4169623549 145 // bit 17: PCMCPWM: Motor control PWM power/clock enable
steniu01 0:5c4169623549 146 #define LPC1768_PCONP_PCMCPWM 0x20000
steniu01 0:5c4169623549 147 // bit 18: PCQEI: Quadrature encoder interface power/clock enable
steniu01 0:5c4169623549 148 #define LPC1768_PCONP_PCQEI 0x40000
steniu01 0:5c4169623549 149 // bit 19: PCI2C1: I2C interface 1 power/clock enable
steniu01 0:5c4169623549 150 #define LPC1768_PCONP_PCI2C1 0x80000
steniu01 0:5c4169623549 151 // bit 20: Reserved
steniu01 0:5c4169623549 152 // bit 21: PCSSP0: SSP interface 0 power/clock enable
steniu01 0:5c4169623549 153 #define LPC1768_PCONP_PCSSP0 0x200000
steniu01 0:5c4169623549 154 // bit 22: PCTIM2: Timer 2 power/clock enable
steniu01 0:5c4169623549 155 #define LPC1768_PCONP_PCTIM2 0x400000
steniu01 0:5c4169623549 156 // bit 23: PCTIM3: Timer 3 power/clock enable
steniu01 0:5c4169623549 157 #define LPC1768_PCONP_PCQTIM3 0x800000
steniu01 0:5c4169623549 158 // bit 24: PCUART2: UART 2 power/clock enable
steniu01 0:5c4169623549 159 #define LPC1768_PCONP_PCUART2 0x1000000
steniu01 0:5c4169623549 160 // bit 25: PCUART3: UART 3 power/clock enable
steniu01 0:5c4169623549 161 #define LPC1768_PCONP_PCUART3 0x2000000
steniu01 0:5c4169623549 162 // bit 26: PCI2C2: I2C interface 2 power/clock enable
steniu01 0:5c4169623549 163 #define LPC1768_PCONP_PCI2C2 0x4000000
steniu01 0:5c4169623549 164 // bit 27: PCI2S: I2S interface power/clock enable
steniu01 0:5c4169623549 165 #define LPC1768_PCONP_PCI2S 0x8000000
steniu01 0:5c4169623549 166 // bit 28: Reserved
steniu01 0:5c4169623549 167 // bit 29: PCGPDMA: GP DMA function power/clock enable
steniu01 0:5c4169623549 168 #define LPC1768_PCONP_PCGPDMA 0x20000000
steniu01 0:5c4169623549 169 // bit 30: PCENET: Ethernet block power/clock enable
steniu01 0:5c4169623549 170 #define LPC1768_PCONP_PCENET 0x40000000
steniu01 0:5c4169623549 171 // bit 31: PCUSB: USB interface power/clock enable
steniu01 0:5c4169623549 172 #define LPC1768_PCONP_PCUSB 0x80000000
steniu01 0:5c4169623549 173
steniu01 0:5c4169623549 174 //Powers Up specified Peripheral(s)
steniu01 0:5c4169623549 175 inline unsigned int Peripheral_PowerUp(unsigned int bitMask)
steniu01 0:5c4169623549 176 {
steniu01 0:5c4169623549 177 return LPC_SC->PCONP |= bitMask;
steniu01 0:5c4169623549 178 }
steniu01 0:5c4169623549 179
steniu01 0:5c4169623549 180 //Powers Down specified Peripheral(s)
steniu01 0:5c4169623549 181 inline unsigned int Peripheral_PowerDown(unsigned int bitMask)
steniu01 0:5c4169623549 182 {
steniu01 0:5c4169623549 183 return LPC_SC->PCONP &= ~bitMask;
steniu01 0:5c4169623549 184 }
steniu01 0:5c4169623549 185
steniu01 0:5c4169623549 186 //returns if the peripheral is on or off
steniu01 0:5c4169623549 187 inline bool Peripheral_GetStatus(unsigned int peripheral)
steniu01 0:5c4169623549 188 {
steniu01 0:5c4169623549 189 return (LPC_SC->PCONP & peripheral) ? true : false;
steniu01 0:5c4169623549 190 }
steniu01 0:5c4169623549 191
steniu01 0:5c4169623549 192 #endif