Class to provide simple access to I2C EEPROM chiles like Microchip's 24LC range or AMTELS AT24C range. Chips up to 64Kb in size are directly supported. Updated to Mbed OS v 5.1
I2CEeprom.h@7:29e505d37158, 2020-03-28 (annotated)
- Committer:
- skyscraper
- Date:
- Sat Mar 28 13:42:18 2020 +0000
- Revision:
- 7:29e505d37158
- Parent:
- 6:0b18a49e03b9
- Child:
- 8:0c122f839dc9
more doc updates
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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rhourahane | 1:b23f5561266c | 1 | /* Simple access class for I2C EEPROM chips like Microchip 24LC |
rhourahane | 1:b23f5561266c | 2 | * Copyright (c) 2015 Robin Hourahane |
rhourahane | 1:b23f5561266c | 3 | * |
rhourahane | 1:b23f5561266c | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
rhourahane | 1:b23f5561266c | 5 | * you may not use this file except in compliance with the License. |
rhourahane | 1:b23f5561266c | 6 | * You may obtain a copy of the License at |
rhourahane | 1:b23f5561266c | 7 | * |
rhourahane | 1:b23f5561266c | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
rhourahane | 1:b23f5561266c | 9 | * |
rhourahane | 1:b23f5561266c | 10 | * Unless required by applicable law or agreed to in writing, software |
rhourahane | 1:b23f5561266c | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
rhourahane | 1:b23f5561266c | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
rhourahane | 1:b23f5561266c | 13 | * See the License for the specific language governing permissions and |
rhourahane | 1:b23f5561266c | 14 | * limitations under the License. |
rhourahane | 1:b23f5561266c | 15 | */ |
skyscraper | 6:0b18a49e03b9 | 16 | |
skyscraper | 6:0b18a49e03b9 | 17 | #ifndef __I2CEEPROM_H__ |
skyscraper | 6:0b18a49e03b9 | 18 | #define __I2CEEPROM_H__ |
rhourahane | 1:b23f5561266c | 19 | |
rhourahane | 1:b23f5561266c | 20 | #include <mbed.h> |
rhourahane | 1:b23f5561266c | 21 | |
skyscraper | 2:f3188aaccf80 | 22 | /// Class to provide simple access to I2C EEPROM chips like Microchip's 24LC range |
rhourahane | 1:b23f5561266c | 23 | /// or AMTELS AT24C range. |
rhourahane | 1:b23f5561266c | 24 | /// Chips up to 64Kb in size are directly supported. |
rhourahane | 1:b23f5561266c | 25 | /// The class handles multiple page writes so any amount of data can be written in |
skyscraper | 2:f3188aaccf80 | 26 | /// a single call to write. |
skyscraper | 7:29e505d37158 | 27 | /// At start of a write(addr,buffer,size), a buffer of up to pageSize + 2 |
skyscraper | 7:29e505d37158 | 28 | /// is allocated on the heap, and the data and address are copied to it. |
skyscraper | 7:29e505d37158 | 29 | /// This allows the write to proceed without unlocking, which might allow |
skyscraper | 7:29e505d37158 | 30 | /// another device on the bus access and so corrupt the write. |
skyscraper | 7:29e505d37158 | 31 | /// This allocation per write fits my usecase, where eeeprom variables |
skyscraper | 7:29e505d37158 | 32 | /// are written in a special menu mode at start up, but it may be better to |
skyscraper | 7:29e505d37158 | 33 | /// preallocate a buffer once at startup, if writes are occurring at arbitrary |
skyscraper | 7:29e505d37158 | 34 | /// times during execution to prevent surprises with out of memory issues |
skyscraper | 7:29e505d37158 | 35 | /// when trying to write during normal execution. |
skyscraper | 7:29e505d37158 | 36 | /// |
skyscraper | 7:29e505d37158 | 37 | /// Tested on a Microchip 24LC128. |
rhourahane | 1:b23f5561266c | 38 | class I2CEeprom { |
rhourahane | 1:b23f5561266c | 39 | public: |
rhourahane | 1:b23f5561266c | 40 | /// Constructor to create a new instance of the class. |
skyscraper | 2:f3188aaccf80 | 41 | /// @param i2c a reference to the i2c bus the chip is connected to. |
skyscraper | 6:0b18a49e03b9 | 42 | /// @param address The 8bit I2C address of the chip. |
rhourahane | 1:b23f5561266c | 43 | /// @param pageSize The size of the page used in writing to the chip. |
skyscraper | 5:315872eec0ae | 44 | /// @param chipSize The size of the memory in the chip for range check. |
skyscraper | 6:0b18a49e03b9 | 45 | /// @param writeCycleTime_ms The write cycle time in ms. |
skyscraper | 2:f3188aaccf80 | 46 | I2CEeprom( |
skyscraper | 2:f3188aaccf80 | 47 | I2C& i2c, |
skyscraper | 2:f3188aaccf80 | 48 | int address, |
skyscraper | 2:f3188aaccf80 | 49 | size_t pageSize, |
skyscraper | 2:f3188aaccf80 | 50 | size_t chipSize, |
skyscraper | 5:315872eec0ae | 51 | uint8_t writeCycleTime_ms); |
rhourahane | 1:b23f5561266c | 52 | |
rhourahane | 1:b23f5561266c | 53 | /// Read a single byte from the address in memory. |
rhourahane | 1:b23f5561266c | 54 | /// @param address Memory address to read from. |
rhourahane | 1:b23f5561266c | 55 | /// @param value Variable to receive value read. |
rhourahane | 1:b23f5561266c | 56 | /// @returns Number of bytes read from memory. |
rhourahane | 1:b23f5561266c | 57 | size_t read(size_t address, char &value); |
rhourahane | 1:b23f5561266c | 58 | |
rhourahane | 1:b23f5561266c | 59 | /// Read multiple bytes starting from the address in memory. |
rhourahane | 1:b23f5561266c | 60 | /// @param address Memory address to start reading from. |
rhourahane | 1:b23f5561266c | 61 | /// @param buffer Pointer to buffer to hold bytes read from memory. |
rhourahane | 1:b23f5561266c | 62 | /// @param size Number of bytes to be read from memory. |
rhourahane | 1:b23f5561266c | 63 | /// @returns Number of bytes read from memory. |
rhourahane | 1:b23f5561266c | 64 | size_t read(size_t address, char *buffer, size_t size); |
rhourahane | 1:b23f5561266c | 65 | |
rhourahane | 1:b23f5561266c | 66 | /// Read either an instance or an array of a POD type from memory. |
rhourahane | 1:b23f5561266c | 67 | /// Note the value of the type can't contain pointers. |
rhourahane | 1:b23f5561266c | 68 | /// @param address Start address for reading memory. |
rhourahane | 1:b23f5561266c | 69 | /// @param value Object to be read from memory. |
rhourahane | 1:b23f5561266c | 70 | /// @returns Number of bytes read from memory. |
rhourahane | 1:b23f5561266c | 71 | template<typename T> size_t read(size_t address, T &value) { |
rhourahane | 1:b23f5561266c | 72 | return read(address, reinterpret_cast<char *>(&value), sizeof(T)); |
rhourahane | 1:b23f5561266c | 73 | } |
rhourahane | 1:b23f5561266c | 74 | |
rhourahane | 1:b23f5561266c | 75 | /// Write a single byte to the address in memory. |
rhourahane | 1:b23f5561266c | 76 | /// @param address Memory address to write to. |
rhourahane | 1:b23f5561266c | 77 | /// @param value Value to be written to memory. |
rhourahane | 1:b23f5561266c | 78 | /// @returns Number of bytes written to memory. |
rhourahane | 1:b23f5561266c | 79 | size_t write(size_t address, char value); |
rhourahane | 1:b23f5561266c | 80 | |
rhourahane | 1:b23f5561266c | 81 | /// Write multiple bytes starting from the address in memory. |
skyscraper | 5:315872eec0ae | 82 | /// Note that in this implementation, a buffer is allocated on the heap |
skyscraper | 5:315872eec0ae | 83 | /// for the |
rhourahane | 1:b23f5561266c | 84 | /// @param address Memory address to start writting to. |
rhourahane | 1:b23f5561266c | 85 | /// @param buffer Pointer to buffer holding the bytes to write to memory. |
rhourahane | 1:b23f5561266c | 86 | /// @param size Number of bytes to be written to memory. |
rhourahane | 1:b23f5561266c | 87 | /// @returns Number of bytes written to memory. |
rhourahane | 1:b23f5561266c | 88 | size_t write(size_t address, const char *buffer, size_t size); |
skyscraper | 2:f3188aaccf80 | 89 | |
rhourahane | 1:b23f5561266c | 90 | /// Write either an instance or an array of a POD type to memory. |
rhourahane | 1:b23f5561266c | 91 | /// Note the value of the type can't contain pointers. |
rhourahane | 1:b23f5561266c | 92 | /// @param address Start address to write to memory. |
rhourahane | 1:b23f5561266c | 93 | /// @returns Number of bytes written to memory. |
rhourahane | 1:b23f5561266c | 94 | template<typename T> size_t write(size_t address, const T &value) { |
rhourahane | 1:b23f5561266c | 95 | return write(address, reinterpret_cast<const char *>(&value), sizeof(T)); |
rhourahane | 1:b23f5561266c | 96 | } |
skyscraper | 2:f3188aaccf80 | 97 | |
rhourahane | 1:b23f5561266c | 98 | private: |
rhourahane | 1:b23f5561266c | 99 | // Wait for a write cycle to complete using polling and small waits. |
rhourahane | 1:b23f5561266c | 100 | void waitForWrite(); |
skyscraper | 2:f3188aaccf80 | 101 | size_t ll_write(size_t address, const char *buffer, size_t size); |
rhourahane | 1:b23f5561266c | 102 | |
rhourahane | 1:b23f5561266c | 103 | // Validate that the proposed opperation will fit in the size of |
rhourahane | 1:b23f5561266c | 104 | // the chip. |
skyscraper | 4:d8f51b136dbd | 105 | bool checkSpace(size_t address, size_t size) |
skyscraper | 4:d8f51b136dbd | 106 | { |
skyscraper | 4:d8f51b136dbd | 107 | return (address + size) < m_chipSize ; |
skyscraper | 4:d8f51b136dbd | 108 | } |
rhourahane | 1:b23f5561266c | 109 | |
rhourahane | 1:b23f5561266c | 110 | private: |
skyscraper | 2:f3188aaccf80 | 111 | I2C & m_i2c; |
skyscraper | 2:f3188aaccf80 | 112 | int const m_i2cAddress; |
skyscraper | 2:f3188aaccf80 | 113 | size_t const m_chipSize; |
skyscraper | 2:f3188aaccf80 | 114 | size_t const m_pageSize; |
skyscraper | 2:f3188aaccf80 | 115 | uint8_t const m_writeCycleTime_ms; |
rhourahane | 1:b23f5561266c | 116 | }; |
rhourahane | 1:b23f5561266c | 117 | |
rhourahane | 1:b23f5561266c | 118 | #endif |