Andy Little / I2CEeprom

Class to provide simple access to I2C EEPROM chiles like Microchip's 24LC range or AMTELS AT24C range. Chips up to 64Kb in size are directly supported. Updated to Mbed OS v 5.1

Dependents:   storage_test

I2CEeprom.h@4:d8f51b136dbd, 2020-03-28 (annotated)

Committer:
skyscraper
Date:
Sat Mar 28 01:50:44 2020 +0000
Revision:
4:d8f51b136dbd
Parent:
2:f3188aaccf80
Child:
5:315872eec0ae
Streamline EEprom and remove some unneded functionality

Who changed what in which revision?

UserRevisionLine numberNew contents of line
skyscraper 2:f3188aaccf80 1 #ifndef __I2CEEPROM_H__
skyscraper 2:f3188aaccf80 2 #define __I2CEEPROM_H__
rhourahane 1:b23f5561266c 3 /* Simple access class for I2C EEPROM chips like Microchip 24LC
rhourahane 1:b23f5561266c 4 * Copyright (c) 2015 Robin Hourahane
rhourahane 1:b23f5561266c 5 *
rhourahane 1:b23f5561266c 6 * Licensed under the Apache License, Version 2.0 (the "License");
rhourahane 1:b23f5561266c 7 * you may not use this file except in compliance with the License.
rhourahane 1:b23f5561266c 8 * You may obtain a copy of the License at
rhourahane 1:b23f5561266c 9 *
rhourahane 1:b23f5561266c 10 * http://www.apache.org/licenses/LICENSE-2.0
rhourahane 1:b23f5561266c 11 *
rhourahane 1:b23f5561266c 12 * Unless required by applicable law or agreed to in writing, software
rhourahane 1:b23f5561266c 13 * distributed under the License is distributed on an "AS IS" BASIS,
rhourahane 1:b23f5561266c 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
rhourahane 1:b23f5561266c 15 * See the License for the specific language governing permissions and
rhourahane 1:b23f5561266c 16 * limitations under the License.
rhourahane 1:b23f5561266c 17 */
rhourahane 1:b23f5561266c 18
rhourahane 1:b23f5561266c 19 #include <mbed.h>
rhourahane 1:b23f5561266c 20
skyscraper 2:f3188aaccf80 21 /// Class to provide simple access to I2C EEPROM chips like Microchip's 24LC range
rhourahane 1:b23f5561266c 22 /// or AMTELS AT24C range.
rhourahane 1:b23f5561266c 23 /// Chips up to 64Kb in size are directly supported.
rhourahane 1:b23f5561266c 24 /// The class handles multiple page writes so any amount of data can be written in
skyscraper 2:f3188aaccf80 25 /// a single call to write.
rhourahane 1:b23f5561266c 26 ///
rhourahane 1:b23f5561266c 27 /// Although not tested it should work with the MAC versions of Microchip range
rhourahane 1:b23f5561266c 28 /// as well but the chipSize will need to be set to include the ROM area as well.
rhourahane 1:b23f5561266c 29 class I2CEeprom {
rhourahane 1:b23f5561266c 30 public:
rhourahane 1:b23f5561266c 31 /// Constructor to create a new instance of the class.
skyscraper 2:f3188aaccf80 32 /// @param i2c a reference to the i2c bus the chip is connected to.
rhourahane 1:b23f5561266c 33 /// @param address The 8bit I2C address of the chip in the range 0xA0 - 0xAE.
rhourahane 1:b23f5561266c 34 /// @param pageSize The size of the page used in writing to the chip.
rhourahane 1:b23f5561266c 35 /// @param chipSize The size of the memory in the chip to allow range checkng. Set to
rhourahane 1:b23f5561266c 36 /// 0 to disable checks.
skyscraper 2:f3188aaccf80 37 /// @param The write cycle time in ms.
skyscraper 2:f3188aaccf80 38 /// TODO : Could use bus frequency to cap the speed of the bus
skyscraper 2:f3188aaccf80 39 I2CEeprom(
skyscraper 2:f3188aaccf80 40 I2C& i2c,
skyscraper 2:f3188aaccf80 41 int address,
skyscraper 2:f3188aaccf80 42 size_t pageSize,
skyscraper 2:f3188aaccf80 43 size_t chipSize,
skyscraper 2:f3188aaccf80 44 uint8_t write_cycle_time_ms);
rhourahane 1:b23f5561266c 45
rhourahane 1:b23f5561266c 46 /// Read a single byte from the address in memory.
rhourahane 1:b23f5561266c 47 /// @param address Memory address to read from.
rhourahane 1:b23f5561266c 48 /// @param value Variable to receive value read.
rhourahane 1:b23f5561266c 49 /// @returns Number of bytes read from memory.
rhourahane 1:b23f5561266c 50 size_t read(size_t address, char &value);
rhourahane 1:b23f5561266c 51
rhourahane 1:b23f5561266c 52 /// Read multiple bytes starting from the address in memory.
rhourahane 1:b23f5561266c 53 /// @param address Memory address to start reading from.
rhourahane 1:b23f5561266c 54 /// @param buffer Pointer to buffer to hold bytes read from memory.
rhourahane 1:b23f5561266c 55 /// @param size Number of bytes to be read from memory.
rhourahane 1:b23f5561266c 56 /// @returns Number of bytes read from memory.
rhourahane 1:b23f5561266c 57 size_t read(size_t address, char *buffer, size_t size);
rhourahane 1:b23f5561266c 58
rhourahane 1:b23f5561266c 59 /// Read either an instance or an array of a POD type from memory.
rhourahane 1:b23f5561266c 60 /// Note the value of the type can't contain pointers.
rhourahane 1:b23f5561266c 61 /// @param address Start address for reading memory.
rhourahane 1:b23f5561266c 62 /// @param value Object to be read from memory.
rhourahane 1:b23f5561266c 63 /// @returns Number of bytes read from memory.
rhourahane 1:b23f5561266c 64 template<typename T> size_t read(size_t address, T &value) {
rhourahane 1:b23f5561266c 65 return read(address, reinterpret_cast<char *>(&value), sizeof(T));
rhourahane 1:b23f5561266c 66 }
rhourahane 1:b23f5561266c 67
rhourahane 1:b23f5561266c 68 /// Write a single byte to the address in memory.
rhourahane 1:b23f5561266c 69 /// @param address Memory address to write to.
rhourahane 1:b23f5561266c 70 /// @param value Value to be written to memory.
rhourahane 1:b23f5561266c 71 /// @returns Number of bytes written to memory.
rhourahane 1:b23f5561266c 72 size_t write(size_t address, char value);
rhourahane 1:b23f5561266c 73
rhourahane 1:b23f5561266c 74 /// Write multiple bytes starting from the address in memory.
rhourahane 1:b23f5561266c 75 /// @param address Memory address to start writting to.
rhourahane 1:b23f5561266c 76 /// @param buffer Pointer to buffer holding the bytes to write to memory.
rhourahane 1:b23f5561266c 77 /// @param size Number of bytes to be written to memory.
rhourahane 1:b23f5561266c 78 /// @returns Number of bytes written to memory.
rhourahane 1:b23f5561266c 79 size_t write(size_t address, const char *buffer, size_t size);
skyscraper 2:f3188aaccf80 80
rhourahane 1:b23f5561266c 81 /// Write either an instance or an array of a POD type to memory.
rhourahane 1:b23f5561266c 82 /// Note the value of the type can't contain pointers.
rhourahane 1:b23f5561266c 83 /// @param address Start address to write to memory.
rhourahane 1:b23f5561266c 84 /// @returns Number of bytes written to memory.
rhourahane 1:b23f5561266c 85 template<typename T> size_t write(size_t address, const T &value) {
rhourahane 1:b23f5561266c 86 return write(address, reinterpret_cast<const char *>(&value), sizeof(T));
rhourahane 1:b23f5561266c 87 }
skyscraper 2:f3188aaccf80 88
rhourahane 1:b23f5561266c 89 private:
rhourahane 1:b23f5561266c 90 // Wait for a write cycle to complete using polling and small waits.
rhourahane 1:b23f5561266c 91 void waitForWrite();
skyscraper 2:f3188aaccf80 92 size_t ll_write(size_t address, const char *buffer, size_t size);
rhourahane 1:b23f5561266c 93
rhourahane 1:b23f5561266c 94 // Validate that the proposed opperation will fit in the size of
rhourahane 1:b23f5561266c 95 // the chip.
skyscraper 4:d8f51b136dbd 96 bool checkSpace(size_t address, size_t size)
skyscraper 4:d8f51b136dbd 97 {
skyscraper 4:d8f51b136dbd 98 return (address + size) < m_chipSize ;
skyscraper 4:d8f51b136dbd 99 }
rhourahane 1:b23f5561266c 100
rhourahane 1:b23f5561266c 101 private:
skyscraper 2:f3188aaccf80 102 I2C & m_i2c;
skyscraper 2:f3188aaccf80 103 int const m_i2cAddress;
skyscraper 2:f3188aaccf80 104 size_t const m_chipSize;
skyscraper 2:f3188aaccf80 105 size_t const m_pageSize;
skyscraper 2:f3188aaccf80 106 uint8_t const m_writeCycleTime_ms;
rhourahane 1:b23f5561266c 107 };
rhourahane 1:b23f5561266c 108
rhourahane 1:b23f5561266c 109 #endif