Shivanand Gowda / S2568FBLL

Static RAM 256 kilo bytes using SPI single IO Serial SRAM

Dependents:   SPI_SRAM_READ_WRITE

IS62/65WVS2568FBLL

KEY FEATURES

• SPI-Compatible Bus Interface: - 16/20 MHz Clock rate - SPI/SDI/SQI mode • Low-Power CMOS Technology: - Read Current: 8 mA (max) at 3.6V, 20 MHz, 85°C. - CMOS Standby Current: 4 uA (typ). • 256K x 8-bit Organization: - 32-byte page • Byte, Page and Sequential mode for Reads and Writes.

https://www.mouser.in/datasheet/2/198/IS62-65WVS2568FALL-BLL-1147362.pdf for more details please look into datasheet

S2568FBLL.h@1:7d8adf80c30d, 2018-05-22 (annotated)

Committer:
shivanandgowdakr
Date:
Tue May 22 10:43:05 2018 +0000
Revision:
1:7d8adf80c30d
Parent:
0:0339901bb4b0 
Read Write operations in SRAM 2 Megabit or 256 k bytes.; ; Serial SPI SRAM NUCLEO F767ZI

Who changed what in which revision?

UserRevisionLine numberNew contents of line
shivanandgowdakr 0:0339901bb4b0 1 // S2568FBLL.h
shivanandgowdakr 0:0339901bb4b0 2
shivanandgowdakr 0:0339901bb4b0 3 //Instruction Name Instruction Format Hex
shivanandgowdakr 0:0339901bb4b0 4 //Code Description
shivanandgowdakr 0:0339901bb4b0 5 //READ 0000 0011 0x03 Read data from memory array beginning at selected address
shivanandgowdakr 0:0339901bb4b0 6 //WRITE 0000 0010 0x02 Write data to memory array beginning at selected address
shivanandgowdakr 0:0339901bb4b0 7 //ESDI 0011 1011 0x3B Enter SDI mode
shivanandgowdakr 0:0339901bb4b0 8 //ESQI 0011 1000 0x38 Enter SQI mode
shivanandgowdakr 0:0339901bb4b0 9 //RSTDQI 1111 1111 0xFF Reset SDI/SQI mode
shivanandgowdakr 0:0339901bb4b0 10 //RDMR 0000 0101 0x05 Read Mode Register
shivanandgowdakr 0:0339901bb4b0 11 //WRMR 0000 0001 0x01 Write Mode Register
shivanandgowdakr 0:0339901bb4b0 12
shivanandgowdakr 0:0339901bb4b0 13 #ifndef S2568FBLL_H
shivanandgowdakr 0:0339901bb4b0 14 #define S2568FBLL_H
shivanandgowdakr 0:0339901bb4b0 15
shivanandgowdakr 0:0339901bb4b0 16 #include "mbed.h"
shivanandgowdakr 0:0339901bb4b0 17 #include <string>
shivanandgowdakr 0:0339901bb4b0 18
shivanandgowdakr 0:0339901bb4b0 19 #define SPI_FREQ 5000000 //Change SPI Frequency Here
shivanandgowdakr 0:0339901bb4b0 20 #define SPI_MODE 0 // SPI Mode can be 0 or 3 . see data sheet
shivanandgowdakr 0:0339901bb4b0 21 #define SPI_NBIT 8 // Number of bits 8.
shivanandgowdakr 0:0339901bb4b0 22
shivanandgowdakr 0:0339901bb4b0 23
shivanandgowdakr 0:0339901bb4b0 24
shivanandgowdakr 0:0339901bb4b0 25 #define DUMMY_ADDR 0x00
shivanandgowdakr 0:0339901bb4b0 26 #define WAIT_TIME 1
shivanandgowdakr 0:0339901bb4b0 27
shivanandgowdakr 0:0339901bb4b0 28 #define ADDR_BMASK3 0xff000000
shivanandgowdakr 0:0339901bb4b0 29 #define ADDR_BMASK2 0x00ff0000
shivanandgowdakr 0:0339901bb4b0 30 #define ADDR_BMASK1 0x0000ff00
shivanandgowdakr 0:0339901bb4b0 31 #define ADDR_BMASK0 0x000000ff
shivanandgowdakr 0:0339901bb4b0 32
shivanandgowdakr 0:0339901bb4b0 33 #define ADDR_BSHIFT3 24
shivanandgowdakr 0:0339901bb4b0 34 #define ADDR_BSHIFT2 16
shivanandgowdakr 0:0339901bb4b0 35 #define ADDR_BSHIFT1 8
shivanandgowdakr 0:0339901bb4b0 36 #define ADDR_BSHIFT0 0
shivanandgowdakr 0:0339901bb4b0 37
shivanandgowdakr 0:0339901bb4b0 38 #define READ 0x03 // Read data from memory array beginning at selected address
shivanandgowdakr 0:0339901bb4b0 39 #define WRITE 0x02 //Write data to memory array beginning at selected address
shivanandgowdakr 0:0339901bb4b0 40 #define ESDI 0x3B //Enter SDI mode
shivanandgowdakr 0:0339901bb4b0 41 #define ESQI 0x38 //Enter SQI mode
shivanandgowdakr 0:0339901bb4b0 42 #define RSTDQI 0xFF //Reset SDI/SQI mode
shivanandgowdakr 0:0339901bb4b0 43 #define RDMR 0x05 //Read Mode Register
shivanandgowdakr 0:0339901bb4b0 44 #define WRMR 0x01 //Write Mode Register
shivanandgowdakr 0:0339901bb4b0 45
shivanandgowdakr 0:0339901bb4b0 46 #define RWMODE_BYTE 0x00 //7th bit=0 and 6th bit =0 Byte mode 5 TO 0 BITS ARE RESERVED FOR FUTURE
shivanandgowdakr 0:0339901bb4b0 47 #define RWMODE_PAGE 0x80 // 1 0 Page mode
shivanandgowdakr 0:0339901bb4b0 48 #define RWMODE_SEQ 0x40 // 0 1= Sequential mode (default operation)
shivanandgowdakr 0:0339901bb4b0 49
shivanandgowdakr 0:0339901bb4b0 50
shivanandgowdakr 0:0339901bb4b0 51
shivanandgowdakr 0:0339901bb4b0 52 class S2568FBLL: public SPI {
shivanandgowdakr 0:0339901bb4b0 53 public:
shivanandgowdakr 0:0339901bb4b0 54 S2568FBLL(PinName mosi, PinName miso, PinName sclk, PinName cs,PinName hold);
shivanandgowdakr 0:0339901bb4b0 55
shivanandgowdakr 0:0339901bb4b0 56 int readByte(int addr); // takes a 24-bit (3 bytes) address and returns the data (1 byte) at that location
shivanandgowdakr 0:0339901bb4b0 57 void readStream(int addr, char* buf, int count); // takes a 24-bit address, reads count bytes, and stores results in buf
shivanandgowdakr 0:0339901bb4b0 58 void writeByte(int addr, int data); // takes a 24-bit (3 bytes) address and a byte of data to write at that location
shivanandgowdakr 0:0339901bb4b0 59 void writeStream(int addr, char* buf, int count); // write count bytes of data from buf to memory, starting at addr
shivanandgowdakr 0:0339901bb4b0 60 void writeString(int add, string str);
shivanandgowdakr 0:0339901bb4b0 61 long raedLong(int addr);
shivanandgowdakr 0:0339901bb4b0 62 void writeLong(int addr, long value);
shivanandgowdakr 0:0339901bb4b0 63 uint8_t readRegister(void); // Write Long Integer Number
shivanandgowdakr 0:0339901bb4b0 64 private:
shivanandgowdakr 0:0339901bb4b0 65
shivanandgowdakr 0:0339901bb4b0 66 void writeRegister(uint8_t regValue);
shivanandgowdakr 0:0339901bb4b0 67 void chipEnable(); // chip enable
shivanandgowdakr 0:0339901bb4b0 68 void chipDisable();
shivanandgowdakr 0:0339901bb4b0 69 void holdEnable();
shivanandgowdakr 0:0339901bb4b0 70 void holdDisable();
shivanandgowdakr 0:0339901bb4b0 71 // chip disable
shivanandgowdakr 0:0339901bb4b0 72
shivanandgowdakr 0:0339901bb4b0 73 // SPI _spi;
shivanandgowdakr 0:0339901bb4b0 74 DigitalOut _cs;
shivanandgowdakr 0:0339901bb4b0 75 DigitalOut _hold;
shivanandgowdakr 0:0339901bb4b0 76 };
shivanandgowdakr 0:0339901bb4b0 77
shivanandgowdakr 0:0339901bb4b0 78 #endif