Shivanand Gowda / MFRC522_Updated

RC522 Read Write Blocks CARD

Dependents:   RC522_Read_Write_CARD_MIFARE_1K_CARDS EscanerRf escaner_RTOS escaner_RTOS

MFRC522.h@0:f0aa9cbf7f0e, 2018-09-11 (annotated)

Committer:
shivanandgowdakr
Date:
Tue Sep 11 09:20:18 2018 +0000
Revision:
0:f0aa9cbf7f0e
Read Write Card MIFARE RC522

Who changed what in which revision?

UserRevisionLine numberNew contents of line
shivanandgowdakr 0:f0aa9cbf7f0e 1 /**
shivanandgowdakr 0:f0aa9cbf7f0e 2 * MFRC522.h - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
shivanandgowdakr 0:f0aa9cbf7f0e 3 * Based on code Dr.Leong ( WWW.B2CQSHOP.COM )
shivanandgowdakr 0:f0aa9cbf7f0e 4 * Created by Miguel Balboa (circuitito.com), Jan, 2012.
shivanandgowdakr 0:f0aa9cbf7f0e 5 * Rewritten by Soren Thing Andersen (access.thing.dk), fall of 2013 (Translation to English, refactored, comments, anti collision, cascade levels.)
shivanandgowdakr 0:f0aa9cbf7f0e 6 * Ported to mbed by Martin Olejar, Dec, 2013
shivanandgowdakr 0:f0aa9cbf7f0e 7 *
shivanandgowdakr 0:f0aa9cbf7f0e 8 * Please read this file for an overview and then MFRC522.cpp for comments on the specific functions.
shivanandgowdakr 0:f0aa9cbf7f0e 9 * Search for "mf-rc522" on ebay.com to purchase the MF-RC522 board.
shivanandgowdakr 0:f0aa9cbf7f0e 10 *
shivanandgowdakr 0:f0aa9cbf7f0e 11 * There are three hardware components involved:
shivanandgowdakr 0:f0aa9cbf7f0e 12 * 1) The micro controller: An Arduino
shivanandgowdakr 0:f0aa9cbf7f0e 13 * 2) The PCD (short for Proximity Coupling Device): NXP MFRC522 Contactless Reader IC
shivanandgowdakr 0:f0aa9cbf7f0e 14 * 3) The PICC (short for Proximity Integrated Circuit Card): A card or tag using the ISO 14443A interface, eg Mifare or NTAG203.
shivanandgowdakr 0:f0aa9cbf7f0e 15 *
shivanandgowdakr 0:f0aa9cbf7f0e 16 * The microcontroller and card reader uses SPI for communication.
shivanandgowdakr 0:f0aa9cbf7f0e 17 * The protocol is described in the MFRC522 datasheet: http://www.nxp.com/documents/data_sheet/MFRC522.pdf
shivanandgowdakr 0:f0aa9cbf7f0e 18 *
shivanandgowdakr 0:f0aa9cbf7f0e 19 * The card reader and the tags communicate using a 13.56MHz electromagnetic field.
shivanandgowdakr 0:f0aa9cbf7f0e 20 * The protocol is defined in ISO/IEC 14443-3 Identification cards -- Contactless integrated circuit cards -- Proximity cards -- Part 3: Initialization and anticollision".
shivanandgowdakr 0:f0aa9cbf7f0e 21 * A free version of the final draft can be found at http://wg8.de/wg8n1496_17n3613_Ballot_FCD14443-3.pdf
shivanandgowdakr 0:f0aa9cbf7f0e 22 * Details are found in chapter 6, Type A: Initialization and anticollision.
shivanandgowdakr 0:f0aa9cbf7f0e 23 *
shivanandgowdakr 0:f0aa9cbf7f0e 24 * If only the PICC UID is wanted, the above documents has all the needed information.
shivanandgowdakr 0:f0aa9cbf7f0e 25 * To read and write from MIFARE PICCs, the MIFARE protocol is used after the PICC has been selected.
shivanandgowdakr 0:f0aa9cbf7f0e 26 * The MIFARE Classic chips and protocol is described in the datasheets:
shivanandgowdakr 0:f0aa9cbf7f0e 27 * 1K: http://www.nxp.com/documents/data_sheet/MF1S503x.pdf
shivanandgowdakr 0:f0aa9cbf7f0e 28 * 4K: http://www.nxp.com/documents/data_sheet/MF1S703x.pdf
shivanandgowdakr 0:f0aa9cbf7f0e 29 * Mini: http://www.idcardmarket.com/download/mifare_S20_datasheet.pdf
shivanandgowdakr 0:f0aa9cbf7f0e 30 * The MIFARE Ultralight chip and protocol is described in the datasheets:
shivanandgowdakr 0:f0aa9cbf7f0e 31 * Ultralight: http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf
shivanandgowdakr 0:f0aa9cbf7f0e 32 * Ultralight C: http://www.nxp.com/documents/short_data_sheet/MF0ICU2_SDS.pdf
shivanandgowdakr 0:f0aa9cbf7f0e 33 *
shivanandgowdakr 0:f0aa9cbf7f0e 34 * MIFARE Classic 1K (MF1S503x):
shivanandgowdakr 0:f0aa9cbf7f0e 35 * Has 16 sectors * 4 blocks/sector * 16 bytes/block = 1024 bytes.
shivanandgowdakr 0:f0aa9cbf7f0e 36 * The blocks are numbered 0-63.
shivanandgowdakr 0:f0aa9cbf7f0e 37 * Block 3 in each sector is the Sector Trailer. See http://www.nxp.com/documents/data_sheet/MF1S503x.pdf sections 8.6 and 8.7:
shivanandgowdakr 0:f0aa9cbf7f0e 38 * Bytes 0-5: Key A
shivanandgowdakr 0:f0aa9cbf7f0e 39 * Bytes 6-8: Access Bits
shivanandgowdakr 0:f0aa9cbf7f0e 40 * Bytes 9: User data
shivanandgowdakr 0:f0aa9cbf7f0e 41 * Bytes 10-15: Key B (or user data)
shivanandgowdakr 0:f0aa9cbf7f0e 42 * Block 0 is read only manufacturer data.
shivanandgowdakr 0:f0aa9cbf7f0e 43 * To access a block, an authentication using a key from the block's sector must be performed first.
shivanandgowdakr 0:f0aa9cbf7f0e 44 * Example: To read from block 10, first authenticate using a key from sector 3 (blocks 8-11).
shivanandgowdakr 0:f0aa9cbf7f0e 45 * All keys are set to FFFFFFFFFFFFh at chip delivery.
shivanandgowdakr 0:f0aa9cbf7f0e 46 * Warning: Please read section 8.7 "Memory Access". It includes this text: if the PICC detects a format violation the whole sector is irreversibly blocked.
shivanandgowdakr 0:f0aa9cbf7f0e 47 * To use a block in "value block" mode (for Increment/Decrement operations) you need to change the sector trailer. Use PICC_SetAccessBits() to calculate the bit patterns.
shivanandgowdakr 0:f0aa9cbf7f0e 48 * MIFARE Classic 4K (MF1S703x):
shivanandgowdakr 0:f0aa9cbf7f0e 49 * Has (32 sectors * 4 blocks/sector + 8 sectors * 16 blocks/sector) * 16 bytes/block = 4096 bytes.
shivanandgowdakr 0:f0aa9cbf7f0e 50 * The blocks are numbered 0-255.
shivanandgowdakr 0:f0aa9cbf7f0e 51 * The last block in each sector is the Sector Trailer like above.
shivanandgowdakr 0:f0aa9cbf7f0e 52 * MIFARE Classic Mini (MF1 IC S20):
shivanandgowdakr 0:f0aa9cbf7f0e 53 * Has 5 sectors * 4 blocks/sector * 16 bytes/block = 320 bytes.
shivanandgowdakr 0:f0aa9cbf7f0e 54 * The blocks are numbered 0-19.
shivanandgowdakr 0:f0aa9cbf7f0e 55 * The last block in each sector is the Sector Trailer like above.
shivanandgowdakr 0:f0aa9cbf7f0e 56 *
shivanandgowdakr 0:f0aa9cbf7f0e 57 * MIFARE Ultralight (MF0ICU1):
shivanandgowdakr 0:f0aa9cbf7f0e 58 * Has 16 pages of 4 bytes = 64 bytes.
shivanandgowdakr 0:f0aa9cbf7f0e 59 * Pages 0 + 1 is used for the 7-byte UID.
shivanandgowdakr 0:f0aa9cbf7f0e 60 * Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
shivanandgowdakr 0:f0aa9cbf7f0e 61 * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
shivanandgowdakr 0:f0aa9cbf7f0e 62 * Pages 4-15 are read/write unless blocked by the lock bytes in page 2.
shivanandgowdakr 0:f0aa9cbf7f0e 63 * MIFARE Ultralight C (MF0ICU2):
shivanandgowdakr 0:f0aa9cbf7f0e 64 * Has 48 pages of 4 bytes = 64 bytes.
shivanandgowdakr 0:f0aa9cbf7f0e 65 * Pages 0 + 1 is used for the 7-byte UID.
shivanandgowdakr 0:f0aa9cbf7f0e 66 * Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
shivanandgowdakr 0:f0aa9cbf7f0e 67 * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
shivanandgowdakr 0:f0aa9cbf7f0e 68 * Pages 4-39 are read/write unless blocked by the lock bytes in page 2.
shivanandgowdakr 0:f0aa9cbf7f0e 69 * Page 40 Lock bytes
shivanandgowdakr 0:f0aa9cbf7f0e 70 * Page 41 16 bit one way counter
shivanandgowdakr 0:f0aa9cbf7f0e 71 * Pages 42-43 Authentication configuration
shivanandgowdakr 0:f0aa9cbf7f0e 72 * Pages 44-47 Authentication key
shivanandgowdakr 0:f0aa9cbf7f0e 73 */
shivanandgowdakr 0:f0aa9cbf7f0e 74 #ifndef MFRC522_h
shivanandgowdakr 0:f0aa9cbf7f0e 75 #define MFRC522_h
shivanandgowdakr 0:f0aa9cbf7f0e 76
shivanandgowdakr 0:f0aa9cbf7f0e 77 #include "mbed.h"
shivanandgowdakr 0:f0aa9cbf7f0e 78
shivanandgowdakr 0:f0aa9cbf7f0e 79 /**
shivanandgowdakr 0:f0aa9cbf7f0e 80 * MFRC522 example
shivanandgowdakr 0:f0aa9cbf7f0e 81 *
shivanandgowdakr 0:f0aa9cbf7f0e 82 * @code
shivanandgowdakr 0:f0aa9cbf7f0e 83 * #include "mbed.h"
shivanandgowdakr 0:f0aa9cbf7f0e 84 * #include "MFRC522.h"
shivanandgowdakr 0:f0aa9cbf7f0e 85 *
shivanandgowdakr 0:f0aa9cbf7f0e 86 * //KL25Z Pins for MFRC522 SPI interface
shivanandgowdakr 0:f0aa9cbf7f0e 87 * #define SPI_MOSI PTC6
shivanandgowdakr 0:f0aa9cbf7f0e 88 * #define SPI_MISO PTC7
shivanandgowdakr 0:f0aa9cbf7f0e 89 * #define SPI_SCLK PTC5
shivanandgowdakr 0:f0aa9cbf7f0e 90 * #define SPI_CS PTC4
shivanandgowdakr 0:f0aa9cbf7f0e 91 * // KL25Z Pin for MFRC522 reset
shivanandgowdakr 0:f0aa9cbf7f0e 92 * #define MF_RESET PTC3
shivanandgowdakr 0:f0aa9cbf7f0e 93 * // KL25Z Pins for Debug UART port
shivanandgowdakr 0:f0aa9cbf7f0e 94 * #define UART_RX PTA1
shivanandgowdakr 0:f0aa9cbf7f0e 95 * #define UART_TX PTA2
shivanandgowdakr 0:f0aa9cbf7f0e 96 *
shivanandgowdakr 0:f0aa9cbf7f0e 97 * DigitalOut LedRed (LED_RED);
shivanandgowdakr 0:f0aa9cbf7f0e 98 * DigitalOut LedGreen (LED_GREEN);
shivanandgowdakr 0:f0aa9cbf7f0e 99 *
shivanandgowdakr 0:f0aa9cbf7f0e 100 * Serial DebugUART(UART_TX, UART_RX);
shivanandgowdakr 0:f0aa9cbf7f0e 101 * MFRC522 RfChip (SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_CS, MF_RESET);
shivanandgowdakr 0:f0aa9cbf7f0e 102 *
shivanandgowdakr 0:f0aa9cbf7f0e 103 * int main(void) {
shivanandgowdakr 0:f0aa9cbf7f0e 104 * // Set debug UART speed
shivanandgowdakr 0:f0aa9cbf7f0e 105 * DebugUART.baud(115200);
shivanandgowdakr 0:f0aa9cbf7f0e 106 *
shivanandgowdakr 0:f0aa9cbf7f0e 107 * // Init. RC522 Chip
shivanandgowdakr 0:f0aa9cbf7f0e 108 * RfChip.PCD_Init();
shivanandgowdakr 0:f0aa9cbf7f0e 109 *
shivanandgowdakr 0:f0aa9cbf7f0e 110 * while (true) {
shivanandgowdakr 0:f0aa9cbf7f0e 111 * LedRed = 1;
shivanandgowdakr 0:f0aa9cbf7f0e 112 * LedGreen = 1;
shivanandgowdakr 0:f0aa9cbf7f0e 113 *
shivanandgowdakr 0:f0aa9cbf7f0e 114 * // Look for new cards
shivanandgowdakr 0:f0aa9cbf7f0e 115 * if ( ! RfChip.PICC_IsNewCardPresent())
shivanandgowdakr 0:f0aa9cbf7f0e 116 * {
shivanandgowdakr 0:f0aa9cbf7f0e 117 * wait_ms(500);
shivanandgowdakr 0:f0aa9cbf7f0e 118 * continue;
shivanandgowdakr 0:f0aa9cbf7f0e 119 * }
shivanandgowdakr 0:f0aa9cbf7f0e 120 *
shivanandgowdakr 0:f0aa9cbf7f0e 121 * LedRed = 0;
shivanandgowdakr 0:f0aa9cbf7f0e 122 *
shivanandgowdakr 0:f0aa9cbf7f0e 123 * // Select one of the cards
shivanandgowdakr 0:f0aa9cbf7f0e 124 * if ( ! RfChip.PICC_ReadCardSerial())
shivanandgowdakr 0:f0aa9cbf7f0e 125 * {
shivanandgowdakr 0:f0aa9cbf7f0e 126 * wait_ms(500);
shivanandgowdakr 0:f0aa9cbf7f0e 127 * continue;
shivanandgowdakr 0:f0aa9cbf7f0e 128 * }
shivanandgowdakr 0:f0aa9cbf7f0e 129 *
shivanandgowdakr 0:f0aa9cbf7f0e 130 * LedRed = 1;
shivanandgowdakr 0:f0aa9cbf7f0e 131 * LedGreen = 0;
shivanandgowdakr 0:f0aa9cbf7f0e 132 *
shivanandgowdakr 0:f0aa9cbf7f0e 133 * // Print Card UID
shivanandgowdakr 0:f0aa9cbf7f0e 134 * printf("Card UID: ");
shivanandgowdakr 0:f0aa9cbf7f0e 135 * for (uint8_t i = 0; i < RfChip.uid.size; i++)
shivanandgowdakr 0:f0aa9cbf7f0e 136 * {
shivanandgowdakr 0:f0aa9cbf7f0e 137 * printf(" %X02", RfChip.uid.uidByte[i]);
shivanandgowdakr 0:f0aa9cbf7f0e 138 * }
shivanandgowdakr 0:f0aa9cbf7f0e 139 * printf("\n\r");
shivanandgowdakr 0:f0aa9cbf7f0e 140 *
shivanandgowdakr 0:f0aa9cbf7f0e 141 * // Print Card type
shivanandgowdakr 0:f0aa9cbf7f0e 142 * uint8_t piccType = RfChip.PICC_GetType(RfChip.uid.sak);
shivanandgowdakr 0:f0aa9cbf7f0e 143 * printf("PICC Type: %s \n\r", RfChip.PICC_GetTypeName(piccType));
shivanandgowdakr 0:f0aa9cbf7f0e 144 * wait_ms(1000);
shivanandgowdakr 0:f0aa9cbf7f0e 145 * }
shivanandgowdakr 0:f0aa9cbf7f0e 146 * }
shivanandgowdakr 0:f0aa9cbf7f0e 147 * @endcode
shivanandgowdakr 0:f0aa9cbf7f0e 148 */
shivanandgowdakr 0:f0aa9cbf7f0e 149
shivanandgowdakr 0:f0aa9cbf7f0e 150 class MFRC522 {
shivanandgowdakr 0:f0aa9cbf7f0e 151 public:
shivanandgowdakr 0:f0aa9cbf7f0e 152
shivanandgowdakr 0:f0aa9cbf7f0e 153 /**
shivanandgowdakr 0:f0aa9cbf7f0e 154 * MFRC522 registers (described in chapter 9 of the datasheet).
shivanandgowdakr 0:f0aa9cbf7f0e 155 * When using SPI all addresses are shifted one bit left in the "SPI address byte" (section 8.1.2.3)
shivanandgowdakr 0:f0aa9cbf7f0e 156 */
shivanandgowdakr 0:f0aa9cbf7f0e 157 enum PCD_Register {
shivanandgowdakr 0:f0aa9cbf7f0e 158 // Page 0: Command and status
shivanandgowdakr 0:f0aa9cbf7f0e 159 // 0x00 // reserved for future use
shivanandgowdakr 0:f0aa9cbf7f0e 160 CommandReg = 0x01 << 1, // starts and stops command execution
shivanandgowdakr 0:f0aa9cbf7f0e 161 ComIEnReg = 0x02 << 1, // enable and disable interrupt request control bits
shivanandgowdakr 0:f0aa9cbf7f0e 162 DivIEnReg = 0x03 << 1, // enable and disable interrupt request control bits
shivanandgowdakr 0:f0aa9cbf7f0e 163 ComIrqReg = 0x04 << 1, // interrupt request bits
shivanandgowdakr 0:f0aa9cbf7f0e 164 DivIrqReg = 0x05 << 1, // interrupt request bits
shivanandgowdakr 0:f0aa9cbf7f0e 165 ErrorReg = 0x06 << 1, // error bits showing the error status of the last command executed
shivanandgowdakr 0:f0aa9cbf7f0e 166 Status1Reg = 0x07 << 1, // communication status bits
shivanandgowdakr 0:f0aa9cbf7f0e 167 Status2Reg = 0x08 << 1, // receiver and transmitter status bits
shivanandgowdakr 0:f0aa9cbf7f0e 168 FIFODataReg = 0x09 << 1, // input and output of 64 byte FIFO buffer
shivanandgowdakr 0:f0aa9cbf7f0e 169 FIFOLevelReg = 0x0A << 1, // number of bytes stored in the FIFO buffer
shivanandgowdakr 0:f0aa9cbf7f0e 170 WaterLevelReg = 0x0B << 1, // level for FIFO underflow and overflow warning
shivanandgowdakr 0:f0aa9cbf7f0e 171 ControlReg = 0x0C << 1, // miscellaneous control registers
shivanandgowdakr 0:f0aa9cbf7f0e 172 BitFramingReg = 0x0D << 1, // adjustments for bit-oriented frames
shivanandgowdakr 0:f0aa9cbf7f0e 173 CollReg = 0x0E << 1, // bit position of the first bit-collision detected on the RF interface
shivanandgowdakr 0:f0aa9cbf7f0e 174 // 0x0F // reserved for future use
shivanandgowdakr 0:f0aa9cbf7f0e 175
shivanandgowdakr 0:f0aa9cbf7f0e 176 // Page 1:Command
shivanandgowdakr 0:f0aa9cbf7f0e 177 // 0x10 // reserved for future use
shivanandgowdakr 0:f0aa9cbf7f0e 178 ModeReg = 0x11 << 1, // defines general modes for transmitting and receiving
shivanandgowdakr 0:f0aa9cbf7f0e 179 TxModeReg = 0x12 << 1, // defines transmission data rate and framing
shivanandgowdakr 0:f0aa9cbf7f0e 180 RxModeReg = 0x13 << 1, // defines reception data rate and framing
shivanandgowdakr 0:f0aa9cbf7f0e 181 TxControlReg = 0x14 << 1, // controls the logical behavior of the antenna driver pins TX1 and TX2
shivanandgowdakr 0:f0aa9cbf7f0e 182 TxASKReg = 0x15 << 1, // controls the setting of the transmission modulation
shivanandgowdakr 0:f0aa9cbf7f0e 183 TxSelReg = 0x16 << 1, // selects the internal sources for the antenna driver
shivanandgowdakr 0:f0aa9cbf7f0e 184 RxSelReg = 0x17 << 1, // selects internal receiver settings
shivanandgowdakr 0:f0aa9cbf7f0e 185 RxThresholdReg = 0x18 << 1, // selects thresholds for the bit decoder
shivanandgowdakr 0:f0aa9cbf7f0e 186 DemodReg = 0x19 << 1, // defines demodulator settings
shivanandgowdakr 0:f0aa9cbf7f0e 187 // 0x1A // reserved for future use
shivanandgowdakr 0:f0aa9cbf7f0e 188 // 0x1B // reserved for future use
shivanandgowdakr 0:f0aa9cbf7f0e 189 MfTxReg = 0x1C << 1, // controls some MIFARE communication transmit parameters
shivanandgowdakr 0:f0aa9cbf7f0e 190 MfRxReg = 0x1D << 1, // controls some MIFARE communication receive parameters
shivanandgowdakr 0:f0aa9cbf7f0e 191 // 0x1E // reserved for future use
shivanandgowdakr 0:f0aa9cbf7f0e 192 SerialSpeedReg = 0x1F << 1, // selects the speed of the serial UART interface
shivanandgowdakr 0:f0aa9cbf7f0e 193
shivanandgowdakr 0:f0aa9cbf7f0e 194 // Page 2: Configuration
shivanandgowdakr 0:f0aa9cbf7f0e 195 // 0x20 // reserved for future use
shivanandgowdakr 0:f0aa9cbf7f0e 196 CRCResultRegH = 0x21 << 1, // shows the MSB and LSB values of the CRC calculation
shivanandgowdakr 0:f0aa9cbf7f0e 197 CRCResultRegL = 0x22 << 1,
shivanandgowdakr 0:f0aa9cbf7f0e 198 // 0x23 // reserved for future use
shivanandgowdakr 0:f0aa9cbf7f0e 199 ModWidthReg = 0x24 << 1, // controls the ModWidth setting?
shivanandgowdakr 0:f0aa9cbf7f0e 200 // 0x25 // reserved for future use
shivanandgowdakr 0:f0aa9cbf7f0e 201 RFCfgReg = 0x26 << 1, // configures the receiver gain
shivanandgowdakr 0:f0aa9cbf7f0e 202 GsNReg = 0x27 << 1, // selects the conductance of the antenna driver pins TX1 and TX2 for modulation
shivanandgowdakr 0:f0aa9cbf7f0e 203 CWGsPReg = 0x28 << 1, // defines the conductance of the p-driver output during periods of no modulation
shivanandgowdakr 0:f0aa9cbf7f0e 204 ModGsPReg = 0x29 << 1, // defines the conductance of the p-driver output during periods of modulation
shivanandgowdakr 0:f0aa9cbf7f0e 205 TModeReg = 0x2A << 1, // defines settings for the internal timer
shivanandgowdakr 0:f0aa9cbf7f0e 206 TPrescalerReg = 0x2B << 1, // the lower 8 bits of the TPrescaler value. The 4 high bits are in TModeReg.
shivanandgowdakr 0:f0aa9cbf7f0e 207 TReloadRegH = 0x2C << 1, // defines the 16-bit timer reload value
shivanandgowdakr 0:f0aa9cbf7f0e 208 TReloadRegL = 0x2D << 1,
shivanandgowdakr 0:f0aa9cbf7f0e 209 TCntValueRegH = 0x2E << 1, // shows the 16-bit timer value
shivanandgowdakr 0:f0aa9cbf7f0e 210 TCntValueRegL = 0x2F << 1,
shivanandgowdakr 0:f0aa9cbf7f0e 211
shivanandgowdakr 0:f0aa9cbf7f0e 212 // Page 3:Test Registers
shivanandgowdakr 0:f0aa9cbf7f0e 213 // 0x30 // reserved for future use
shivanandgowdakr 0:f0aa9cbf7f0e 214 TestSel1Reg = 0x31 << 1, // general test signal configuration
shivanandgowdakr 0:f0aa9cbf7f0e 215 TestSel2Reg = 0x32 << 1, // general test signal configuration
shivanandgowdakr 0:f0aa9cbf7f0e 216 TestPinEnReg = 0x33 << 1, // enables pin output driver on pins D1 to D7
shivanandgowdakr 0:f0aa9cbf7f0e 217 TestPinValueReg = 0x34 << 1, // defines the values for D1 to D7 when it is used as an I/O bus
shivanandgowdakr 0:f0aa9cbf7f0e 218 TestBusReg = 0x35 << 1, // shows the status of the internal test bus
shivanandgowdakr 0:f0aa9cbf7f0e 219 AutoTestReg = 0x36 << 1, // controls the digital self test
shivanandgowdakr 0:f0aa9cbf7f0e 220 VersionReg = 0x37 << 1, // shows the software version
shivanandgowdakr 0:f0aa9cbf7f0e 221 AnalogTestReg = 0x38 << 1, // controls the pins AUX1 and AUX2
shivanandgowdakr 0:f0aa9cbf7f0e 222 TestDAC1Reg = 0x39 << 1, // defines the test value for TestDAC1
shivanandgowdakr 0:f0aa9cbf7f0e 223 TestDAC2Reg = 0x3A << 1, // defines the test value for TestDAC2
shivanandgowdakr 0:f0aa9cbf7f0e 224 TestADCReg = 0x3B << 1 // shows the value of ADC I and Q channels
shivanandgowdakr 0:f0aa9cbf7f0e 225 // 0x3C // reserved for production tests
shivanandgowdakr 0:f0aa9cbf7f0e 226 // 0x3D // reserved for production tests
shivanandgowdakr 0:f0aa9cbf7f0e 227 // 0x3E // reserved for production tests
shivanandgowdakr 0:f0aa9cbf7f0e 228 // 0x3F // reserved for production tests
shivanandgowdakr 0:f0aa9cbf7f0e 229 };
shivanandgowdakr 0:f0aa9cbf7f0e 230
shivanandgowdakr 0:f0aa9cbf7f0e 231 // MFRC522 commands Described in chapter 10 of the datasheet.
shivanandgowdakr 0:f0aa9cbf7f0e 232 enum PCD_Command {
shivanandgowdakr 0:f0aa9cbf7f0e 233 PCD_Idle = 0x00, // no action, cancels current command execution
shivanandgowdakr 0:f0aa9cbf7f0e 234 PCD_Mem = 0x01, // stores 25 bytes into the internal buffer
shivanandgowdakr 0:f0aa9cbf7f0e 235 PCD_GenerateRandomID = 0x02, // generates a 10-byte random ID number
shivanandgowdakr 0:f0aa9cbf7f0e 236 PCD_CalcCRC = 0x03, // activates the CRC coprocessor or performs a self test
shivanandgowdakr 0:f0aa9cbf7f0e 237 PCD_Transmit = 0x04, // transmits data from the FIFO buffer
shivanandgowdakr 0:f0aa9cbf7f0e 238 PCD_NoCmdChange = 0x07, // no command change, can be used to modify the CommandReg register bits without affecting the command, for example, the PowerDown bit
shivanandgowdakr 0:f0aa9cbf7f0e 239 PCD_Receive = 0x08, // activates the receiver circuits
shivanandgowdakr 0:f0aa9cbf7f0e 240 PCD_Transceive = 0x0C, // transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission
shivanandgowdakr 0:f0aa9cbf7f0e 241 PCD_MFAuthent = 0x0E, // performs the MIFARE standard authentication as a reader
shivanandgowdakr 0:f0aa9cbf7f0e 242 PCD_SoftReset = 0x0F // resets the MFRC522
shivanandgowdakr 0:f0aa9cbf7f0e 243 };
shivanandgowdakr 0:f0aa9cbf7f0e 244
shivanandgowdakr 0:f0aa9cbf7f0e 245 // Commands sent to the PICC.
shivanandgowdakr 0:f0aa9cbf7f0e 246 enum PICC_Command {
shivanandgowdakr 0:f0aa9cbf7f0e 247 // The commands used by the PCD to manage communication with several PICCs (ISO 14443-3, Type A, section 6.4)
shivanandgowdakr 0:f0aa9cbf7f0e 248 PICC_CMD_REQA = 0x26, // REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
shivanandgowdakr 0:f0aa9cbf7f0e 249 PICC_CMD_WUPA = 0x52, // Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
shivanandgowdakr 0:f0aa9cbf7f0e 250 PICC_CMD_CT = 0x88, // Cascade Tag. Not really a command, but used during anti collision.
shivanandgowdakr 0:f0aa9cbf7f0e 251 PICC_CMD_SEL_CL1 = 0x93, // Anti collision/Select, Cascade Level 1
shivanandgowdakr 0:f0aa9cbf7f0e 252 PICC_CMD_SEL_CL2 = 0x95, // Anti collision/Select, Cascade Level 1
shivanandgowdakr 0:f0aa9cbf7f0e 253 PICC_CMD_SEL_CL3 = 0x97, // Anti collision/Select, Cascade Level 1
shivanandgowdakr 0:f0aa9cbf7f0e 254 PICC_CMD_HLTA = 0x50, // HaLT command, Type A. Instructs an ACTIVE PICC to go to state HALT.
shivanandgowdakr 0:f0aa9cbf7f0e 255
shivanandgowdakr 0:f0aa9cbf7f0e 256 // The commands used for MIFARE Classic (from http://www.nxp.com/documents/data_sheet/MF1S503x.pdf, Section 9)
shivanandgowdakr 0:f0aa9cbf7f0e 257 // Use PCD_MFAuthent to authenticate access to a sector, then use these commands to read/write/modify the blocks on the sector.
shivanandgowdakr 0:f0aa9cbf7f0e 258 // The read/write commands can also be used for MIFARE Ultralight.
shivanandgowdakr 0:f0aa9cbf7f0e 259 PICC_CMD_MF_AUTH_KEY_A = 0x60, // Perform authentication with Key A
shivanandgowdakr 0:f0aa9cbf7f0e 260 PICC_CMD_MF_AUTH_KEY_B = 0x61, // Perform authentication with Key B
shivanandgowdakr 0:f0aa9cbf7f0e 261 PICC_CMD_MF_READ = 0x30, // Reads one 16 byte block from the authenticated sector of the PICC. Also used for MIFARE Ultralight.
shivanandgowdakr 0:f0aa9cbf7f0e 262 PICC_CMD_MF_WRITE = 0xA0, // Writes one 16 byte block to the authenticated sector of the PICC. Called "COMPATIBILITY WRITE" for MIFARE Ultralight.
shivanandgowdakr 0:f0aa9cbf7f0e 263 PICC_CMD_MF_DECREMENT = 0xC0, // Decrements the contents of a block and stores the result in the internal data register.
shivanandgowdakr 0:f0aa9cbf7f0e 264 PICC_CMD_MF_INCREMENT = 0xC1, // Increments the contents of a block and stores the result in the internal data register.
shivanandgowdakr 0:f0aa9cbf7f0e 265 PICC_CMD_MF_RESTORE = 0xC2, // Reads the contents of a block into the internal data register.
shivanandgowdakr 0:f0aa9cbf7f0e 266 PICC_CMD_MF_TRANSFER = 0xB0, // Writes the contents of the internal data register to a block.
shivanandgowdakr 0:f0aa9cbf7f0e 267
shivanandgowdakr 0:f0aa9cbf7f0e 268 // The commands used for MIFARE Ultralight (from http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf, Section 8.6)
shivanandgowdakr 0:f0aa9cbf7f0e 269 // The PICC_CMD_MF_READ and PICC_CMD_MF_WRITE can also be used for MIFARE Ultralight.
shivanandgowdakr 0:f0aa9cbf7f0e 270 PICC_CMD_UL_WRITE = 0xA2 // Writes one 4 byte page to the PICC.
shivanandgowdakr 0:f0aa9cbf7f0e 271 };
shivanandgowdakr 0:f0aa9cbf7f0e 272
shivanandgowdakr 0:f0aa9cbf7f0e 273 // MIFARE constants that does not fit anywhere else
shivanandgowdakr 0:f0aa9cbf7f0e 274 enum MIFARE_Misc {
shivanandgowdakr 0:f0aa9cbf7f0e 275 MF_ACK = 0xA, // The MIFARE Classic uses a 4 bit ACK/NAK. Any other value than 0xA is NAK.
shivanandgowdakr 0:f0aa9cbf7f0e 276 MF_KEY_SIZE = 6 // A Mifare Crypto1 key is 6 bytes.
shivanandgowdakr 0:f0aa9cbf7f0e 277 };
shivanandgowdakr 0:f0aa9cbf7f0e 278
shivanandgowdakr 0:f0aa9cbf7f0e 279 // PICC types we can detect. Remember to update PICC_GetTypeName() if you add more.
shivanandgowdakr 0:f0aa9cbf7f0e 280 enum PICC_Type {
shivanandgowdakr 0:f0aa9cbf7f0e 281 PICC_TYPE_UNKNOWN = 0,
shivanandgowdakr 0:f0aa9cbf7f0e 282 PICC_TYPE_ISO_14443_4 = 1, // PICC compliant with ISO/IEC 14443-4
shivanandgowdakr 0:f0aa9cbf7f0e 283 PICC_TYPE_ISO_18092 = 2, // PICC compliant with ISO/IEC 18092 (NFC)
shivanandgowdakr 0:f0aa9cbf7f0e 284 PICC_TYPE_MIFARE_MINI = 3, // MIFARE Classic protocol, 320 bytes
shivanandgowdakr 0:f0aa9cbf7f0e 285 PICC_TYPE_MIFARE_1K = 4, // MIFARE Classic protocol, 1KB
shivanandgowdakr 0:f0aa9cbf7f0e 286 PICC_TYPE_MIFARE_4K = 5, // MIFARE Classic protocol, 4KB
shivanandgowdakr 0:f0aa9cbf7f0e 287 PICC_TYPE_MIFARE_UL = 6, // MIFARE Ultralight or Ultralight C
shivanandgowdakr 0:f0aa9cbf7f0e 288 PICC_TYPE_MIFARE_PLUS = 7, // MIFARE Plus
shivanandgowdakr 0:f0aa9cbf7f0e 289 PICC_TYPE_TNP3XXX = 8, // Only mentioned in NXP AN 10833 MIFARE Type Identification Procedure
shivanandgowdakr 0:f0aa9cbf7f0e 290 PICC_TYPE_NOT_COMPLETE = 255 // SAK indicates UID is not complete.
shivanandgowdakr 0:f0aa9cbf7f0e 291 };
shivanandgowdakr 0:f0aa9cbf7f0e 292
shivanandgowdakr 0:f0aa9cbf7f0e 293 // Return codes from the functions in this class. Remember to update GetStatusCodeName() if you add more.
shivanandgowdakr 0:f0aa9cbf7f0e 294 enum StatusCode {
shivanandgowdakr 0:f0aa9cbf7f0e 295 STATUS_OK = 1, // Success
shivanandgowdakr 0:f0aa9cbf7f0e 296 STATUS_ERROR = 2, // Error in communication
shivanandgowdakr 0:f0aa9cbf7f0e 297 STATUS_COLLISION = 3, // Collision detected
shivanandgowdakr 0:f0aa9cbf7f0e 298 STATUS_TIMEOUT = 4, // Timeout in communication.
shivanandgowdakr 0:f0aa9cbf7f0e 299 STATUS_NO_ROOM = 5, // A buffer is not big enough.
shivanandgowdakr 0:f0aa9cbf7f0e 300 STATUS_INTERNAL_ERROR = 6, // Internal error in the code. Should not happen ;-)
shivanandgowdakr 0:f0aa9cbf7f0e 301 STATUS_INVALID = 7, // Invalid argument.
shivanandgowdakr 0:f0aa9cbf7f0e 302 STATUS_CRC_WRONG = 8, // The CRC_A does not match
shivanandgowdakr 0:f0aa9cbf7f0e 303 STATUS_MIFARE_NACK = 9 // A MIFARE PICC responded with NAK.
shivanandgowdakr 0:f0aa9cbf7f0e 304 };
shivanandgowdakr 0:f0aa9cbf7f0e 305
shivanandgowdakr 0:f0aa9cbf7f0e 306 // A struct used for passing the UID of a PICC.
shivanandgowdakr 0:f0aa9cbf7f0e 307 typedef struct {
shivanandgowdakr 0:f0aa9cbf7f0e 308 uint8_t size; // Number of bytes in the UID. 4, 7 or 10.
shivanandgowdakr 0:f0aa9cbf7f0e 309 uint8_t uidByte[10];
shivanandgowdakr 0:f0aa9cbf7f0e 310 uint8_t sak; // The SAK (Select acknowledge) byte returned from the PICC after successful selection.
shivanandgowdakr 0:f0aa9cbf7f0e 311 } Uid;
shivanandgowdakr 0:f0aa9cbf7f0e 312
shivanandgowdakr 0:f0aa9cbf7f0e 313 // A struct used for passing a MIFARE Crypto1 key
shivanandgowdakr 0:f0aa9cbf7f0e 314 typedef struct {
shivanandgowdakr 0:f0aa9cbf7f0e 315 uint8_t keyByte[MF_KEY_SIZE];
shivanandgowdakr 0:f0aa9cbf7f0e 316 } MIFARE_Key;
shivanandgowdakr 0:f0aa9cbf7f0e 317
shivanandgowdakr 0:f0aa9cbf7f0e 318 // Member variables
shivanandgowdakr 0:f0aa9cbf7f0e 319 Uid uid; // Used by PICC_ReadCardSerial().
shivanandgowdakr 0:f0aa9cbf7f0e 320
shivanandgowdakr 0:f0aa9cbf7f0e 321 // Size of the MFRC522 FIFO
shivanandgowdakr 0:f0aa9cbf7f0e 322 static const uint8_t FIFO_SIZE = 64; // The FIFO is 64 bytes.
shivanandgowdakr 0:f0aa9cbf7f0e 323
shivanandgowdakr 0:f0aa9cbf7f0e 324 /**
shivanandgowdakr 0:f0aa9cbf7f0e 325 * MFRC522 constructor
shivanandgowdakr 0:f0aa9cbf7f0e 326 *
shivanandgowdakr 0:f0aa9cbf7f0e 327 * @param mosi SPI MOSI pin
shivanandgowdakr 0:f0aa9cbf7f0e 328 * @param miso SPI MISO pin
shivanandgowdakr 0:f0aa9cbf7f0e 329 * @param sclk SPI SCLK pin
shivanandgowdakr 0:f0aa9cbf7f0e 330 * @param cs SPI CS pin
shivanandgowdakr 0:f0aa9cbf7f0e 331 * @param reset Reset pin
shivanandgowdakr 0:f0aa9cbf7f0e 332 */
shivanandgowdakr 0:f0aa9cbf7f0e 333 MFRC522(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName reset);
shivanandgowdakr 0:f0aa9cbf7f0e 334
shivanandgowdakr 0:f0aa9cbf7f0e 335 /**
shivanandgowdakr 0:f0aa9cbf7f0e 336 * MFRC522 destructor
shivanandgowdakr 0:f0aa9cbf7f0e 337 */
shivanandgowdakr 0:f0aa9cbf7f0e 338 ~MFRC522();
shivanandgowdakr 0:f0aa9cbf7f0e 339
shivanandgowdakr 0:f0aa9cbf7f0e 340
shivanandgowdakr 0:f0aa9cbf7f0e 341 // ************************************************************************************
shivanandgowdakr 0:f0aa9cbf7f0e 342 //! @name Functions for manipulating the MFRC522
shivanandgowdakr 0:f0aa9cbf7f0e 343 // ************************************************************************************
shivanandgowdakr 0:f0aa9cbf7f0e 344 //@{
shivanandgowdakr 0:f0aa9cbf7f0e 345
shivanandgowdakr 0:f0aa9cbf7f0e 346 /**
shivanandgowdakr 0:f0aa9cbf7f0e 347 * Initializes the MFRC522 chip.
shivanandgowdakr 0:f0aa9cbf7f0e 348 */
shivanandgowdakr 0:f0aa9cbf7f0e 349 void PCD_Init (void);
shivanandgowdakr 0:f0aa9cbf7f0e 350
shivanandgowdakr 0:f0aa9cbf7f0e 351 /**
shivanandgowdakr 0:f0aa9cbf7f0e 352 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
shivanandgowdakr 0:f0aa9cbf7f0e 353 */
shivanandgowdakr 0:f0aa9cbf7f0e 354 void PCD_Reset (void);
shivanandgowdakr 0:f0aa9cbf7f0e 355
shivanandgowdakr 0:f0aa9cbf7f0e 356 /**
shivanandgowdakr 0:f0aa9cbf7f0e 357 * Turns the antenna on by enabling pins TX1 and TX2.
shivanandgowdakr 0:f0aa9cbf7f0e 358 * After a reset these pins disabled.
shivanandgowdakr 0:f0aa9cbf7f0e 359 */
shivanandgowdakr 0:f0aa9cbf7f0e 360 void PCD_AntennaOn (void);
shivanandgowdakr 0:f0aa9cbf7f0e 361
shivanandgowdakr 0:f0aa9cbf7f0e 362 /**
shivanandgowdakr 0:f0aa9cbf7f0e 363 * Writes a byte to the specified register in the MFRC522 chip.
shivanandgowdakr 0:f0aa9cbf7f0e 364 * The interface is described in the datasheet section 8.1.2.
shivanandgowdakr 0:f0aa9cbf7f0e 365 *
shivanandgowdakr 0:f0aa9cbf7f0e 366 * @param reg The register to write to. One of the PCD_Register enums.
shivanandgowdakr 0:f0aa9cbf7f0e 367 * @param value The value to write.
shivanandgowdakr 0:f0aa9cbf7f0e 368 */
shivanandgowdakr 0:f0aa9cbf7f0e 369 void PCD_WriteRegister (uint8_t reg, uint8_t value);
shivanandgowdakr 0:f0aa9cbf7f0e 370
shivanandgowdakr 0:f0aa9cbf7f0e 371 /**
shivanandgowdakr 0:f0aa9cbf7f0e 372 * Writes a number of bytes to the specified register in the MFRC522 chip.
shivanandgowdakr 0:f0aa9cbf7f0e 373 * The interface is described in the datasheet section 8.1.2.
shivanandgowdakr 0:f0aa9cbf7f0e 374 *
shivanandgowdakr 0:f0aa9cbf7f0e 375 * @param reg The register to write to. One of the PCD_Register enums.
shivanandgowdakr 0:f0aa9cbf7f0e 376 * @param count The number of bytes to write to the register
shivanandgowdakr 0:f0aa9cbf7f0e 377 * @param values The values to write. Byte array.
shivanandgowdakr 0:f0aa9cbf7f0e 378 */
shivanandgowdakr 0:f0aa9cbf7f0e 379 void PCD_WriteRegister (uint8_t reg, uint8_t count, uint8_t *values);
shivanandgowdakr 0:f0aa9cbf7f0e 380
shivanandgowdakr 0:f0aa9cbf7f0e 381 /**
shivanandgowdakr 0:f0aa9cbf7f0e 382 * Reads a byte from the specified register in the MFRC522 chip.
shivanandgowdakr 0:f0aa9cbf7f0e 383 * The interface is described in the datasheet section 8.1.2.
shivanandgowdakr 0:f0aa9cbf7f0e 384 *
shivanandgowdakr 0:f0aa9cbf7f0e 385 * @param reg The register to read from. One of the PCD_Register enums.
shivanandgowdakr 0:f0aa9cbf7f0e 386 * @returns Register value
shivanandgowdakr 0:f0aa9cbf7f0e 387 */
shivanandgowdakr 0:f0aa9cbf7f0e 388 uint8_t PCD_ReadRegister (uint8_t reg);
shivanandgowdakr 0:f0aa9cbf7f0e 389
shivanandgowdakr 0:f0aa9cbf7f0e 390 /**
shivanandgowdakr 0:f0aa9cbf7f0e 391 * Reads a number of bytes from the specified register in the MFRC522 chip.
shivanandgowdakr 0:f0aa9cbf7f0e 392 * The interface is described in the datasheet section 8.1.2.
shivanandgowdakr 0:f0aa9cbf7f0e 393 *
shivanandgowdakr 0:f0aa9cbf7f0e 394 * @param reg The register to read from. One of the PCD_Register enums.
shivanandgowdakr 0:f0aa9cbf7f0e 395 * @param count The number of bytes to read.
shivanandgowdakr 0:f0aa9cbf7f0e 396 * @param values Byte array to store the values in.
shivanandgowdakr 0:f0aa9cbf7f0e 397 * @param rxAlign Only bit positions rxAlign..7 in values[0] are updated.
shivanandgowdakr 0:f0aa9cbf7f0e 398 */
shivanandgowdakr 0:f0aa9cbf7f0e 399 void PCD_ReadRegister (uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign = 0);
shivanandgowdakr 0:f0aa9cbf7f0e 400
shivanandgowdakr 0:f0aa9cbf7f0e 401 /**
shivanandgowdakr 0:f0aa9cbf7f0e 402 * Sets the bits given in mask in register reg.
shivanandgowdakr 0:f0aa9cbf7f0e 403 *
shivanandgowdakr 0:f0aa9cbf7f0e 404 * @param reg The register to update. One of the PCD_Register enums.
shivanandgowdakr 0:f0aa9cbf7f0e 405 * @param mask The bits to set.
shivanandgowdakr 0:f0aa9cbf7f0e 406 */
shivanandgowdakr 0:f0aa9cbf7f0e 407 void PCD_SetRegisterBits(uint8_t reg, uint8_t mask);
shivanandgowdakr 0:f0aa9cbf7f0e 408
shivanandgowdakr 0:f0aa9cbf7f0e 409 /**
shivanandgowdakr 0:f0aa9cbf7f0e 410 * Clears the bits given in mask from register reg.
shivanandgowdakr 0:f0aa9cbf7f0e 411 *
shivanandgowdakr 0:f0aa9cbf7f0e 412 * @param reg The register to update. One of the PCD_Register enums.
shivanandgowdakr 0:f0aa9cbf7f0e 413 * @param mask The bits to clear.
shivanandgowdakr 0:f0aa9cbf7f0e 414 */
shivanandgowdakr 0:f0aa9cbf7f0e 415 void PCD_ClrRegisterBits(uint8_t reg, uint8_t mask);
shivanandgowdakr 0:f0aa9cbf7f0e 416
shivanandgowdakr 0:f0aa9cbf7f0e 417 /**
shivanandgowdakr 0:f0aa9cbf7f0e 418 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
shivanandgowdakr 0:f0aa9cbf7f0e 419 *
shivanandgowdakr 0:f0aa9cbf7f0e 420 * @param data Pointer to the data to transfer to the FIFO for CRC calculation.
shivanandgowdakr 0:f0aa9cbf7f0e 421 * @param length The number of bytes to transfer.
shivanandgowdakr 0:f0aa9cbf7f0e 422 * @param result Pointer to result buffer. Result is written to result[0..1], low byte first.
shivanandgowdakr 0:f0aa9cbf7f0e 423 * @return STATUS_OK on success, STATUS_??? otherwise.
shivanandgowdakr 0:f0aa9cbf7f0e 424 */
shivanandgowdakr 0:f0aa9cbf7f0e 425 uint8_t PCD_CalculateCRC (uint8_t *data, uint8_t length, uint8_t *result);
shivanandgowdakr 0:f0aa9cbf7f0e 426
shivanandgowdakr 0:f0aa9cbf7f0e 427 /**
shivanandgowdakr 0:f0aa9cbf7f0e 428 * Executes the Transceive command.
shivanandgowdakr 0:f0aa9cbf7f0e 429 * CRC validation can only be done if backData and backLen are specified.
shivanandgowdakr 0:f0aa9cbf7f0e 430 *
shivanandgowdakr 0:f0aa9cbf7f0e 431 * @param sendData Pointer to the data to transfer to the FIFO.
shivanandgowdakr 0:f0aa9cbf7f0e 432 * @param sendLen Number of bytes to transfer to the FIFO.
shivanandgowdakr 0:f0aa9cbf7f0e 433 * @param backData NULL or pointer to buffer if data should be read back after executing the command.
shivanandgowdakr 0:f0aa9cbf7f0e 434 * @param backLen Max number of bytes to write to *backData. Out: The number of bytes returned.
shivanandgowdakr 0:f0aa9cbf7f0e 435 * @param validBits The number of valid bits in the last byte. 0 for 8 valid bits. Default NULL.
shivanandgowdakr 0:f0aa9cbf7f0e 436 * @param rxAlign Defines the bit position in backData[0] for the first bit received. Default 0.
shivanandgowdakr 0:f0aa9cbf7f0e 437 * @param checkCRC True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
shivanandgowdakr 0:f0aa9cbf7f0e 438 *
shivanandgowdakr 0:f0aa9cbf7f0e 439 * @return STATUS_OK on success, STATUS_??? otherwise.
shivanandgowdakr 0:f0aa9cbf7f0e 440 */
shivanandgowdakr 0:f0aa9cbf7f0e 441 uint8_t PCD_TransceiveData (uint8_t *sendData,
shivanandgowdakr 0:f0aa9cbf7f0e 442 uint8_t sendLen,
shivanandgowdakr 0:f0aa9cbf7f0e 443 uint8_t *backData,
shivanandgowdakr 0:f0aa9cbf7f0e 444 uint8_t *backLen,
shivanandgowdakr 0:f0aa9cbf7f0e 445 uint8_t *validBits = NULL,
shivanandgowdakr 0:f0aa9cbf7f0e 446 uint8_t rxAlign = 0,
shivanandgowdakr 0:f0aa9cbf7f0e 447 bool checkCRC = false);
shivanandgowdakr 0:f0aa9cbf7f0e 448
shivanandgowdakr 0:f0aa9cbf7f0e 449
shivanandgowdakr 0:f0aa9cbf7f0e 450 /**
shivanandgowdakr 0:f0aa9cbf7f0e 451 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
shivanandgowdakr 0:f0aa9cbf7f0e 452 * CRC validation can only be done if backData and backLen are specified.
shivanandgowdakr 0:f0aa9cbf7f0e 453 *
shivanandgowdakr 0:f0aa9cbf7f0e 454 * @param command The command to execute. One of the PCD_Command enums.
shivanandgowdakr 0:f0aa9cbf7f0e 455 * @param waitIRq The bits in the ComIrqReg register that signals successful completion of the command.
shivanandgowdakr 0:f0aa9cbf7f0e 456 * @param sendData Pointer to the data to transfer to the FIFO.
shivanandgowdakr 0:f0aa9cbf7f0e 457 * @param sendLen Number of bytes to transfer to the FIFO.
shivanandgowdakr 0:f0aa9cbf7f0e 458 * @param backData NULL or pointer to buffer if data should be read back after executing the command.
shivanandgowdakr 0:f0aa9cbf7f0e 459 * @param backLen In: Max number of bytes to write to *backData. Out: The number of bytes returned.
shivanandgowdakr 0:f0aa9cbf7f0e 460 * @param validBits In/Out: The number of valid bits in the last byte. 0 for 8 valid bits.
shivanandgowdakr 0:f0aa9cbf7f0e 461 * @param rxAlign In: Defines the bit position in backData[0] for the first bit received. Default 0.
shivanandgowdakr 0:f0aa9cbf7f0e 462 * @param checkCRC In: True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
shivanandgowdakr 0:f0aa9cbf7f0e 463 *
shivanandgowdakr 0:f0aa9cbf7f0e 464 * @return STATUS_OK on success, STATUS_??? otherwise.
shivanandgowdakr 0:f0aa9cbf7f0e 465 */
shivanandgowdakr 0:f0aa9cbf7f0e 466 uint8_t PCD_CommunicateWithPICC(uint8_t command,
shivanandgowdakr 0:f0aa9cbf7f0e 467 uint8_t waitIRq,
shivanandgowdakr 0:f0aa9cbf7f0e 468 uint8_t *sendData,
shivanandgowdakr 0:f0aa9cbf7f0e 469 uint8_t sendLen,
shivanandgowdakr 0:f0aa9cbf7f0e 470 uint8_t *backData = NULL,
shivanandgowdakr 0:f0aa9cbf7f0e 471 uint8_t *backLen = NULL,
shivanandgowdakr 0:f0aa9cbf7f0e 472 uint8_t *validBits = NULL,
shivanandgowdakr 0:f0aa9cbf7f0e 473 uint8_t rxAlign = 0,
shivanandgowdakr 0:f0aa9cbf7f0e 474 bool checkCRC = false);
shivanandgowdakr 0:f0aa9cbf7f0e 475
shivanandgowdakr 0:f0aa9cbf7f0e 476 /**
shivanandgowdakr 0:f0aa9cbf7f0e 477 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
shivanandgowdakr 0:f0aa9cbf7f0e 478 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
shivanandgowdakr 0:f0aa9cbf7f0e 479 *
shivanandgowdakr 0:f0aa9cbf7f0e 480 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
shivanandgowdakr 0:f0aa9cbf7f0e 481 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
shivanandgowdakr 0:f0aa9cbf7f0e 482 *
shivanandgowdakr 0:f0aa9cbf7f0e 483 * @return STATUS_OK on success, STATUS_??? otherwise.
shivanandgowdakr 0:f0aa9cbf7f0e 484 */
shivanandgowdakr 0:f0aa9cbf7f0e 485 uint8_t PICC_RequestA (uint8_t *bufferATQA, uint8_t *bufferSize);
shivanandgowdakr 0:f0aa9cbf7f0e 486
shivanandgowdakr 0:f0aa9cbf7f0e 487 /**
shivanandgowdakr 0:f0aa9cbf7f0e 488 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
shivanandgowdakr 0:f0aa9cbf7f0e 489 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
shivanandgowdakr 0:f0aa9cbf7f0e 490 *
shivanandgowdakr 0:f0aa9cbf7f0e 491 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
shivanandgowdakr 0:f0aa9cbf7f0e 492 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
shivanandgowdakr 0:f0aa9cbf7f0e 493 *
shivanandgowdakr 0:f0aa9cbf7f0e 494 * @return STATUS_OK on success, STATUS_??? otherwise.
shivanandgowdakr 0:f0aa9cbf7f0e 495 */
shivanandgowdakr 0:f0aa9cbf7f0e 496 uint8_t PICC_WakeupA (uint8_t *bufferATQA, uint8_t *bufferSize);
shivanandgowdakr 0:f0aa9cbf7f0e 497
shivanandgowdakr 0:f0aa9cbf7f0e 498 /**
shivanandgowdakr 0:f0aa9cbf7f0e 499 * Transmits REQA or WUPA commands.
shivanandgowdakr 0:f0aa9cbf7f0e 500 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
shivanandgowdakr 0:f0aa9cbf7f0e 501 *
shivanandgowdakr 0:f0aa9cbf7f0e 502 * @param command The command to send - PICC_CMD_REQA or PICC_CMD_WUPA
shivanandgowdakr 0:f0aa9cbf7f0e 503 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
shivanandgowdakr 0:f0aa9cbf7f0e 504 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
shivanandgowdakr 0:f0aa9cbf7f0e 505 *
shivanandgowdakr 0:f0aa9cbf7f0e 506 * @return STATUS_OK on success, STATUS_??? otherwise.
shivanandgowdakr 0:f0aa9cbf7f0e 507 */
shivanandgowdakr 0:f0aa9cbf7f0e 508 uint8_t PICC_REQA_or_WUPA (uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize);
shivanandgowdakr 0:f0aa9cbf7f0e 509
shivanandgowdakr 0:f0aa9cbf7f0e 510 /**
shivanandgowdakr 0:f0aa9cbf7f0e 511 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
shivanandgowdakr 0:f0aa9cbf7f0e 512 * Before calling this function the PICCs must be placed in the READY(*) state by calling PICC_RequestA() or PICC_WakeupA().
shivanandgowdakr 0:f0aa9cbf7f0e 513 * On success:
shivanandgowdakr 0:f0aa9cbf7f0e 514 * - The chosen PICC is in state ACTIVE(*) and all other PICCs have returned to state IDLE/HALT. (Figure 7 of the ISO/IEC 14443-3 draft.)
shivanandgowdakr 0:f0aa9cbf7f0e 515 * - The UID size and value of the chosen PICC is returned in *uid along with the SAK.
shivanandgowdakr 0:f0aa9cbf7f0e 516 *
shivanandgowdakr 0:f0aa9cbf7f0e 517 * A PICC UID consists of 4, 7 or 10 bytes.
shivanandgowdakr 0:f0aa9cbf7f0e 518 * Only 4 bytes can be specified in a SELECT command, so for the longer UIDs two or three iterations are used:
shivanandgowdakr 0:f0aa9cbf7f0e 519 *
shivanandgowdakr 0:f0aa9cbf7f0e 520 * UID size Number of UID bytes Cascade levels Example of PICC
shivanandgowdakr 0:f0aa9cbf7f0e 521 * ======== =================== ============== ===============
shivanandgowdakr 0:f0aa9cbf7f0e 522 * single 4 1 MIFARE Classic
shivanandgowdakr 0:f0aa9cbf7f0e 523 * double 7 2 MIFARE Ultralight
shivanandgowdakr 0:f0aa9cbf7f0e 524 * triple 10 3 Not currently in use?
shivanandgowdakr 0:f0aa9cbf7f0e 525 *
shivanandgowdakr 0:f0aa9cbf7f0e 526 *
shivanandgowdakr 0:f0aa9cbf7f0e 527 * @param uid Pointer to Uid struct. Normally output, but can also be used to supply a known UID.
shivanandgowdakr 0:f0aa9cbf7f0e 528 * @param validBits The number of known UID bits supplied in *uid. Normally 0. If set you must also supply uid->size.
shivanandgowdakr 0:f0aa9cbf7f0e 529 *
shivanandgowdakr 0:f0aa9cbf7f0e 530 * @return STATUS_OK on success, STATUS_??? otherwise.
shivanandgowdakr 0:f0aa9cbf7f0e 531 */
shivanandgowdakr 0:f0aa9cbf7f0e 532 uint8_t PICC_Select (Uid *uid, uint8_t validBits = 0);
shivanandgowdakr 0:f0aa9cbf7f0e 533
shivanandgowdakr 0:f0aa9cbf7f0e 534 /**
shivanandgowdakr 0:f0aa9cbf7f0e 535 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
shivanandgowdakr 0:f0aa9cbf7f0e 536 *
shivanandgowdakr 0:f0aa9cbf7f0e 537 * @return STATUS_OK on success, STATUS_??? otherwise.
shivanandgowdakr 0:f0aa9cbf7f0e 538 */
shivanandgowdakr 0:f0aa9cbf7f0e 539 uint8_t PICC_HaltA (void);
shivanandgowdakr 0:f0aa9cbf7f0e 540
shivanandgowdakr 0:f0aa9cbf7f0e 541 // ************************************************************************************
shivanandgowdakr 0:f0aa9cbf7f0e 542 //@}
shivanandgowdakr 0:f0aa9cbf7f0e 543
shivanandgowdakr 0:f0aa9cbf7f0e 544
shivanandgowdakr 0:f0aa9cbf7f0e 545 // ************************************************************************************
shivanandgowdakr 0:f0aa9cbf7f0e 546 //! @name Functions for communicating with MIFARE PICCs
shivanandgowdakr 0:f0aa9cbf7f0e 547 // ************************************************************************************
shivanandgowdakr 0:f0aa9cbf7f0e 548 //@{
shivanandgowdakr 0:f0aa9cbf7f0e 549
shivanandgowdakr 0:f0aa9cbf7f0e 550 /**
shivanandgowdakr 0:f0aa9cbf7f0e 551 * Executes the MFRC522 MFAuthent command.
shivanandgowdakr 0:f0aa9cbf7f0e 552 * This command manages MIFARE authentication to enable a secure communication to any MIFARE Mini, MIFARE 1K and MIFARE 4K card.
shivanandgowdakr 0:f0aa9cbf7f0e 553 * The authentication is described in the MFRC522 datasheet section 10.3.1.9 and http://www.nxp.com/documents/data_sheet/MF1S503x.pdf section 10.1.
shivanandgowdakr 0:f0aa9cbf7f0e 554 * For use with MIFARE Classic PICCs.
shivanandgowdakr 0:f0aa9cbf7f0e 555 * The PICC must be selected - ie in state ACTIVE(*) - before calling this function.
shivanandgowdakr 0:f0aa9cbf7f0e 556 * Remember to call PCD_StopCrypto1() after communicating with the authenticated PICC - otherwise no new communications can start.
shivanandgowdakr 0:f0aa9cbf7f0e 557 *
shivanandgowdakr 0:f0aa9cbf7f0e 558 * All keys are set to FFFFFFFFFFFFh at chip delivery.
shivanandgowdakr 0:f0aa9cbf7f0e 559 *
shivanandgowdakr 0:f0aa9cbf7f0e 560 * @param command PICC_CMD_MF_AUTH_KEY_A or PICC_CMD_MF_AUTH_KEY_B
shivanandgowdakr 0:f0aa9cbf7f0e 561 * @param blockAddr The block number. See numbering in the comments in the .h file.
shivanandgowdakr 0:f0aa9cbf7f0e 562 * @param key Pointer to the Crypteo1 key to use (6 bytes)
shivanandgowdakr 0:f0aa9cbf7f0e 563 * @param uid Pointer to Uid struct. The first 4 bytes of the UID is used.
shivanandgowdakr 0:f0aa9cbf7f0e 564 *
shivanandgowdakr 0:f0aa9cbf7f0e 565 * @return STATUS_OK on success, STATUS_??? otherwise. Probably STATUS_TIMEOUT if you supply the wrong key.
shivanandgowdakr 0:f0aa9cbf7f0e 566 */
shivanandgowdakr 0:f0aa9cbf7f0e 567 uint8_t PCD_Authenticate (uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid);
shivanandgowdakr 0:f0aa9cbf7f0e 568
shivanandgowdakr 0:f0aa9cbf7f0e 569 /**
shivanandgowdakr 0:f0aa9cbf7f0e 570 * Used to exit the PCD from its authenticated state.
shivanandgowdakr 0:f0aa9cbf7f0e 571 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
shivanandgowdakr 0:f0aa9cbf7f0e 572 */
shivanandgowdakr 0:f0aa9cbf7f0e 573 void PCD_StopCrypto1 (void);
shivanandgowdakr 0:f0aa9cbf7f0e 574
shivanandgowdakr 0:f0aa9cbf7f0e 575 /**
shivanandgowdakr 0:f0aa9cbf7f0e 576 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
shivanandgowdakr 0:f0aa9cbf7f0e 577 *
shivanandgowdakr 0:f0aa9cbf7f0e 578 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
shivanandgowdakr 0:f0aa9cbf7f0e 579 *
shivanandgowdakr 0:f0aa9cbf7f0e 580 * For MIFARE Ultralight only addresses 00h to 0Fh are decoded.
shivanandgowdakr 0:f0aa9cbf7f0e 581 * The MF0ICU1 returns a NAK for higher addresses.
shivanandgowdakr 0:f0aa9cbf7f0e 582 * The MF0ICU1 responds to the READ command by sending 16 bytes starting from the page address defined by the command argument.
shivanandgowdakr 0:f0aa9cbf7f0e 583 * For example; if blockAddr is 03h then pages 03h, 04h, 05h, 06h are returned.
shivanandgowdakr 0:f0aa9cbf7f0e 584 * A roll-back is implemented: If blockAddr is 0Eh, then the contents of pages 0Eh, 0Fh, 00h and 01h are returned.
shivanandgowdakr 0:f0aa9cbf7f0e 585 *
shivanandgowdakr 0:f0aa9cbf7f0e 586 * The buffer must be at least 18 bytes because a CRC_A is also returned.
shivanandgowdakr 0:f0aa9cbf7f0e 587 * Checks the CRC_A before returning STATUS_OK.
shivanandgowdakr 0:f0aa9cbf7f0e 588 *
shivanandgowdakr 0:f0aa9cbf7f0e 589 * @param blockAddr MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The first page to return data from.
shivanandgowdakr 0:f0aa9cbf7f0e 590 * @param buffer The buffer to store the data in
shivanandgowdakr 0:f0aa9cbf7f0e 591 * @param bufferSize Buffer size, at least 18 bytes. Also number of bytes returned if STATUS_OK.
shivanandgowdakr 0:f0aa9cbf7f0e 592 *
shivanandgowdakr 0:f0aa9cbf7f0e 593 * @return STATUS_OK on success, STATUS_??? otherwise.
shivanandgowdakr 0:f0aa9cbf7f0e 594 */
shivanandgowdakr 0:f0aa9cbf7f0e 595 uint8_t MIFARE_Read (uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize);
shivanandgowdakr 0:f0aa9cbf7f0e 596
shivanandgowdakr 0:f0aa9cbf7f0e 597 /**
shivanandgowdakr 0:f0aa9cbf7f0e 598 * Writes 16 bytes to the active PICC.
shivanandgowdakr 0:f0aa9cbf7f0e 599 *
shivanandgowdakr 0:f0aa9cbf7f0e 600 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
shivanandgowdakr 0:f0aa9cbf7f0e 601 *
shivanandgowdakr 0:f0aa9cbf7f0e 602 * For MIFARE Ultralight the opretaion is called "COMPATIBILITY WRITE".
shivanandgowdakr 0:f0aa9cbf7f0e 603 * Even though 16 bytes are transferred to the Ultralight PICC, only the least significant 4 bytes (bytes 0 to 3)
shivanandgowdakr 0:f0aa9cbf7f0e 604 * are written to the specified address. It is recommended to set the remaining bytes 04h to 0Fh to all logic 0.
shivanandgowdakr 0:f0aa9cbf7f0e 605 *
shivanandgowdakr 0:f0aa9cbf7f0e 606 * @param blockAddr MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The page (2-15) to write to.
shivanandgowdakr 0:f0aa9cbf7f0e 607 * @param buffer The 16 bytes to write to the PICC
shivanandgowdakr 0:f0aa9cbf7f0e 608 * @param bufferSize Buffer size, must be at least 16 bytes. Exactly 16 bytes are written.
shivanandgowdakr 0:f0aa9cbf7f0e 609 *
shivanandgowdakr 0:f0aa9cbf7f0e 610 * @return STATUS_OK on success, STATUS_??? otherwise.
shivanandgowdakr 0:f0aa9cbf7f0e 611 */
shivanandgowdakr 0:f0aa9cbf7f0e 612 uint8_t MIFARE_Write (uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize);
shivanandgowdakr 0:f0aa9cbf7f0e 613
shivanandgowdakr 0:f0aa9cbf7f0e 614 /**
shivanandgowdakr 0:f0aa9cbf7f0e 615 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
shivanandgowdakr 0:f0aa9cbf7f0e 616 *
shivanandgowdakr 0:f0aa9cbf7f0e 617 * @param page The page (2-15) to write to.
shivanandgowdakr 0:f0aa9cbf7f0e 618 * @param buffer The 4 bytes to write to the PICC
shivanandgowdakr 0:f0aa9cbf7f0e 619 * @param bufferSize Buffer size, must be at least 4 bytes. Exactly 4 bytes are written.
shivanandgowdakr 0:f0aa9cbf7f0e 620 *
shivanandgowdakr 0:f0aa9cbf7f0e 621 * @return STATUS_OK on success, STATUS_??? otherwise.
shivanandgowdakr 0:f0aa9cbf7f0e 622 */
shivanandgowdakr 0:f0aa9cbf7f0e 623 uint8_t MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize);
shivanandgowdakr 0:f0aa9cbf7f0e 624
shivanandgowdakr 0:f0aa9cbf7f0e 625 /**
shivanandgowdakr 0:f0aa9cbf7f0e 626 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
shivanandgowdakr 0:f0aa9cbf7f0e 627 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
shivanandgowdakr 0:f0aa9cbf7f0e 628 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
shivanandgowdakr 0:f0aa9cbf7f0e 629 * Use MIFARE_Transfer() to store the result in a block.
shivanandgowdakr 0:f0aa9cbf7f0e 630 *
shivanandgowdakr 0:f0aa9cbf7f0e 631 * @param blockAddr The block (0-0xff) number.
shivanandgowdakr 0:f0aa9cbf7f0e 632 * @param delta This number is subtracted from the value of block blockAddr.
shivanandgowdakr 0:f0aa9cbf7f0e 633 *
shivanandgowdakr 0:f0aa9cbf7f0e 634 * @return STATUS_OK on success, STATUS_??? otherwise.
shivanandgowdakr 0:f0aa9cbf7f0e 635 */
shivanandgowdakr 0:f0aa9cbf7f0e 636 uint8_t MIFARE_Decrement (uint8_t blockAddr, uint32_t delta);
shivanandgowdakr 0:f0aa9cbf7f0e 637
shivanandgowdakr 0:f0aa9cbf7f0e 638 /**
shivanandgowdakr 0:f0aa9cbf7f0e 639 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
shivanandgowdakr 0:f0aa9cbf7f0e 640 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
shivanandgowdakr 0:f0aa9cbf7f0e 641 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
shivanandgowdakr 0:f0aa9cbf7f0e 642 * Use MIFARE_Transfer() to store the result in a block.
shivanandgowdakr 0:f0aa9cbf7f0e 643 *
shivanandgowdakr 0:f0aa9cbf7f0e 644 * @param blockAddr The block (0-0xff) number.
shivanandgowdakr 0:f0aa9cbf7f0e 645 * @param delta This number is added to the value of block blockAddr.
shivanandgowdakr 0:f0aa9cbf7f0e 646 *
shivanandgowdakr 0:f0aa9cbf7f0e 647 * @return STATUS_OK on success, STATUS_??? otherwise.
shivanandgowdakr 0:f0aa9cbf7f0e 648 */
shivanandgowdakr 0:f0aa9cbf7f0e 649 uint8_t MIFARE_Increment (uint8_t blockAddr, uint32_t delta);
shivanandgowdakr 0:f0aa9cbf7f0e 650
shivanandgowdakr 0:f0aa9cbf7f0e 651 /**
shivanandgowdakr 0:f0aa9cbf7f0e 652 * MIFARE Restore copies the value of the addressed block into a volatile memory.
shivanandgowdakr 0:f0aa9cbf7f0e 653 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
shivanandgowdakr 0:f0aa9cbf7f0e 654 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
shivanandgowdakr 0:f0aa9cbf7f0e 655 * Use MIFARE_Transfer() to store the result in a block.
shivanandgowdakr 0:f0aa9cbf7f0e 656 *
shivanandgowdakr 0:f0aa9cbf7f0e 657 * @param blockAddr The block (0-0xff) number.
shivanandgowdakr 0:f0aa9cbf7f0e 658 *
shivanandgowdakr 0:f0aa9cbf7f0e 659 * @return STATUS_OK on success, STATUS_??? otherwise.
shivanandgowdakr 0:f0aa9cbf7f0e 660 */
shivanandgowdakr 0:f0aa9cbf7f0e 661 uint8_t MIFARE_Restore (uint8_t blockAddr);
shivanandgowdakr 0:f0aa9cbf7f0e 662
shivanandgowdakr 0:f0aa9cbf7f0e 663 /**
shivanandgowdakr 0:f0aa9cbf7f0e 664 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
shivanandgowdakr 0:f0aa9cbf7f0e 665 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
shivanandgowdakr 0:f0aa9cbf7f0e 666 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
shivanandgowdakr 0:f0aa9cbf7f0e 667 *
shivanandgowdakr 0:f0aa9cbf7f0e 668 * @param blockAddr The block (0-0xff) number.
shivanandgowdakr 0:f0aa9cbf7f0e 669 *
shivanandgowdakr 0:f0aa9cbf7f0e 670 * @return STATUS_OK on success, STATUS_??? otherwise.
shivanandgowdakr 0:f0aa9cbf7f0e 671 */
shivanandgowdakr 0:f0aa9cbf7f0e 672 uint8_t MIFARE_Transfer (uint8_t blockAddr);
shivanandgowdakr 0:f0aa9cbf7f0e 673
shivanandgowdakr 0:f0aa9cbf7f0e 674 // ************************************************************************************
shivanandgowdakr 0:f0aa9cbf7f0e 675 //@}
shivanandgowdakr 0:f0aa9cbf7f0e 676
shivanandgowdakr 0:f0aa9cbf7f0e 677
shivanandgowdakr 0:f0aa9cbf7f0e 678 // ************************************************************************************
shivanandgowdakr 0:f0aa9cbf7f0e 679 //! @name Support functions
shivanandgowdakr 0:f0aa9cbf7f0e 680 // ************************************************************************************
shivanandgowdakr 0:f0aa9cbf7f0e 681 //@{
shivanandgowdakr 0:f0aa9cbf7f0e 682
shivanandgowdakr 0:f0aa9cbf7f0e 683 /**
shivanandgowdakr 0:f0aa9cbf7f0e 684 * Wrapper for MIFARE protocol communication.
shivanandgowdakr 0:f0aa9cbf7f0e 685 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
shivanandgowdakr 0:f0aa9cbf7f0e 686 *
shivanandgowdakr 0:f0aa9cbf7f0e 687 * @param sendData Pointer to the data to transfer to the FIFO. Do NOT include the CRC_A.
shivanandgowdakr 0:f0aa9cbf7f0e 688 * @param sendLen Number of bytes in sendData.
shivanandgowdakr 0:f0aa9cbf7f0e 689 * @param acceptTimeout True => A timeout is also success
shivanandgowdakr 0:f0aa9cbf7f0e 690 *
shivanandgowdakr 0:f0aa9cbf7f0e 691 * @return STATUS_OK on success, STATUS_??? otherwise.
shivanandgowdakr 0:f0aa9cbf7f0e 692 */
shivanandgowdakr 0:f0aa9cbf7f0e 693 uint8_t PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout = false);
shivanandgowdakr 0:f0aa9cbf7f0e 694
shivanandgowdakr 0:f0aa9cbf7f0e 695 /**
shivanandgowdakr 0:f0aa9cbf7f0e 696 * Translates the SAK (Select Acknowledge) to a PICC type.
shivanandgowdakr 0:f0aa9cbf7f0e 697 *
shivanandgowdakr 0:f0aa9cbf7f0e 698 * @param sak The SAK byte returned from PICC_Select().
shivanandgowdakr 0:f0aa9cbf7f0e 699 *
shivanandgowdakr 0:f0aa9cbf7f0e 700 * @return PICC_Type
shivanandgowdakr 0:f0aa9cbf7f0e 701 */
shivanandgowdakr 0:f0aa9cbf7f0e 702 uint8_t PICC_GetType (uint8_t sak);
shivanandgowdakr 0:f0aa9cbf7f0e 703
shivanandgowdakr 0:f0aa9cbf7f0e 704 /**
shivanandgowdakr 0:f0aa9cbf7f0e 705 * Returns a string pointer to the PICC type name.
shivanandgowdakr 0:f0aa9cbf7f0e 706 *
shivanandgowdakr 0:f0aa9cbf7f0e 707 * @param type One of the PICC_Type enums.
shivanandgowdakr 0:f0aa9cbf7f0e 708 *
shivanandgowdakr 0:f0aa9cbf7f0e 709 * @return A string pointer to the PICC type name.
shivanandgowdakr 0:f0aa9cbf7f0e 710 */
shivanandgowdakr 0:f0aa9cbf7f0e 711 char* PICC_GetTypeName (uint8_t type);
shivanandgowdakr 0:f0aa9cbf7f0e 712
shivanandgowdakr 0:f0aa9cbf7f0e 713 /**
shivanandgowdakr 0:f0aa9cbf7f0e 714 * Returns a string pointer to a status code name.
shivanandgowdakr 0:f0aa9cbf7f0e 715 *
shivanandgowdakr 0:f0aa9cbf7f0e 716 * @param code One of the StatusCode enums.
shivanandgowdakr 0:f0aa9cbf7f0e 717 *
shivanandgowdakr 0:f0aa9cbf7f0e 718 * @return A string pointer to a status code name.
shivanandgowdakr 0:f0aa9cbf7f0e 719 */
shivanandgowdakr 0:f0aa9cbf7f0e 720 char* GetStatusCodeName (uint8_t code);
shivanandgowdakr 0:f0aa9cbf7f0e 721
shivanandgowdakr 0:f0aa9cbf7f0e 722 /**
shivanandgowdakr 0:f0aa9cbf7f0e 723 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
shivanandgowdakr 0:f0aa9cbf7f0e 724 *
shivanandgowdakr 0:f0aa9cbf7f0e 725 * @param accessBitBuffer Pointer to byte 6, 7 and 8 in the sector trailer. Bytes [0..2] will be set.
shivanandgowdakr 0:f0aa9cbf7f0e 726 * @param g0 Access bits [C1 C2 C3] for block 0 (for sectors 0-31) or blocks 0-4 (for sectors 32-39)
shivanandgowdakr 0:f0aa9cbf7f0e 727 * @param g1 Access bits [C1 C2 C3] for block 1 (for sectors 0-31) or blocks 5-9 (for sectors 32-39)
shivanandgowdakr 0:f0aa9cbf7f0e 728 * @param g2 Access bits [C1 C2 C3] for block 2 (for sectors 0-31) or blocks 10-14 (for sectors 32-39)
shivanandgowdakr 0:f0aa9cbf7f0e 729 * @param g3 Access bits [C1 C2 C3] for the sector trailer, block 3 (for sectors 0-31) or block 15 (for sectors 32-39)
shivanandgowdakr 0:f0aa9cbf7f0e 730 */
shivanandgowdakr 0:f0aa9cbf7f0e 731 void MIFARE_SetAccessBits (uint8_t *accessBitBuffer,
shivanandgowdakr 0:f0aa9cbf7f0e 732 uint8_t g0,
shivanandgowdakr 0:f0aa9cbf7f0e 733 uint8_t g1,
shivanandgowdakr 0:f0aa9cbf7f0e 734 uint8_t g2,
shivanandgowdakr 0:f0aa9cbf7f0e 735 uint8_t g3);
shivanandgowdakr 0:f0aa9cbf7f0e 736
shivanandgowdakr 0:f0aa9cbf7f0e 737 // ************************************************************************************
shivanandgowdakr 0:f0aa9cbf7f0e 738 //@}
shivanandgowdakr 0:f0aa9cbf7f0e 739
shivanandgowdakr 0:f0aa9cbf7f0e 740
shivanandgowdakr 0:f0aa9cbf7f0e 741 // ************************************************************************************
shivanandgowdakr 0:f0aa9cbf7f0e 742 //! @name Convenience functions - does not add extra functionality
shivanandgowdakr 0:f0aa9cbf7f0e 743 // ************************************************************************************
shivanandgowdakr 0:f0aa9cbf7f0e 744 //@{
shivanandgowdakr 0:f0aa9cbf7f0e 745
shivanandgowdakr 0:f0aa9cbf7f0e 746 /**
shivanandgowdakr 0:f0aa9cbf7f0e 747 * Returns true if a PICC responds to PICC_CMD_REQA.
shivanandgowdakr 0:f0aa9cbf7f0e 748 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
shivanandgowdakr 0:f0aa9cbf7f0e 749 *
shivanandgowdakr 0:f0aa9cbf7f0e 750 * @return bool
shivanandgowdakr 0:f0aa9cbf7f0e 751 */
shivanandgowdakr 0:f0aa9cbf7f0e 752 bool PICC_IsNewCardPresent(void);
shivanandgowdakr 0:f0aa9cbf7f0e 753
shivanandgowdakr 0:f0aa9cbf7f0e 754 /**
shivanandgowdakr 0:f0aa9cbf7f0e 755 * Simple wrapper around PICC_Select.
shivanandgowdakr 0:f0aa9cbf7f0e 756 * Returns true if a UID could be read.
shivanandgowdakr 0:f0aa9cbf7f0e 757 * Remember to call PICC_IsNewCardPresent(), PICC_RequestA() or PICC_WakeupA() first.
shivanandgowdakr 0:f0aa9cbf7f0e 758 * The read UID is available in the class variable uid.
shivanandgowdakr 0:f0aa9cbf7f0e 759 *
shivanandgowdakr 0:f0aa9cbf7f0e 760 * @return bool
shivanandgowdakr 0:f0aa9cbf7f0e 761 */
shivanandgowdakr 0:f0aa9cbf7f0e 762 bool PICC_ReadCardSerial (void);
shivanandgowdakr 0:f0aa9cbf7f0e 763
shivanandgowdakr 0:f0aa9cbf7f0e 764 // ************************************************************************************
shivanandgowdakr 0:f0aa9cbf7f0e 765 //@}
shivanandgowdakr 0:f0aa9cbf7f0e 766
shivanandgowdakr 0:f0aa9cbf7f0e 767
shivanandgowdakr 0:f0aa9cbf7f0e 768 private:
shivanandgowdakr 0:f0aa9cbf7f0e 769 SPI m_SPI;
shivanandgowdakr 0:f0aa9cbf7f0e 770 DigitalOut m_CS;
shivanandgowdakr 0:f0aa9cbf7f0e 771 DigitalOut m_RESET;
shivanandgowdakr 0:f0aa9cbf7f0e 772
shivanandgowdakr 0:f0aa9cbf7f0e 773 /**
shivanandgowdakr 0:f0aa9cbf7f0e 774 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
shivanandgowdakr 0:f0aa9cbf7f0e 775 *
shivanandgowdakr 0:f0aa9cbf7f0e 776 * @param command The command to use
shivanandgowdakr 0:f0aa9cbf7f0e 777 * @param blockAddr The block (0-0xff) number.
shivanandgowdakr 0:f0aa9cbf7f0e 778 * @param data The data to transfer in step 2
shivanandgowdakr 0:f0aa9cbf7f0e 779 *
shivanandgowdakr 0:f0aa9cbf7f0e 780 * @return STATUS_OK on success, STATUS_??? otherwise.
shivanandgowdakr 0:f0aa9cbf7f0e 781 */
shivanandgowdakr 0:f0aa9cbf7f0e 782 uint8_t MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data);
shivanandgowdakr 0:f0aa9cbf7f0e 783 };
shivanandgowdakr 0:f0aa9cbf7f0e 784
shivanandgowdakr 0:f0aa9cbf7f0e 785 #endif