Shivanand Gowda / MFRC522

MIFARE RC522

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MFRC522.cpp@0:0ee2c6d9ee0d, 2018-08-21 (annotated)

Committer:
shivanandgowdakr
Date:
Tue Aug 21 11:16:31 2018 +0000
Revision:
0:0ee2c6d9ee0d
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shivanandgowdakr 0:0ee2c6d9ee0d 1 /*
shivanandgowdakr 0:0ee2c6d9ee0d 2 * MFRC522.cpp - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
shivanandgowdakr 0:0ee2c6d9ee0d 3 * _Please_ see the comments in MFRC522.h - they give useful hints and background.
shivanandgowdakr 0:0ee2c6d9ee0d 4 * Released into the public domain.
shivanandgowdakr 0:0ee2c6d9ee0d 5 */
shivanandgowdakr 0:0ee2c6d9ee0d 6
shivanandgowdakr 0:0ee2c6d9ee0d 7 #include "MFRC522.h"
shivanandgowdakr 0:0ee2c6d9ee0d 8
shivanandgowdakr 0:0ee2c6d9ee0d 9 static const char* const _TypeNamePICC[] =
shivanandgowdakr 0:0ee2c6d9ee0d 10 {
shivanandgowdakr 0:0ee2c6d9ee0d 11 "Unknown type",
shivanandgowdakr 0:0ee2c6d9ee0d 12 "PICC compliant with ISO/IEC 14443-4",
shivanandgowdakr 0:0ee2c6d9ee0d 13 "PICC compliant with ISO/IEC 18092 (NFC)",
shivanandgowdakr 0:0ee2c6d9ee0d 14 "MIFARE Mini, 320 bytes",
shivanandgowdakr 0:0ee2c6d9ee0d 15 "MIFARE 1KB",
shivanandgowdakr 0:0ee2c6d9ee0d 16 "MIFARE 4KB",
shivanandgowdakr 0:0ee2c6d9ee0d 17 "MIFARE Ultralight or Ultralight C",
shivanandgowdakr 0:0ee2c6d9ee0d 18 "MIFARE Plus",
shivanandgowdakr 0:0ee2c6d9ee0d 19 "MIFARE TNP3XXX",
shivanandgowdakr 0:0ee2c6d9ee0d 20
shivanandgowdakr 0:0ee2c6d9ee0d 21 /* not complete UID */
shivanandgowdakr 0:0ee2c6d9ee0d 22 "SAK indicates UID is not complete"
shivanandgowdakr 0:0ee2c6d9ee0d 23 };
shivanandgowdakr 0:0ee2c6d9ee0d 24
shivanandgowdakr 0:0ee2c6d9ee0d 25 static const char* const _ErrorMessage[] =
shivanandgowdakr 0:0ee2c6d9ee0d 26 {
shivanandgowdakr 0:0ee2c6d9ee0d 27 "Unknown error",
shivanandgowdakr 0:0ee2c6d9ee0d 28 "Success",
shivanandgowdakr 0:0ee2c6d9ee0d 29 "Error in communication",
shivanandgowdakr 0:0ee2c6d9ee0d 30 "Collision detected",
shivanandgowdakr 0:0ee2c6d9ee0d 31 "Timeout in communication",
shivanandgowdakr 0:0ee2c6d9ee0d 32 "A buffer is not big enough",
shivanandgowdakr 0:0ee2c6d9ee0d 33 "Internal error in the code, should not happen",
shivanandgowdakr 0:0ee2c6d9ee0d 34 "Invalid argument",
shivanandgowdakr 0:0ee2c6d9ee0d 35 "The CRC_A does not match",
shivanandgowdakr 0:0ee2c6d9ee0d 36 "A MIFARE PICC responded with NAK"
shivanandgowdakr 0:0ee2c6d9ee0d 37 };
shivanandgowdakr 0:0ee2c6d9ee0d 38
shivanandgowdakr 0:0ee2c6d9ee0d 39 #define MFRC522_MaxPICCs (sizeof(_TypeNamePICC)/sizeof(_TypeNamePICC[0]))
shivanandgowdakr 0:0ee2c6d9ee0d 40 #define MFRC522_MaxError (sizeof(_ErrorMessage)/sizeof(_ErrorMessage[0]))
shivanandgowdakr 0:0ee2c6d9ee0d 41
shivanandgowdakr 0:0ee2c6d9ee0d 42 /////////////////////////////////////////////////////////////////////////////////////
shivanandgowdakr 0:0ee2c6d9ee0d 43 // Functions for setting up the driver
shivanandgowdakr 0:0ee2c6d9ee0d 44 /////////////////////////////////////////////////////////////////////////////////////
shivanandgowdakr 0:0ee2c6d9ee0d 45
shivanandgowdakr 0:0ee2c6d9ee0d 46 /**
shivanandgowdakr 0:0ee2c6d9ee0d 47 * Constructor.
shivanandgowdakr 0:0ee2c6d9ee0d 48 * Prepares the output pins.
shivanandgowdakr 0:0ee2c6d9ee0d 49 */
shivanandgowdakr 0:0ee2c6d9ee0d 50 MFRC522::MFRC522(PinName mosi,
shivanandgowdakr 0:0ee2c6d9ee0d 51 PinName miso,
shivanandgowdakr 0:0ee2c6d9ee0d 52 PinName sclk,
shivanandgowdakr 0:0ee2c6d9ee0d 53 PinName cs,
shivanandgowdakr 0:0ee2c6d9ee0d 54 PinName reset) : m_SPI(mosi, miso, sclk), m_CS(cs), m_RESET(reset)
shivanandgowdakr 0:0ee2c6d9ee0d 55 {
shivanandgowdakr 0:0ee2c6d9ee0d 56 /* Configure SPI bus */
shivanandgowdakr 0:0ee2c6d9ee0d 57 m_SPI.format(8, 0);
shivanandgowdakr 0:0ee2c6d9ee0d 58 m_SPI.frequency(8000000);
shivanandgowdakr 0:0ee2c6d9ee0d 59
shivanandgowdakr 0:0ee2c6d9ee0d 60 /* Release SPI-CS pin */
shivanandgowdakr 0:0ee2c6d9ee0d 61 m_CS = 1;
shivanandgowdakr 0:0ee2c6d9ee0d 62
shivanandgowdakr 0:0ee2c6d9ee0d 63 /* Release RESET pin */
shivanandgowdakr 0:0ee2c6d9ee0d 64 m_RESET = 1;
shivanandgowdakr 0:0ee2c6d9ee0d 65 } // End constructor
shivanandgowdakr 0:0ee2c6d9ee0d 66
shivanandgowdakr 0:0ee2c6d9ee0d 67
shivanandgowdakr 0:0ee2c6d9ee0d 68 /**
shivanandgowdakr 0:0ee2c6d9ee0d 69 * Destructor.
shivanandgowdakr 0:0ee2c6d9ee0d 70 */
shivanandgowdakr 0:0ee2c6d9ee0d 71 MFRC522::~MFRC522()
shivanandgowdakr 0:0ee2c6d9ee0d 72 {
shivanandgowdakr 0:0ee2c6d9ee0d 73
shivanandgowdakr 0:0ee2c6d9ee0d 74 }
shivanandgowdakr 0:0ee2c6d9ee0d 75
shivanandgowdakr 0:0ee2c6d9ee0d 76
shivanandgowdakr 0:0ee2c6d9ee0d 77 /////////////////////////////////////////////////////////////////////////////////////
shivanandgowdakr 0:0ee2c6d9ee0d 78 // Basic interface functions for communicating with the MFRC522
shivanandgowdakr 0:0ee2c6d9ee0d 79 /////////////////////////////////////////////////////////////////////////////////////
shivanandgowdakr 0:0ee2c6d9ee0d 80
shivanandgowdakr 0:0ee2c6d9ee0d 81 /**
shivanandgowdakr 0:0ee2c6d9ee0d 82 * Writes a byte to the specified register in the MFRC522 chip.
shivanandgowdakr 0:0ee2c6d9ee0d 83 * The interface is described in the datasheet section 8.1.2.
shivanandgowdakr 0:0ee2c6d9ee0d 84 */
shivanandgowdakr 0:0ee2c6d9ee0d 85 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t value)
shivanandgowdakr 0:0ee2c6d9ee0d 86 {
shivanandgowdakr 0:0ee2c6d9ee0d 87 m_CS = 0; /* Select SPI Chip MFRC522 */
shivanandgowdakr 0:0ee2c6d9ee0d 88
shivanandgowdakr 0:0ee2c6d9ee0d 89 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
shivanandgowdakr 0:0ee2c6d9ee0d 90 (void) m_SPI.write(reg & 0x7E);
shivanandgowdakr 0:0ee2c6d9ee0d 91 (void) m_SPI.write(value);
shivanandgowdakr 0:0ee2c6d9ee0d 92
shivanandgowdakr 0:0ee2c6d9ee0d 93 m_CS = 1; /* Release SPI Chip MFRC522 */
shivanandgowdakr 0:0ee2c6d9ee0d 94 } // End PCD_WriteRegister()
shivanandgowdakr 0:0ee2c6d9ee0d 95
shivanandgowdakr 0:0ee2c6d9ee0d 96 /**
shivanandgowdakr 0:0ee2c6d9ee0d 97 * Writes a number of bytes to the specified register in the MFRC522 chip.
shivanandgowdakr 0:0ee2c6d9ee0d 98 * The interface is described in the datasheet section 8.1.2.
shivanandgowdakr 0:0ee2c6d9ee0d 99 */
shivanandgowdakr 0:0ee2c6d9ee0d 100 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t count, uint8_t *values)
shivanandgowdakr 0:0ee2c6d9ee0d 101 {
shivanandgowdakr 0:0ee2c6d9ee0d 102 m_CS = 0; /* Select SPI Chip MFRC522 */
shivanandgowdakr 0:0ee2c6d9ee0d 103
shivanandgowdakr 0:0ee2c6d9ee0d 104 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
shivanandgowdakr 0:0ee2c6d9ee0d 105 (void) m_SPI.write(reg & 0x7E);
shivanandgowdakr 0:0ee2c6d9ee0d 106 for (uint8_t index = 0; index < count; index++)
shivanandgowdakr 0:0ee2c6d9ee0d 107 {
shivanandgowdakr 0:0ee2c6d9ee0d 108 (void) m_SPI.write(values[index]);
shivanandgowdakr 0:0ee2c6d9ee0d 109 }
shivanandgowdakr 0:0ee2c6d9ee0d 110
shivanandgowdakr 0:0ee2c6d9ee0d 111 m_CS = 1; /* Release SPI Chip MFRC522 */
shivanandgowdakr 0:0ee2c6d9ee0d 112 } // End PCD_WriteRegister()
shivanandgowdakr 0:0ee2c6d9ee0d 113
shivanandgowdakr 0:0ee2c6d9ee0d 114 /**
shivanandgowdakr 0:0ee2c6d9ee0d 115 * Reads a byte from the specified register in the MFRC522 chip.
shivanandgowdakr 0:0ee2c6d9ee0d 116 * The interface is described in the datasheet section 8.1.2.
shivanandgowdakr 0:0ee2c6d9ee0d 117 */
shivanandgowdakr 0:0ee2c6d9ee0d 118 uint8_t MFRC522::PCD_ReadRegister(uint8_t reg)
shivanandgowdakr 0:0ee2c6d9ee0d 119 {
shivanandgowdakr 0:0ee2c6d9ee0d 120 uint8_t value;
shivanandgowdakr 0:0ee2c6d9ee0d 121 m_CS = 0; /* Select SPI Chip MFRC522 */
shivanandgowdakr 0:0ee2c6d9ee0d 122
shivanandgowdakr 0:0ee2c6d9ee0d 123 // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
shivanandgowdakr 0:0ee2c6d9ee0d 124 (void) m_SPI.write(0x80 | reg);
shivanandgowdakr 0:0ee2c6d9ee0d 125
shivanandgowdakr 0:0ee2c6d9ee0d 126 // Read the value back. Send 0 to stop reading.
shivanandgowdakr 0:0ee2c6d9ee0d 127 value = m_SPI.write(0);
shivanandgowdakr 0:0ee2c6d9ee0d 128
shivanandgowdakr 0:0ee2c6d9ee0d 129 m_CS = 1; /* Release SPI Chip MFRC522 */
shivanandgowdakr 0:0ee2c6d9ee0d 130
shivanandgowdakr 0:0ee2c6d9ee0d 131 return value;
shivanandgowdakr 0:0ee2c6d9ee0d 132 } // End PCD_ReadRegister()
shivanandgowdakr 0:0ee2c6d9ee0d 133
shivanandgowdakr 0:0ee2c6d9ee0d 134 /**
shivanandgowdakr 0:0ee2c6d9ee0d 135 * Reads a number of bytes from the specified register in the MFRC522 chip.
shivanandgowdakr 0:0ee2c6d9ee0d 136 * The interface is described in the datasheet section 8.1.2.
shivanandgowdakr 0:0ee2c6d9ee0d 137 */
shivanandgowdakr 0:0ee2c6d9ee0d 138 void MFRC522::PCD_ReadRegister(uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign)
shivanandgowdakr 0:0ee2c6d9ee0d 139 {
shivanandgowdakr 0:0ee2c6d9ee0d 140 if (count == 0) { return; }
shivanandgowdakr 0:0ee2c6d9ee0d 141
shivanandgowdakr 0:0ee2c6d9ee0d 142 uint8_t address = 0x80 | reg; // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
shivanandgowdakr 0:0ee2c6d9ee0d 143 uint8_t index = 0; // Index in values array.
shivanandgowdakr 0:0ee2c6d9ee0d 144
shivanandgowdakr 0:0ee2c6d9ee0d 145 m_CS = 0; /* Select SPI Chip MFRC522 */
shivanandgowdakr 0:0ee2c6d9ee0d 146 count--; // One read is performed outside of the loop
shivanandgowdakr 0:0ee2c6d9ee0d 147 (void) m_SPI.write(address); // Tell MFRC522 which address we want to read
shivanandgowdakr 0:0ee2c6d9ee0d 148
shivanandgowdakr 0:0ee2c6d9ee0d 149 while (index < count)
shivanandgowdakr 0:0ee2c6d9ee0d 150 {
shivanandgowdakr 0:0ee2c6d9ee0d 151 if ((index == 0) && rxAlign) // Only update bit positions rxAlign..7 in values[0]
shivanandgowdakr 0:0ee2c6d9ee0d 152 {
shivanandgowdakr 0:0ee2c6d9ee0d 153 // Create bit mask for bit positions rxAlign..7
shivanandgowdakr 0:0ee2c6d9ee0d 154 uint8_t mask = 0;
shivanandgowdakr 0:0ee2c6d9ee0d 155 for (uint8_t i = rxAlign; i <= 7; i++)
shivanandgowdakr 0:0ee2c6d9ee0d 156 {
shivanandgowdakr 0:0ee2c6d9ee0d 157 mask |= (1 << i);
shivanandgowdakr 0:0ee2c6d9ee0d 158 }
shivanandgowdakr 0:0ee2c6d9ee0d 159
shivanandgowdakr 0:0ee2c6d9ee0d 160 // Read value and tell that we want to read the same address again.
shivanandgowdakr 0:0ee2c6d9ee0d 161 uint8_t value = m_SPI.write(address);
shivanandgowdakr 0:0ee2c6d9ee0d 162
shivanandgowdakr 0:0ee2c6d9ee0d 163 // Apply mask to both current value of values[0] and the new data in value.
shivanandgowdakr 0:0ee2c6d9ee0d 164 values[0] = (values[index] & ~mask) | (value & mask);
shivanandgowdakr 0:0ee2c6d9ee0d 165 }
shivanandgowdakr 0:0ee2c6d9ee0d 166 else
shivanandgowdakr 0:0ee2c6d9ee0d 167 {
shivanandgowdakr 0:0ee2c6d9ee0d 168 // Read value and tell that we want to read the same address again.
shivanandgowdakr 0:0ee2c6d9ee0d 169 values[index] = m_SPI.write(address);
shivanandgowdakr 0:0ee2c6d9ee0d 170 }
shivanandgowdakr 0:0ee2c6d9ee0d 171
shivanandgowdakr 0:0ee2c6d9ee0d 172 index++;
shivanandgowdakr 0:0ee2c6d9ee0d 173 }
shivanandgowdakr 0:0ee2c6d9ee0d 174
shivanandgowdakr 0:0ee2c6d9ee0d 175 values[index] = m_SPI.write(0); // Read the final byte. Send 0 to stop reading.
shivanandgowdakr 0:0ee2c6d9ee0d 176
shivanandgowdakr 0:0ee2c6d9ee0d 177 m_CS = 1; /* Release SPI Chip MFRC522 */
shivanandgowdakr 0:0ee2c6d9ee0d 178 } // End PCD_ReadRegister()
shivanandgowdakr 0:0ee2c6d9ee0d 179
shivanandgowdakr 0:0ee2c6d9ee0d 180 /**
shivanandgowdakr 0:0ee2c6d9ee0d 181 * Sets the bits given in mask in register reg.
shivanandgowdakr 0:0ee2c6d9ee0d 182 */
shivanandgowdakr 0:0ee2c6d9ee0d 183 void MFRC522::PCD_SetRegisterBits(uint8_t reg, uint8_t mask)
shivanandgowdakr 0:0ee2c6d9ee0d 184 {
shivanandgowdakr 0:0ee2c6d9ee0d 185 uint8_t tmp = PCD_ReadRegister(reg);
shivanandgowdakr 0:0ee2c6d9ee0d 186 PCD_WriteRegister(reg, tmp | mask); // set bit mask
shivanandgowdakr 0:0ee2c6d9ee0d 187 } // End PCD_SetRegisterBitMask()
shivanandgowdakr 0:0ee2c6d9ee0d 188
shivanandgowdakr 0:0ee2c6d9ee0d 189 /**
shivanandgowdakr 0:0ee2c6d9ee0d 190 * Clears the bits given in mask from register reg.
shivanandgowdakr 0:0ee2c6d9ee0d 191 */
shivanandgowdakr 0:0ee2c6d9ee0d 192 void MFRC522::PCD_ClrRegisterBits(uint8_t reg, uint8_t mask)
shivanandgowdakr 0:0ee2c6d9ee0d 193 {
shivanandgowdakr 0:0ee2c6d9ee0d 194 uint8_t tmp = PCD_ReadRegister(reg);
shivanandgowdakr 0:0ee2c6d9ee0d 195 PCD_WriteRegister(reg, tmp & (~mask)); // clear bit mask
shivanandgowdakr 0:0ee2c6d9ee0d 196 } // End PCD_ClearRegisterBitMask()
shivanandgowdakr 0:0ee2c6d9ee0d 197
shivanandgowdakr 0:0ee2c6d9ee0d 198
shivanandgowdakr 0:0ee2c6d9ee0d 199 /**
shivanandgowdakr 0:0ee2c6d9ee0d 200 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
shivanandgowdakr 0:0ee2c6d9ee0d 201 */
shivanandgowdakr 0:0ee2c6d9ee0d 202 uint8_t MFRC522::PCD_CalculateCRC(uint8_t *data, uint8_t length, uint8_t *result)
shivanandgowdakr 0:0ee2c6d9ee0d 203 {
shivanandgowdakr 0:0ee2c6d9ee0d 204 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
shivanandgowdakr 0:0ee2c6d9ee0d 205 PCD_WriteRegister(DivIrqReg, 0x04); // Clear the CRCIRq interrupt request bit
shivanandgowdakr 0:0ee2c6d9ee0d 206 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
shivanandgowdakr 0:0ee2c6d9ee0d 207 PCD_WriteRegister(FIFODataReg, length, data); // Write data to the FIFO
shivanandgowdakr 0:0ee2c6d9ee0d 208 PCD_WriteRegister(CommandReg, PCD_CalcCRC); // Start the calculation
shivanandgowdakr 0:0ee2c6d9ee0d 209
shivanandgowdakr 0:0ee2c6d9ee0d 210 // Wait for the CRC calculation to complete. Each iteration of the while-loop takes 17.73us.
shivanandgowdakr 0:0ee2c6d9ee0d 211 uint16_t i = 5000;
shivanandgowdakr 0:0ee2c6d9ee0d 212 uint8_t n;
shivanandgowdakr 0:0ee2c6d9ee0d 213 while (1)
shivanandgowdakr 0:0ee2c6d9ee0d 214 {
shivanandgowdakr 0:0ee2c6d9ee0d 215 n = PCD_ReadRegister(DivIrqReg); // DivIrqReg[7..0] bits are: Set2 reserved reserved MfinActIRq reserved CRCIRq reserved reserved
shivanandgowdakr 0:0ee2c6d9ee0d 216 if (n & 0x04)
shivanandgowdakr 0:0ee2c6d9ee0d 217 {
shivanandgowdakr 0:0ee2c6d9ee0d 218 // CRCIRq bit set - calculation done
shivanandgowdakr 0:0ee2c6d9ee0d 219 break;
shivanandgowdakr 0:0ee2c6d9ee0d 220 }
shivanandgowdakr 0:0ee2c6d9ee0d 221
shivanandgowdakr 0:0ee2c6d9ee0d 222 if (--i == 0)
shivanandgowdakr 0:0ee2c6d9ee0d 223 {
shivanandgowdakr 0:0ee2c6d9ee0d 224 // The emergency break. We will eventually terminate on this one after 89ms.
shivanandgowdakr 0:0ee2c6d9ee0d 225 // Communication with the MFRC522 might be down.
shivanandgowdakr 0:0ee2c6d9ee0d 226 return STATUS_TIMEOUT;
shivanandgowdakr 0:0ee2c6d9ee0d 227 }
shivanandgowdakr 0:0ee2c6d9ee0d 228 }
shivanandgowdakr 0:0ee2c6d9ee0d 229
shivanandgowdakr 0:0ee2c6d9ee0d 230 // Stop calculating CRC for new content in the FIFO.
shivanandgowdakr 0:0ee2c6d9ee0d 231 PCD_WriteRegister(CommandReg, PCD_Idle);
shivanandgowdakr 0:0ee2c6d9ee0d 232
shivanandgowdakr 0:0ee2c6d9ee0d 233 // Transfer the result from the registers to the result buffer
shivanandgowdakr 0:0ee2c6d9ee0d 234 result[0] = PCD_ReadRegister(CRCResultRegL);
shivanandgowdakr 0:0ee2c6d9ee0d 235 result[1] = PCD_ReadRegister(CRCResultRegH);
shivanandgowdakr 0:0ee2c6d9ee0d 236 return STATUS_OK;
shivanandgowdakr 0:0ee2c6d9ee0d 237 } // End PCD_CalculateCRC()
shivanandgowdakr 0:0ee2c6d9ee0d 238
shivanandgowdakr 0:0ee2c6d9ee0d 239
shivanandgowdakr 0:0ee2c6d9ee0d 240 /////////////////////////////////////////////////////////////////////////////////////
shivanandgowdakr 0:0ee2c6d9ee0d 241 // Functions for manipulating the MFRC522
shivanandgowdakr 0:0ee2c6d9ee0d 242 /////////////////////////////////////////////////////////////////////////////////////
shivanandgowdakr 0:0ee2c6d9ee0d 243
shivanandgowdakr 0:0ee2c6d9ee0d 244 /**
shivanandgowdakr 0:0ee2c6d9ee0d 245 * Initializes the MFRC522 chip.
shivanandgowdakr 0:0ee2c6d9ee0d 246 */
shivanandgowdakr 0:0ee2c6d9ee0d 247 void MFRC522::PCD_Init()
shivanandgowdakr 0:0ee2c6d9ee0d 248 {
shivanandgowdakr 0:0ee2c6d9ee0d 249 /* Reset MFRC522 */
shivanandgowdakr 0:0ee2c6d9ee0d 250 m_RESET = 0;
shivanandgowdakr 0:0ee2c6d9ee0d 251 wait_ms(10);
shivanandgowdakr 0:0ee2c6d9ee0d 252 m_RESET = 1;
shivanandgowdakr 0:0ee2c6d9ee0d 253
shivanandgowdakr 0:0ee2c6d9ee0d 254 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
shivanandgowdakr 0:0ee2c6d9ee0d 255 wait_ms(50);
shivanandgowdakr 0:0ee2c6d9ee0d 256
shivanandgowdakr 0:0ee2c6d9ee0d 257 // When communicating with a PICC we need a timeout if something goes wrong.
shivanandgowdakr 0:0ee2c6d9ee0d 258 // f_timer = 13.56 MHz / (2*TPreScaler+1) where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo].
shivanandgowdakr 0:0ee2c6d9ee0d 259 // TPrescaler_Hi are the four low bits in TModeReg. TPrescaler_Lo is TPrescalerReg.
shivanandgowdakr 0:0ee2c6d9ee0d 260 PCD_WriteRegister(TModeReg, 0x80); // TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds
shivanandgowdakr 0:0ee2c6d9ee0d 261 PCD_WriteRegister(TPrescalerReg, 0xA9); // TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25us.
shivanandgowdakr 0:0ee2c6d9ee0d 262 PCD_WriteRegister(TReloadRegH, 0x03); // Reload timer with 0x3E8 = 1000, ie 25ms before timeout.
shivanandgowdakr 0:0ee2c6d9ee0d 263 PCD_WriteRegister(TReloadRegL, 0xE8);
shivanandgowdakr 0:0ee2c6d9ee0d 264
shivanandgowdakr 0:0ee2c6d9ee0d 265 PCD_WriteRegister(TxASKReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
shivanandgowdakr 0:0ee2c6d9ee0d 266 PCD_WriteRegister(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
shivanandgowdakr 0:0ee2c6d9ee0d 267
shivanandgowdakr 0:0ee2c6d9ee0d 268 PCD_WriteRegister(RFCfgReg, (0x07<<4)); // Set Rx Gain to max
shivanandgowdakr 0:0ee2c6d9ee0d 269
shivanandgowdakr 0:0ee2c6d9ee0d 270 PCD_AntennaOn(); // Enable the antenna driver pins TX1 and TX2 (they were disabled by the reset)
shivanandgowdakr 0:0ee2c6d9ee0d 271 } // End PCD_Init()
shivanandgowdakr 0:0ee2c6d9ee0d 272
shivanandgowdakr 0:0ee2c6d9ee0d 273 /**
shivanandgowdakr 0:0ee2c6d9ee0d 274 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
shivanandgowdakr 0:0ee2c6d9ee0d 275 */
shivanandgowdakr 0:0ee2c6d9ee0d 276 void MFRC522::PCD_Reset()
shivanandgowdakr 0:0ee2c6d9ee0d 277 {
shivanandgowdakr 0:0ee2c6d9ee0d 278 PCD_WriteRegister(CommandReg, PCD_SoftReset); // Issue the SoftReset command.
shivanandgowdakr 0:0ee2c6d9ee0d 279 // The datasheet does not mention how long the SoftRest command takes to complete.
shivanandgowdakr 0:0ee2c6d9ee0d 280 // But the MFRC522 might have been in soft power-down mode (triggered by bit 4 of CommandReg)
shivanandgowdakr 0:0ee2c6d9ee0d 281 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
shivanandgowdakr 0:0ee2c6d9ee0d 282 wait_ms(50);
shivanandgowdakr 0:0ee2c6d9ee0d 283
shivanandgowdakr 0:0ee2c6d9ee0d 284 // Wait for the PowerDown bit in CommandReg to be cleared
shivanandgowdakr 0:0ee2c6d9ee0d 285 while (PCD_ReadRegister(CommandReg) & (1<<4))
shivanandgowdakr 0:0ee2c6d9ee0d 286 {
shivanandgowdakr 0:0ee2c6d9ee0d 287 // PCD still restarting - unlikely after waiting 50ms, but better safe than sorry.
shivanandgowdakr 0:0ee2c6d9ee0d 288 }
shivanandgowdakr 0:0ee2c6d9ee0d 289 } // End PCD_Reset()
shivanandgowdakr 0:0ee2c6d9ee0d 290
shivanandgowdakr 0:0ee2c6d9ee0d 291 /**
shivanandgowdakr 0:0ee2c6d9ee0d 292 * Turns the antenna on by enabling pins TX1 and TX2.
shivanandgowdakr 0:0ee2c6d9ee0d 293 * After a reset these pins disabled.
shivanandgowdakr 0:0ee2c6d9ee0d 294 */
shivanandgowdakr 0:0ee2c6d9ee0d 295 void MFRC522::PCD_AntennaOn()
shivanandgowdakr 0:0ee2c6d9ee0d 296 {
shivanandgowdakr 0:0ee2c6d9ee0d 297 uint8_t value = PCD_ReadRegister(TxControlReg);
shivanandgowdakr 0:0ee2c6d9ee0d 298 if ((value & 0x03) != 0x03)
shivanandgowdakr 0:0ee2c6d9ee0d 299 {
shivanandgowdakr 0:0ee2c6d9ee0d 300 PCD_WriteRegister(TxControlReg, value | 0x03);
shivanandgowdakr 0:0ee2c6d9ee0d 301 }
shivanandgowdakr 0:0ee2c6d9ee0d 302 } // End PCD_AntennaOn()
shivanandgowdakr 0:0ee2c6d9ee0d 303
shivanandgowdakr 0:0ee2c6d9ee0d 304 /////////////////////////////////////////////////////////////////////////////////////
shivanandgowdakr 0:0ee2c6d9ee0d 305 // Functions for communicating with PICCs
shivanandgowdakr 0:0ee2c6d9ee0d 306 /////////////////////////////////////////////////////////////////////////////////////
shivanandgowdakr 0:0ee2c6d9ee0d 307
shivanandgowdakr 0:0ee2c6d9ee0d 308 /**
shivanandgowdakr 0:0ee2c6d9ee0d 309 * Executes the Transceive command.
shivanandgowdakr 0:0ee2c6d9ee0d 310 * CRC validation can only be done if backData and backLen are specified.
shivanandgowdakr 0:0ee2c6d9ee0d 311 */
shivanandgowdakr 0:0ee2c6d9ee0d 312 uint8_t MFRC522::PCD_TransceiveData(uint8_t *sendData,
shivanandgowdakr 0:0ee2c6d9ee0d 313 uint8_t sendLen,
shivanandgowdakr 0:0ee2c6d9ee0d 314 uint8_t *backData,
shivanandgowdakr 0:0ee2c6d9ee0d 315 uint8_t *backLen,
shivanandgowdakr 0:0ee2c6d9ee0d 316 uint8_t *validBits,
shivanandgowdakr 0:0ee2c6d9ee0d 317 uint8_t rxAlign,
shivanandgowdakr 0:0ee2c6d9ee0d 318 bool checkCRC)
shivanandgowdakr 0:0ee2c6d9ee0d 319 {
shivanandgowdakr 0:0ee2c6d9ee0d 320 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
shivanandgowdakr 0:0ee2c6d9ee0d 321 return PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, sendData, sendLen, backData, backLen, validBits, rxAlign, checkCRC);
shivanandgowdakr 0:0ee2c6d9ee0d 322 } // End PCD_TransceiveData()
shivanandgowdakr 0:0ee2c6d9ee0d 323
shivanandgowdakr 0:0ee2c6d9ee0d 324 /**
shivanandgowdakr 0:0ee2c6d9ee0d 325 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
shivanandgowdakr 0:0ee2c6d9ee0d 326 * CRC validation can only be done if backData and backLen are specified.
shivanandgowdakr 0:0ee2c6d9ee0d 327 */
shivanandgowdakr 0:0ee2c6d9ee0d 328 uint8_t MFRC522::PCD_CommunicateWithPICC(uint8_t command,
shivanandgowdakr 0:0ee2c6d9ee0d 329 uint8_t waitIRq,
shivanandgowdakr 0:0ee2c6d9ee0d 330 uint8_t *sendData,
shivanandgowdakr 0:0ee2c6d9ee0d 331 uint8_t sendLen,
shivanandgowdakr 0:0ee2c6d9ee0d 332 uint8_t *backData,
shivanandgowdakr 0:0ee2c6d9ee0d 333 uint8_t *backLen,
shivanandgowdakr 0:0ee2c6d9ee0d 334 uint8_t *validBits,
shivanandgowdakr 0:0ee2c6d9ee0d 335 uint8_t rxAlign,
shivanandgowdakr 0:0ee2c6d9ee0d 336 bool checkCRC)
shivanandgowdakr 0:0ee2c6d9ee0d 337 {
shivanandgowdakr 0:0ee2c6d9ee0d 338 uint8_t n, _validBits = 0;
shivanandgowdakr 0:0ee2c6d9ee0d 339 uint32_t i;
shivanandgowdakr 0:0ee2c6d9ee0d 340
shivanandgowdakr 0:0ee2c6d9ee0d 341 // Prepare values for BitFramingReg
shivanandgowdakr 0:0ee2c6d9ee0d 342 uint8_t txLastBits = validBits ? *validBits : 0;
shivanandgowdakr 0:0ee2c6d9ee0d 343 uint8_t bitFraming = (rxAlign << 4) + txLastBits; // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
shivanandgowdakr 0:0ee2c6d9ee0d 344
shivanandgowdakr 0:0ee2c6d9ee0d 345 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
shivanandgowdakr 0:0ee2c6d9ee0d 346 PCD_WriteRegister(ComIrqReg, 0x7F); // Clear all seven interrupt request bits
shivanandgowdakr 0:0ee2c6d9ee0d 347 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
shivanandgowdakr 0:0ee2c6d9ee0d 348 PCD_WriteRegister(FIFODataReg, sendLen, sendData); // Write sendData to the FIFO
shivanandgowdakr 0:0ee2c6d9ee0d 349 PCD_WriteRegister(BitFramingReg, bitFraming); // Bit adjustments
shivanandgowdakr 0:0ee2c6d9ee0d 350 PCD_WriteRegister(CommandReg, command); // Execute the command
shivanandgowdakr 0:0ee2c6d9ee0d 351 if (command == PCD_Transceive)
shivanandgowdakr 0:0ee2c6d9ee0d 352 {
shivanandgowdakr 0:0ee2c6d9ee0d 353 PCD_SetRegisterBits(BitFramingReg, 0x80); // StartSend=1, transmission of data starts
shivanandgowdakr 0:0ee2c6d9ee0d 354 }
shivanandgowdakr 0:0ee2c6d9ee0d 355
shivanandgowdakr 0:0ee2c6d9ee0d 356 // Wait for the command to complete.
shivanandgowdakr 0:0ee2c6d9ee0d 357 // In PCD_Init() we set the TAuto flag in TModeReg. This means the timer automatically starts when the PCD stops transmitting.
shivanandgowdakr 0:0ee2c6d9ee0d 358 // Each iteration of the do-while-loop takes 17.86us.
shivanandgowdakr 0:0ee2c6d9ee0d 359 i = 2000;
shivanandgowdakr 0:0ee2c6d9ee0d 360 while (1)
shivanandgowdakr 0:0ee2c6d9ee0d 361 {
shivanandgowdakr 0:0ee2c6d9ee0d 362 n = PCD_ReadRegister(ComIrqReg); // ComIrqReg[7..0] bits are: Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
shivanandgowdakr 0:0ee2c6d9ee0d 363 if (n & waitIRq)
shivanandgowdakr 0:0ee2c6d9ee0d 364 { // One of the interrupts that signal success has been set.
shivanandgowdakr 0:0ee2c6d9ee0d 365 break;
shivanandgowdakr 0:0ee2c6d9ee0d 366 }
shivanandgowdakr 0:0ee2c6d9ee0d 367
shivanandgowdakr 0:0ee2c6d9ee0d 368 if (n & 0x01)
shivanandgowdakr 0:0ee2c6d9ee0d 369 { // Timer interrupt - nothing received in 25ms
shivanandgowdakr 0:0ee2c6d9ee0d 370 return STATUS_TIMEOUT;
shivanandgowdakr 0:0ee2c6d9ee0d 371 }
shivanandgowdakr 0:0ee2c6d9ee0d 372
shivanandgowdakr 0:0ee2c6d9ee0d 373 if (--i == 0)
shivanandgowdakr 0:0ee2c6d9ee0d 374 { // The emergency break. If all other condions fail we will eventually terminate on this one after 35.7ms. Communication with the MFRC522 might be down.
shivanandgowdakr 0:0ee2c6d9ee0d 375 return STATUS_TIMEOUT;
shivanandgowdakr 0:0ee2c6d9ee0d 376 }
shivanandgowdakr 0:0ee2c6d9ee0d 377 }
shivanandgowdakr 0:0ee2c6d9ee0d 378
shivanandgowdakr 0:0ee2c6d9ee0d 379 // Stop now if any errors except collisions were detected.
shivanandgowdakr 0:0ee2c6d9ee0d 380 uint8_t errorRegValue = PCD_ReadRegister(ErrorReg); // ErrorReg[7..0] bits are: WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr
shivanandgowdakr 0:0ee2c6d9ee0d 381 if (errorRegValue & 0x13)
shivanandgowdakr 0:0ee2c6d9ee0d 382 { // BufferOvfl ParityErr ProtocolErr
shivanandgowdakr 0:0ee2c6d9ee0d 383 return STATUS_ERROR;
shivanandgowdakr 0:0ee2c6d9ee0d 384 }
shivanandgowdakr 0:0ee2c6d9ee0d 385
shivanandgowdakr 0:0ee2c6d9ee0d 386 // If the caller wants data back, get it from the MFRC522.
shivanandgowdakr 0:0ee2c6d9ee0d 387 if (backData && backLen)
shivanandgowdakr 0:0ee2c6d9ee0d 388 {
shivanandgowdakr 0:0ee2c6d9ee0d 389 n = PCD_ReadRegister(FIFOLevelReg); // Number of bytes in the FIFO
shivanandgowdakr 0:0ee2c6d9ee0d 390 if (n > *backLen)
shivanandgowdakr 0:0ee2c6d9ee0d 391 {
shivanandgowdakr 0:0ee2c6d9ee0d 392 return STATUS_NO_ROOM;
shivanandgowdakr 0:0ee2c6d9ee0d 393 }
shivanandgowdakr 0:0ee2c6d9ee0d 394
shivanandgowdakr 0:0ee2c6d9ee0d 395 *backLen = n; // Number of bytes returned
shivanandgowdakr 0:0ee2c6d9ee0d 396 PCD_ReadRegister(FIFODataReg, n, backData, rxAlign); // Get received data from FIFO
shivanandgowdakr 0:0ee2c6d9ee0d 397 _validBits = PCD_ReadRegister(ControlReg) & 0x07; // RxLastBits[2:0] indicates the number of valid bits in the last received byte. If this value is 000b, the whole byte is valid.
shivanandgowdakr 0:0ee2c6d9ee0d 398 if (validBits)
shivanandgowdakr 0:0ee2c6d9ee0d 399 {
shivanandgowdakr 0:0ee2c6d9ee0d 400 *validBits = _validBits;
shivanandgowdakr 0:0ee2c6d9ee0d 401 }
shivanandgowdakr 0:0ee2c6d9ee0d 402 }
shivanandgowdakr 0:0ee2c6d9ee0d 403
shivanandgowdakr 0:0ee2c6d9ee0d 404 // Tell about collisions
shivanandgowdakr 0:0ee2c6d9ee0d 405 if (errorRegValue & 0x08)
shivanandgowdakr 0:0ee2c6d9ee0d 406 { // CollErr
shivanandgowdakr 0:0ee2c6d9ee0d 407 return STATUS_COLLISION;
shivanandgowdakr 0:0ee2c6d9ee0d 408 }
shivanandgowdakr 0:0ee2c6d9ee0d 409
shivanandgowdakr 0:0ee2c6d9ee0d 410 // Perform CRC_A validation if requested.
shivanandgowdakr 0:0ee2c6d9ee0d 411 if (backData && backLen && checkCRC)
shivanandgowdakr 0:0ee2c6d9ee0d 412 {
shivanandgowdakr 0:0ee2c6d9ee0d 413 // In this case a MIFARE Classic NAK is not OK.
shivanandgowdakr 0:0ee2c6d9ee0d 414 if ((*backLen == 1) && (_validBits == 4))
shivanandgowdakr 0:0ee2c6d9ee0d 415 {
shivanandgowdakr 0:0ee2c6d9ee0d 416 return STATUS_MIFARE_NACK;
shivanandgowdakr 0:0ee2c6d9ee0d 417 }
shivanandgowdakr 0:0ee2c6d9ee0d 418
shivanandgowdakr 0:0ee2c6d9ee0d 419 // We need at least the CRC_A value and all 8 bits of the last byte must be received.
shivanandgowdakr 0:0ee2c6d9ee0d 420 if ((*backLen < 2) || (_validBits != 0))
shivanandgowdakr 0:0ee2c6d9ee0d 421 {
shivanandgowdakr 0:0ee2c6d9ee0d 422 return STATUS_CRC_WRONG;
shivanandgowdakr 0:0ee2c6d9ee0d 423 }
shivanandgowdakr 0:0ee2c6d9ee0d 424
shivanandgowdakr 0:0ee2c6d9ee0d 425 // Verify CRC_A - do our own calculation and store the control in controlBuffer.
shivanandgowdakr 0:0ee2c6d9ee0d 426 uint8_t controlBuffer[2];
shivanandgowdakr 0:0ee2c6d9ee0d 427 n = PCD_CalculateCRC(&backData[0], *backLen - 2, &controlBuffer[0]);
shivanandgowdakr 0:0ee2c6d9ee0d 428 if (n != STATUS_OK)
shivanandgowdakr 0:0ee2c6d9ee0d 429 {
shivanandgowdakr 0:0ee2c6d9ee0d 430 return n;
shivanandgowdakr 0:0ee2c6d9ee0d 431 }
shivanandgowdakr 0:0ee2c6d9ee0d 432
shivanandgowdakr 0:0ee2c6d9ee0d 433 if ((backData[*backLen - 2] != controlBuffer[0]) || (backData[*backLen - 1] != controlBuffer[1]))
shivanandgowdakr 0:0ee2c6d9ee0d 434 {
shivanandgowdakr 0:0ee2c6d9ee0d 435 return STATUS_CRC_WRONG;
shivanandgowdakr 0:0ee2c6d9ee0d 436 }
shivanandgowdakr 0:0ee2c6d9ee0d 437 }
shivanandgowdakr 0:0ee2c6d9ee0d 438
shivanandgowdakr 0:0ee2c6d9ee0d 439 return STATUS_OK;
shivanandgowdakr 0:0ee2c6d9ee0d 440 } // End PCD_CommunicateWithPICC()
shivanandgowdakr 0:0ee2c6d9ee0d 441
shivanandgowdakr 0:0ee2c6d9ee0d 442 /*
shivanandgowdakr 0:0ee2c6d9ee0d 443 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
shivanandgowdakr 0:0ee2c6d9ee0d 444 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
shivanandgowdakr 0:0ee2c6d9ee0d 445 */
shivanandgowdakr 0:0ee2c6d9ee0d 446 uint8_t MFRC522::PICC_RequestA(uint8_t *bufferATQA, uint8_t *bufferSize)
shivanandgowdakr 0:0ee2c6d9ee0d 447 {
shivanandgowdakr 0:0ee2c6d9ee0d 448 return PICC_REQA_or_WUPA(PICC_CMD_REQA, bufferATQA, bufferSize);
shivanandgowdakr 0:0ee2c6d9ee0d 449 } // End PICC_RequestA()
shivanandgowdakr 0:0ee2c6d9ee0d 450
shivanandgowdakr 0:0ee2c6d9ee0d 451 /**
shivanandgowdakr 0:0ee2c6d9ee0d 452 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
shivanandgowdakr 0:0ee2c6d9ee0d 453 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
shivanandgowdakr 0:0ee2c6d9ee0d 454 */
shivanandgowdakr 0:0ee2c6d9ee0d 455 uint8_t MFRC522::PICC_WakeupA(uint8_t *bufferATQA, uint8_t *bufferSize)
shivanandgowdakr 0:0ee2c6d9ee0d 456 {
shivanandgowdakr 0:0ee2c6d9ee0d 457 return PICC_REQA_or_WUPA(PICC_CMD_WUPA, bufferATQA, bufferSize);
shivanandgowdakr 0:0ee2c6d9ee0d 458 } // End PICC_WakeupA()
shivanandgowdakr 0:0ee2c6d9ee0d 459
shivanandgowdakr 0:0ee2c6d9ee0d 460 /*
shivanandgowdakr 0:0ee2c6d9ee0d 461 * Transmits REQA or WUPA commands.
shivanandgowdakr 0:0ee2c6d9ee0d 462 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
shivanandgowdakr 0:0ee2c6d9ee0d 463 */
shivanandgowdakr 0:0ee2c6d9ee0d 464 uint8_t MFRC522::PICC_REQA_or_WUPA(uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize)
shivanandgowdakr 0:0ee2c6d9ee0d 465 {
shivanandgowdakr 0:0ee2c6d9ee0d 466 uint8_t validBits;
shivanandgowdakr 0:0ee2c6d9ee0d 467 uint8_t status;
shivanandgowdakr 0:0ee2c6d9ee0d 468
shivanandgowdakr 0:0ee2c6d9ee0d 469 if (bufferATQA == NULL || *bufferSize < 2)
shivanandgowdakr 0:0ee2c6d9ee0d 470 { // The ATQA response is 2 bytes long.
shivanandgowdakr 0:0ee2c6d9ee0d 471 return STATUS_NO_ROOM;
shivanandgowdakr 0:0ee2c6d9ee0d 472 }
shivanandgowdakr 0:0ee2c6d9ee0d 473
shivanandgowdakr 0:0ee2c6d9ee0d 474 // ValuesAfterColl=1 => Bits received after collision are cleared.
shivanandgowdakr 0:0ee2c6d9ee0d 475 PCD_ClrRegisterBits(CollReg, 0x80);
shivanandgowdakr 0:0ee2c6d9ee0d 476
shivanandgowdakr 0:0ee2c6d9ee0d 477 // For REQA and WUPA we need the short frame format
shivanandgowdakr 0:0ee2c6d9ee0d 478 // - transmit only 7 bits of the last (and only) byte. TxLastBits = BitFramingReg[2..0]
shivanandgowdakr 0:0ee2c6d9ee0d 479 validBits = 7;
shivanandgowdakr 0:0ee2c6d9ee0d 480
shivanandgowdakr 0:0ee2c6d9ee0d 481 status = PCD_TransceiveData(&command, 1, bufferATQA, bufferSize, &validBits);
shivanandgowdakr 0:0ee2c6d9ee0d 482 if (status != STATUS_OK)
shivanandgowdakr 0:0ee2c6d9ee0d 483 {
shivanandgowdakr 0:0ee2c6d9ee0d 484 return status;
shivanandgowdakr 0:0ee2c6d9ee0d 485 }
shivanandgowdakr 0:0ee2c6d9ee0d 486
shivanandgowdakr 0:0ee2c6d9ee0d 487 if ((*bufferSize != 2) || (validBits != 0))
shivanandgowdakr 0:0ee2c6d9ee0d 488 { // ATQA must be exactly 16 bits.
shivanandgowdakr 0:0ee2c6d9ee0d 489 return STATUS_ERROR;
shivanandgowdakr 0:0ee2c6d9ee0d 490 }
shivanandgowdakr 0:0ee2c6d9ee0d 491
shivanandgowdakr 0:0ee2c6d9ee0d 492 return STATUS_OK;
shivanandgowdakr 0:0ee2c6d9ee0d 493 } // End PICC_REQA_or_WUPA()
shivanandgowdakr 0:0ee2c6d9ee0d 494
shivanandgowdakr 0:0ee2c6d9ee0d 495 /*
shivanandgowdakr 0:0ee2c6d9ee0d 496 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
shivanandgowdakr 0:0ee2c6d9ee0d 497 */
shivanandgowdakr 0:0ee2c6d9ee0d 498 uint8_t MFRC522::PICC_Select(Uid *uid, uint8_t validBits)
shivanandgowdakr 0:0ee2c6d9ee0d 499 {
shivanandgowdakr 0:0ee2c6d9ee0d 500 bool uidComplete;
shivanandgowdakr 0:0ee2c6d9ee0d 501 bool selectDone;
shivanandgowdakr 0:0ee2c6d9ee0d 502 bool useCascadeTag;
shivanandgowdakr 0:0ee2c6d9ee0d 503 uint8_t cascadeLevel = 1;
shivanandgowdakr 0:0ee2c6d9ee0d 504 uint8_t result;
shivanandgowdakr 0:0ee2c6d9ee0d 505 uint8_t count;
shivanandgowdakr 0:0ee2c6d9ee0d 506 uint8_t index;
shivanandgowdakr 0:0ee2c6d9ee0d 507 uint8_t uidIndex; // The first index in uid->uidByte[] that is used in the current Cascade Level.
shivanandgowdakr 0:0ee2c6d9ee0d 508 uint8_t currentLevelKnownBits; // The number of known UID bits in the current Cascade Level.
shivanandgowdakr 0:0ee2c6d9ee0d 509 uint8_t buffer[9]; // The SELECT/ANTICOLLISION commands uses a 7 byte standard frame + 2 bytes CRC_A
shivanandgowdakr 0:0ee2c6d9ee0d 510 uint8_t bufferUsed; // The number of bytes used in the buffer, ie the number of bytes to transfer to the FIFO.
shivanandgowdakr 0:0ee2c6d9ee0d 511 uint8_t rxAlign; // Used in BitFramingReg. Defines the bit position for the first bit received.
shivanandgowdakr 0:0ee2c6d9ee0d 512 uint8_t txLastBits; // Used in BitFramingReg. The number of valid bits in the last transmitted byte.
shivanandgowdakr 0:0ee2c6d9ee0d 513 uint8_t *responseBuffer;
shivanandgowdakr 0:0ee2c6d9ee0d 514 uint8_t responseLength;
shivanandgowdakr 0:0ee2c6d9ee0d 515
shivanandgowdakr 0:0ee2c6d9ee0d 516 // Description of buffer structure:
shivanandgowdakr 0:0ee2c6d9ee0d 517 // Byte 0: SEL Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3
shivanandgowdakr 0:0ee2c6d9ee0d 518 // Byte 1: NVB Number of Valid Bits (in complete command, not just the UID): High nibble: complete bytes, Low nibble: Extra bits.
shivanandgowdakr 0:0ee2c6d9ee0d 519 // Byte 2: UID-data or CT See explanation below. CT means Cascade Tag.
shivanandgowdakr 0:0ee2c6d9ee0d 520 // Byte 3: UID-data
shivanandgowdakr 0:0ee2c6d9ee0d 521 // Byte 4: UID-data
shivanandgowdakr 0:0ee2c6d9ee0d 522 // Byte 5: UID-data
shivanandgowdakr 0:0ee2c6d9ee0d 523 // Byte 6: BCC Block Check Character - XOR of bytes 2-5
shivanandgowdakr 0:0ee2c6d9ee0d 524 // Byte 7: CRC_A
shivanandgowdakr 0:0ee2c6d9ee0d 525 // Byte 8: CRC_A
shivanandgowdakr 0:0ee2c6d9ee0d 526 // The BCC and CRC_A is only transmitted if we know all the UID bits of the current Cascade Level.
shivanandgowdakr 0:0ee2c6d9ee0d 527 //
shivanandgowdakr 0:0ee2c6d9ee0d 528 // Description of bytes 2-5: (Section 6.5.4 of the ISO/IEC 14443-3 draft: UID contents and cascade levels)
shivanandgowdakr 0:0ee2c6d9ee0d 529 // UID size Cascade level Byte2 Byte3 Byte4 Byte5
shivanandgowdakr 0:0ee2c6d9ee0d 530 // ======== ============= ===== ===== ===== =====
shivanandgowdakr 0:0ee2c6d9ee0d 531 // 4 bytes 1 uid0 uid1 uid2 uid3
shivanandgowdakr 0:0ee2c6d9ee0d 532 // 7 bytes 1 CT uid0 uid1 uid2
shivanandgowdakr 0:0ee2c6d9ee0d 533 // 2 uid3 uid4 uid5 uid6
shivanandgowdakr 0:0ee2c6d9ee0d 534 // 10 bytes 1 CT uid0 uid1 uid2
shivanandgowdakr 0:0ee2c6d9ee0d 535 // 2 CT uid3 uid4 uid5
shivanandgowdakr 0:0ee2c6d9ee0d 536 // 3 uid6 uid7 uid8 uid9
shivanandgowdakr 0:0ee2c6d9ee0d 537
shivanandgowdakr 0:0ee2c6d9ee0d 538 // Sanity checks
shivanandgowdakr 0:0ee2c6d9ee0d 539 if (validBits > 80)
shivanandgowdakr 0:0ee2c6d9ee0d 540 {
shivanandgowdakr 0:0ee2c6d9ee0d 541 return STATUS_INVALID;
shivanandgowdakr 0:0ee2c6d9ee0d 542 }
shivanandgowdakr 0:0ee2c6d9ee0d 543
shivanandgowdakr 0:0ee2c6d9ee0d 544 // Prepare MFRC522
shivanandgowdakr 0:0ee2c6d9ee0d 545 // ValuesAfterColl=1 => Bits received after collision are cleared.
shivanandgowdakr 0:0ee2c6d9ee0d 546 PCD_ClrRegisterBits(CollReg, 0x80);
shivanandgowdakr 0:0ee2c6d9ee0d 547
shivanandgowdakr 0:0ee2c6d9ee0d 548 // Repeat Cascade Level loop until we have a complete UID.
shivanandgowdakr 0:0ee2c6d9ee0d 549 uidComplete = false;
shivanandgowdakr 0:0ee2c6d9ee0d 550 while ( ! uidComplete)
shivanandgowdakr 0:0ee2c6d9ee0d 551 {
shivanandgowdakr 0:0ee2c6d9ee0d 552 // Set the Cascade Level in the SEL byte, find out if we need to use the Cascade Tag in byte 2.
shivanandgowdakr 0:0ee2c6d9ee0d 553 switch (cascadeLevel)
shivanandgowdakr 0:0ee2c6d9ee0d 554 {
shivanandgowdakr 0:0ee2c6d9ee0d 555 case 1:
shivanandgowdakr 0:0ee2c6d9ee0d 556 buffer[0] = PICC_CMD_SEL_CL1;
shivanandgowdakr 0:0ee2c6d9ee0d 557 uidIndex = 0;
shivanandgowdakr 0:0ee2c6d9ee0d 558 useCascadeTag = validBits && (uid->size > 4); // When we know that the UID has more than 4 bytes
shivanandgowdakr 0:0ee2c6d9ee0d 559 break;
shivanandgowdakr 0:0ee2c6d9ee0d 560
shivanandgowdakr 0:0ee2c6d9ee0d 561 case 2:
shivanandgowdakr 0:0ee2c6d9ee0d 562 buffer[0] = PICC_CMD_SEL_CL2;
shivanandgowdakr 0:0ee2c6d9ee0d 563 uidIndex = 3;
shivanandgowdakr 0:0ee2c6d9ee0d 564 useCascadeTag = validBits && (uid->size > 7); // When we know that the UID has more than 7 bytes
shivanandgowdakr 0:0ee2c6d9ee0d 565 break;
shivanandgowdakr 0:0ee2c6d9ee0d 566
shivanandgowdakr 0:0ee2c6d9ee0d 567 case 3:
shivanandgowdakr 0:0ee2c6d9ee0d 568 buffer[0] = PICC_CMD_SEL_CL3;
shivanandgowdakr 0:0ee2c6d9ee0d 569 uidIndex = 6;
shivanandgowdakr 0:0ee2c6d9ee0d 570 useCascadeTag = false; // Never used in CL3.
shivanandgowdakr 0:0ee2c6d9ee0d 571 break;
shivanandgowdakr 0:0ee2c6d9ee0d 572
shivanandgowdakr 0:0ee2c6d9ee0d 573 default:
shivanandgowdakr 0:0ee2c6d9ee0d 574 return STATUS_INTERNAL_ERROR;
shivanandgowdakr 0:0ee2c6d9ee0d 575 //break;
shivanandgowdakr 0:0ee2c6d9ee0d 576 }
shivanandgowdakr 0:0ee2c6d9ee0d 577
shivanandgowdakr 0:0ee2c6d9ee0d 578 // How many UID bits are known in this Cascade Level?
shivanandgowdakr 0:0ee2c6d9ee0d 579 if(validBits > (8 * uidIndex))
shivanandgowdakr 0:0ee2c6d9ee0d 580 {
shivanandgowdakr 0:0ee2c6d9ee0d 581 currentLevelKnownBits = validBits - (8 * uidIndex);
shivanandgowdakr 0:0ee2c6d9ee0d 582 }
shivanandgowdakr 0:0ee2c6d9ee0d 583 else
shivanandgowdakr 0:0ee2c6d9ee0d 584 {
shivanandgowdakr 0:0ee2c6d9ee0d 585 currentLevelKnownBits = 0;
shivanandgowdakr 0:0ee2c6d9ee0d 586 }
shivanandgowdakr 0:0ee2c6d9ee0d 587
shivanandgowdakr 0:0ee2c6d9ee0d 588 // Copy the known bits from uid->uidByte[] to buffer[]
shivanandgowdakr 0:0ee2c6d9ee0d 589 index = 2; // destination index in buffer[]
shivanandgowdakr 0:0ee2c6d9ee0d 590 if (useCascadeTag)
shivanandgowdakr 0:0ee2c6d9ee0d 591 {
shivanandgowdakr 0:0ee2c6d9ee0d 592 buffer[index++] = PICC_CMD_CT;
shivanandgowdakr 0:0ee2c6d9ee0d 593 }
shivanandgowdakr 0:0ee2c6d9ee0d 594
shivanandgowdakr 0:0ee2c6d9ee0d 595 uint8_t bytesToCopy = currentLevelKnownBits / 8 + (currentLevelKnownBits % 8 ? 1 : 0); // The number of bytes needed to represent the known bits for this level.
shivanandgowdakr 0:0ee2c6d9ee0d 596 if (bytesToCopy)
shivanandgowdakr 0:0ee2c6d9ee0d 597 {
shivanandgowdakr 0:0ee2c6d9ee0d 598 // Max 4 bytes in each Cascade Level. Only 3 left if we use the Cascade Tag
shivanandgowdakr 0:0ee2c6d9ee0d 599 uint8_t maxBytes = useCascadeTag ? 3 : 4;
shivanandgowdakr 0:0ee2c6d9ee0d 600 if (bytesToCopy > maxBytes)
shivanandgowdakr 0:0ee2c6d9ee0d 601 {
shivanandgowdakr 0:0ee2c6d9ee0d 602 bytesToCopy = maxBytes;
shivanandgowdakr 0:0ee2c6d9ee0d 603 }
shivanandgowdakr 0:0ee2c6d9ee0d 604
shivanandgowdakr 0:0ee2c6d9ee0d 605 for (count = 0; count < bytesToCopy; count++)
shivanandgowdakr 0:0ee2c6d9ee0d 606 {
shivanandgowdakr 0:0ee2c6d9ee0d 607 buffer[index++] = uid->uidByte[uidIndex + count];
shivanandgowdakr 0:0ee2c6d9ee0d 608 }
shivanandgowdakr 0:0ee2c6d9ee0d 609 }
shivanandgowdakr 0:0ee2c6d9ee0d 610
shivanandgowdakr 0:0ee2c6d9ee0d 611 // Now that the data has been copied we need to include the 8 bits in CT in currentLevelKnownBits
shivanandgowdakr 0:0ee2c6d9ee0d 612 if (useCascadeTag)
shivanandgowdakr 0:0ee2c6d9ee0d 613 {
shivanandgowdakr 0:0ee2c6d9ee0d 614 currentLevelKnownBits += 8;
shivanandgowdakr 0:0ee2c6d9ee0d 615 }
shivanandgowdakr 0:0ee2c6d9ee0d 616
shivanandgowdakr 0:0ee2c6d9ee0d 617 // Repeat anti collision loop until we can transmit all UID bits + BCC and receive a SAK - max 32 iterations.
shivanandgowdakr 0:0ee2c6d9ee0d 618 selectDone = false;
shivanandgowdakr 0:0ee2c6d9ee0d 619 while ( ! selectDone)
shivanandgowdakr 0:0ee2c6d9ee0d 620 {
shivanandgowdakr 0:0ee2c6d9ee0d 621 // Find out how many bits and bytes to send and receive.
shivanandgowdakr 0:0ee2c6d9ee0d 622 if (currentLevelKnownBits >= 32)
shivanandgowdakr 0:0ee2c6d9ee0d 623 { // All UID bits in this Cascade Level are known. This is a SELECT.
shivanandgowdakr 0:0ee2c6d9ee0d 624 //Serial.print("SELECT: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
shivanandgowdakr 0:0ee2c6d9ee0d 625 buffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes
shivanandgowdakr 0:0ee2c6d9ee0d 626
shivanandgowdakr 0:0ee2c6d9ee0d 627 // Calulate BCC - Block Check Character
shivanandgowdakr 0:0ee2c6d9ee0d 628 buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5];
shivanandgowdakr 0:0ee2c6d9ee0d 629
shivanandgowdakr 0:0ee2c6d9ee0d 630 // Calculate CRC_A
shivanandgowdakr 0:0ee2c6d9ee0d 631 result = PCD_CalculateCRC(buffer, 7, &buffer[7]);
shivanandgowdakr 0:0ee2c6d9ee0d 632 if (result != STATUS_OK)
shivanandgowdakr 0:0ee2c6d9ee0d 633 {
shivanandgowdakr 0:0ee2c6d9ee0d 634 return result;
shivanandgowdakr 0:0ee2c6d9ee0d 635 }
shivanandgowdakr 0:0ee2c6d9ee0d 636
shivanandgowdakr 0:0ee2c6d9ee0d 637 txLastBits = 0; // 0 => All 8 bits are valid.
shivanandgowdakr 0:0ee2c6d9ee0d 638 bufferUsed = 9;
shivanandgowdakr 0:0ee2c6d9ee0d 639
shivanandgowdakr 0:0ee2c6d9ee0d 640 // Store response in the last 3 bytes of buffer (BCC and CRC_A - not needed after tx)
shivanandgowdakr 0:0ee2c6d9ee0d 641 responseBuffer = &buffer[6];
shivanandgowdakr 0:0ee2c6d9ee0d 642 responseLength = 3;
shivanandgowdakr 0:0ee2c6d9ee0d 643 }
shivanandgowdakr 0:0ee2c6d9ee0d 644 else
shivanandgowdakr 0:0ee2c6d9ee0d 645 { // This is an ANTICOLLISION.
shivanandgowdakr 0:0ee2c6d9ee0d 646 //Serial.print("ANTICOLLISION: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
shivanandgowdakr 0:0ee2c6d9ee0d 647 txLastBits = currentLevelKnownBits % 8;
shivanandgowdakr 0:0ee2c6d9ee0d 648 count = currentLevelKnownBits / 8; // Number of whole bytes in the UID part.
shivanandgowdakr 0:0ee2c6d9ee0d 649 index = 2 + count; // Number of whole bytes: SEL + NVB + UIDs
shivanandgowdakr 0:0ee2c6d9ee0d 650 buffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits
shivanandgowdakr 0:0ee2c6d9ee0d 651 bufferUsed = index + (txLastBits ? 1 : 0);
shivanandgowdakr 0:0ee2c6d9ee0d 652
shivanandgowdakr 0:0ee2c6d9ee0d 653 // Store response in the unused part of buffer
shivanandgowdakr 0:0ee2c6d9ee0d 654 responseBuffer = &buffer[index];
shivanandgowdakr 0:0ee2c6d9ee0d 655 responseLength = sizeof(buffer) - index;
shivanandgowdakr 0:0ee2c6d9ee0d 656 }
shivanandgowdakr 0:0ee2c6d9ee0d 657
shivanandgowdakr 0:0ee2c6d9ee0d 658 // Set bit adjustments
shivanandgowdakr 0:0ee2c6d9ee0d 659 rxAlign = txLastBits; // Having a seperate variable is overkill. But it makes the next line easier to read.
shivanandgowdakr 0:0ee2c6d9ee0d 660 PCD_WriteRegister(BitFramingReg, (rxAlign << 4) + txLastBits); // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
shivanandgowdakr 0:0ee2c6d9ee0d 661
shivanandgowdakr 0:0ee2c6d9ee0d 662 // Transmit the buffer and receive the response.
shivanandgowdakr 0:0ee2c6d9ee0d 663 result = PCD_TransceiveData(buffer, bufferUsed, responseBuffer, &responseLength, &txLastBits, rxAlign);
shivanandgowdakr 0:0ee2c6d9ee0d 664 if (result == STATUS_COLLISION)
shivanandgowdakr 0:0ee2c6d9ee0d 665 { // More than one PICC in the field => collision.
shivanandgowdakr 0:0ee2c6d9ee0d 666 result = PCD_ReadRegister(CollReg); // CollReg[7..0] bits are: ValuesAfterColl reserved CollPosNotValid CollPos[4:0]
shivanandgowdakr 0:0ee2c6d9ee0d 667 if (result & 0x20)
shivanandgowdakr 0:0ee2c6d9ee0d 668 { // CollPosNotValid
shivanandgowdakr 0:0ee2c6d9ee0d 669 return STATUS_COLLISION; // Without a valid collision position we cannot continue
shivanandgowdakr 0:0ee2c6d9ee0d 670 }
shivanandgowdakr 0:0ee2c6d9ee0d 671
shivanandgowdakr 0:0ee2c6d9ee0d 672 uint8_t collisionPos = result & 0x1F; // Values 0-31, 0 means bit 32.
shivanandgowdakr 0:0ee2c6d9ee0d 673 if (collisionPos == 0)
shivanandgowdakr 0:0ee2c6d9ee0d 674 {
shivanandgowdakr 0:0ee2c6d9ee0d 675 collisionPos = 32;
shivanandgowdakr 0:0ee2c6d9ee0d 676 }
shivanandgowdakr 0:0ee2c6d9ee0d 677
shivanandgowdakr 0:0ee2c6d9ee0d 678 if (collisionPos <= currentLevelKnownBits)
shivanandgowdakr 0:0ee2c6d9ee0d 679 { // No progress - should not happen
shivanandgowdakr 0:0ee2c6d9ee0d 680 return STATUS_INTERNAL_ERROR;
shivanandgowdakr 0:0ee2c6d9ee0d 681 }
shivanandgowdakr 0:0ee2c6d9ee0d 682
shivanandgowdakr 0:0ee2c6d9ee0d 683 // Choose the PICC with the bit set.
shivanandgowdakr 0:0ee2c6d9ee0d 684 currentLevelKnownBits = collisionPos;
shivanandgowdakr 0:0ee2c6d9ee0d 685 count = (currentLevelKnownBits - 1) % 8; // The bit to modify
shivanandgowdakr 0:0ee2c6d9ee0d 686 index = 1 + (currentLevelKnownBits / 8) + (count ? 1 : 0); // First byte is index 0.
shivanandgowdakr 0:0ee2c6d9ee0d 687 buffer[index] |= (1 << count);
shivanandgowdakr 0:0ee2c6d9ee0d 688 }
shivanandgowdakr 0:0ee2c6d9ee0d 689 else if (result != STATUS_OK)
shivanandgowdakr 0:0ee2c6d9ee0d 690 {
shivanandgowdakr 0:0ee2c6d9ee0d 691 return result;
shivanandgowdakr 0:0ee2c6d9ee0d 692 }
shivanandgowdakr 0:0ee2c6d9ee0d 693 else
shivanandgowdakr 0:0ee2c6d9ee0d 694 { // STATUS_OK
shivanandgowdakr 0:0ee2c6d9ee0d 695 if (currentLevelKnownBits >= 32)
shivanandgowdakr 0:0ee2c6d9ee0d 696 { // This was a SELECT.
shivanandgowdakr 0:0ee2c6d9ee0d 697 selectDone = true; // No more anticollision
shivanandgowdakr 0:0ee2c6d9ee0d 698 // We continue below outside the while.
shivanandgowdakr 0:0ee2c6d9ee0d 699 }
shivanandgowdakr 0:0ee2c6d9ee0d 700 else
shivanandgowdakr 0:0ee2c6d9ee0d 701 { // This was an ANTICOLLISION.
shivanandgowdakr 0:0ee2c6d9ee0d 702 // We now have all 32 bits of the UID in this Cascade Level
shivanandgowdakr 0:0ee2c6d9ee0d 703 currentLevelKnownBits = 32;
shivanandgowdakr 0:0ee2c6d9ee0d 704 // Run loop again to do the SELECT.
shivanandgowdakr 0:0ee2c6d9ee0d 705 }
shivanandgowdakr 0:0ee2c6d9ee0d 706 }
shivanandgowdakr 0:0ee2c6d9ee0d 707 } // End of while ( ! selectDone)
shivanandgowdakr 0:0ee2c6d9ee0d 708
shivanandgowdakr 0:0ee2c6d9ee0d 709 // We do not check the CBB - it was constructed by us above.
shivanandgowdakr 0:0ee2c6d9ee0d 710
shivanandgowdakr 0:0ee2c6d9ee0d 711 // Copy the found UID bytes from buffer[] to uid->uidByte[]
shivanandgowdakr 0:0ee2c6d9ee0d 712 index = (buffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[]
shivanandgowdakr 0:0ee2c6d9ee0d 713 bytesToCopy = (buffer[2] == PICC_CMD_CT) ? 3 : 4;
shivanandgowdakr 0:0ee2c6d9ee0d 714 for (count = 0; count < bytesToCopy; count++)
shivanandgowdakr 0:0ee2c6d9ee0d 715 {
shivanandgowdakr 0:0ee2c6d9ee0d 716 uid->uidByte[uidIndex + count] = buffer[index++];
shivanandgowdakr 0:0ee2c6d9ee0d 717 }
shivanandgowdakr 0:0ee2c6d9ee0d 718
shivanandgowdakr 0:0ee2c6d9ee0d 719 // Check response SAK (Select Acknowledge)
shivanandgowdakr 0:0ee2c6d9ee0d 720 if (responseLength != 3 || txLastBits != 0)
shivanandgowdakr 0:0ee2c6d9ee0d 721 { // SAK must be exactly 24 bits (1 byte + CRC_A).
shivanandgowdakr 0:0ee2c6d9ee0d 722 return STATUS_ERROR;
shivanandgowdakr 0:0ee2c6d9ee0d 723 }
shivanandgowdakr 0:0ee2c6d9ee0d 724
shivanandgowdakr 0:0ee2c6d9ee0d 725 // Verify CRC_A - do our own calculation and store the control in buffer[2..3] - those bytes are not needed anymore.
shivanandgowdakr 0:0ee2c6d9ee0d 726 result = PCD_CalculateCRC(responseBuffer, 1, &buffer[2]);
shivanandgowdakr 0:0ee2c6d9ee0d 727 if (result != STATUS_OK)
shivanandgowdakr 0:0ee2c6d9ee0d 728 {
shivanandgowdakr 0:0ee2c6d9ee0d 729 return result;
shivanandgowdakr 0:0ee2c6d9ee0d 730 }
shivanandgowdakr 0:0ee2c6d9ee0d 731
shivanandgowdakr 0:0ee2c6d9ee0d 732 if ((buffer[2] != responseBuffer[1]) || (buffer[3] != responseBuffer[2]))
shivanandgowdakr 0:0ee2c6d9ee0d 733 {
shivanandgowdakr 0:0ee2c6d9ee0d 734 return STATUS_CRC_WRONG;
shivanandgowdakr 0:0ee2c6d9ee0d 735 }
shivanandgowdakr 0:0ee2c6d9ee0d 736
shivanandgowdakr 0:0ee2c6d9ee0d 737 if (responseBuffer[0] & 0x04)
shivanandgowdakr 0:0ee2c6d9ee0d 738 { // Cascade bit set - UID not complete yes
shivanandgowdakr 0:0ee2c6d9ee0d 739 cascadeLevel++;
shivanandgowdakr 0:0ee2c6d9ee0d 740 }
shivanandgowdakr 0:0ee2c6d9ee0d 741 else
shivanandgowdakr 0:0ee2c6d9ee0d 742 {
shivanandgowdakr 0:0ee2c6d9ee0d 743 uidComplete = true;
shivanandgowdakr 0:0ee2c6d9ee0d 744 uid->sak = responseBuffer[0];
shivanandgowdakr 0:0ee2c6d9ee0d 745 }
shivanandgowdakr 0:0ee2c6d9ee0d 746 } // End of while ( ! uidComplete)
shivanandgowdakr 0:0ee2c6d9ee0d 747
shivanandgowdakr 0:0ee2c6d9ee0d 748 // Set correct uid->size
shivanandgowdakr 0:0ee2c6d9ee0d 749 uid->size = 3 * cascadeLevel + 1;
shivanandgowdakr 0:0ee2c6d9ee0d 750
shivanandgowdakr 0:0ee2c6d9ee0d 751 return STATUS_OK;
shivanandgowdakr 0:0ee2c6d9ee0d 752 } // End PICC_Select()
shivanandgowdakr 0:0ee2c6d9ee0d 753
shivanandgowdakr 0:0ee2c6d9ee0d 754 /*
shivanandgowdakr 0:0ee2c6d9ee0d 755 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
shivanandgowdakr 0:0ee2c6d9ee0d 756 */
shivanandgowdakr 0:0ee2c6d9ee0d 757 uint8_t MFRC522::PICC_HaltA()
shivanandgowdakr 0:0ee2c6d9ee0d 758 {
shivanandgowdakr 0:0ee2c6d9ee0d 759 uint8_t result;
shivanandgowdakr 0:0ee2c6d9ee0d 760 uint8_t buffer[4];
shivanandgowdakr 0:0ee2c6d9ee0d 761
shivanandgowdakr 0:0ee2c6d9ee0d 762 // Build command buffer
shivanandgowdakr 0:0ee2c6d9ee0d 763 buffer[0] = PICC_CMD_HLTA;
shivanandgowdakr 0:0ee2c6d9ee0d 764 buffer[1] = 0;
shivanandgowdakr 0:0ee2c6d9ee0d 765
shivanandgowdakr 0:0ee2c6d9ee0d 766 // Calculate CRC_A
shivanandgowdakr 0:0ee2c6d9ee0d 767 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
shivanandgowdakr 0:0ee2c6d9ee0d 768 if (result == STATUS_OK)
shivanandgowdakr 0:0ee2c6d9ee0d 769 {
shivanandgowdakr 0:0ee2c6d9ee0d 770 // Send the command.
shivanandgowdakr 0:0ee2c6d9ee0d 771 // The standard says:
shivanandgowdakr 0:0ee2c6d9ee0d 772 // If the PICC responds with any modulation during a period of 1 ms after the end of the frame containing the
shivanandgowdakr 0:0ee2c6d9ee0d 773 // HLTA command, this response shall be interpreted as 'not acknowledge'.
shivanandgowdakr 0:0ee2c6d9ee0d 774 // We interpret that this way: Only STATUS_TIMEOUT is an success.
shivanandgowdakr 0:0ee2c6d9ee0d 775 result = PCD_TransceiveData(buffer, sizeof(buffer), NULL, 0);
shivanandgowdakr 0:0ee2c6d9ee0d 776 if (result == STATUS_TIMEOUT)
shivanandgowdakr 0:0ee2c6d9ee0d 777 {
shivanandgowdakr 0:0ee2c6d9ee0d 778 result = STATUS_OK;
shivanandgowdakr 0:0ee2c6d9ee0d 779 }
shivanandgowdakr 0:0ee2c6d9ee0d 780 else if (result == STATUS_OK)
shivanandgowdakr 0:0ee2c6d9ee0d 781 { // That is ironically NOT ok in this case ;-)
shivanandgowdakr 0:0ee2c6d9ee0d 782 result = STATUS_ERROR;
shivanandgowdakr 0:0ee2c6d9ee0d 783 }
shivanandgowdakr 0:0ee2c6d9ee0d 784 }
shivanandgowdakr 0:0ee2c6d9ee0d 785
shivanandgowdakr 0:0ee2c6d9ee0d 786 return result;
shivanandgowdakr 0:0ee2c6d9ee0d 787 } // End PICC_HaltA()
shivanandgowdakr 0:0ee2c6d9ee0d 788
shivanandgowdakr 0:0ee2c6d9ee0d 789
shivanandgowdakr 0:0ee2c6d9ee0d 790 /////////////////////////////////////////////////////////////////////////////////////
shivanandgowdakr 0:0ee2c6d9ee0d 791 // Functions for communicating with MIFARE PICCs
shivanandgowdakr 0:0ee2c6d9ee0d 792 /////////////////////////////////////////////////////////////////////////////////////
shivanandgowdakr 0:0ee2c6d9ee0d 793
shivanandgowdakr 0:0ee2c6d9ee0d 794 /*
shivanandgowdakr 0:0ee2c6d9ee0d 795 * Executes the MFRC522 MFAuthent command.
shivanandgowdakr 0:0ee2c6d9ee0d 796 */
shivanandgowdakr 0:0ee2c6d9ee0d 797 uint8_t MFRC522::PCD_Authenticate(uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid)
shivanandgowdakr 0:0ee2c6d9ee0d 798 {
shivanandgowdakr 0:0ee2c6d9ee0d 799 uint8_t i, waitIRq = 0x10; // IdleIRq
shivanandgowdakr 0:0ee2c6d9ee0d 800
shivanandgowdakr 0:0ee2c6d9ee0d 801 // Build command buffer
shivanandgowdakr 0:0ee2c6d9ee0d 802 uint8_t sendData[12];
shivanandgowdakr 0:0ee2c6d9ee0d 803 sendData[0] = command;
shivanandgowdakr 0:0ee2c6d9ee0d 804 sendData[1] = blockAddr;
shivanandgowdakr 0:0ee2c6d9ee0d 805
shivanandgowdakr 0:0ee2c6d9ee0d 806 for (i = 0; i < MF_KEY_SIZE; i++)
shivanandgowdakr 0:0ee2c6d9ee0d 807 { // 6 key bytes
shivanandgowdakr 0:0ee2c6d9ee0d 808 sendData[2+i] = key->keyByte[i];
shivanandgowdakr 0:0ee2c6d9ee0d 809 }
shivanandgowdakr 0:0ee2c6d9ee0d 810
shivanandgowdakr 0:0ee2c6d9ee0d 811 for (i = 0; i < 4; i++)
shivanandgowdakr 0:0ee2c6d9ee0d 812 { // The first 4 bytes of the UID
shivanandgowdakr 0:0ee2c6d9ee0d 813 sendData[8+i] = uid->uidByte[i];
shivanandgowdakr 0:0ee2c6d9ee0d 814 }
shivanandgowdakr 0:0ee2c6d9ee0d 815
shivanandgowdakr 0:0ee2c6d9ee0d 816 // Start the authentication.
shivanandgowdakr 0:0ee2c6d9ee0d 817 return PCD_CommunicateWithPICC(PCD_MFAuthent, waitIRq, &sendData[0], sizeof(sendData));
shivanandgowdakr 0:0ee2c6d9ee0d 818 } // End PCD_Authenticate()
shivanandgowdakr 0:0ee2c6d9ee0d 819
shivanandgowdakr 0:0ee2c6d9ee0d 820 /*
shivanandgowdakr 0:0ee2c6d9ee0d 821 * Used to exit the PCD from its authenticated state.
shivanandgowdakr 0:0ee2c6d9ee0d 822 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
shivanandgowdakr 0:0ee2c6d9ee0d 823 */
shivanandgowdakr 0:0ee2c6d9ee0d 824 void MFRC522::PCD_StopCrypto1()
shivanandgowdakr 0:0ee2c6d9ee0d 825 {
shivanandgowdakr 0:0ee2c6d9ee0d 826 // Clear MFCrypto1On bit
shivanandgowdakr 0:0ee2c6d9ee0d 827 PCD_ClrRegisterBits(Status2Reg, 0x08); // Status2Reg[7..0] bits are: TempSensClear I2CForceHS reserved reserved MFCrypto1On ModemState[2:0]
shivanandgowdakr 0:0ee2c6d9ee0d 828 } // End PCD_StopCrypto1()
shivanandgowdakr 0:0ee2c6d9ee0d 829
shivanandgowdakr 0:0ee2c6d9ee0d 830 /*
shivanandgowdakr 0:0ee2c6d9ee0d 831 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
shivanandgowdakr 0:0ee2c6d9ee0d 832 */
shivanandgowdakr 0:0ee2c6d9ee0d 833 uint8_t MFRC522::MIFARE_Read(uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize)
shivanandgowdakr 0:0ee2c6d9ee0d 834 {
shivanandgowdakr 0:0ee2c6d9ee0d 835 uint8_t result = STATUS_NO_ROOM;
shivanandgowdakr 0:0ee2c6d9ee0d 836
shivanandgowdakr 0:0ee2c6d9ee0d 837 // Sanity check
shivanandgowdakr 0:0ee2c6d9ee0d 838 if ((buffer == NULL) || (*bufferSize < 18))
shivanandgowdakr 0:0ee2c6d9ee0d 839 {
shivanandgowdakr 0:0ee2c6d9ee0d 840 return result;
shivanandgowdakr 0:0ee2c6d9ee0d 841 }
shivanandgowdakr 0:0ee2c6d9ee0d 842
shivanandgowdakr 0:0ee2c6d9ee0d 843 // Build command buffer
shivanandgowdakr 0:0ee2c6d9ee0d 844 buffer[0] = PICC_CMD_MF_READ;
shivanandgowdakr 0:0ee2c6d9ee0d 845 buffer[1] = blockAddr;
shivanandgowdakr 0:0ee2c6d9ee0d 846
shivanandgowdakr 0:0ee2c6d9ee0d 847 // Calculate CRC_A
shivanandgowdakr 0:0ee2c6d9ee0d 848 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
shivanandgowdakr 0:0ee2c6d9ee0d 849 if (result != STATUS_OK)
shivanandgowdakr 0:0ee2c6d9ee0d 850 {
shivanandgowdakr 0:0ee2c6d9ee0d 851 return result;
shivanandgowdakr 0:0ee2c6d9ee0d 852 }
shivanandgowdakr 0:0ee2c6d9ee0d 853
shivanandgowdakr 0:0ee2c6d9ee0d 854 // Transmit the buffer and receive the response, validate CRC_A.
shivanandgowdakr 0:0ee2c6d9ee0d 855 return PCD_TransceiveData(buffer, 4, buffer, bufferSize, NULL, 0, true);
shivanandgowdakr 0:0ee2c6d9ee0d 856 } // End MIFARE_Read()
shivanandgowdakr 0:0ee2c6d9ee0d 857
shivanandgowdakr 0:0ee2c6d9ee0d 858 /*
shivanandgowdakr 0:0ee2c6d9ee0d 859 * Writes 16 bytes to the active PICC.
shivanandgowdakr 0:0ee2c6d9ee0d 860 */
shivanandgowdakr 0:0ee2c6d9ee0d 861 uint8_t MFRC522::MIFARE_Write(uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize)
shivanandgowdakr 0:0ee2c6d9ee0d 862 {
shivanandgowdakr 0:0ee2c6d9ee0d 863 uint8_t result;
shivanandgowdakr 0:0ee2c6d9ee0d 864
shivanandgowdakr 0:0ee2c6d9ee0d 865 // Sanity check
shivanandgowdakr 0:0ee2c6d9ee0d 866 if (buffer == NULL || bufferSize < 16)
shivanandgowdakr 0:0ee2c6d9ee0d 867 {
shivanandgowdakr 0:0ee2c6d9ee0d 868 return STATUS_INVALID;
shivanandgowdakr 0:0ee2c6d9ee0d 869 }
shivanandgowdakr 0:0ee2c6d9ee0d 870
shivanandgowdakr 0:0ee2c6d9ee0d 871 // Mifare Classic protocol requires two communications to perform a write.
shivanandgowdakr 0:0ee2c6d9ee0d 872 // Step 1: Tell the PICC we want to write to block blockAddr.
shivanandgowdakr 0:0ee2c6d9ee0d 873 uint8_t cmdBuffer[2];
shivanandgowdakr 0:0ee2c6d9ee0d 874 cmdBuffer[0] = PICC_CMD_MF_WRITE;
shivanandgowdakr 0:0ee2c6d9ee0d 875 cmdBuffer[1] = blockAddr;
shivanandgowdakr 0:0ee2c6d9ee0d 876 // Adds CRC_A and checks that the response is MF_ACK.
shivanandgowdakr 0:0ee2c6d9ee0d 877 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
shivanandgowdakr 0:0ee2c6d9ee0d 878 if (result != STATUS_OK)
shivanandgowdakr 0:0ee2c6d9ee0d 879 {
shivanandgowdakr 0:0ee2c6d9ee0d 880 return result;
shivanandgowdakr 0:0ee2c6d9ee0d 881 }
shivanandgowdakr 0:0ee2c6d9ee0d 882
shivanandgowdakr 0:0ee2c6d9ee0d 883 // Step 2: Transfer the data
shivanandgowdakr 0:0ee2c6d9ee0d 884 // Adds CRC_A and checks that the response is MF_ACK.
shivanandgowdakr 0:0ee2c6d9ee0d 885 result = PCD_MIFARE_Transceive(buffer, bufferSize);
shivanandgowdakr 0:0ee2c6d9ee0d 886 if (result != STATUS_OK)
shivanandgowdakr 0:0ee2c6d9ee0d 887 {
shivanandgowdakr 0:0ee2c6d9ee0d 888 return result;
shivanandgowdakr 0:0ee2c6d9ee0d 889 }
shivanandgowdakr 0:0ee2c6d9ee0d 890
shivanandgowdakr 0:0ee2c6d9ee0d 891 return STATUS_OK;
shivanandgowdakr 0:0ee2c6d9ee0d 892 } // End MIFARE_Write()
shivanandgowdakr 0:0ee2c6d9ee0d 893
shivanandgowdakr 0:0ee2c6d9ee0d 894 /*
shivanandgowdakr 0:0ee2c6d9ee0d 895 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
shivanandgowdakr 0:0ee2c6d9ee0d 896 */
shivanandgowdakr 0:0ee2c6d9ee0d 897 uint8_t MFRC522::MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize)
shivanandgowdakr 0:0ee2c6d9ee0d 898 {
shivanandgowdakr 0:0ee2c6d9ee0d 899 uint8_t result;
shivanandgowdakr 0:0ee2c6d9ee0d 900
shivanandgowdakr 0:0ee2c6d9ee0d 901 // Sanity check
shivanandgowdakr 0:0ee2c6d9ee0d 902 if (buffer == NULL || bufferSize < 4)
shivanandgowdakr 0:0ee2c6d9ee0d 903 {
shivanandgowdakr 0:0ee2c6d9ee0d 904 return STATUS_INVALID;
shivanandgowdakr 0:0ee2c6d9ee0d 905 }
shivanandgowdakr 0:0ee2c6d9ee0d 906
shivanandgowdakr 0:0ee2c6d9ee0d 907 // Build commmand buffer
shivanandgowdakr 0:0ee2c6d9ee0d 908 uint8_t cmdBuffer[6];
shivanandgowdakr 0:0ee2c6d9ee0d 909 cmdBuffer[0] = PICC_CMD_UL_WRITE;
shivanandgowdakr 0:0ee2c6d9ee0d 910 cmdBuffer[1] = page;
shivanandgowdakr 0:0ee2c6d9ee0d 911 memcpy(&cmdBuffer[2], buffer, 4);
shivanandgowdakr 0:0ee2c6d9ee0d 912
shivanandgowdakr 0:0ee2c6d9ee0d 913 // Perform the write
shivanandgowdakr 0:0ee2c6d9ee0d 914 result = PCD_MIFARE_Transceive(cmdBuffer, 6); // Adds CRC_A and checks that the response is MF_ACK.
shivanandgowdakr 0:0ee2c6d9ee0d 915 if (result != STATUS_OK)
shivanandgowdakr 0:0ee2c6d9ee0d 916 {
shivanandgowdakr 0:0ee2c6d9ee0d 917 return result;
shivanandgowdakr 0:0ee2c6d9ee0d 918 }
shivanandgowdakr 0:0ee2c6d9ee0d 919
shivanandgowdakr 0:0ee2c6d9ee0d 920 return STATUS_OK;
shivanandgowdakr 0:0ee2c6d9ee0d 921 } // End MIFARE_Ultralight_Write()
shivanandgowdakr 0:0ee2c6d9ee0d 922
shivanandgowdakr 0:0ee2c6d9ee0d 923 /*
shivanandgowdakr 0:0ee2c6d9ee0d 924 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
shivanandgowdakr 0:0ee2c6d9ee0d 925 */
shivanandgowdakr 0:0ee2c6d9ee0d 926 uint8_t MFRC522::MIFARE_Decrement(uint8_t blockAddr, uint32_t delta)
shivanandgowdakr 0:0ee2c6d9ee0d 927 {
shivanandgowdakr 0:0ee2c6d9ee0d 928 return MIFARE_TwoStepHelper(PICC_CMD_MF_DECREMENT, blockAddr, delta);
shivanandgowdakr 0:0ee2c6d9ee0d 929 } // End MIFARE_Decrement()
shivanandgowdakr 0:0ee2c6d9ee0d 930
shivanandgowdakr 0:0ee2c6d9ee0d 931 /*
shivanandgowdakr 0:0ee2c6d9ee0d 932 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
shivanandgowdakr 0:0ee2c6d9ee0d 933 */
shivanandgowdakr 0:0ee2c6d9ee0d 934 uint8_t MFRC522::MIFARE_Increment(uint8_t blockAddr, uint32_t delta)
shivanandgowdakr 0:0ee2c6d9ee0d 935 {
shivanandgowdakr 0:0ee2c6d9ee0d 936 return MIFARE_TwoStepHelper(PICC_CMD_MF_INCREMENT, blockAddr, delta);
shivanandgowdakr 0:0ee2c6d9ee0d 937 } // End MIFARE_Increment()
shivanandgowdakr 0:0ee2c6d9ee0d 938
shivanandgowdakr 0:0ee2c6d9ee0d 939 /**
shivanandgowdakr 0:0ee2c6d9ee0d 940 * MIFARE Restore copies the value of the addressed block into a volatile memory.
shivanandgowdakr 0:0ee2c6d9ee0d 941 */
shivanandgowdakr 0:0ee2c6d9ee0d 942 uint8_t MFRC522::MIFARE_Restore(uint8_t blockAddr)
shivanandgowdakr 0:0ee2c6d9ee0d 943 {
shivanandgowdakr 0:0ee2c6d9ee0d 944 // The datasheet describes Restore as a two step operation, but does not explain what data to transfer in step 2.
shivanandgowdakr 0:0ee2c6d9ee0d 945 // Doing only a single step does not work, so I chose to transfer 0L in step two.
shivanandgowdakr 0:0ee2c6d9ee0d 946 return MIFARE_TwoStepHelper(PICC_CMD_MF_RESTORE, blockAddr, 0L);
shivanandgowdakr 0:0ee2c6d9ee0d 947 } // End MIFARE_Restore()
shivanandgowdakr 0:0ee2c6d9ee0d 948
shivanandgowdakr 0:0ee2c6d9ee0d 949 /*
shivanandgowdakr 0:0ee2c6d9ee0d 950 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
shivanandgowdakr 0:0ee2c6d9ee0d 951 */
shivanandgowdakr 0:0ee2c6d9ee0d 952 uint8_t MFRC522::MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data)
shivanandgowdakr 0:0ee2c6d9ee0d 953 {
shivanandgowdakr 0:0ee2c6d9ee0d 954 uint8_t result;
shivanandgowdakr 0:0ee2c6d9ee0d 955 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
shivanandgowdakr 0:0ee2c6d9ee0d 956
shivanandgowdakr 0:0ee2c6d9ee0d 957 // Step 1: Tell the PICC the command and block address
shivanandgowdakr 0:0ee2c6d9ee0d 958 cmdBuffer[0] = command;
shivanandgowdakr 0:0ee2c6d9ee0d 959 cmdBuffer[1] = blockAddr;
shivanandgowdakr 0:0ee2c6d9ee0d 960
shivanandgowdakr 0:0ee2c6d9ee0d 961 // Adds CRC_A and checks that the response is MF_ACK.
shivanandgowdakr 0:0ee2c6d9ee0d 962 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
shivanandgowdakr 0:0ee2c6d9ee0d 963 if (result != STATUS_OK)
shivanandgowdakr 0:0ee2c6d9ee0d 964 {
shivanandgowdakr 0:0ee2c6d9ee0d 965 return result;
shivanandgowdakr 0:0ee2c6d9ee0d 966 }
shivanandgowdakr 0:0ee2c6d9ee0d 967
shivanandgowdakr 0:0ee2c6d9ee0d 968 // Step 2: Transfer the data
shivanandgowdakr 0:0ee2c6d9ee0d 969 // Adds CRC_A and accept timeout as success.
shivanandgowdakr 0:0ee2c6d9ee0d 970 result = PCD_MIFARE_Transceive((uint8_t *) &data, 4, true);
shivanandgowdakr 0:0ee2c6d9ee0d 971 if (result != STATUS_OK)
shivanandgowdakr 0:0ee2c6d9ee0d 972 {
shivanandgowdakr 0:0ee2c6d9ee0d 973 return result;
shivanandgowdakr 0:0ee2c6d9ee0d 974 }
shivanandgowdakr 0:0ee2c6d9ee0d 975
shivanandgowdakr 0:0ee2c6d9ee0d 976 return STATUS_OK;
shivanandgowdakr 0:0ee2c6d9ee0d 977 } // End MIFARE_TwoStepHelper()
shivanandgowdakr 0:0ee2c6d9ee0d 978
shivanandgowdakr 0:0ee2c6d9ee0d 979 /*
shivanandgowdakr 0:0ee2c6d9ee0d 980 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
shivanandgowdakr 0:0ee2c6d9ee0d 981 */
shivanandgowdakr 0:0ee2c6d9ee0d 982 uint8_t MFRC522::MIFARE_Transfer(uint8_t blockAddr)
shivanandgowdakr 0:0ee2c6d9ee0d 983 {
shivanandgowdakr 0:0ee2c6d9ee0d 984 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
shivanandgowdakr 0:0ee2c6d9ee0d 985
shivanandgowdakr 0:0ee2c6d9ee0d 986 // Tell the PICC we want to transfer the result into block blockAddr.
shivanandgowdakr 0:0ee2c6d9ee0d 987 cmdBuffer[0] = PICC_CMD_MF_TRANSFER;
shivanandgowdakr 0:0ee2c6d9ee0d 988 cmdBuffer[1] = blockAddr;
shivanandgowdakr 0:0ee2c6d9ee0d 989
shivanandgowdakr 0:0ee2c6d9ee0d 990 // Adds CRC_A and checks that the response is MF_ACK.
shivanandgowdakr 0:0ee2c6d9ee0d 991 return PCD_MIFARE_Transceive(cmdBuffer, 2);
shivanandgowdakr 0:0ee2c6d9ee0d 992 } // End MIFARE_Transfer()
shivanandgowdakr 0:0ee2c6d9ee0d 993
shivanandgowdakr 0:0ee2c6d9ee0d 994
shivanandgowdakr 0:0ee2c6d9ee0d 995 /////////////////////////////////////////////////////////////////////////////////////
shivanandgowdakr 0:0ee2c6d9ee0d 996 // Support functions
shivanandgowdakr 0:0ee2c6d9ee0d 997 /////////////////////////////////////////////////////////////////////////////////////
shivanandgowdakr 0:0ee2c6d9ee0d 998
shivanandgowdakr 0:0ee2c6d9ee0d 999 /*
shivanandgowdakr 0:0ee2c6d9ee0d 1000 * Wrapper for MIFARE protocol communication.
shivanandgowdakr 0:0ee2c6d9ee0d 1001 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
shivanandgowdakr 0:0ee2c6d9ee0d 1002 */
shivanandgowdakr 0:0ee2c6d9ee0d 1003 uint8_t MFRC522::PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout)
shivanandgowdakr 0:0ee2c6d9ee0d 1004 {
shivanandgowdakr 0:0ee2c6d9ee0d 1005 uint8_t result;
shivanandgowdakr 0:0ee2c6d9ee0d 1006 uint8_t cmdBuffer[18]; // We need room for 16 bytes data and 2 bytes CRC_A.
shivanandgowdakr 0:0ee2c6d9ee0d 1007
shivanandgowdakr 0:0ee2c6d9ee0d 1008 // Sanity check
shivanandgowdakr 0:0ee2c6d9ee0d 1009 if (sendData == NULL || sendLen > 16)
shivanandgowdakr 0:0ee2c6d9ee0d 1010 {
shivanandgowdakr 0:0ee2c6d9ee0d 1011 return STATUS_INVALID;
shivanandgowdakr 0:0ee2c6d9ee0d 1012 }
shivanandgowdakr 0:0ee2c6d9ee0d 1013
shivanandgowdakr 0:0ee2c6d9ee0d 1014 // Copy sendData[] to cmdBuffer[] and add CRC_A
shivanandgowdakr 0:0ee2c6d9ee0d 1015 memcpy(cmdBuffer, sendData, sendLen);
shivanandgowdakr 0:0ee2c6d9ee0d 1016 result = PCD_CalculateCRC(cmdBuffer, sendLen, &cmdBuffer[sendLen]);
shivanandgowdakr 0:0ee2c6d9ee0d 1017 if (result != STATUS_OK)
shivanandgowdakr 0:0ee2c6d9ee0d 1018 {
shivanandgowdakr 0:0ee2c6d9ee0d 1019 return result;
shivanandgowdakr 0:0ee2c6d9ee0d 1020 }
shivanandgowdakr 0:0ee2c6d9ee0d 1021
shivanandgowdakr 0:0ee2c6d9ee0d 1022 sendLen += 2;
shivanandgowdakr 0:0ee2c6d9ee0d 1023
shivanandgowdakr 0:0ee2c6d9ee0d 1024 // Transceive the data, store the reply in cmdBuffer[]
shivanandgowdakr 0:0ee2c6d9ee0d 1025 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
shivanandgowdakr 0:0ee2c6d9ee0d 1026 uint8_t cmdBufferSize = sizeof(cmdBuffer);
shivanandgowdakr 0:0ee2c6d9ee0d 1027 uint8_t validBits = 0;
shivanandgowdakr 0:0ee2c6d9ee0d 1028 result = PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, cmdBuffer, sendLen, cmdBuffer, &cmdBufferSize, &validBits);
shivanandgowdakr 0:0ee2c6d9ee0d 1029 if (acceptTimeout && result == STATUS_TIMEOUT)
shivanandgowdakr 0:0ee2c6d9ee0d 1030 {
shivanandgowdakr 0:0ee2c6d9ee0d 1031 return STATUS_OK;
shivanandgowdakr 0:0ee2c6d9ee0d 1032 }
shivanandgowdakr 0:0ee2c6d9ee0d 1033
shivanandgowdakr 0:0ee2c6d9ee0d 1034 if (result != STATUS_OK)
shivanandgowdakr 0:0ee2c6d9ee0d 1035 {
shivanandgowdakr 0:0ee2c6d9ee0d 1036 return result;
shivanandgowdakr 0:0ee2c6d9ee0d 1037 }
shivanandgowdakr 0:0ee2c6d9ee0d 1038
shivanandgowdakr 0:0ee2c6d9ee0d 1039 // The PICC must reply with a 4 bit ACK
shivanandgowdakr 0:0ee2c6d9ee0d 1040 if (cmdBufferSize != 1 || validBits != 4)
shivanandgowdakr 0:0ee2c6d9ee0d 1041 {
shivanandgowdakr 0:0ee2c6d9ee0d 1042 return STATUS_ERROR;
shivanandgowdakr 0:0ee2c6d9ee0d 1043 }
shivanandgowdakr 0:0ee2c6d9ee0d 1044
shivanandgowdakr 0:0ee2c6d9ee0d 1045 if (cmdBuffer[0] != MF_ACK)
shivanandgowdakr 0:0ee2c6d9ee0d 1046 {
shivanandgowdakr 0:0ee2c6d9ee0d 1047 return STATUS_MIFARE_NACK;
shivanandgowdakr 0:0ee2c6d9ee0d 1048 }
shivanandgowdakr 0:0ee2c6d9ee0d 1049
shivanandgowdakr 0:0ee2c6d9ee0d 1050 return STATUS_OK;
shivanandgowdakr 0:0ee2c6d9ee0d 1051 } // End PCD_MIFARE_Transceive()
shivanandgowdakr 0:0ee2c6d9ee0d 1052
shivanandgowdakr 0:0ee2c6d9ee0d 1053
shivanandgowdakr 0:0ee2c6d9ee0d 1054 /*
shivanandgowdakr 0:0ee2c6d9ee0d 1055 * Translates the SAK (Select Acknowledge) to a PICC type.
shivanandgowdakr 0:0ee2c6d9ee0d 1056 */
shivanandgowdakr 0:0ee2c6d9ee0d 1057 uint8_t MFRC522::PICC_GetType(uint8_t sak)
shivanandgowdakr 0:0ee2c6d9ee0d 1058 {
shivanandgowdakr 0:0ee2c6d9ee0d 1059 uint8_t retType = PICC_TYPE_UNKNOWN;
shivanandgowdakr 0:0ee2c6d9ee0d 1060
shivanandgowdakr 0:0ee2c6d9ee0d 1061 if (sak & 0x04)
shivanandgowdakr 0:0ee2c6d9ee0d 1062 { // UID not complete
shivanandgowdakr 0:0ee2c6d9ee0d 1063 retType = PICC_TYPE_NOT_COMPLETE;
shivanandgowdakr 0:0ee2c6d9ee0d 1064 }
shivanandgowdakr 0:0ee2c6d9ee0d 1065 else
shivanandgowdakr 0:0ee2c6d9ee0d 1066 {
shivanandgowdakr 0:0ee2c6d9ee0d 1067 switch (sak)
shivanandgowdakr 0:0ee2c6d9ee0d 1068 {
shivanandgowdakr 0:0ee2c6d9ee0d 1069 case 0x09: retType = PICC_TYPE_MIFARE_MINI; break;
shivanandgowdakr 0:0ee2c6d9ee0d 1070 case 0x08: retType = PICC_TYPE_MIFARE_1K; break;
shivanandgowdakr 0:0ee2c6d9ee0d 1071 case 0x18: retType = PICC_TYPE_MIFARE_4K; break;
shivanandgowdakr 0:0ee2c6d9ee0d 1072 case 0x00: retType = PICC_TYPE_MIFARE_UL; break;
shivanandgowdakr 0:0ee2c6d9ee0d 1073 case 0x10:
shivanandgowdakr 0:0ee2c6d9ee0d 1074 case 0x11: retType = PICC_TYPE_MIFARE_PLUS; break;
shivanandgowdakr 0:0ee2c6d9ee0d 1075 case 0x01: retType = PICC_TYPE_TNP3XXX; break;
shivanandgowdakr 0:0ee2c6d9ee0d 1076 default:
shivanandgowdakr 0:0ee2c6d9ee0d 1077 if (sak & 0x20)
shivanandgowdakr 0:0ee2c6d9ee0d 1078 {
shivanandgowdakr 0:0ee2c6d9ee0d 1079 retType = PICC_TYPE_ISO_14443_4;
shivanandgowdakr 0:0ee2c6d9ee0d 1080 }
shivanandgowdakr 0:0ee2c6d9ee0d 1081 else if (sak & 0x40)
shivanandgowdakr 0:0ee2c6d9ee0d 1082 {
shivanandgowdakr 0:0ee2c6d9ee0d 1083 retType = PICC_TYPE_ISO_18092;
shivanandgowdakr 0:0ee2c6d9ee0d 1084 }
shivanandgowdakr 0:0ee2c6d9ee0d 1085 break;
shivanandgowdakr 0:0ee2c6d9ee0d 1086 }
shivanandgowdakr 0:0ee2c6d9ee0d 1087 }
shivanandgowdakr 0:0ee2c6d9ee0d 1088
shivanandgowdakr 0:0ee2c6d9ee0d 1089 return (retType);
shivanandgowdakr 0:0ee2c6d9ee0d 1090 } // End PICC_GetType()
shivanandgowdakr 0:0ee2c6d9ee0d 1091
shivanandgowdakr 0:0ee2c6d9ee0d 1092 /*
shivanandgowdakr 0:0ee2c6d9ee0d 1093 * Returns a string pointer to the PICC type name.
shivanandgowdakr 0:0ee2c6d9ee0d 1094 */
shivanandgowdakr 0:0ee2c6d9ee0d 1095 char* MFRC522::PICC_GetTypeName(uint8_t piccType)
shivanandgowdakr 0:0ee2c6d9ee0d 1096 {
shivanandgowdakr 0:0ee2c6d9ee0d 1097 if(piccType == PICC_TYPE_NOT_COMPLETE)
shivanandgowdakr 0:0ee2c6d9ee0d 1098 {
shivanandgowdakr 0:0ee2c6d9ee0d 1099 piccType = MFRC522_MaxPICCs - 1;
shivanandgowdakr 0:0ee2c6d9ee0d 1100 }
shivanandgowdakr 0:0ee2c6d9ee0d 1101
shivanandgowdakr 0:0ee2c6d9ee0d 1102 return((char *) _TypeNamePICC[piccType]);
shivanandgowdakr 0:0ee2c6d9ee0d 1103 } // End PICC_GetTypeName()
shivanandgowdakr 0:0ee2c6d9ee0d 1104
shivanandgowdakr 0:0ee2c6d9ee0d 1105 /*
shivanandgowdakr 0:0ee2c6d9ee0d 1106 * Returns a string pointer to a status code name.
shivanandgowdakr 0:0ee2c6d9ee0d 1107 */
shivanandgowdakr 0:0ee2c6d9ee0d 1108 char* MFRC522::GetStatusCodeName(uint8_t code)
shivanandgowdakr 0:0ee2c6d9ee0d 1109 {
shivanandgowdakr 0:0ee2c6d9ee0d 1110 return((char *) _ErrorMessage[code]);
shivanandgowdakr 0:0ee2c6d9ee0d 1111 } // End GetStatusCodeName()
shivanandgowdakr 0:0ee2c6d9ee0d 1112
shivanandgowdakr 0:0ee2c6d9ee0d 1113 /*
shivanandgowdakr 0:0ee2c6d9ee0d 1114 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
shivanandgowdakr 0:0ee2c6d9ee0d 1115 */
shivanandgowdakr 0:0ee2c6d9ee0d 1116 void MFRC522::MIFARE_SetAccessBits(uint8_t *accessBitBuffer,
shivanandgowdakr 0:0ee2c6d9ee0d 1117 uint8_t g0,
shivanandgowdakr 0:0ee2c6d9ee0d 1118 uint8_t g1,
shivanandgowdakr 0:0ee2c6d9ee0d 1119 uint8_t g2,
shivanandgowdakr 0:0ee2c6d9ee0d 1120 uint8_t g3)
shivanandgowdakr 0:0ee2c6d9ee0d 1121 {
shivanandgowdakr 0:0ee2c6d9ee0d 1122 uint8_t c1 = ((g3 & 4) << 1) | ((g2 & 4) << 0) | ((g1 & 4) >> 1) | ((g0 & 4) >> 2);
shivanandgowdakr 0:0ee2c6d9ee0d 1123 uint8_t c2 = ((g3 & 2) << 2) | ((g2 & 2) << 1) | ((g1 & 2) << 0) | ((g0 & 2) >> 1);
shivanandgowdakr 0:0ee2c6d9ee0d 1124 uint8_t c3 = ((g3 & 1) << 3) | ((g2 & 1) << 2) | ((g1 & 1) << 1) | ((g0 & 1) << 0);
shivanandgowdakr 0:0ee2c6d9ee0d 1125
shivanandgowdakr 0:0ee2c6d9ee0d 1126 accessBitBuffer[0] = (~c2 & 0xF) << 4 | (~c1 & 0xF);
shivanandgowdakr 0:0ee2c6d9ee0d 1127 accessBitBuffer[1] = c1 << 4 | (~c3 & 0xF);
shivanandgowdakr 0:0ee2c6d9ee0d 1128 accessBitBuffer[2] = c3 << 4 | c2;
shivanandgowdakr 0:0ee2c6d9ee0d 1129 } // End MIFARE_SetAccessBits()
shivanandgowdakr 0:0ee2c6d9ee0d 1130
shivanandgowdakr 0:0ee2c6d9ee0d 1131 /////////////////////////////////////////////////////////////////////////////////////
shivanandgowdakr 0:0ee2c6d9ee0d 1132 // Convenience functions - does not add extra functionality
shivanandgowdakr 0:0ee2c6d9ee0d 1133 /////////////////////////////////////////////////////////////////////////////////////
shivanandgowdakr 0:0ee2c6d9ee0d 1134
shivanandgowdakr 0:0ee2c6d9ee0d 1135 /*
shivanandgowdakr 0:0ee2c6d9ee0d 1136 * Returns true if a PICC responds to PICC_CMD_REQA.
shivanandgowdakr 0:0ee2c6d9ee0d 1137 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
shivanandgowdakr 0:0ee2c6d9ee0d 1138 */
shivanandgowdakr 0:0ee2c6d9ee0d 1139 bool MFRC522::PICC_IsNewCardPresent(void)
shivanandgowdakr 0:0ee2c6d9ee0d 1140 {
shivanandgowdakr 0:0ee2c6d9ee0d 1141 uint8_t bufferATQA[2];
shivanandgowdakr 0:0ee2c6d9ee0d 1142 uint8_t bufferSize = sizeof(bufferATQA);
shivanandgowdakr 0:0ee2c6d9ee0d 1143 uint8_t result = PICC_RequestA(bufferATQA, &bufferSize);
shivanandgowdakr 0:0ee2c6d9ee0d 1144 return ((result == STATUS_OK) || (result == STATUS_COLLISION));
shivanandgowdakr 0:0ee2c6d9ee0d 1145 } // End PICC_IsNewCardPresent()
shivanandgowdakr 0:0ee2c6d9ee0d 1146
shivanandgowdakr 0:0ee2c6d9ee0d 1147 /*
shivanandgowdakr 0:0ee2c6d9ee0d 1148 * Simple wrapper around PICC_Select.
shivanandgowdakr 0:0ee2c6d9ee0d 1149 */
shivanandgowdakr 0:0ee2c6d9ee0d 1150 bool MFRC522::PICC_ReadCardSerial(void)
shivanandgowdakr 0:0ee2c6d9ee0d 1151 {
shivanandgowdakr 0:0ee2c6d9ee0d 1152 uint8_t result = PICC_Select(&uid);
shivanandgowdakr 0:0ee2c6d9ee0d 1153 return (result == STATUS_OK);
shivanandgowdakr 0:0ee2c6d9ee0d 1154 } // End PICC_ReadCardSerial()