Diff: main.cpp

Revision:

2:849b0ab61874

Parent:

1:f468352a5408

--- a/main.cpp	Sun May 04 04:43:19 2014 +0000
+++ b/main.cpp	Fri Aug 29 14:58:54 2014 +0000
@@ -53,10 +53,11 @@
     0x04,   // [0] Control0                  
     // TRUNC=1 - Incoming data is truncated according to the length specified in the channel status data.
     
-    0x80,   // [1] Control1                  
+    0x84,   // [1] Control1                  
     // SWCLK=1 - Enable automatic clock switching on PLL unlock. OMCK clock input is automatically output on RMCK on PLL Unlock.
     // MUTESAO=0 - SDOUT not muted.
-    // HOLD[1:0]=00 - hold last audio sample.
+    // HOLD[1:0]=01 - replace the current audio sample with all zeros (mute).
+    // RMCKF=0 - (MUST)
     
     0x45,   // [2] Control2                  
     // EMPH_CNTL[2:0]=100 - deemphasis filter auto select.
@@ -66,6 +67,7 @@
 
     0x80,   // [4] Control4                  
     // RUN=1 - normal part operation
+    // RXSEL=0 - (MUST)
 
     0x85,   // [5] Serial Audio Data Format
     // SOMS=1 - Serial audio output port is in master mode. OSCLK and OLRCK are outputs.
@@ -253,10 +255,6 @@
         pin_led1 = 0;
         u8_data = 0x00;             // (01h)[1] RMCKF - Recovered Master Clock Frequency @ 0 : 256 Fs
     }
-    
-    if (g_freq == 0) {
-        u8_data |= 0x40;             // (01h)[6] MUTESAO - Mute control for the serial audio output port
-    }
     cs8416_write(0x01, DEF_REGVAL[1] | u8_data);    // (01h) : Control1
 }
 
@@ -282,14 +280,13 @@
     fn1242_init();
     
     while (1) {
-        uint32_t u32_freq = g_freq;
         
         uint8_t u8_addr18 = cs8416_read(0x18);  // (18h) : OMCK/RMCK Ratio
         decide_freq(u8_addr18);
         set_led();
         
         uint8_t u8_addr0B = cs8416_read(0x0b);  // (0Bh) : Format Detect Status
-        if ((g_cur_frmt != u8_addr0B) || (g_freq != u32_freq)) {
+        if (g_cur_frmt != u8_addr0B) {
             g_cur_frmt = u8_addr0B;
             set_rmckf();
         }