Atsushi Shinbo
/
CS8416_SPI
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main.cpp@2:849b0ab61874, 2014-08-29 (annotated)
- Committer:
- shinbo
- Date:
- Fri Aug 29 14:58:54 2014 +0000
- Revision:
- 2:849b0ab61874
- Parent:
- 1:f468352a5408
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| shinbo | 0:cb6ecbfcf585 | 1 | #include "mbed.h" |
| shinbo | 0:cb6ecbfcf585 | 2 | |
| shinbo | 1:f468352a5408 | 3 | // this program control CS8416 in software mode(SPI) with LPC1114FN28. |
| shinbo | 0:cb6ecbfcf585 | 4 | |
| shinbo | 0:cb6ecbfcf585 | 5 | // CS8416 : 192 kHz Digital Audio Interface Receiver |
| shinbo | 0:cb6ecbfcf585 | 6 | // http://www.cirrus.com/jp/pubs/proDatasheet/CS8416_F3.pdf |
| shinbo | 0:cb6ecbfcf585 | 7 | |
| shinbo | 0:cb6ecbfcf585 | 8 | // FN1242A : 24bit/192KHz/2ch DAC |
| shinbo | 0:cb6ecbfcf585 | 9 | // http://akizukidenshi.com/download/ds/niigataseimitsu/FN1242Ajspec.pdf |
| shinbo | 0:cb6ecbfcf585 | 10 | |
| shinbo | 0:cb6ecbfcf585 | 11 | |
| shinbo | 0:cb6ecbfcf585 | 12 | // LPC1114FN28 connect to |
| shinbo | 0:cb6ecbfcf585 | 13 | // 1 MISO cs8416 / CDOUT |
| shinbo | 0:cb6ecbfcf585 | 14 | // 2 MOSI cs8416 / CDIN |
| shinbo | 0:cb6ecbfcf585 | 15 | // 3 SWCLK LPC-Link |
| shinbo | 0:cb6ecbfcf585 | 16 | // 4 PIO cs8416 / CS |
| shinbo | 0:cb6ecbfcf585 | 17 | // 6 SCK cs8416 / CCLK |
| shinbo | 0:cb6ecbfcf585 | 18 | // 7 AVIN 3.3V |
| shinbo | 0:cb6ecbfcf585 | 19 | // 8 AGND |
| shinbo | 0:cb6ecbfcf585 | 20 | // 9 PIO toggle switch : input source select. |
| shinbo | 0:cb6ecbfcf585 | 21 | // 12 SWDIO LPC-Link |
| shinbo | 0:cb6ecbfcf585 | 22 | // 14 PIO cs8416 / reset |
| shinbo | 0:cb6ecbfcf585 | 23 | // 15 PIO led1 : left |
| shinbo | 0:cb6ecbfcf585 | 24 | // 16 PIO led2 |
| shinbo | 0:cb6ecbfcf585 | 25 | // 17 PIO led3 |
| shinbo | 0:cb6ecbfcf585 | 26 | // 18 PIO led4 : right |
| shinbo | 0:cb6ecbfcf585 | 27 | // 21 VIN 3.3V |
| shinbo | 0:cb6ecbfcf585 | 28 | // 22 GND |
| shinbo | 0:cb6ecbfcf585 | 29 | // 23 RESET LPC-Link |
| shinbo | 0:cb6ecbfcf585 | 30 | // 24 PIO fn1242a / ML |
| shinbo | 0:cb6ecbfcf585 | 31 | // 25 PIO fn1242a / MD |
| shinbo | 0:cb6ecbfcf585 | 32 | // 26 PIO fn1242a / MC |
| shinbo | 0:cb6ecbfcf585 | 33 | |
| shinbo | 0:cb6ecbfcf585 | 34 | // CS8416 |
| shinbo | 0:cb6ecbfcf585 | 35 | // RXP0 : S/PDIF TOSLINK input |
| shinbo | 0:cb6ecbfcf585 | 36 | // RXP1 : S/PDIF COAX input |
| shinbo | 0:cb6ecbfcf585 | 37 | // OMCK : 11.2896 MHz |
| shinbo | 0:cb6ecbfcf585 | 38 | |
| shinbo | 0:cb6ecbfcf585 | 39 | SPI spi(dp2, dp1, dp6); // mosi, miso, sclk |
| shinbo | 0:cb6ecbfcf585 | 40 | DigitalOut pin_cs (dp4); |
| shinbo | 0:cb6ecbfcf585 | 41 | DigitalOut pin_rst (dp14); |
| shinbo | 0:cb6ecbfcf585 | 42 | DigitalOut pin_led1(dp15); |
| shinbo | 0:cb6ecbfcf585 | 43 | DigitalOut pin_led2(dp16); |
| shinbo | 0:cb6ecbfcf585 | 44 | DigitalOut pin_led3(dp17); |
| shinbo | 0:cb6ecbfcf585 | 45 | DigitalOut pin_led4(dp18); |
| shinbo | 0:cb6ecbfcf585 | 46 | DigitalIn pin_tgl (dp9); |
| shinbo | 0:cb6ecbfcf585 | 47 | DigitalOut pin_ML (dp24); |
| shinbo | 0:cb6ecbfcf585 | 48 | DigitalOut pin_MD (dp25); |
| shinbo | 0:cb6ecbfcf585 | 49 | DigitalOut pin_MC (dp26); |
| shinbo | 0:cb6ecbfcf585 | 50 | |
| shinbo | 0:cb6ecbfcf585 | 51 | |
| shinbo | 0:cb6ecbfcf585 | 52 | const uint8_t DEF_REGVAL[10] = { |
| shinbo | 1:f468352a5408 | 53 | 0x04, // [0] Control0 |
| shinbo | 1:f468352a5408 | 54 | // TRUNC=1 - Incoming data is truncated according to the length specified in the channel status data. |
| shinbo | 1:f468352a5408 | 55 | |
| shinbo | 2:849b0ab61874 | 56 | 0x84, // [1] Control1 |
| shinbo | 1:f468352a5408 | 57 | // SWCLK=1 - Enable automatic clock switching on PLL unlock. OMCK clock input is automatically output on RMCK on PLL Unlock. |
| shinbo | 1:f468352a5408 | 58 | // MUTESAO=0 - SDOUT not muted. |
| shinbo | 2:849b0ab61874 | 59 | // HOLD[1:0]=01 - replace the current audio sample with all zeros (mute). |
| shinbo | 2:849b0ab61874 | 60 | // RMCKF=0 - (MUST) |
| shinbo | 1:f468352a5408 | 61 | |
| shinbo | 1:f468352a5408 | 62 | 0x45, // [2] Control2 |
| shinbo | 1:f468352a5408 | 63 | // EMPH_CNTL[2:0]=100 - deemphasis filter auto select. |
| shinbo | 1:f468352a5408 | 64 | // GPO0SEL[3:0]=0101 - RERR/Receiver Error |
| shinbo | 1:f468352a5408 | 65 | |
| shinbo | 1:f468352a5408 | 66 | 0x00, // [3] Control3 |
| shinbo | 1:f468352a5408 | 67 | |
| shinbo | 1:f468352a5408 | 68 | 0x80, // [4] Control4 |
| shinbo | 1:f468352a5408 | 69 | // RUN=1 - normal part operation |
| shinbo | 2:849b0ab61874 | 70 | // RXSEL=0 - (MUST) |
| shinbo | 1:f468352a5408 | 71 | |
| shinbo | 1:f468352a5408 | 72 | 0x85, // [5] Serial Audio Data Format |
| shinbo | 1:f468352a5408 | 73 | // SOMS=1 - Serial audio output port is in master mode. OSCLK and OLRCK are outputs. |
| shinbo | 1:f468352a5408 | 74 | // SOSF=0 - OSCLK output frequency is 64*Fs. |
| shinbo | 1:f468352a5408 | 75 | // SORES[1:0]=00 - 24-bit resolution. |
| shinbo | 1:f468352a5408 | 76 | // SOJUST=0 - Left-Justified. |
| shinbo | 1:f468352a5408 | 77 | // SODEL=1 - second OSCLK period. |
| shinbo | 1:f468352a5408 | 78 | // SOSPOL=0 - SDOUT is sampled on rising edges of OSCLK. |
| shinbo | 1:f468352a5408 | 79 | // SOLRPOL=1 - right channel when OLRCK is high. |
| shinbo | 1:f468352a5408 | 80 | |
| shinbo | 0:cb6ecbfcf585 | 81 | 0x00, // 0x06 : Receiver Error Mask |
| shinbo | 0:cb6ecbfcf585 | 82 | 0x00, // 0x07 : Interrupt Mask |
| shinbo | 0:cb6ecbfcf585 | 83 | 0x00, // 0x08 : Interrupt Mode MSB |
| shinbo | 0:cb6ecbfcf585 | 84 | 0x00 // 0x09 : Interrupt Mode LSB |
| shinbo | 0:cb6ecbfcf585 | 85 | }; |
| shinbo | 0:cb6ecbfcf585 | 86 | |
| shinbo | 0:cb6ecbfcf585 | 87 | uint32_t g_freq = 0; |
| shinbo | 0:cb6ecbfcf585 | 88 | uint8_t g_cur_frmt = 0; |
| shinbo | 0:cb6ecbfcf585 | 89 | uint32_t g_cur_tgl = 0; |
| shinbo | 0:cb6ecbfcf585 | 90 | |
| shinbo | 0:cb6ecbfcf585 | 91 | |
| shinbo | 0:cb6ecbfcf585 | 92 | void fn1242_write(uint16_t word) { |
| shinbo | 0:cb6ecbfcf585 | 93 | |
| shinbo | 0:cb6ecbfcf585 | 94 | pin_ML = 1; |
| shinbo | 0:cb6ecbfcf585 | 95 | |
| shinbo | 0:cb6ecbfcf585 | 96 | for (int iii = 0; iii < 16; iii++) { |
| shinbo | 0:cb6ecbfcf585 | 97 | pin_MC = 0; |
| shinbo | 0:cb6ecbfcf585 | 98 | pin_MD = (word & 0x8000) == 0 ? 0 : 1; // msb first |
| shinbo | 0:cb6ecbfcf585 | 99 | wait_us(10); // us |
| shinbo | 0:cb6ecbfcf585 | 100 | |
| shinbo | 0:cb6ecbfcf585 | 101 | pin_MC = 1; |
| shinbo | 0:cb6ecbfcf585 | 102 | wait_us(10); // us |
| shinbo | 0:cb6ecbfcf585 | 103 | |
| shinbo | 0:cb6ecbfcf585 | 104 | word = word << 1; |
| shinbo | 0:cb6ecbfcf585 | 105 | } |
| shinbo | 0:cb6ecbfcf585 | 106 | |
| shinbo | 0:cb6ecbfcf585 | 107 | pin_MD = 0; |
| shinbo | 0:cb6ecbfcf585 | 108 | pin_MC = 0; |
| shinbo | 0:cb6ecbfcf585 | 109 | pin_ML = 0; |
| shinbo | 0:cb6ecbfcf585 | 110 | wait_us(10); // us |
| shinbo | 0:cb6ecbfcf585 | 111 | |
| shinbo | 0:cb6ecbfcf585 | 112 | pin_ML = 1; |
| shinbo | 0:cb6ecbfcf585 | 113 | wait_us(10); // us |
| shinbo | 0:cb6ecbfcf585 | 114 | } |
| shinbo | 0:cb6ecbfcf585 | 115 | |
| shinbo | 0:cb6ecbfcf585 | 116 | void fn1242_init() { |
| shinbo | 0:cb6ecbfcf585 | 117 | |
| shinbo | 0:cb6ecbfcf585 | 118 | pin_ML = 1; |
| shinbo | 0:cb6ecbfcf585 | 119 | pin_MD = 0; |
| shinbo | 0:cb6ecbfcf585 | 120 | pin_MC = 0; |
| shinbo | 0:cb6ecbfcf585 | 121 | wait_us(10); // us |
| shinbo | 0:cb6ecbfcf585 | 122 | |
| shinbo | 0:cb6ecbfcf585 | 123 | fn1242_write( |
| shinbo | 0:cb6ecbfcf585 | 124 | (2 << 11) // MODE2 |
| shinbo | 0:cb6ecbfcf585 | 125 | | (0 << 9) // OM (default) |
| shinbo | 0:cb6ecbfcf585 | 126 | | (0 << 8) // RST (OFF/default) |
| shinbo | 0:cb6ecbfcf585 | 127 | | (2 << 6) // BIT (24bit) |
| shinbo | 0:cb6ecbfcf585 | 128 | | (0 << 4) // ZM (default) |
| shinbo | 0:cb6ecbfcf585 | 129 | | (0 << 3) // ATC (default) |
| shinbo | 0:cb6ecbfcf585 | 130 | | (0 << 2) // MUTE (OFF/default) |
| shinbo | 0:cb6ecbfcf585 | 131 | | (0 ) ); // EMPH (OFF/default) |
| shinbo | 1:f468352a5408 | 132 | |
| shinbo | 1:f468352a5408 | 133 | wait_us(10); // us |
| shinbo | 1:f468352a5408 | 134 | fn1242_write( |
| shinbo | 1:f468352a5408 | 135 | (0 << 11) // MODE0 |
| shinbo | 1:f468352a5408 | 136 | | (0 << 10) // LDL -> disable |
| shinbo | 1:f468352a5408 | 137 | | 1023); // 10bit |
| shinbo | 1:f468352a5408 | 138 | wait_us(10); // us |
| shinbo | 1:f468352a5408 | 139 | fn1242_write( |
| shinbo | 1:f468352a5408 | 140 | (1 << 11) // MODE1 |
| shinbo | 1:f468352a5408 | 141 | | (0 << 10) // LDR -> disable |
| shinbo | 1:f468352a5408 | 142 | | 1023); // 10bit |
| shinbo | 1:f468352a5408 | 143 | |
| shinbo | 0:cb6ecbfcf585 | 144 | } |
| shinbo | 0:cb6ecbfcf585 | 145 | |
| shinbo | 0:cb6ecbfcf585 | 146 | void cs8416_write(uint8_t u8_addr, uint8_t u8_data) { |
| shinbo | 0:cb6ecbfcf585 | 147 | uint8_t u8_recv = 0; |
| shinbo | 0:cb6ecbfcf585 | 148 | |
| shinbo | 0:cb6ecbfcf585 | 149 | pin_cs = 0; |
| shinbo | 0:cb6ecbfcf585 | 150 | wait_us(10); // us |
| shinbo | 0:cb6ecbfcf585 | 151 | u8_recv = spi.write(0x20); |
| shinbo | 0:cb6ecbfcf585 | 152 | u8_recv = spi.write(u8_addr); |
| shinbo | 0:cb6ecbfcf585 | 153 | u8_recv = spi.write(u8_data); |
| shinbo | 0:cb6ecbfcf585 | 154 | pin_cs = 1; |
| shinbo | 0:cb6ecbfcf585 | 155 | wait_us(10); // us |
| shinbo | 0:cb6ecbfcf585 | 156 | } |
| shinbo | 0:cb6ecbfcf585 | 157 | |
| shinbo | 0:cb6ecbfcf585 | 158 | |
| shinbo | 0:cb6ecbfcf585 | 159 | uint8_t cs8416_read(uint8_t u8_addr) { |
| shinbo | 0:cb6ecbfcf585 | 160 | uint8_t u8_recv = 0; |
| shinbo | 0:cb6ecbfcf585 | 161 | |
| shinbo | 0:cb6ecbfcf585 | 162 | pin_cs = 0; |
| shinbo | 0:cb6ecbfcf585 | 163 | wait_us(10); // us |
| shinbo | 0:cb6ecbfcf585 | 164 | u8_recv = spi.write(0x20); |
| shinbo | 0:cb6ecbfcf585 | 165 | u8_recv = spi.write(u8_addr); |
| shinbo | 0:cb6ecbfcf585 | 166 | pin_cs = 1; |
| shinbo | 0:cb6ecbfcf585 | 167 | wait_us(10); // us |
| shinbo | 0:cb6ecbfcf585 | 168 | |
| shinbo | 0:cb6ecbfcf585 | 169 | pin_cs = 0; |
| shinbo | 0:cb6ecbfcf585 | 170 | wait_us(10); // us |
| shinbo | 0:cb6ecbfcf585 | 171 | u8_recv = spi.write(0x21); |
| shinbo | 0:cb6ecbfcf585 | 172 | u8_recv = spi.write(0x00); |
| shinbo | 0:cb6ecbfcf585 | 173 | pin_cs = 1; |
| shinbo | 0:cb6ecbfcf585 | 174 | wait_us(10); // us |
| shinbo | 0:cb6ecbfcf585 | 175 | |
| shinbo | 0:cb6ecbfcf585 | 176 | return u8_recv; |
| shinbo | 0:cb6ecbfcf585 | 177 | } |
| shinbo | 0:cb6ecbfcf585 | 178 | |
| shinbo | 0:cb6ecbfcf585 | 179 | |
| shinbo | 0:cb6ecbfcf585 | 180 | void cs8416_init() { |
| shinbo | 0:cb6ecbfcf585 | 181 | |
| shinbo | 0:cb6ecbfcf585 | 182 | pin_rst = 0; // reset |
| shinbo | 0:cb6ecbfcf585 | 183 | wait_ms(100); // ms |
| shinbo | 0:cb6ecbfcf585 | 184 | pin_rst = 1; |
| shinbo | 0:cb6ecbfcf585 | 185 | wait_ms(1); // ms |
| shinbo | 0:cb6ecbfcf585 | 186 | |
| shinbo | 0:cb6ecbfcf585 | 187 | // SPI Mode is selected if there is a high to low transition on the AD0/CS pin, after the RST pin has been brought high. |
| shinbo | 0:cb6ecbfcf585 | 188 | pin_cs = 1; wait_ms(1); |
| shinbo | 0:cb6ecbfcf585 | 189 | pin_cs = 0; wait_ms(1); // enter SPI mode |
| shinbo | 0:cb6ecbfcf585 | 190 | pin_cs = 1; wait_ms(1); |
| shinbo | 0:cb6ecbfcf585 | 191 | |
| shinbo | 0:cb6ecbfcf585 | 192 | for (int iii = 0; iii < 10; iii++) { |
| shinbo | 0:cb6ecbfcf585 | 193 | uint8_t u8_addr = (uint8_t) iii; |
| shinbo | 0:cb6ecbfcf585 | 194 | uint8_t u8_data = DEF_REGVAL[iii]; |
| shinbo | 0:cb6ecbfcf585 | 195 | cs8416_write(u8_addr, u8_data); |
| shinbo | 0:cb6ecbfcf585 | 196 | } |
| shinbo | 0:cb6ecbfcf585 | 197 | } |
| shinbo | 0:cb6ecbfcf585 | 198 | |
| shinbo | 0:cb6ecbfcf585 | 199 | |
| shinbo | 0:cb6ecbfcf585 | 200 | void decide_freq(uint8_t u8_addr18) { |
| shinbo | 0:cb6ecbfcf585 | 201 | |
| shinbo | 0:cb6ecbfcf585 | 202 | switch (u8_addr18) { |
| shinbo | 0:cb6ecbfcf585 | 203 | case 0x59: |
| shinbo | 0:cb6ecbfcf585 | 204 | case 0x58: |
| shinbo | 0:cb6ecbfcf585 | 205 | case 0x57: g_freq = 32; break; |
| shinbo | 0:cb6ecbfcf585 | 206 | |
| shinbo | 0:cb6ecbfcf585 | 207 | case 0x40: |
| shinbo | 0:cb6ecbfcf585 | 208 | case 0x3f: g_freq = 44; break; |
| shinbo | 0:cb6ecbfcf585 | 209 | |
| shinbo | 0:cb6ecbfcf585 | 210 | case 0x3b: |
| shinbo | 0:cb6ecbfcf585 | 211 | case 0x3a: g_freq = 48; break; |
| shinbo | 0:cb6ecbfcf585 | 212 | |
| shinbo | 0:cb6ecbfcf585 | 213 | case 0x20: |
| shinbo | 0:cb6ecbfcf585 | 214 | case 0x1f: g_freq = 88; break; |
| shinbo | 0:cb6ecbfcf585 | 215 | |
| shinbo | 0:cb6ecbfcf585 | 216 | case 0x1d: |
| shinbo | 0:cb6ecbfcf585 | 217 | case 0x1c: g_freq = 96; break; |
| shinbo | 0:cb6ecbfcf585 | 218 | |
| shinbo | 0:cb6ecbfcf585 | 219 | case 0x10: |
| shinbo | 0:cb6ecbfcf585 | 220 | case 0x0f: g_freq = 176; break; |
| shinbo | 0:cb6ecbfcf585 | 221 | |
| shinbo | 0:cb6ecbfcf585 | 222 | case 0x0e: g_freq = 192; break; |
| shinbo | 0:cb6ecbfcf585 | 223 | |
| shinbo | 0:cb6ecbfcf585 | 224 | default: g_freq = 0; break; |
| shinbo | 0:cb6ecbfcf585 | 225 | } |
| shinbo | 0:cb6ecbfcf585 | 226 | } |
| shinbo | 0:cb6ecbfcf585 | 227 | |
| shinbo | 0:cb6ecbfcf585 | 228 | |
| shinbo | 0:cb6ecbfcf585 | 229 | void set_led() { |
| shinbo | 0:cb6ecbfcf585 | 230 | uint32_t u32_val = 0; |
| shinbo | 0:cb6ecbfcf585 | 231 | |
| shinbo | 0:cb6ecbfcf585 | 232 | switch (g_freq) { |
| shinbo | 0:cb6ecbfcf585 | 233 | case 32: u32_val = 0x01; break; // 0001 |
| shinbo | 0:cb6ecbfcf585 | 234 | case 44: u32_val = 0x02; break; // 0010 |
| shinbo | 0:cb6ecbfcf585 | 235 | case 48: u32_val = 0x03; break; // 0011 |
| shinbo | 0:cb6ecbfcf585 | 236 | case 88: u32_val = 0x04; break; // 0100 |
| shinbo | 0:cb6ecbfcf585 | 237 | case 96: u32_val = 0x05; break; // 0101 |
| shinbo | 0:cb6ecbfcf585 | 238 | case 176: u32_val = 0x06; break; // 0110 |
| shinbo | 0:cb6ecbfcf585 | 239 | case 192: u32_val = 0x07; break; // 0111 |
| shinbo | 0:cb6ecbfcf585 | 240 | } |
| shinbo | 0:cb6ecbfcf585 | 241 | |
| shinbo | 0:cb6ecbfcf585 | 242 | pin_led4 = (u32_val & 1); u32_val = u32_val >> 1; |
| shinbo | 0:cb6ecbfcf585 | 243 | pin_led3 = (u32_val & 1); u32_val = u32_val >> 1; |
| shinbo | 0:cb6ecbfcf585 | 244 | pin_led2 = (u32_val & 1); u32_val = u32_val >> 1; |
| shinbo | 0:cb6ecbfcf585 | 245 | } |
| shinbo | 0:cb6ecbfcf585 | 246 | |
| shinbo | 0:cb6ecbfcf585 | 247 | |
| shinbo | 0:cb6ecbfcf585 | 248 | void set_rmckf() { |
| shinbo | 0:cb6ecbfcf585 | 249 | uint8_t u8_data = 0; |
| shinbo | 0:cb6ecbfcf585 | 250 | |
| shinbo | 0:cb6ecbfcf585 | 251 | if (g_cur_frmt & 1) { // (0Bh)[0] 96KHZ - If the input sample rate is <= 48 kHz, outputs a "0". Outputs a "1" if the sample rate is >= 88.1 kHz. Otherwise the output is indeterminate. |
| shinbo | 0:cb6ecbfcf585 | 252 | pin_led1 = 1; |
| shinbo | 0:cb6ecbfcf585 | 253 | u8_data = 0x02; // (01h)[1] RMCKF - Recovered Master Clock Frequency @ 1 : 128 Fs |
| shinbo | 0:cb6ecbfcf585 | 254 | } else { |
| shinbo | 0:cb6ecbfcf585 | 255 | pin_led1 = 0; |
| shinbo | 0:cb6ecbfcf585 | 256 | u8_data = 0x00; // (01h)[1] RMCKF - Recovered Master Clock Frequency @ 0 : 256 Fs |
| shinbo | 0:cb6ecbfcf585 | 257 | } |
| shinbo | 1:f468352a5408 | 258 | cs8416_write(0x01, DEF_REGVAL[1] | u8_data); // (01h) : Control1 |
| shinbo | 0:cb6ecbfcf585 | 259 | } |
| shinbo | 0:cb6ecbfcf585 | 260 | |
| shinbo | 0:cb6ecbfcf585 | 261 | |
| shinbo | 0:cb6ecbfcf585 | 262 | void set_source() { |
| shinbo | 0:cb6ecbfcf585 | 263 | uint8_t u8_data = 0; |
| shinbo | 0:cb6ecbfcf585 | 264 | |
| shinbo | 0:cb6ecbfcf585 | 265 | if (g_cur_tgl & 1) { |
| shinbo | 0:cb6ecbfcf585 | 266 | u8_data = 0x08; // (04h)[5:3] RXSEL2:0 |
| shinbo | 0:cb6ecbfcf585 | 267 | } else { |
| shinbo | 0:cb6ecbfcf585 | 268 | u8_data = 0x00; // (04h)[5:3] RXSEL2:0 |
| shinbo | 0:cb6ecbfcf585 | 269 | } |
| shinbo | 1:f468352a5408 | 270 | cs8416_write(0x04, DEF_REGVAL[4] | u8_data); // (04h) : Control4 |
| shinbo | 0:cb6ecbfcf585 | 271 | } |
| shinbo | 0:cb6ecbfcf585 | 272 | |
| shinbo | 0:cb6ecbfcf585 | 273 | |
| shinbo | 0:cb6ecbfcf585 | 274 | int main() { |
| shinbo | 0:cb6ecbfcf585 | 275 | |
| shinbo | 0:cb6ecbfcf585 | 276 | spi.format(8, 3); // 8bit, mode3 |
| shinbo | 0:cb6ecbfcf585 | 277 | spi.frequency(1000000); // 1MHz : default |
| shinbo | 0:cb6ecbfcf585 | 278 | |
| shinbo | 0:cb6ecbfcf585 | 279 | cs8416_init(); |
| shinbo | 0:cb6ecbfcf585 | 280 | fn1242_init(); |
| shinbo | 0:cb6ecbfcf585 | 281 | |
| shinbo | 0:cb6ecbfcf585 | 282 | while (1) { |
| shinbo | 1:f468352a5408 | 283 | |
| shinbo | 0:cb6ecbfcf585 | 284 | uint8_t u8_addr18 = cs8416_read(0x18); // (18h) : OMCK/RMCK Ratio |
| shinbo | 0:cb6ecbfcf585 | 285 | decide_freq(u8_addr18); |
| shinbo | 0:cb6ecbfcf585 | 286 | set_led(); |
| shinbo | 0:cb6ecbfcf585 | 287 | |
| shinbo | 0:cb6ecbfcf585 | 288 | uint8_t u8_addr0B = cs8416_read(0x0b); // (0Bh) : Format Detect Status |
| shinbo | 2:849b0ab61874 | 289 | if (g_cur_frmt != u8_addr0B) { |
| shinbo | 0:cb6ecbfcf585 | 290 | g_cur_frmt = u8_addr0B; |
| shinbo | 0:cb6ecbfcf585 | 291 | set_rmckf(); |
| shinbo | 0:cb6ecbfcf585 | 292 | } |
| shinbo | 0:cb6ecbfcf585 | 293 | |
| shinbo | 0:cb6ecbfcf585 | 294 | uint32_t u32_tgl = pin_tgl; |
| shinbo | 0:cb6ecbfcf585 | 295 | if (g_cur_tgl != u32_tgl) { |
| shinbo | 0:cb6ecbfcf585 | 296 | g_cur_tgl = u32_tgl; |
| shinbo | 0:cb6ecbfcf585 | 297 | set_source(); |
| shinbo | 0:cb6ecbfcf585 | 298 | } |
| shinbo | 0:cb6ecbfcf585 | 299 | |
| shinbo | 0:cb6ecbfcf585 | 300 | wait_ms(200); // ms |
| shinbo | 0:cb6ecbfcf585 | 301 | } |
| shinbo | 1:f468352a5408 | 302 | |
| shinbo | 0:cb6ecbfcf585 | 303 | } |