shao ziyang
/
mbed-src-kl05
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Dependents: frdm_kl05z_gpio_test
Fork of
mbed-src
by 
mbed official
Revision 279:26b9e96a0278, committed 2014-08-11
- Comitter:
- mbed_official
- Date:
- Mon Aug 11 14:00:06 2014 +0100
- Parent:
- 278:268467ee0266
- Child:
- 280:a62e2e63cfbd
- Commit message:
- Synchronized with git revision ca36374e2e6ddc5a5dc7364ebece4489b2023bbd
Full URL: https://github.com/mbedmicro/mbed/commit/ca36374e2e6ddc5a5dc7364ebece4489b2023bbd/
fixed L6235E link error for Xadow M0
Changed in this revision
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U35_501/LPC11U35.sct Mon Aug 11 08:45:06 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,20 +0,0 @@
-
-LR_IROM1 0x00000000 0x10000 { ; load region size_region (64k)
- ER_IROM1 0x00000000 0x10000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
- ; 8KB - 0xC0 = 0x1F40
- RW_IRAM1 0x100000C0 0x1F40 {
- .ANY (+RW +ZI)
- }
- RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM
- .ANY (IOHANDLER_RAM)
- }
- RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM
- .ANY (USBRAM)
- }
-}
-
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U35_501/startup_LPC11xx.s Mon Aug 11 08:45:06 2014 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,325 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC11xx.s -; * @purpose: CMSIS Cortex-M0 Core Device Startup File -; * for the NXP LPC11xx Device Series -; * @version: V1.0 -; * @date: 25. Nov. 2008 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2008 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __initial_sp - -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U3x - - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT __heap_base - EXPORT __heap_limit - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - ; for LPC11Uxx (With USB) - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled -; for particular peripheral. -;NMI_Handler PROC -; EXPORT NMI_Handler [WEAK] -; B . -; ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Reserved_IRQHandler PROC - EXPORT Reserved_IRQHandler [WEAK] - B . - ENDP - -Default_Handler PROC -; for LPC11Uxx (With USB) - EXPORT NMI_Handler [WEAK] - EXPORT FLEX_INT0_IRQHandler [WEAK] - EXPORT FLEX_INT1_IRQHandler [WEAK] - EXPORT FLEX_INT2_IRQHandler [WEAK] - EXPORT FLEX_INT3_IRQHandler [WEAK] - EXPORT FLEX_INT4_IRQHandler [WEAK] - EXPORT FLEX_INT5_IRQHandler [WEAK] - EXPORT FLEX_INT6_IRQHandler [WEAK] - EXPORT FLEX_INT7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT I2C_IRQHandler [WEAK] - EXPORT TIMER16_0_IRQHandler [WEAK] - EXPORT TIMER16_1_IRQHandler [WEAK] - EXPORT TIMER32_0_IRQHandler [WEAK] - EXPORT TIMER32_1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT UART_IRQHandler [WEAK] - - EXPORT USB_IRQHandler [WEAK] - EXPORT USB_FIQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT USBWakeup_IRQHandler [WEAK] - -NMI_Handler -FLEX_INT0_IRQHandler -FLEX_INT1_IRQHandler -FLEX_INT2_IRQHandler -FLEX_INT3_IRQHandler -FLEX_INT4_IRQHandler -FLEX_INT5_IRQHandler -FLEX_INT6_IRQHandler -FLEX_INT7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -SSP1_IRQHandler -I2C_IRQHandler -TIMER16_0_IRQHandler -TIMER16_1_IRQHandler -TIMER32_0_IRQHandler -TIMER32_1_IRQHandler -SSP0_IRQHandler -UART_IRQHandler -USB_IRQHandler -USB_FIQHandler -ADC_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -FMC_IRQHandler -USBWakeup_IRQHandler - - B . - - ENDP - - ALIGN - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_MCU_LPC11U35_501/LPC11U35.sct Mon Aug 11 14:00:06 2014 +0100
@@ -0,0 +1,20 @@
+
+LR_IROM1 0x00000000 0x10000 { ; load region size_region (64k)
+ ER_IROM1 0x00000000 0x10000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM
+ .ANY (IOHANDLER_RAM)
+ }
+ RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_MCU_LPC11U35_501/startup_LPC11xx.s Mon Aug 11 14:00:06 2014 +0100 @@ -0,0 +1,325 @@ +;/***************************************************************************** +; * @file: startup_LPC11xx.s +; * @purpose: CMSIS Cortex-M0 Core Device Startup File +; * for the NXP LPC11xx Device Series +; * @version: V1.0 +; * @date: 25. Nov. 2008 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * Copyright (C) 2008 ARM Limited. All rights reserved. +; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; *****************************************************************************/ + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U3x + + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + ; for LPC11Uxx (With USB) + DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx + DCD FLEX_INT1_IRQHandler + DCD FLEX_INT2_IRQHandler + DCD FLEX_INT3_IRQHandler + DCD FLEX_INT4_IRQHandler + DCD FLEX_INT5_IRQHandler + DCD FLEX_INT6_IRQHandler + DCD FLEX_INT7_IRQHandler + DCD GINT0_IRQHandler + DCD GINT1_IRQHandler ; PIO0 (0:7) + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD SSP1_IRQHandler ; SSP1 + DCD I2C_IRQHandler ; I2C + DCD TIMER16_0_IRQHandler ; 16-bit Timer0 + DCD TIMER16_1_IRQHandler ; 16-bit Timer1 + DCD TIMER32_0_IRQHandler ; 32-bit Timer0 + DCD TIMER32_1_IRQHandler ; 32-bit Timer1 + DCD SSP0_IRQHandler ; SSP0 + DCD UART_IRQHandler ; UART + DCD USB_IRQHandler ; USB IRQ + DCD USB_FIQHandler ; USB FIQ + DCD ADC_IRQHandler ; A/D Converter + DCD WDT_IRQHandler ; Watchdog timer + DCD BOD_IRQHandler ; Brown Out Detect + DCD FMC_IRQHandler ; IP2111 Flash Memory Controller + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler ; Reserved + DCD USBWakeup_IRQHandler ; USB wake up + DCD Reserved_IRQHandler ; Reserved + + ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + IF :LNOT::DEF:NO_CRP + AREA |.ARM.__at_0x02FC|, CODE, READONLY +CRP_Key DCD 0xFFFFFFFF + ENDIF + + + AREA |.text|, CODE, READONLY + + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled +; for particular peripheral. +;NMI_Handler PROC +; EXPORT NMI_Handler [WEAK] +; B . +; ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Reserved_IRQHandler PROC + EXPORT Reserved_IRQHandler [WEAK] + B . + ENDP + +Default_Handler PROC +; for LPC11Uxx (With USB) + EXPORT NMI_Handler [WEAK] + EXPORT FLEX_INT0_IRQHandler [WEAK] + EXPORT FLEX_INT1_IRQHandler [WEAK] + EXPORT FLEX_INT2_IRQHandler [WEAK] + EXPORT FLEX_INT3_IRQHandler [WEAK] + EXPORT FLEX_INT4_IRQHandler [WEAK] + EXPORT FLEX_INT5_IRQHandler [WEAK] + EXPORT FLEX_INT6_IRQHandler [WEAK] + EXPORT FLEX_INT7_IRQHandler [WEAK] + EXPORT GINT0_IRQHandler [WEAK] + EXPORT GINT1_IRQHandler [WEAK] + EXPORT SSP1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT TIMER16_0_IRQHandler [WEAK] + EXPORT TIMER16_1_IRQHandler [WEAK] + EXPORT TIMER32_0_IRQHandler [WEAK] + EXPORT TIMER32_1_IRQHandler [WEAK] + EXPORT SSP0_IRQHandler [WEAK] + EXPORT UART_IRQHandler [WEAK] + + EXPORT USB_IRQHandler [WEAK] + EXPORT USB_FIQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT USBWakeup_IRQHandler [WEAK] + +NMI_Handler +FLEX_INT0_IRQHandler +FLEX_INT1_IRQHandler +FLEX_INT2_IRQHandler +FLEX_INT3_IRQHandler +FLEX_INT4_IRQHandler +FLEX_INT5_IRQHandler +FLEX_INT6_IRQHandler +FLEX_INT7_IRQHandler +GINT0_IRQHandler +GINT1_IRQHandler +SSP1_IRQHandler +I2C_IRQHandler +TIMER16_0_IRQHandler +TIMER16_1_IRQHandler +TIMER32_0_IRQHandler +TIMER32_1_IRQHandler +SSP0_IRQHandler +UART_IRQHandler +USB_IRQHandler +USB_FIQHandler +ADC_IRQHandler +WDT_IRQHandler +BOD_IRQHandler +FMC_IRQHandler +USBWakeup_IRQHandler + + B . + + ENDP + + ALIGN + END
--- a/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_501/PeripheralNames.h Mon Aug 11 08:45:06 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,71 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- UART_0 = (int)LPC_USART_BASE
-} UARTName;
-
-typedef enum {
- I2C_0 = (int)LPC_I2C_BASE
-} I2CName;
-
-typedef enum {
- ADC0_0 = 0,
- ADC0_1,
- ADC0_2,
- ADC0_3,
- ADC0_4,
- ADC0_5,
- ADC0_6,
- ADC0_7
-} ADCName;
-
-typedef enum {
- SPI_0 = (int)LPC_SSP0_BASE,
- SPI_1 = (int)LPC_SSP1_BASE
-} SPIName;
-
-typedef enum {
- PWM_1 = 0,
- PWM_2,
- PWM_3,
- PWM_4,
- PWM_5,
- PWM_6,
- PWM_7,
- PWM_8,
- PWM_9,
- PWM_10,
- PWM_11
-} PWMName;
-
-#define STDIO_UART_TX UART_TX
-#define STDIO_UART_RX UART_RX
-#define STDIO_UART UART_0
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_501/PeripheralPins.c Mon Aug 11 08:45:06 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,117 +0,0 @@
-
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "PeripheralPins.h"
-
-/************ADC***************/
-const PinMap PinMap_ADC[] = {
- {P0_11, ADC0_0, 0x02},
- {P0_12, ADC0_1, 0x02},
- {P0_13, ADC0_2, 0x02},
- {P0_14, ADC0_3, 0x02},
- {P0_15, ADC0_4, 0x02},
- {P0_16, ADC0_5, 0x01},
- {P0_22, ADC0_6, 0x01},
- {P0_23, ADC0_7, 0x01},
- {NC , NC , 0 }
-};
-
-/************I2C***************/
-const PinMap PinMap_I2C_SDA[] = {
- {P0_5, I2C_0, 1},
- {NC , NC , 0}
-};
-
-const PinMap PinMap_I2C_SCL[] = {
- {P0_4, I2C_0, 1},
- {NC , NC, 0}
-};
-
-/************UART***************/
-const PinMap PinMap_UART_TX[] = {
- {P0_19, UART_0, 1},
- {P1_13, UART_0, 3},
- {P1_27, UART_0, 2},
- { NC , NC , 0}
-};
-
-const PinMap PinMap_UART_RX[] = {
- {P0_18, UART_0, 1},
- {P1_14, UART_0, 3},
- {P1_26, UART_0, 2},
- {NC , NC , 0}
-};
-
-/************SPI***************/
-const PinMap PinMap_SPI_SCLK[] = {
- {P0_6 , SPI_0, 0x02},
- {P0_10, SPI_0, 0x02},
- {P1_29, SPI_0, 0x01},
- {P1_15, SPI_1, 0x03},
- {P1_20, SPI_1, 0x02},
- {NC , NC , 0}
-};
-
-const PinMap PinMap_SPI_MOSI[] = {
- {P0_9 , SPI_0, 0x01},
- {P0_21, SPI_1, 0x02},
- {P1_22, SPI_1, 0x02},
- {NC , NC , 0}
-};
-
-const PinMap PinMap_SPI_MISO[] = {
- {P0_8 , SPI_0, 0x01},
- {P0_22, SPI_1, 0x03},
- {P1_21, SPI_1, 0x02},
- {NC , NC , 0}
-};
-
-const PinMap PinMap_SPI_SSEL[] = {
- {P0_2 , SPI_0, 0x01},
- {P1_19, SPI_1, 0x02},
- {P1_23, SPI_1, 0x02},
- {NC , NC , 0}
-};
-
-/************PWM***************/
-/* To have a PWM where we can change both the period and the duty cycle,
- * we need an entire timer. With the following conventions:
- * * MR3 is used for the PWM period
- * * MR0, MR1, MR2 are used for the duty cycle
- */
-const PinMap PinMap_PWM[] = {
- /* CT16B0 */
- {P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */
- {P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */
- {P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */
-
- /* CT16B1 */
- {P0_21, PWM_4, 1}, /* MR0 */
- {P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */
-
- /* CT32B0 */
- {P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */
- {P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */
- {P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */
-
- /* CT32B1 */
- {P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */
- {P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */
- {P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */
-
- {NC, NC, 0}
-};
--- a/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_501/PinNames.h Mon Aug 11 08:45:06 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,176 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
-#define PORT_SHIFT 5
-
-typedef enum {
- // LPC11U Pin Names
- P0_0 = 0,
- P0_1 = 1,
- P0_2 = 2,
- P0_3 = 3,
- P0_4 = 4,
- P0_5 = 5,
- P0_6 = 6,
- P0_7 = 7,
- P0_8 = 8,
- P0_9 = 9,
- P0_10 = 10,
- P0_11 = 11,
- P0_12 = 12,
- P0_13 = 13,
- P0_14 = 14,
- P0_15 = 15,
- P0_16 = 16,
- P0_17 = 17,
- P0_18 = 18,
- P0_19 = 19,
- P0_20 = 20,
- P0_21 = 21,
- P0_22 = 22,
- P0_23 = 23,
- P0_24 = 24,
- P0_25 = 25,
- P0_26 = 26,
- P0_27 = 27,
-
- P1_0 = 32,
- P1_1 = 33,
- P1_2 = 34,
- P1_3 = 35,
- P1_4 = 36,
- P1_5 = 37,
- P1_6 = 38,
- P1_7 = 39,
- P1_8 = 40,
- P1_9 = 41,
- P1_10 = 42,
- P1_11 = 43,
- P1_12 = 44,
- P1_13 = 45,
- P1_14 = 46,
- P1_15 = 47,
- P1_16 = 48,
- P1_17 = 49,
- P1_18 = 50,
- P1_19 = 51,
- P1_20 = 52,
- P1_21 = 53,
- P1_22 = 54,
- P1_23 = 55,
- P1_24 = 56,
- P1_25 = 57,
- P1_26 = 58,
- P1_27 = 59,
- P1_28 = 60,
- P1_29 = 61,
-
- P1_31 = 63,
-
- // mbed DIP Pin Names
- // CN1-1 (GND)
- // CN1-2 (EXTPOWER)
- // CN1-3 (NC)
- p4 = P0_0, // CN1-4
- p5 = P0_9, // CN1-5
- p6 = P0_8, // CN1-6
- p7 = P0_10, // CN1-7
- p8 = P0_7, // CN1-8
- p9 = P0_19, // CN1-9
- p10 = P0_18, // CN1-10
- p11 = P0_21, // CN1-11
- p12 = P0_22, // CN1-12
- p13 = P1_15, // CN1-13
- p14 = P0_6, // CN1-14
- p15 = P0_11, // CN1-15
- p16 = P0_12, // CN1-16
- p17 = P0_13, // CN1-17
- p18 = P0_14, // CN1-18
- p19 = P0_15, // CN1-19
- p20 = P0_16, // CN1-20
-
- p21 = P0_14, // CN2-20
- p22 = P0_2, // CN2-19
- p23 = P0_23, // CN2-18
- p24 = P0_17, // CN2-17
- p25 = P0_20, // CN2-16
- p26 = P1_15, // CN2-15
- p27 = P0_4, // CN2-14
- p28 = P0_5, // CN2-13
- p29 = P1_19, // CN2-12
- p30 = P0_1, // CN2-11
- // CN2-10 (D+USB)
- // CN2-9 (D-USB)
- p33 = P0_3, // CN2-8 (USB-VBUS)
- // CN2-7 (NC)
- // CN2-6 (NC)
- // CN2-5 (NC)
- // CN2-4 (NC)
- // CN2-3 (NC)
- // CN2-2 (VDD)
- // CN2-1 (VDD)
-
- // Other mbed Pin Names
- LED1 = P0_20,
- LED2 = P0_21,
- LED3 = P0_20,
- LED4 = P0_21,
-
- UART_TX = P0_19,
- UART_RX = P0_18,
-
- // Not connected
- NC = (int)0xFFFFFFFF,
-} PinName;
-
-typedef enum {
- CHANNEL0 = FLEX_INT0_IRQn,
- CHANNEL1 = FLEX_INT1_IRQn,
- CHANNEL2 = FLEX_INT2_IRQn,
- CHANNEL3 = FLEX_INT3_IRQn,
- CHANNEL4 = FLEX_INT4_IRQn,
- CHANNEL5 = FLEX_INT5_IRQn,
- CHANNEL6 = FLEX_INT6_IRQn,
- CHANNEL7 = FLEX_INT7_IRQn
-} Channel;
-
-typedef enum {
- PullUp = 2,
- PullDown = 1,
- PullNone = 0,
- Repeater = 3,
- OpenDrain = 4,
- PullDefault = PullDown
-} PinMode;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_501/device.h Mon Aug 11 08:45:06 2014 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,59 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 0 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 1 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 - -#define DEVICE_CAN 0 - -#define DEVICE_RTC 0 - -#define DEVICE_ETHERNET 0 - -#define DEVICE_PWMOUT 1 - -#define DEVICE_SEMIHOST 0 -#define DEVICE_LOCALFILESYSTEM 0 -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - -#define DEVICE_SLEEP 1 - -#define DEVICE_DEBUG_AWARENESS 0 - -#define DEVICE_STDIO_MESSAGES 0 - -#define DEVICE_ERROR_PATTERN 1 - -#include "objects.h" - -#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/PeripheralNames.h Mon Aug 11 14:00:06 2014 +0100
@@ -0,0 +1,71 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = (int)LPC_USART_BASE
+} UARTName;
+
+typedef enum {
+ I2C_0 = (int)LPC_I2C_BASE
+} I2CName;
+
+typedef enum {
+ ADC0_0 = 0,
+ ADC0_1,
+ ADC0_2,
+ ADC0_3,
+ ADC0_4,
+ ADC0_5,
+ ADC0_6,
+ ADC0_7
+} ADCName;
+
+typedef enum {
+ SPI_0 = (int)LPC_SSP0_BASE,
+ SPI_1 = (int)LPC_SSP1_BASE
+} SPIName;
+
+typedef enum {
+ PWM_1 = 0,
+ PWM_2,
+ PWM_3,
+ PWM_4,
+ PWM_5,
+ PWM_6,
+ PWM_7,
+ PWM_8,
+ PWM_9,
+ PWM_10,
+ PWM_11
+} PWMName;
+
+#define STDIO_UART_TX UART_TX
+#define STDIO_UART_RX UART_RX
+#define STDIO_UART UART_0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/PeripheralPins.c Mon Aug 11 14:00:06 2014 +0100
@@ -0,0 +1,117 @@
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PeripheralPins.h"
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+ {P0_11, ADC0_0, 0x02},
+ {P0_12, ADC0_1, 0x02},
+ {P0_13, ADC0_2, 0x02},
+ {P0_14, ADC0_3, 0x02},
+ {P0_15, ADC0_4, 0x02},
+ {P0_16, ADC0_5, 0x01},
+ {P0_22, ADC0_6, 0x01},
+ {P0_23, ADC0_7, 0x01},
+ {NC , NC , 0 }
+};
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+ {P0_5, I2C_0, 1},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {P0_4, I2C_0, 1},
+ {NC , NC, 0}
+};
+
+/************UART***************/
+const PinMap PinMap_UART_TX[] = {
+ {P0_19, UART_0, 1},
+ {P1_13, UART_0, 3},
+ {P1_27, UART_0, 2},
+ { NC , NC , 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {P0_18, UART_0, 1},
+ {P1_14, UART_0, 3},
+ {P1_26, UART_0, 2},
+ {NC , NC , 0}
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+ {P0_6 , SPI_0, 0x02},
+ {P0_10, SPI_0, 0x02},
+ {P1_29, SPI_0, 0x01},
+ {P1_15, SPI_1, 0x03},
+ {P1_20, SPI_1, 0x02},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {P0_9 , SPI_0, 0x01},
+ {P0_21, SPI_1, 0x02},
+ {P1_22, SPI_1, 0x02},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {P0_8 , SPI_0, 0x01},
+ {P0_22, SPI_1, 0x03},
+ {P1_21, SPI_1, 0x02},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+ {P0_2 , SPI_0, 0x01},
+ {P1_19, SPI_1, 0x02},
+ {P1_23, SPI_1, 0x02},
+ {NC , NC , 0}
+};
+
+/************PWM***************/
+/* To have a PWM where we can change both the period and the duty cycle,
+ * we need an entire timer. With the following conventions:
+ * * MR3 is used for the PWM period
+ * * MR0, MR1, MR2 are used for the duty cycle
+ */
+const PinMap PinMap_PWM[] = {
+ /* CT16B0 */
+ {P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */
+ {P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */
+ {P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */
+
+ /* CT16B1 */
+ {P0_21, PWM_4, 1}, /* MR0 */
+ {P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */
+
+ /* CT32B0 */
+ {P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */
+ {P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */
+ {P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */
+
+ /* CT32B1 */
+ {P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */
+ {P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */
+ {P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */
+
+ {NC, NC, 0}
+};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_501/PinNames.h Mon Aug 11 14:00:06 2014 +0100
@@ -0,0 +1,176 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 5
+
+typedef enum {
+ // LPC11U Pin Names
+ P0_0 = 0,
+ P0_1 = 1,
+ P0_2 = 2,
+ P0_3 = 3,
+ P0_4 = 4,
+ P0_5 = 5,
+ P0_6 = 6,
+ P0_7 = 7,
+ P0_8 = 8,
+ P0_9 = 9,
+ P0_10 = 10,
+ P0_11 = 11,
+ P0_12 = 12,
+ P0_13 = 13,
+ P0_14 = 14,
+ P0_15 = 15,
+ P0_16 = 16,
+ P0_17 = 17,
+ P0_18 = 18,
+ P0_19 = 19,
+ P0_20 = 20,
+ P0_21 = 21,
+ P0_22 = 22,
+ P0_23 = 23,
+ P0_24 = 24,
+ P0_25 = 25,
+ P0_26 = 26,
+ P0_27 = 27,
+
+ P1_0 = 32,
+ P1_1 = 33,
+ P1_2 = 34,
+ P1_3 = 35,
+ P1_4 = 36,
+ P1_5 = 37,
+ P1_6 = 38,
+ P1_7 = 39,
+ P1_8 = 40,
+ P1_9 = 41,
+ P1_10 = 42,
+ P1_11 = 43,
+ P1_12 = 44,
+ P1_13 = 45,
+ P1_14 = 46,
+ P1_15 = 47,
+ P1_16 = 48,
+ P1_17 = 49,
+ P1_18 = 50,
+ P1_19 = 51,
+ P1_20 = 52,
+ P1_21 = 53,
+ P1_22 = 54,
+ P1_23 = 55,
+ P1_24 = 56,
+ P1_25 = 57,
+ P1_26 = 58,
+ P1_27 = 59,
+ P1_28 = 60,
+ P1_29 = 61,
+
+ P1_31 = 63,
+
+ // mbed DIP Pin Names
+ // CN1-1 (GND)
+ // CN1-2 (EXTPOWER)
+ // CN1-3 (NC)
+ p4 = P0_0, // CN1-4
+ p5 = P0_9, // CN1-5
+ p6 = P0_8, // CN1-6
+ p7 = P0_10, // CN1-7
+ p8 = P0_7, // CN1-8
+ p9 = P0_19, // CN1-9
+ p10 = P0_18, // CN1-10
+ p11 = P0_21, // CN1-11
+ p12 = P0_22, // CN1-12
+ p13 = P1_15, // CN1-13
+ p14 = P0_6, // CN1-14
+ p15 = P0_11, // CN1-15
+ p16 = P0_12, // CN1-16
+ p17 = P0_13, // CN1-17
+ p18 = P0_14, // CN1-18
+ p19 = P0_15, // CN1-19
+ p20 = P0_16, // CN1-20
+
+ p21 = P0_14, // CN2-20
+ p22 = P0_2, // CN2-19
+ p23 = P0_23, // CN2-18
+ p24 = P0_17, // CN2-17
+ p25 = P0_20, // CN2-16
+ p26 = P1_15, // CN2-15
+ p27 = P0_4, // CN2-14
+ p28 = P0_5, // CN2-13
+ p29 = P1_19, // CN2-12
+ p30 = P0_1, // CN2-11
+ // CN2-10 (D+USB)
+ // CN2-9 (D-USB)
+ p33 = P0_3, // CN2-8 (USB-VBUS)
+ // CN2-7 (NC)
+ // CN2-6 (NC)
+ // CN2-5 (NC)
+ // CN2-4 (NC)
+ // CN2-3 (NC)
+ // CN2-2 (VDD)
+ // CN2-1 (VDD)
+
+ // Other mbed Pin Names
+ LED1 = P0_20,
+ LED2 = P0_21,
+ LED3 = P0_20,
+ LED4 = P0_21,
+
+ UART_TX = P0_19,
+ UART_RX = P0_18,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+} PinName;
+
+typedef enum {
+ CHANNEL0 = FLEX_INT0_IRQn,
+ CHANNEL1 = FLEX_INT1_IRQn,
+ CHANNEL2 = FLEX_INT2_IRQn,
+ CHANNEL3 = FLEX_INT3_IRQn,
+ CHANNEL4 = FLEX_INT4_IRQn,
+ CHANNEL5 = FLEX_INT5_IRQn,
+ CHANNEL6 = FLEX_INT6_IRQn,
+ CHANNEL7 = FLEX_INT7_IRQn
+} Channel;
+
+typedef enum {
+ PullUp = 2,
+ PullDown = 1,
+ PullNone = 0,
+ Repeater = 3,
+ OpenDrain = 4,
+ PullDefault = PullDown
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_501/device.h Mon Aug 11 14:00:06 2014 +0100 @@ -0,0 +1,59 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 32 +#define DEVICE_MAC_OFFSET 20 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 0 + +#define DEVICE_ERROR_PATTERN 1 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_XADOW_M0/PinNames.h Mon Aug 11 14:00:06 2014 +0100
@@ -0,0 +1,179 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 5
+
+typedef enum {
+ // LPC11U Pin Names
+ P0_0 = 0,
+ P0_1 = 1,
+ P0_2 = 2,
+ P0_3 = 3,
+ P0_4 = 4,
+ P0_5 = 5,
+ P0_6 = 6,
+ P0_7 = 7,
+ P0_8 = 8,
+ P0_9 = 9,
+ P0_10 = 10,
+ P0_11 = 11,
+ P0_12 = 12,
+ P0_13 = 13,
+ P0_14 = 14,
+ P0_15 = 15,
+ P0_16 = 16,
+ P0_17 = 17,
+ P0_18 = 18,
+ P0_19 = 19,
+ P0_20 = 20,
+ P0_21 = 21,
+ P0_22 = 22,
+ P0_23 = 23,
+ P0_24 = 24,
+ P0_25 = 25,
+ P0_26 = 26,
+ P0_27 = 27,
+
+ P1_0 = 32,
+ P1_1 = 33,
+ P1_2 = 34,
+ P1_3 = 35,
+ P1_4 = 36,
+ P1_5 = 37,
+ P1_6 = 38,
+ P1_7 = 39,
+ P1_8 = 40,
+ P1_9 = 41,
+ P1_10 = 42,
+ P1_11 = 43,
+ P1_12 = 44,
+ P1_13 = 45,
+ P1_14 = 46,
+ P1_15 = 47,
+ P1_16 = 48,
+ P1_17 = 49,
+ P1_18 = 50,
+ P1_19 = 51,
+ P1_20 = 52,
+ P1_21 = 53,
+ P1_22 = 54,
+ P1_23 = 55,
+ P1_24 = 56,
+ P1_25 = 57,
+ P1_26 = 58,
+ P1_27 = 59,
+ P1_28 = 60,
+ P1_29 = 61,
+
+ P1_31 = 63,
+
+ // mbed DIP Pin Names
+ // CN1-1 (GND)
+ // CN1-2 (EXTPOWER)
+ // CN1-3 (NC)
+ p4 = P0_0, // CN1-4
+ p5 = P0_9, // CN1-5
+ p6 = P0_8, // CN1-6
+ p7 = P0_10, // CN1-7
+ p8 = P0_7, // CN1-8
+ p9 = P0_19, // CN1-9
+ p10 = P0_18, // CN1-10
+ p11 = P0_21, // CN1-11
+ p12 = P0_22, // CN1-12
+ p13 = P1_15, // CN1-13
+ p14 = P0_6, // CN1-14
+ p15 = P0_11, // CN1-15
+ p16 = P0_12, // CN1-16
+ p17 = P0_13, // CN1-17
+ p18 = P0_14, // CN1-18
+ p19 = P0_15, // CN1-19
+ p20 = P0_16, // CN1-20
+
+ p21 = P0_14, // CN2-20
+ p22 = P0_2, // CN2-19
+ p23 = P0_23, // CN2-18
+ p24 = P0_17, // CN2-17
+ p25 = P0_20, // CN2-16
+ p26 = P1_15, // CN2-15
+ p27 = P0_4, // CN2-14
+ p28 = P0_5, // CN2-13
+ p29 = P1_19, // CN2-12
+ p30 = P0_1, // CN2-11
+ // CN2-10 (D+USB)
+ // CN2-9 (D-USB)
+ p33 = P0_3, // CN2-8 (USB-VBUS)
+ // CN2-7 (NC)
+ // CN2-6 (NC)
+ // CN2-5 (NC)
+ // CN2-4 (NC)
+ // CN2-3 (NC)
+ // CN2-2 (VDD)
+ // CN2-1 (VDD)
+
+ // Other mbed Pin Names
+ LED1 = P0_20,
+ LED2 = P0_23,
+ LED3 = P0_20,
+ LED4 = P0_23,
+
+ UART_TX = P0_19,
+ UART_RX = P0_18,
+
+ I2C_SCL = P0_4,
+ I2C_SDA = P0_5,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+} PinName;
+
+typedef enum {
+ CHANNEL0 = FLEX_INT0_IRQn,
+ CHANNEL1 = FLEX_INT1_IRQn,
+ CHANNEL2 = FLEX_INT2_IRQn,
+ CHANNEL3 = FLEX_INT3_IRQn,
+ CHANNEL4 = FLEX_INT4_IRQn,
+ CHANNEL5 = FLEX_INT5_IRQn,
+ CHANNEL6 = FLEX_INT6_IRQn,
+ CHANNEL7 = FLEX_INT7_IRQn
+} Channel;
+
+typedef enum {
+ PullUp = 2,
+ PullDown = 1,
+ PullNone = 0,
+ Repeater = 3,
+ OpenDrain = 4,
+ PullDefault = PullDown
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_XADOW_M0/device.h Mon Aug 11 14:00:06 2014 +0100 @@ -0,0 +1,59 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 32 +#define DEVICE_MAC_OFFSET 20 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 0 + +#define DEVICE_ERROR_PATTERN 1 + +#include "objects.h" + +#endif