shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.c@185:e752b4ee7de1, 2014-05-09 (annotated)

Committer:
mbed_official
Date:
Fri May 09 14:00:08 2014 +0100
Revision:
185:e752b4ee7de1
Parent:
126:549ba18ddd81
Child:
226:b062af740e40
Synchronized with git revision c761a5e0a90087e87817c38ae4e3034675dacfde



Full URL: https://github.com/mbedmicro/mbed/commit/c761a5e0a90087e87817c38ae4e3034675dacfde/



Solve also the problem with the SetSysClock function not declared in

sleep.c



Conflicts:

	libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/i2c_api.c

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 87:085cde657901 1 /**
mbed_official 87:085cde657901 2 ******************************************************************************
mbed_official 87:085cde657901 3 * @file system_stm32f4xx.c
mbed_official 87:085cde657901 4 * @author MCD Application Team
mbed_official 185:e752b4ee7de1 5 * @version V2.0.0
mbed_official 106:ced8cbb51063 6 * @date 18-February-2014
mbed_official 87:085cde657901 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
mbed_official 87:085cde657901 8 *
mbed_official 87:085cde657901 9 * This file provides two functions and one global variable to be called from
mbed_official 87:085cde657901 10 * user application:
mbed_official 87:085cde657901 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 87:085cde657901 12 * before branch to main program. This call is made inside
mbed_official 87:085cde657901 13 * the "startup_stm32f4xx.s" file.
mbed_official 87:085cde657901 14 *
mbed_official 87:085cde657901 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 87:085cde657901 16 * by the user application to setup the SysTick
mbed_official 87:085cde657901 17 * timer or configure other parameters.
mbed_official 87:085cde657901 18 *
mbed_official 87:085cde657901 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 87:085cde657901 20 * be called whenever the core clock is changed
mbed_official 87:085cde657901 21 * during program execution.
mbed_official 87:085cde657901 22 *
mbed_official 185:e752b4ee7de1 23 * This file configures the system clock as follows:
mbed_official 185:e752b4ee7de1 24 *-----------------------------------------------------------------------------
mbed_official 185:e752b4ee7de1 25 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 185:e752b4ee7de1 26 * | (external 8 MHz clock) | (internal 16 MHz)
mbed_official 185:e752b4ee7de1 27 * | 2- PLL_HSE_XTAL |
mbed_official 185:e752b4ee7de1 28 * | (external 8 MHz xtal) |
mbed_official 185:e752b4ee7de1 29 *-----------------------------------------------------------------------------
mbed_official 185:e752b4ee7de1 30 * SYSCLK(MHz) | 84 | 84
mbed_official 185:e752b4ee7de1 31 *-----------------------------------------------------------------------------
mbed_official 185:e752b4ee7de1 32 * AHBCLK (MHz) | 84 | 84
mbed_official 185:e752b4ee7de1 33 *-----------------------------------------------------------------------------
mbed_official 185:e752b4ee7de1 34 * APB1CLK (MHz) | 42 | 42
mbed_official 185:e752b4ee7de1 35 *-----------------------------------------------------------------------------
mbed_official 185:e752b4ee7de1 36 * APB2CLK (MHz) | 84 | 84
mbed_official 185:e752b4ee7de1 37 *-----------------------------------------------------------------------------
mbed_official 185:e752b4ee7de1 38 * USB capable (48 MHz precise clock) | YES | NO
mbed_official 185:e752b4ee7de1 39 *-----------------------------------------------------------------------------
mbed_official 87:085cde657901 40 ******************************************************************************
mbed_official 87:085cde657901 41 * @attention
mbed_official 87:085cde657901 42 *
mbed_official 87:085cde657901 43 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
mbed_official 87:085cde657901 44 *
mbed_official 106:ced8cbb51063 45 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 106:ced8cbb51063 46 * are permitted provided that the following conditions are met:
mbed_official 106:ced8cbb51063 47 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 106:ced8cbb51063 48 * this list of conditions and the following disclaimer.
mbed_official 106:ced8cbb51063 49 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 106:ced8cbb51063 50 * this list of conditions and the following disclaimer in the documentation
mbed_official 106:ced8cbb51063 51 * and/or other materials provided with the distribution.
mbed_official 106:ced8cbb51063 52 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 106:ced8cbb51063 53 * may be used to endorse or promote products derived from this software
mbed_official 106:ced8cbb51063 54 * without specific prior written permission.
mbed_official 87:085cde657901 55 *
mbed_official 106:ced8cbb51063 56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 106:ced8cbb51063 57 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 106:ced8cbb51063 58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 106:ced8cbb51063 59 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 106:ced8cbb51063 60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 106:ced8cbb51063 61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 106:ced8cbb51063 62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 106:ced8cbb51063 63 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 106:ced8cbb51063 64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 106:ced8cbb51063 65 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 87:085cde657901 66 *
mbed_official 87:085cde657901 67 ******************************************************************************
mbed_official 87:085cde657901 68 */
mbed_official 87:085cde657901 69
mbed_official 87:085cde657901 70 /** @addtogroup CMSIS
mbed_official 87:085cde657901 71 * @{
mbed_official 87:085cde657901 72 */
mbed_official 87:085cde657901 73
mbed_official 87:085cde657901 74 /** @addtogroup stm32f4xx_system
mbed_official 87:085cde657901 75 * @{
mbed_official 87:085cde657901 76 */
mbed_official 87:085cde657901 77
mbed_official 87:085cde657901 78 /** @addtogroup STM32F4xx_System_Private_Includes
mbed_official 87:085cde657901 79 * @{
mbed_official 87:085cde657901 80 */
mbed_official 87:085cde657901 81
mbed_official 87:085cde657901 82 #include "stm32f4xx_hal.h"
mbed_official 87:085cde657901 83
mbed_official 87:085cde657901 84 /**
mbed_official 87:085cde657901 85 * @}
mbed_official 87:085cde657901 86 */
mbed_official 87:085cde657901 87
mbed_official 87:085cde657901 88 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
mbed_official 87:085cde657901 89 * @{
mbed_official 87:085cde657901 90 */
mbed_official 87:085cde657901 91
mbed_official 87:085cde657901 92 /**
mbed_official 87:085cde657901 93 * @}
mbed_official 87:085cde657901 94 */
mbed_official 87:085cde657901 95
mbed_official 87:085cde657901 96 /** @addtogroup STM32F4xx_System_Private_Defines
mbed_official 87:085cde657901 97 * @{
mbed_official 87:085cde657901 98 */
mbed_official 87:085cde657901 99
mbed_official 87:085cde657901 100 /************************* Miscellaneous Configuration ************************/
mbed_official 185:e752b4ee7de1 101 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
mbed_official 185:e752b4ee7de1 102 on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
mbed_official 185:e752b4ee7de1 103 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 185:e752b4ee7de1 104 /* #define DATA_IN_ExtSRAM */
mbed_official 185:e752b4ee7de1 105 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 185:e752b4ee7de1 106
mbed_official 185:e752b4ee7de1 107 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 185:e752b4ee7de1 108 /* #define DATA_IN_ExtSDRAM */
mbed_official 185:e752b4ee7de1 109 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 185:e752b4ee7de1 110
mbed_official 185:e752b4ee7de1 111 #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
mbed_official 185:e752b4ee7de1 112 #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
mbed_official 185:e752b4ee7de1 113 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
mbed_official 87:085cde657901 114
mbed_official 87:085cde657901 115 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 87:085cde657901 116 Internal SRAM. */
mbed_official 87:085cde657901 117 /* #define VECT_TAB_SRAM */
mbed_official 87:085cde657901 118 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
mbed_official 87:085cde657901 119 This value must be a multiple of 0x200. */
mbed_official 87:085cde657901 120 /******************************************************************************/
mbed_official 87:085cde657901 121
mbed_official 87:085cde657901 122 /**
mbed_official 87:085cde657901 123 * @}
mbed_official 87:085cde657901 124 */
mbed_official 87:085cde657901 125
mbed_official 87:085cde657901 126 /** @addtogroup STM32F4xx_System_Private_Macros
mbed_official 87:085cde657901 127 * @{
mbed_official 87:085cde657901 128 */
mbed_official 87:085cde657901 129
mbed_official 185:e752b4ee7de1 130 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 185:e752b4ee7de1 131 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 185:e752b4ee7de1 132 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 185:e752b4ee7de1 133
mbed_official 87:085cde657901 134 /**
mbed_official 87:085cde657901 135 * @}
mbed_official 87:085cde657901 136 */
mbed_official 87:085cde657901 137
mbed_official 87:085cde657901 138 /** @addtogroup STM32F4xx_System_Private_Variables
mbed_official 87:085cde657901 139 * @{
mbed_official 87:085cde657901 140 */
mbed_official 87:085cde657901 141 /* This variable is updated in three ways:
mbed_official 87:085cde657901 142 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 87:085cde657901 143 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 87:085cde657901 144 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 87:085cde657901 145 Note: If you use this function to configure the system clock; then there
mbed_official 87:085cde657901 146 is no need to call the 2 first functions listed above, since SystemCoreClock
mbed_official 87:085cde657901 147 variable is updated automatically.
mbed_official 87:085cde657901 148 */
mbed_official 185:e752b4ee7de1 149 uint32_t SystemCoreClock = 84000000;
mbed_official 185:e752b4ee7de1 150 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 87:085cde657901 151
mbed_official 87:085cde657901 152 /**
mbed_official 87:085cde657901 153 * @}
mbed_official 87:085cde657901 154 */
mbed_official 87:085cde657901 155
mbed_official 87:085cde657901 156 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
mbed_official 87:085cde657901 157 * @{
mbed_official 87:085cde657901 158 */
mbed_official 87:085cde657901 159
mbed_official 185:e752b4ee7de1 160 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 185:e752b4ee7de1 161 static void SystemInit_ExtMemCtl(void);
mbed_official 185:e752b4ee7de1 162 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 185:e752b4ee7de1 163
mbed_official 185:e752b4ee7de1 164 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 185:e752b4ee7de1 165 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 185:e752b4ee7de1 166 #endif
mbed_official 185:e752b4ee7de1 167
mbed_official 185:e752b4ee7de1 168 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 185:e752b4ee7de1 169
mbed_official 87:085cde657901 170 /**
mbed_official 87:085cde657901 171 * @}
mbed_official 87:085cde657901 172 */
mbed_official 87:085cde657901 173
mbed_official 87:085cde657901 174 /** @addtogroup STM32F4xx_System_Private_Functions
mbed_official 87:085cde657901 175 * @{
mbed_official 87:085cde657901 176 */
mbed_official 87:085cde657901 177
mbed_official 87:085cde657901 178 /**
mbed_official 87:085cde657901 179 * @brief Setup the microcontroller system
mbed_official 87:085cde657901 180 * Initialize the FPU setting, vector table location and External memory
mbed_official 87:085cde657901 181 * configuration.
mbed_official 87:085cde657901 182 * @param None
mbed_official 87:085cde657901 183 * @retval None
mbed_official 87:085cde657901 184 */
mbed_official 87:085cde657901 185 void SystemInit(void)
mbed_official 87:085cde657901 186 {
mbed_official 87:085cde657901 187 /* FPU settings ------------------------------------------------------------*/
mbed_official 87:085cde657901 188 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 87:085cde657901 189 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
mbed_official 87:085cde657901 190 #endif
mbed_official 87:085cde657901 191 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 87:085cde657901 192 /* Set HSION bit */
mbed_official 87:085cde657901 193 RCC->CR |= (uint32_t)0x00000001;
mbed_official 87:085cde657901 194
mbed_official 87:085cde657901 195 /* Reset CFGR register */
mbed_official 87:085cde657901 196 RCC->CFGR = 0x00000000;
mbed_official 87:085cde657901 197
mbed_official 87:085cde657901 198 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 87:085cde657901 199 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 87:085cde657901 200
mbed_official 87:085cde657901 201 /* Reset PLLCFGR register */
mbed_official 87:085cde657901 202 RCC->PLLCFGR = 0x24003010;
mbed_official 87:085cde657901 203
mbed_official 87:085cde657901 204 /* Reset HSEBYP bit */
mbed_official 87:085cde657901 205 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 87:085cde657901 206
mbed_official 87:085cde657901 207 /* Disable all interrupts */
mbed_official 87:085cde657901 208 RCC->CIR = 0x00000000;
mbed_official 87:085cde657901 209
mbed_official 185:e752b4ee7de1 210 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 185:e752b4ee7de1 211 SystemInit_ExtMemCtl();
mbed_official 185:e752b4ee7de1 212 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 185:e752b4ee7de1 213
mbed_official 87:085cde657901 214 /* Configure the Vector Table location add offset address ------------------*/
mbed_official 87:085cde657901 215 #ifdef VECT_TAB_SRAM
mbed_official 87:085cde657901 216 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 87:085cde657901 217 #else
mbed_official 87:085cde657901 218 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 87:085cde657901 219 #endif
mbed_official 87:085cde657901 220
mbed_official 185:e752b4ee7de1 221 /* Configure the Cube driver */
mbed_official 87:085cde657901 222 HAL_Init();
mbed_official 185:e752b4ee7de1 223
mbed_official 185:e752b4ee7de1 224 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 185:e752b4ee7de1 225 AHB/APBx prescalers and Flash settings */
mbed_official 185:e752b4ee7de1 226 SetSysClock();
mbed_official 87:085cde657901 227 }
mbed_official 87:085cde657901 228
mbed_official 87:085cde657901 229 /**
mbed_official 87:085cde657901 230 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 87:085cde657901 231 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 87:085cde657901 232 * be used by the user application to setup the SysTick timer or configure
mbed_official 87:085cde657901 233 * other parameters.
mbed_official 87:085cde657901 234 *
mbed_official 87:085cde657901 235 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 87:085cde657901 236 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 87:085cde657901 237 * based on this variable will be incorrect.
mbed_official 87:085cde657901 238 *
mbed_official 87:085cde657901 239 * @note - The system frequency computed by this function is not the real
mbed_official 87:085cde657901 240 * frequency in the chip. It is calculated based on the predefined
mbed_official 87:085cde657901 241 * constant and the selected clock source:
mbed_official 87:085cde657901 242 *
mbed_official 87:085cde657901 243 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 87:085cde657901 244 *
mbed_official 87:085cde657901 245 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 87:085cde657901 246 *
mbed_official 87:085cde657901 247 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 87:085cde657901 248 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 87:085cde657901 249 *
mbed_official 106:ced8cbb51063 250 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
mbed_official 87:085cde657901 251 * 16 MHz) but the real value may vary depending on the variations
mbed_official 87:085cde657901 252 * in voltage and temperature.
mbed_official 87:085cde657901 253 *
mbed_official 106:ced8cbb51063 254 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
mbed_official 106:ced8cbb51063 255 * depends on the application requirements), user has to ensure that HSE_VALUE
mbed_official 106:ced8cbb51063 256 * is same as the real frequency of the crystal used. Otherwise, this function
mbed_official 106:ced8cbb51063 257 * may have wrong result.
mbed_official 87:085cde657901 258 *
mbed_official 87:085cde657901 259 * - The result of this function could be not correct when using fractional
mbed_official 87:085cde657901 260 * value for HSE crystal.
mbed_official 87:085cde657901 261 *
mbed_official 87:085cde657901 262 * @param None
mbed_official 87:085cde657901 263 * @retval None
mbed_official 87:085cde657901 264 */
mbed_official 87:085cde657901 265 void SystemCoreClockUpdate(void)
mbed_official 87:085cde657901 266 {
mbed_official 87:085cde657901 267 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
mbed_official 87:085cde657901 268
mbed_official 87:085cde657901 269 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 87:085cde657901 270 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 87:085cde657901 271
mbed_official 87:085cde657901 272 switch (tmp)
mbed_official 87:085cde657901 273 {
mbed_official 87:085cde657901 274 case 0x00: /* HSI used as system clock source */
mbed_official 87:085cde657901 275 SystemCoreClock = HSI_VALUE;
mbed_official 87:085cde657901 276 break;
mbed_official 87:085cde657901 277 case 0x04: /* HSE used as system clock source */
mbed_official 87:085cde657901 278 SystemCoreClock = HSE_VALUE;
mbed_official 87:085cde657901 279 break;
mbed_official 87:085cde657901 280 case 0x08: /* PLL used as system clock source */
mbed_official 87:085cde657901 281
mbed_official 87:085cde657901 282 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
mbed_official 87:085cde657901 283 SYSCLK = PLL_VCO / PLL_P
mbed_official 87:085cde657901 284 */
mbed_official 87:085cde657901 285 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
mbed_official 87:085cde657901 286 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
mbed_official 87:085cde657901 287
mbed_official 87:085cde657901 288 if (pllsource != 0)
mbed_official 87:085cde657901 289 {
mbed_official 87:085cde657901 290 /* HSE used as PLL clock source */
mbed_official 87:085cde657901 291 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official 87:085cde657901 292 }
mbed_official 87:085cde657901 293 else
mbed_official 87:085cde657901 294 {
mbed_official 87:085cde657901 295 /* HSI used as PLL clock source */
mbed_official 87:085cde657901 296 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official 87:085cde657901 297 }
mbed_official 87:085cde657901 298
mbed_official 87:085cde657901 299 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
mbed_official 87:085cde657901 300 SystemCoreClock = pllvco/pllp;
mbed_official 87:085cde657901 301 break;
mbed_official 87:085cde657901 302 default:
mbed_official 87:085cde657901 303 SystemCoreClock = HSI_VALUE;
mbed_official 87:085cde657901 304 break;
mbed_official 87:085cde657901 305 }
mbed_official 87:085cde657901 306 /* Compute HCLK frequency --------------------------------------------------*/
mbed_official 87:085cde657901 307 /* Get HCLK prescaler */
mbed_official 87:085cde657901 308 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 87:085cde657901 309 /* HCLK frequency */
mbed_official 87:085cde657901 310 SystemCoreClock >>= tmp;
mbed_official 87:085cde657901 311 }
mbed_official 87:085cde657901 312
mbed_official 185:e752b4ee7de1 313 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 185:e752b4ee7de1 314 /**
mbed_official 185:e752b4ee7de1 315 * @brief Setup the external memory controller.
mbed_official 185:e752b4ee7de1 316 * Called in startup_stm32f4xx.s before jump to main.
mbed_official 185:e752b4ee7de1 317 * This function configures the external memories (SRAM/SDRAM)
mbed_official 185:e752b4ee7de1 318 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
mbed_official 185:e752b4ee7de1 319 * @param None
mbed_official 185:e752b4ee7de1 320 * @retval None
mbed_official 185:e752b4ee7de1 321 */
mbed_official 185:e752b4ee7de1 322 void SystemInit_ExtMemCtl(void)
mbed_official 185:e752b4ee7de1 323 {
mbed_official 185:e752b4ee7de1 324 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 185:e752b4ee7de1 325 #if defined (DATA_IN_ExtSDRAM)
mbed_official 185:e752b4ee7de1 326 register uint32_t tmpreg = 0, timeout = 0xFFFF;
mbed_official 185:e752b4ee7de1 327 register uint32_t index;
mbed_official 185:e752b4ee7de1 328
mbed_official 185:e752b4ee7de1 329 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
mbed_official 185:e752b4ee7de1 330 clock */
mbed_official 185:e752b4ee7de1 331 RCC->AHB1ENR |= 0x000001F8;
mbed_official 185:e752b4ee7de1 332
mbed_official 185:e752b4ee7de1 333 /* Connect PDx pins to FMC Alternate function */
mbed_official 185:e752b4ee7de1 334 GPIOD->AFR[0] = 0x000000CC;
mbed_official 185:e752b4ee7de1 335 GPIOD->AFR[1] = 0xCC000CCC;
mbed_official 185:e752b4ee7de1 336 /* Configure PDx pins in Alternate function mode */
mbed_official 185:e752b4ee7de1 337 GPIOD->MODER = 0xA02A000A;
mbed_official 185:e752b4ee7de1 338 /* Configure PDx pins speed to 50 MHz */
mbed_official 185:e752b4ee7de1 339 GPIOD->OSPEEDR = 0xA02A000A;
mbed_official 185:e752b4ee7de1 340 /* Configure PDx pins Output type to push-pull */
mbed_official 185:e752b4ee7de1 341 GPIOD->OTYPER = 0x00000000;
mbed_official 185:e752b4ee7de1 342 /* No pull-up, pull-down for PDx pins */
mbed_official 185:e752b4ee7de1 343 GPIOD->PUPDR = 0x00000000;
mbed_official 185:e752b4ee7de1 344
mbed_official 185:e752b4ee7de1 345 /* Connect PEx pins to FMC Alternate function */
mbed_official 185:e752b4ee7de1 346 GPIOE->AFR[0] = 0xC00000CC;
mbed_official 185:e752b4ee7de1 347 GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official 185:e752b4ee7de1 348 /* Configure PEx pins in Alternate function mode */
mbed_official 185:e752b4ee7de1 349 GPIOE->MODER = 0xAAAA800A;
mbed_official 185:e752b4ee7de1 350 /* Configure PEx pins speed to 50 MHz */
mbed_official 185:e752b4ee7de1 351 GPIOE->OSPEEDR = 0xAAAA800A;
mbed_official 185:e752b4ee7de1 352 /* Configure PEx pins Output type to push-pull */
mbed_official 185:e752b4ee7de1 353 GPIOE->OTYPER = 0x00000000;
mbed_official 185:e752b4ee7de1 354 /* No pull-up, pull-down for PEx pins */
mbed_official 185:e752b4ee7de1 355 GPIOE->PUPDR = 0x00000000;
mbed_official 185:e752b4ee7de1 356
mbed_official 185:e752b4ee7de1 357 /* Connect PFx pins to FMC Alternate function */
mbed_official 185:e752b4ee7de1 358 GPIOF->AFR[0] = 0xCCCCCCCC;
mbed_official 185:e752b4ee7de1 359 GPIOF->AFR[1] = 0xCCCCCCCC;
mbed_official 185:e752b4ee7de1 360 /* Configure PFx pins in Alternate function mode */
mbed_official 185:e752b4ee7de1 361 GPIOF->MODER = 0xAA800AAA;
mbed_official 185:e752b4ee7de1 362 /* Configure PFx pins speed to 50 MHz */
mbed_official 185:e752b4ee7de1 363 GPIOF->OSPEEDR = 0xAA800AAA;
mbed_official 185:e752b4ee7de1 364 /* Configure PFx pins Output type to push-pull */
mbed_official 185:e752b4ee7de1 365 GPIOF->OTYPER = 0x00000000;
mbed_official 185:e752b4ee7de1 366 /* No pull-up, pull-down for PFx pins */
mbed_official 185:e752b4ee7de1 367 GPIOF->PUPDR = 0x00000000;
mbed_official 185:e752b4ee7de1 368
mbed_official 185:e752b4ee7de1 369 /* Connect PGx pins to FMC Alternate function */
mbed_official 185:e752b4ee7de1 370 GPIOG->AFR[0] = 0xCCCCCCCC;
mbed_official 185:e752b4ee7de1 371 GPIOG->AFR[1] = 0xCCCCCCCC;
mbed_official 185:e752b4ee7de1 372 /* Configure PGx pins in Alternate function mode */
mbed_official 185:e752b4ee7de1 373 GPIOG->MODER = 0xAAAAAAAA;
mbed_official 185:e752b4ee7de1 374 /* Configure PGx pins speed to 50 MHz */
mbed_official 185:e752b4ee7de1 375 GPIOG->OSPEEDR = 0xAAAAAAAA;
mbed_official 185:e752b4ee7de1 376 /* Configure PGx pins Output type to push-pull */
mbed_official 185:e752b4ee7de1 377 GPIOG->OTYPER = 0x00000000;
mbed_official 185:e752b4ee7de1 378 /* No pull-up, pull-down for PGx pins */
mbed_official 185:e752b4ee7de1 379 GPIOG->PUPDR = 0x00000000;
mbed_official 185:e752b4ee7de1 380
mbed_official 185:e752b4ee7de1 381 /* Connect PHx pins to FMC Alternate function */
mbed_official 185:e752b4ee7de1 382 GPIOH->AFR[0] = 0x00C0CC00;
mbed_official 185:e752b4ee7de1 383 GPIOH->AFR[1] = 0xCCCCCCCC;
mbed_official 185:e752b4ee7de1 384 /* Configure PHx pins in Alternate function mode */
mbed_official 185:e752b4ee7de1 385 GPIOH->MODER = 0xAAAA08A0;
mbed_official 185:e752b4ee7de1 386 /* Configure PHx pins speed to 50 MHz */
mbed_official 185:e752b4ee7de1 387 GPIOH->OSPEEDR = 0xAAAA08A0;
mbed_official 185:e752b4ee7de1 388 /* Configure PHx pins Output type to push-pull */
mbed_official 185:e752b4ee7de1 389 GPIOH->OTYPER = 0x00000000;
mbed_official 185:e752b4ee7de1 390 /* No pull-up, pull-down for PHx pins */
mbed_official 185:e752b4ee7de1 391 GPIOH->PUPDR = 0x00000000;
mbed_official 185:e752b4ee7de1 392
mbed_official 185:e752b4ee7de1 393 /* Connect PIx pins to FMC Alternate function */
mbed_official 185:e752b4ee7de1 394 GPIOI->AFR[0] = 0xCCCCCCCC;
mbed_official 185:e752b4ee7de1 395 GPIOI->AFR[1] = 0x00000CC0;
mbed_official 185:e752b4ee7de1 396 /* Configure PIx pins in Alternate function mode */
mbed_official 185:e752b4ee7de1 397 GPIOI->MODER = 0x0028AAAA;
mbed_official 185:e752b4ee7de1 398 /* Configure PIx pins speed to 50 MHz */
mbed_official 185:e752b4ee7de1 399 GPIOI->OSPEEDR = 0x0028AAAA;
mbed_official 185:e752b4ee7de1 400 /* Configure PIx pins Output type to push-pull */
mbed_official 185:e752b4ee7de1 401 GPIOI->OTYPER = 0x00000000;
mbed_official 185:e752b4ee7de1 402 /* No pull-up, pull-down for PIx pins */
mbed_official 185:e752b4ee7de1 403 GPIOI->PUPDR = 0x00000000;
mbed_official 185:e752b4ee7de1 404
mbed_official 185:e752b4ee7de1 405 /*-- FMC Configuration ------------------------------------------------------*/
mbed_official 185:e752b4ee7de1 406 /* Enable the FMC interface clock */
mbed_official 185:e752b4ee7de1 407 RCC->AHB3ENR |= 0x00000001;
mbed_official 185:e752b4ee7de1 408
mbed_official 185:e752b4ee7de1 409 /* Configure and enable SDRAM bank1 */
mbed_official 185:e752b4ee7de1 410 FMC_Bank5_6->SDCR[0] = 0x000019E0;
mbed_official 185:e752b4ee7de1 411 FMC_Bank5_6->SDTR[0] = 0x01115351;
mbed_official 185:e752b4ee7de1 412
mbed_official 185:e752b4ee7de1 413 /* SDRAM initialization sequence */
mbed_official 185:e752b4ee7de1 414 /* Clock enable command */
mbed_official 185:e752b4ee7de1 415 FMC_Bank5_6->SDCMR = 0x00000011;
mbed_official 185:e752b4ee7de1 416 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 185:e752b4ee7de1 417 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 185:e752b4ee7de1 418 {
mbed_official 185:e752b4ee7de1 419 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 185:e752b4ee7de1 420 }
mbed_official 185:e752b4ee7de1 421
mbed_official 185:e752b4ee7de1 422 /* Delay */
mbed_official 185:e752b4ee7de1 423 for (index = 0; index<1000; index++);
mbed_official 185:e752b4ee7de1 424
mbed_official 185:e752b4ee7de1 425 /* PALL command */
mbed_official 185:e752b4ee7de1 426 FMC_Bank5_6->SDCMR = 0x00000012;
mbed_official 185:e752b4ee7de1 427 timeout = 0xFFFF;
mbed_official 185:e752b4ee7de1 428 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 185:e752b4ee7de1 429 {
mbed_official 185:e752b4ee7de1 430 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 185:e752b4ee7de1 431 }
mbed_official 185:e752b4ee7de1 432
mbed_official 185:e752b4ee7de1 433 /* Auto refresh command */
mbed_official 185:e752b4ee7de1 434 FMC_Bank5_6->SDCMR = 0x00000073;
mbed_official 185:e752b4ee7de1 435 timeout = 0xFFFF;
mbed_official 185:e752b4ee7de1 436 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 185:e752b4ee7de1 437 {
mbed_official 185:e752b4ee7de1 438 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 185:e752b4ee7de1 439 }
mbed_official 185:e752b4ee7de1 440
mbed_official 185:e752b4ee7de1 441 /* MRD register program */
mbed_official 185:e752b4ee7de1 442 FMC_Bank5_6->SDCMR = 0x00046014;
mbed_official 185:e752b4ee7de1 443 timeout = 0xFFFF;
mbed_official 185:e752b4ee7de1 444 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 185:e752b4ee7de1 445 {
mbed_official 185:e752b4ee7de1 446 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 185:e752b4ee7de1 447 }
mbed_official 185:e752b4ee7de1 448
mbed_official 185:e752b4ee7de1 449 /* Set refresh count */
mbed_official 185:e752b4ee7de1 450 tmpreg = FMC_Bank5_6->SDRTR;
mbed_official 185:e752b4ee7de1 451 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
mbed_official 185:e752b4ee7de1 452
mbed_official 185:e752b4ee7de1 453 /* Disable write protection */
mbed_official 185:e752b4ee7de1 454 tmpreg = FMC_Bank5_6->SDCR[0];
mbed_official 185:e752b4ee7de1 455 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
mbed_official 185:e752b4ee7de1 456 #endif /* DATA_IN_ExtSDRAM */
mbed_official 185:e752b4ee7de1 457 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 185:e752b4ee7de1 458
mbed_official 185:e752b4ee7de1 459 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 185:e752b4ee7de1 460 #if defined(DATA_IN_ExtSRAM)
mbed_official 185:e752b4ee7de1 461 /*-- GPIOs Configuration -----------------------------------------------------*/
mbed_official 185:e752b4ee7de1 462 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
mbed_official 185:e752b4ee7de1 463 RCC->AHB1ENR |= 0x00000078;
mbed_official 185:e752b4ee7de1 464
mbed_official 185:e752b4ee7de1 465 /* Connect PDx pins to FMC Alternate function */
mbed_official 185:e752b4ee7de1 466 GPIOD->AFR[0] = 0x00CCC0CC;
mbed_official 185:e752b4ee7de1 467 GPIOD->AFR[1] = 0xCCCCCCCC;
mbed_official 185:e752b4ee7de1 468 /* Configure PDx pins in Alternate function mode */
mbed_official 185:e752b4ee7de1 469 GPIOD->MODER = 0xAAAA0A8A;
mbed_official 185:e752b4ee7de1 470 /* Configure PDx pins speed to 100 MHz */
mbed_official 185:e752b4ee7de1 471 GPIOD->OSPEEDR = 0xFFFF0FCF;
mbed_official 185:e752b4ee7de1 472 /* Configure PDx pins Output type to push-pull */
mbed_official 185:e752b4ee7de1 473 GPIOD->OTYPER = 0x00000000;
mbed_official 185:e752b4ee7de1 474 /* No pull-up, pull-down for PDx pins */
mbed_official 185:e752b4ee7de1 475 GPIOD->PUPDR = 0x00000000;
mbed_official 185:e752b4ee7de1 476
mbed_official 185:e752b4ee7de1 477 /* Connect PEx pins to FMC Alternate function */
mbed_official 185:e752b4ee7de1 478 GPIOE->AFR[0] = 0xC00CC0CC;
mbed_official 185:e752b4ee7de1 479 GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official 185:e752b4ee7de1 480 /* Configure PEx pins in Alternate function mode */
mbed_official 185:e752b4ee7de1 481 GPIOE->MODER = 0xAAAA828A;
mbed_official 185:e752b4ee7de1 482 /* Configure PEx pins speed to 100 MHz */
mbed_official 185:e752b4ee7de1 483 GPIOE->OSPEEDR = 0xFFFFC3CF;
mbed_official 185:e752b4ee7de1 484 /* Configure PEx pins Output type to push-pull */
mbed_official 185:e752b4ee7de1 485 GPIOE->OTYPER = 0x00000000;
mbed_official 185:e752b4ee7de1 486 /* No pull-up, pull-down for PEx pins */
mbed_official 185:e752b4ee7de1 487 GPIOE->PUPDR = 0x00000000;
mbed_official 185:e752b4ee7de1 488
mbed_official 185:e752b4ee7de1 489 /* Connect PFx pins to FMC Alternate function */
mbed_official 185:e752b4ee7de1 490 GPIOF->AFR[0] = 0x00CCCCCC;
mbed_official 185:e752b4ee7de1 491 GPIOF->AFR[1] = 0xCCCC0000;
mbed_official 185:e752b4ee7de1 492 /* Configure PFx pins in Alternate function mode */
mbed_official 185:e752b4ee7de1 493 GPIOF->MODER = 0xAA000AAA;
mbed_official 185:e752b4ee7de1 494 /* Configure PFx pins speed to 100 MHz */
mbed_official 185:e752b4ee7de1 495 GPIOF->OSPEEDR = 0xFF000FFF;
mbed_official 185:e752b4ee7de1 496 /* Configure PFx pins Output type to push-pull */
mbed_official 185:e752b4ee7de1 497 GPIOF->OTYPER = 0x00000000;
mbed_official 185:e752b4ee7de1 498 /* No pull-up, pull-down for PFx pins */
mbed_official 185:e752b4ee7de1 499 GPIOF->PUPDR = 0x00000000;
mbed_official 185:e752b4ee7de1 500
mbed_official 185:e752b4ee7de1 501 /* Connect PGx pins to FMC Alternate function */
mbed_official 185:e752b4ee7de1 502 GPIOG->AFR[0] = 0x00CCCCCC;
mbed_official 185:e752b4ee7de1 503 GPIOG->AFR[1] = 0x000000C0;
mbed_official 185:e752b4ee7de1 504 /* Configure PGx pins in Alternate function mode */
mbed_official 185:e752b4ee7de1 505 GPIOG->MODER = 0x00085AAA;
mbed_official 185:e752b4ee7de1 506 /* Configure PGx pins speed to 100 MHz */
mbed_official 185:e752b4ee7de1 507 GPIOG->OSPEEDR = 0x000CAFFF;
mbed_official 185:e752b4ee7de1 508 /* Configure PGx pins Output type to push-pull */
mbed_official 185:e752b4ee7de1 509 GPIOG->OTYPER = 0x00000000;
mbed_official 185:e752b4ee7de1 510 /* No pull-up, pull-down for PGx pins */
mbed_official 185:e752b4ee7de1 511 GPIOG->PUPDR = 0x00000000;
mbed_official 185:e752b4ee7de1 512
mbed_official 185:e752b4ee7de1 513 /*-- FMC/FSMC Configuration --------------------------------------------------*/
mbed_official 185:e752b4ee7de1 514 /* Enable the FMC/FSMC interface clock */
mbed_official 185:e752b4ee7de1 515 RCC->AHB3ENR |= 0x00000001;
mbed_official 185:e752b4ee7de1 516
mbed_official 185:e752b4ee7de1 517 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 185:e752b4ee7de1 518 /* Configure and enable Bank1_SRAM2 */
mbed_official 185:e752b4ee7de1 519 FMC_Bank1->BTCR[2] = 0x00001011;
mbed_official 185:e752b4ee7de1 520 FMC_Bank1->BTCR[3] = 0x00000201;
mbed_official 185:e752b4ee7de1 521 FMC_Bank1E->BWTR[2] = 0x0fffffff;
mbed_official 185:e752b4ee7de1 522 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 185:e752b4ee7de1 523
mbed_official 185:e752b4ee7de1 524 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
mbed_official 185:e752b4ee7de1 525 /* Configure and enable Bank1_SRAM2 */
mbed_official 185:e752b4ee7de1 526 FSMC_Bank1->BTCR[2] = 0x00001011;
mbed_official 185:e752b4ee7de1 527 FSMC_Bank1->BTCR[3] = 0x00000201;
mbed_official 185:e752b4ee7de1 528 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
mbed_official 185:e752b4ee7de1 529 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
mbed_official 185:e752b4ee7de1 530
mbed_official 185:e752b4ee7de1 531 #endif /* DATA_IN_ExtSRAM */
mbed_official 185:e752b4ee7de1 532 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 185:e752b4ee7de1 533 }
mbed_official 185:e752b4ee7de1 534 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 185:e752b4ee7de1 535
mbed_official 185:e752b4ee7de1 536 /**
mbed_official 185:e752b4ee7de1 537 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 185:e752b4ee7de1 538 * AHB/APBx prescalers and Flash settings
mbed_official 185:e752b4ee7de1 539 * @note This function should be called only once the RCC clock configuration
mbed_official 185:e752b4ee7de1 540 * is reset to the default reset state (done in SystemInit() function).
mbed_official 185:e752b4ee7de1 541 * @param None
mbed_official 185:e752b4ee7de1 542 * @retval None
mbed_official 185:e752b4ee7de1 543 */
mbed_official 185:e752b4ee7de1 544 void SetSysClock(void)
mbed_official 185:e752b4ee7de1 545 {
mbed_official 185:e752b4ee7de1 546 /* 1- Try to start with HSE and external clock */
mbed_official 185:e752b4ee7de1 547 #if USE_PLL_HSE_EXTC != 0
mbed_official 185:e752b4ee7de1 548 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 185:e752b4ee7de1 549 #endif
mbed_official 185:e752b4ee7de1 550 {
mbed_official 185:e752b4ee7de1 551 /* 2- If fail try to start with HSE and external xtal */
mbed_official 185:e752b4ee7de1 552 #if USE_PLL_HSE_XTAL != 0
mbed_official 185:e752b4ee7de1 553 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 185:e752b4ee7de1 554 #endif
mbed_official 185:e752b4ee7de1 555 {
mbed_official 185:e752b4ee7de1 556 /* 3- If fail start with HSI clock */
mbed_official 185:e752b4ee7de1 557 if (SetSysClock_PLL_HSI() == 0)
mbed_official 185:e752b4ee7de1 558 {
mbed_official 185:e752b4ee7de1 559 while(1)
mbed_official 185:e752b4ee7de1 560 {
mbed_official 185:e752b4ee7de1 561 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 185:e752b4ee7de1 562 }
mbed_official 185:e752b4ee7de1 563 }
mbed_official 185:e752b4ee7de1 564 }
mbed_official 185:e752b4ee7de1 565 }
mbed_official 185:e752b4ee7de1 566
mbed_official 185:e752b4ee7de1 567 /* Output clock on MCO2 pin(PC9) for debugging purpose */
mbed_official 185:e752b4ee7de1 568 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_1); // 84 MHz
mbed_official 185:e752b4ee7de1 569 }
mbed_official 185:e752b4ee7de1 570
mbed_official 185:e752b4ee7de1 571 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 185:e752b4ee7de1 572 /******************************************************************************/
mbed_official 185:e752b4ee7de1 573 /* PLL (clocked by HSE) used as System clock source */
mbed_official 185:e752b4ee7de1 574 /******************************************************************************/
mbed_official 185:e752b4ee7de1 575 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 125:23cc3068a9e4 576 {
mbed_official 125:23cc3068a9e4 577 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 125:23cc3068a9e4 578 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 125:23cc3068a9e4 579
mbed_official 125:23cc3068a9e4 580 /* The voltage scaling allows optimizing the power consumption when the device is
mbed_official 125:23cc3068a9e4 581 clocked below the maximum system frequency, to update the voltage scaling value
mbed_official 125:23cc3068a9e4 582 regarding system frequency refer to product datasheet. */
mbed_official 125:23cc3068a9e4 583 __PWR_CLK_ENABLE();
mbed_official 125:23cc3068a9e4 584 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
mbed_official 125:23cc3068a9e4 585
mbed_official 185:e752b4ee7de1 586 /* Enable HSE oscillator and activate PLL with HSE as source */
mbed_official 185:e752b4ee7de1 587 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
mbed_official 185:e752b4ee7de1 588 if (bypass == 0)
mbed_official 185:e752b4ee7de1 589 {
mbed_official 185:e752b4ee7de1 590 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
mbed_official 185:e752b4ee7de1 591 }
mbed_official 185:e752b4ee7de1 592 else
mbed_official 185:e752b4ee7de1 593 {
mbed_official 185:e752b4ee7de1 594 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
mbed_official 185:e752b4ee7de1 595 }
mbed_official 125:23cc3068a9e4 596 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 185:e752b4ee7de1 597 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 185:e752b4ee7de1 598 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
mbed_official 185:e752b4ee7de1 599 RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
mbed_official 185:e752b4ee7de1 600 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
mbed_official 185:e752b4ee7de1 601 RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> OK for USB
mbed_official 125:23cc3068a9e4 602 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 125:23cc3068a9e4 603 {
mbed_official 185:e752b4ee7de1 604 return 0; // FAIL
mbed_official 125:23cc3068a9e4 605 }
mbed_official 125:23cc3068a9e4 606
mbed_official 125:23cc3068a9e4 607 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 125:23cc3068a9e4 608 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 185:e752b4ee7de1 609 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
mbed_official 185:e752b4ee7de1 610 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
mbed_official 185:e752b4ee7de1 611 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
mbed_official 185:e752b4ee7de1 612 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
mbed_official 125:23cc3068a9e4 613 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
mbed_official 125:23cc3068a9e4 614 {
mbed_official 185:e752b4ee7de1 615 return 0; // FAIL
mbed_official 125:23cc3068a9e4 616 }
mbed_official 125:23cc3068a9e4 617
mbed_official 185:e752b4ee7de1 618 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 185:e752b4ee7de1 619 /*
mbed_official 185:e752b4ee7de1 620 if (bypass == 0)
mbed_official 185:e752b4ee7de1 621 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
mbed_official 185:e752b4ee7de1 622 else
mbed_official 185:e752b4ee7de1 623 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
mbed_official 185:e752b4ee7de1 624 */
mbed_official 185:e752b4ee7de1 625
mbed_official 185:e752b4ee7de1 626 return 1; // OK
mbed_official 185:e752b4ee7de1 627 }
mbed_official 185:e752b4ee7de1 628 #endif
mbed_official 185:e752b4ee7de1 629
mbed_official 185:e752b4ee7de1 630 /******************************************************************************/
mbed_official 185:e752b4ee7de1 631 /* PLL (clocked by HSI) used as System clock source */
mbed_official 185:e752b4ee7de1 632 /******************************************************************************/
mbed_official 185:e752b4ee7de1 633 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 185:e752b4ee7de1 634 {
mbed_official 185:e752b4ee7de1 635 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 185:e752b4ee7de1 636 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 125:23cc3068a9e4 637
mbed_official 185:e752b4ee7de1 638 /* The voltage scaling allows optimizing the power consumption when the device is
mbed_official 185:e752b4ee7de1 639 clocked below the maximum system frequency, to update the voltage scaling value
mbed_official 185:e752b4ee7de1 640 regarding system frequency refer to product datasheet. */
mbed_official 185:e752b4ee7de1 641 __PWR_CLK_ENABLE();
mbed_official 185:e752b4ee7de1 642 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
mbed_official 185:e752b4ee7de1 643
mbed_official 185:e752b4ee7de1 644 /* Enable HSI oscillator and activate PLL with HSI as source */
mbed_official 185:e752b4ee7de1 645 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
mbed_official 185:e752b4ee7de1 646 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 185:e752b4ee7de1 647 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official 185:e752b4ee7de1 648 RCC_OscInitStruct.HSICalibrationValue = 16;
mbed_official 185:e752b4ee7de1 649 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 185:e752b4ee7de1 650 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
mbed_official 185:e752b4ee7de1 651 RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
mbed_official 185:e752b4ee7de1 652 RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
mbed_official 185:e752b4ee7de1 653 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
mbed_official 185:e752b4ee7de1 654 RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> freq is ok but not precise enough
mbed_official 185:e752b4ee7de1 655 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 185:e752b4ee7de1 656 {
mbed_official 185:e752b4ee7de1 657 return 0; // FAIL
mbed_official 185:e752b4ee7de1 658 }
mbed_official 185:e752b4ee7de1 659
mbed_official 185:e752b4ee7de1 660 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 185:e752b4ee7de1 661 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 185:e752b4ee7de1 662 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
mbed_official 185:e752b4ee7de1 663 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
mbed_official 185:e752b4ee7de1 664 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
mbed_official 185:e752b4ee7de1 665 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
mbed_official 185:e752b4ee7de1 666 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
mbed_official 185:e752b4ee7de1 667 {
mbed_official 185:e752b4ee7de1 668 return 0; // FAIL
mbed_official 185:e752b4ee7de1 669 }
mbed_official 185:e752b4ee7de1 670
mbed_official 185:e752b4ee7de1 671 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 185:e752b4ee7de1 672 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
mbed_official 185:e752b4ee7de1 673
mbed_official 185:e752b4ee7de1 674 return 1; // OK
mbed_official 125:23cc3068a9e4 675 }
mbed_official 125:23cc3068a9e4 676
mbed_official 185:e752b4ee7de1 677 /* Used for the different timeouts in the HAL */
mbed_official 125:23cc3068a9e4 678 void SysTick_Handler(void)
mbed_official 125:23cc3068a9e4 679 {
mbed_official 125:23cc3068a9e4 680 HAL_IncTick();
mbed_official 125:23cc3068a9e4 681 }
mbed_official 125:23cc3068a9e4 682
mbed_official 87:085cde657901 683 /**
mbed_official 87:085cde657901 684 * @}
mbed_official 87:085cde657901 685 */
mbed_official 87:085cde657901 686
mbed_official 87:085cde657901 687 /**
mbed_official 87:085cde657901 688 * @}
mbed_official 87:085cde657901 689 */
mbed_official 87:085cde657901 690
mbed_official 87:085cde657901 691 /**
mbed_official 87:085cde657901 692 * @}
mbed_official 87:085cde657901 693 */
mbed_official 87:085cde657901 694 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/