shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.c@226:b062af740e40, 2014-06-11 (annotated)

Committer:
mbed_official
Date:
Wed Jun 11 09:45:09 2014 +0100
Revision:
226:b062af740e40
Parent:
185:e752b4ee7de1 
Synchronized with git revision 42deb9ac55f9bdf9835e9c41dc757117d344ffda



Full URL: https://github.com/mbedmicro/mbed/commit/42deb9ac55f9bdf9835e9c41dc757117d344ffda/



[NUCLEO_F401RE] Remove call to Systick + bug fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 87:085cde657901 1 /**
mbed_official 87:085cde657901 2 ******************************************************************************
mbed_official 87:085cde657901 3 * @file system_stm32f4xx.c
mbed_official 87:085cde657901 4 * @author MCD Application Team
mbed_official 226:b062af740e40 5 * @version V2.1.0RC2
mbed_official 226:b062af740e40 6 * @date 14-May-2014
mbed_official 87:085cde657901 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
mbed_official 87:085cde657901 8 *
mbed_official 87:085cde657901 9 * This file provides two functions and one global variable to be called from
mbed_official 87:085cde657901 10 * user application:
mbed_official 87:085cde657901 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 87:085cde657901 12 * before branch to main program. This call is made inside
mbed_official 87:085cde657901 13 * the "startup_stm32f4xx.s" file.
mbed_official 87:085cde657901 14 *
mbed_official 87:085cde657901 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 87:085cde657901 16 * by the user application to setup the SysTick
mbed_official 87:085cde657901 17 * timer or configure other parameters.
mbed_official 87:085cde657901 18 *
mbed_official 87:085cde657901 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 87:085cde657901 20 * be called whenever the core clock is changed
mbed_official 87:085cde657901 21 * during program execution.
mbed_official 87:085cde657901 22 *
mbed_official 185:e752b4ee7de1 23 * This file configures the system clock as follows:
mbed_official 185:e752b4ee7de1 24 *-----------------------------------------------------------------------------
mbed_official 185:e752b4ee7de1 25 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 185:e752b4ee7de1 26 * | (external 8 MHz clock) | (internal 16 MHz)
mbed_official 185:e752b4ee7de1 27 * | 2- PLL_HSE_XTAL |
mbed_official 185:e752b4ee7de1 28 * | (external 8 MHz xtal) |
mbed_official 185:e752b4ee7de1 29 *-----------------------------------------------------------------------------
mbed_official 185:e752b4ee7de1 30 * SYSCLK(MHz) | 84 | 84
mbed_official 185:e752b4ee7de1 31 *-----------------------------------------------------------------------------
mbed_official 185:e752b4ee7de1 32 * AHBCLK (MHz) | 84 | 84
mbed_official 185:e752b4ee7de1 33 *-----------------------------------------------------------------------------
mbed_official 185:e752b4ee7de1 34 * APB1CLK (MHz) | 42 | 42
mbed_official 185:e752b4ee7de1 35 *-----------------------------------------------------------------------------
mbed_official 185:e752b4ee7de1 36 * APB2CLK (MHz) | 84 | 84
mbed_official 185:e752b4ee7de1 37 *-----------------------------------------------------------------------------
mbed_official 185:e752b4ee7de1 38 * USB capable (48 MHz precise clock) | YES | NO
mbed_official 185:e752b4ee7de1 39 *-----------------------------------------------------------------------------
mbed_official 87:085cde657901 40 ******************************************************************************
mbed_official 87:085cde657901 41 * @attention
mbed_official 87:085cde657901 42 *
mbed_official 87:085cde657901 43 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
mbed_official 87:085cde657901 44 *
mbed_official 106:ced8cbb51063 45 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 106:ced8cbb51063 46 * are permitted provided that the following conditions are met:
mbed_official 106:ced8cbb51063 47 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 106:ced8cbb51063 48 * this list of conditions and the following disclaimer.
mbed_official 106:ced8cbb51063 49 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 106:ced8cbb51063 50 * this list of conditions and the following disclaimer in the documentation
mbed_official 106:ced8cbb51063 51 * and/or other materials provided with the distribution.
mbed_official 106:ced8cbb51063 52 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 106:ced8cbb51063 53 * may be used to endorse or promote products derived from this software
mbed_official 106:ced8cbb51063 54 * without specific prior written permission.
mbed_official 87:085cde657901 55 *
mbed_official 106:ced8cbb51063 56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 106:ced8cbb51063 57 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 106:ced8cbb51063 58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 106:ced8cbb51063 59 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 106:ced8cbb51063 60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 106:ced8cbb51063 61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 106:ced8cbb51063 62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 106:ced8cbb51063 63 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 106:ced8cbb51063 64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 106:ced8cbb51063 65 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 87:085cde657901 66 *
mbed_official 87:085cde657901 67 ******************************************************************************
mbed_official 87:085cde657901 68 */
mbed_official 87:085cde657901 69
mbed_official 87:085cde657901 70 /** @addtogroup CMSIS
mbed_official 87:085cde657901 71 * @{
mbed_official 87:085cde657901 72 */
mbed_official 87:085cde657901 73
mbed_official 87:085cde657901 74 /** @addtogroup stm32f4xx_system
mbed_official 87:085cde657901 75 * @{
mbed_official 87:085cde657901 76 */
mbed_official 87:085cde657901 77
mbed_official 87:085cde657901 78 /** @addtogroup STM32F4xx_System_Private_Includes
mbed_official 87:085cde657901 79 * @{
mbed_official 87:085cde657901 80 */
mbed_official 87:085cde657901 81
mbed_official 226:b062af740e40 82 #include "stm32f4xx.h"
mbed_official 226:b062af740e40 83 #include "hal_tick.h"
mbed_official 226:b062af740e40 84
mbed_official 226:b062af740e40 85 #if !defined (HSE_VALUE)
mbed_official 226:b062af740e40 86 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
mbed_official 226:b062af740e40 87 #endif /* HSE_VALUE */
mbed_official 226:b062af740e40 88
mbed_official 226:b062af740e40 89 #if !defined (HSI_VALUE)
mbed_official 226:b062af740e40 90 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
mbed_official 226:b062af740e40 91 #endif /* HSI_VALUE */
mbed_official 87:085cde657901 92
mbed_official 87:085cde657901 93 /**
mbed_official 87:085cde657901 94 * @}
mbed_official 87:085cde657901 95 */
mbed_official 87:085cde657901 96
mbed_official 87:085cde657901 97 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
mbed_official 87:085cde657901 98 * @{
mbed_official 87:085cde657901 99 */
mbed_official 87:085cde657901 100
mbed_official 87:085cde657901 101 /**
mbed_official 87:085cde657901 102 * @}
mbed_official 87:085cde657901 103 */
mbed_official 87:085cde657901 104
mbed_official 87:085cde657901 105 /** @addtogroup STM32F4xx_System_Private_Defines
mbed_official 87:085cde657901 106 * @{
mbed_official 87:085cde657901 107 */
mbed_official 87:085cde657901 108
mbed_official 87:085cde657901 109 /************************* Miscellaneous Configuration ************************/
mbed_official 185:e752b4ee7de1 110 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
mbed_official 185:e752b4ee7de1 111 on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
mbed_official 185:e752b4ee7de1 112 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 185:e752b4ee7de1 113 /* #define DATA_IN_ExtSRAM */
mbed_official 185:e752b4ee7de1 114 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 185:e752b4ee7de1 115
mbed_official 185:e752b4ee7de1 116 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 185:e752b4ee7de1 117 /* #define DATA_IN_ExtSDRAM */
mbed_official 185:e752b4ee7de1 118 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 185:e752b4ee7de1 119
mbed_official 185:e752b4ee7de1 120 #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
mbed_official 185:e752b4ee7de1 121 #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
mbed_official 185:e752b4ee7de1 122 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
mbed_official 87:085cde657901 123
mbed_official 87:085cde657901 124 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 87:085cde657901 125 Internal SRAM. */
mbed_official 87:085cde657901 126 /* #define VECT_TAB_SRAM */
mbed_official 87:085cde657901 127 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
mbed_official 87:085cde657901 128 This value must be a multiple of 0x200. */
mbed_official 87:085cde657901 129 /******************************************************************************/
mbed_official 87:085cde657901 130
mbed_official 87:085cde657901 131 /**
mbed_official 87:085cde657901 132 * @}
mbed_official 87:085cde657901 133 */
mbed_official 87:085cde657901 134
mbed_official 87:085cde657901 135 /** @addtogroup STM32F4xx_System_Private_Macros
mbed_official 87:085cde657901 136 * @{
mbed_official 87:085cde657901 137 */
mbed_official 87:085cde657901 138
mbed_official 185:e752b4ee7de1 139 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 185:e752b4ee7de1 140 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 185:e752b4ee7de1 141 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 185:e752b4ee7de1 142
mbed_official 87:085cde657901 143 /**
mbed_official 87:085cde657901 144 * @}
mbed_official 87:085cde657901 145 */
mbed_official 87:085cde657901 146
mbed_official 87:085cde657901 147 /** @addtogroup STM32F4xx_System_Private_Variables
mbed_official 87:085cde657901 148 * @{
mbed_official 87:085cde657901 149 */
mbed_official 87:085cde657901 150 /* This variable is updated in three ways:
mbed_official 87:085cde657901 151 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 87:085cde657901 152 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 87:085cde657901 153 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 87:085cde657901 154 Note: If you use this function to configure the system clock; then there
mbed_official 87:085cde657901 155 is no need to call the 2 first functions listed above, since SystemCoreClock
mbed_official 87:085cde657901 156 variable is updated automatically.
mbed_official 87:085cde657901 157 */
mbed_official 185:e752b4ee7de1 158 uint32_t SystemCoreClock = 84000000;
mbed_official 185:e752b4ee7de1 159 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 87:085cde657901 160
mbed_official 87:085cde657901 161 /**
mbed_official 87:085cde657901 162 * @}
mbed_official 87:085cde657901 163 */
mbed_official 87:085cde657901 164
mbed_official 87:085cde657901 165 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
mbed_official 87:085cde657901 166 * @{
mbed_official 87:085cde657901 167 */
mbed_official 87:085cde657901 168
mbed_official 185:e752b4ee7de1 169 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 185:e752b4ee7de1 170 static void SystemInit_ExtMemCtl(void);
mbed_official 185:e752b4ee7de1 171 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 185:e752b4ee7de1 172
mbed_official 185:e752b4ee7de1 173 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 185:e752b4ee7de1 174 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 185:e752b4ee7de1 175 #endif
mbed_official 185:e752b4ee7de1 176
mbed_official 185:e752b4ee7de1 177 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 185:e752b4ee7de1 178
mbed_official 87:085cde657901 179 /**
mbed_official 87:085cde657901 180 * @}
mbed_official 87:085cde657901 181 */
mbed_official 87:085cde657901 182
mbed_official 87:085cde657901 183 /** @addtogroup STM32F4xx_System_Private_Functions
mbed_official 87:085cde657901 184 * @{
mbed_official 87:085cde657901 185 */
mbed_official 87:085cde657901 186
mbed_official 87:085cde657901 187 /**
mbed_official 87:085cde657901 188 * @brief Setup the microcontroller system
mbed_official 87:085cde657901 189 * Initialize the FPU setting, vector table location and External memory
mbed_official 87:085cde657901 190 * configuration.
mbed_official 87:085cde657901 191 * @param None
mbed_official 87:085cde657901 192 * @retval None
mbed_official 87:085cde657901 193 */
mbed_official 87:085cde657901 194 void SystemInit(void)
mbed_official 87:085cde657901 195 {
mbed_official 87:085cde657901 196 /* FPU settings ------------------------------------------------------------*/
mbed_official 87:085cde657901 197 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 87:085cde657901 198 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
mbed_official 87:085cde657901 199 #endif
mbed_official 87:085cde657901 200 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 87:085cde657901 201 /* Set HSION bit */
mbed_official 87:085cde657901 202 RCC->CR |= (uint32_t)0x00000001;
mbed_official 87:085cde657901 203
mbed_official 87:085cde657901 204 /* Reset CFGR register */
mbed_official 87:085cde657901 205 RCC->CFGR = 0x00000000;
mbed_official 87:085cde657901 206
mbed_official 87:085cde657901 207 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 87:085cde657901 208 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 87:085cde657901 209
mbed_official 87:085cde657901 210 /* Reset PLLCFGR register */
mbed_official 87:085cde657901 211 RCC->PLLCFGR = 0x24003010;
mbed_official 87:085cde657901 212
mbed_official 87:085cde657901 213 /* Reset HSEBYP bit */
mbed_official 87:085cde657901 214 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 87:085cde657901 215
mbed_official 87:085cde657901 216 /* Disable all interrupts */
mbed_official 87:085cde657901 217 RCC->CIR = 0x00000000;
mbed_official 87:085cde657901 218
mbed_official 185:e752b4ee7de1 219 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 185:e752b4ee7de1 220 SystemInit_ExtMemCtl();
mbed_official 185:e752b4ee7de1 221 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 185:e752b4ee7de1 222
mbed_official 87:085cde657901 223 /* Configure the Vector Table location add offset address ------------------*/
mbed_official 87:085cde657901 224 #ifdef VECT_TAB_SRAM
mbed_official 87:085cde657901 225 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 87:085cde657901 226 #else
mbed_official 87:085cde657901 227 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 87:085cde657901 228 #endif
mbed_official 87:085cde657901 229
mbed_official 185:e752b4ee7de1 230 /* Configure the Cube driver */
mbed_official 226:b062af740e40 231 SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
mbed_official 87:085cde657901 232 HAL_Init();
mbed_official 185:e752b4ee7de1 233
mbed_official 185:e752b4ee7de1 234 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 185:e752b4ee7de1 235 AHB/APBx prescalers and Flash settings */
mbed_official 185:e752b4ee7de1 236 SetSysClock();
mbed_official 226:b062af740e40 237
mbed_official 226:b062af740e40 238 /* Reset the timer to avoid issues after the RAM initialization */
mbed_official 226:b062af740e40 239 TIM_MST_RESET_ON;
mbed_official 226:b062af740e40 240 TIM_MST_RESET_OFF;
mbed_official 87:085cde657901 241 }
mbed_official 87:085cde657901 242
mbed_official 87:085cde657901 243 /**
mbed_official 87:085cde657901 244 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 87:085cde657901 245 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 87:085cde657901 246 * be used by the user application to setup the SysTick timer or configure
mbed_official 87:085cde657901 247 * other parameters.
mbed_official 87:085cde657901 248 *
mbed_official 87:085cde657901 249 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 87:085cde657901 250 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 87:085cde657901 251 * based on this variable will be incorrect.
mbed_official 87:085cde657901 252 *
mbed_official 87:085cde657901 253 * @note - The system frequency computed by this function is not the real
mbed_official 87:085cde657901 254 * frequency in the chip. It is calculated based on the predefined
mbed_official 87:085cde657901 255 * constant and the selected clock source:
mbed_official 87:085cde657901 256 *
mbed_official 87:085cde657901 257 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 87:085cde657901 258 *
mbed_official 87:085cde657901 259 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 87:085cde657901 260 *
mbed_official 87:085cde657901 261 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 87:085cde657901 262 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 87:085cde657901 263 *
mbed_official 106:ced8cbb51063 264 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
mbed_official 87:085cde657901 265 * 16 MHz) but the real value may vary depending on the variations
mbed_official 87:085cde657901 266 * in voltage and temperature.
mbed_official 87:085cde657901 267 *
mbed_official 106:ced8cbb51063 268 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
mbed_official 106:ced8cbb51063 269 * depends on the application requirements), user has to ensure that HSE_VALUE
mbed_official 106:ced8cbb51063 270 * is same as the real frequency of the crystal used. Otherwise, this function
mbed_official 106:ced8cbb51063 271 * may have wrong result.
mbed_official 87:085cde657901 272 *
mbed_official 87:085cde657901 273 * - The result of this function could be not correct when using fractional
mbed_official 87:085cde657901 274 * value for HSE crystal.
mbed_official 87:085cde657901 275 *
mbed_official 87:085cde657901 276 * @param None
mbed_official 87:085cde657901 277 * @retval None
mbed_official 87:085cde657901 278 */
mbed_official 87:085cde657901 279 void SystemCoreClockUpdate(void)
mbed_official 87:085cde657901 280 {
mbed_official 87:085cde657901 281 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
mbed_official 87:085cde657901 282
mbed_official 87:085cde657901 283 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 87:085cde657901 284 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 87:085cde657901 285
mbed_official 87:085cde657901 286 switch (tmp)
mbed_official 87:085cde657901 287 {
mbed_official 87:085cde657901 288 case 0x00: /* HSI used as system clock source */
mbed_official 87:085cde657901 289 SystemCoreClock = HSI_VALUE;
mbed_official 87:085cde657901 290 break;
mbed_official 87:085cde657901 291 case 0x04: /* HSE used as system clock source */
mbed_official 87:085cde657901 292 SystemCoreClock = HSE_VALUE;
mbed_official 87:085cde657901 293 break;
mbed_official 87:085cde657901 294 case 0x08: /* PLL used as system clock source */
mbed_official 87:085cde657901 295
mbed_official 87:085cde657901 296 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
mbed_official 87:085cde657901 297 SYSCLK = PLL_VCO / PLL_P
mbed_official 87:085cde657901 298 */
mbed_official 87:085cde657901 299 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
mbed_official 87:085cde657901 300 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
mbed_official 87:085cde657901 301
mbed_official 87:085cde657901 302 if (pllsource != 0)
mbed_official 87:085cde657901 303 {
mbed_official 87:085cde657901 304 /* HSE used as PLL clock source */
mbed_official 87:085cde657901 305 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official 87:085cde657901 306 }
mbed_official 87:085cde657901 307 else
mbed_official 87:085cde657901 308 {
mbed_official 87:085cde657901 309 /* HSI used as PLL clock source */
mbed_official 87:085cde657901 310 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official 87:085cde657901 311 }
mbed_official 87:085cde657901 312
mbed_official 87:085cde657901 313 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
mbed_official 87:085cde657901 314 SystemCoreClock = pllvco/pllp;
mbed_official 87:085cde657901 315 break;
mbed_official 87:085cde657901 316 default:
mbed_official 87:085cde657901 317 SystemCoreClock = HSI_VALUE;
mbed_official 87:085cde657901 318 break;
mbed_official 87:085cde657901 319 }
mbed_official 87:085cde657901 320 /* Compute HCLK frequency --------------------------------------------------*/
mbed_official 87:085cde657901 321 /* Get HCLK prescaler */
mbed_official 87:085cde657901 322 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 87:085cde657901 323 /* HCLK frequency */
mbed_official 87:085cde657901 324 SystemCoreClock >>= tmp;
mbed_official 87:085cde657901 325 }
mbed_official 87:085cde657901 326
mbed_official 185:e752b4ee7de1 327 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 185:e752b4ee7de1 328 /**
mbed_official 185:e752b4ee7de1 329 * @brief Setup the external memory controller.
mbed_official 185:e752b4ee7de1 330 * Called in startup_stm32f4xx.s before jump to main.
mbed_official 185:e752b4ee7de1 331 * This function configures the external memories (SRAM/SDRAM)
mbed_official 185:e752b4ee7de1 332 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
mbed_official 185:e752b4ee7de1 333 * @param None
mbed_official 185:e752b4ee7de1 334 * @retval None
mbed_official 185:e752b4ee7de1 335 */
mbed_official 185:e752b4ee7de1 336 void SystemInit_ExtMemCtl(void)
mbed_official 185:e752b4ee7de1 337 {
mbed_official 185:e752b4ee7de1 338 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 185:e752b4ee7de1 339 #if defined (DATA_IN_ExtSDRAM)
mbed_official 185:e752b4ee7de1 340 register uint32_t tmpreg = 0, timeout = 0xFFFF;
mbed_official 185:e752b4ee7de1 341 register uint32_t index;
mbed_official 185:e752b4ee7de1 342
mbed_official 185:e752b4ee7de1 343 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
mbed_official 185:e752b4ee7de1 344 clock */
mbed_official 185:e752b4ee7de1 345 RCC->AHB1ENR |= 0x000001F8;
mbed_official 185:e752b4ee7de1 346
mbed_official 185:e752b4ee7de1 347 /* Connect PDx pins to FMC Alternate function */
mbed_official 185:e752b4ee7de1 348 GPIOD->AFR[0] = 0x000000CC;
mbed_official 185:e752b4ee7de1 349 GPIOD->AFR[1] = 0xCC000CCC;
mbed_official 185:e752b4ee7de1 350 /* Configure PDx pins in Alternate function mode */
mbed_official 185:e752b4ee7de1 351 GPIOD->MODER = 0xA02A000A;
mbed_official 185:e752b4ee7de1 352 /* Configure PDx pins speed to 50 MHz */
mbed_official 185:e752b4ee7de1 353 GPIOD->OSPEEDR = 0xA02A000A;
mbed_official 185:e752b4ee7de1 354 /* Configure PDx pins Output type to push-pull */
mbed_official 185:e752b4ee7de1 355 GPIOD->OTYPER = 0x00000000;
mbed_official 185:e752b4ee7de1 356 /* No pull-up, pull-down for PDx pins */
mbed_official 185:e752b4ee7de1 357 GPIOD->PUPDR = 0x00000000;
mbed_official 185:e752b4ee7de1 358
mbed_official 185:e752b4ee7de1 359 /* Connect PEx pins to FMC Alternate function */
mbed_official 185:e752b4ee7de1 360 GPIOE->AFR[0] = 0xC00000CC;
mbed_official 185:e752b4ee7de1 361 GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official 185:e752b4ee7de1 362 /* Configure PEx pins in Alternate function mode */
mbed_official 185:e752b4ee7de1 363 GPIOE->MODER = 0xAAAA800A;
mbed_official 185:e752b4ee7de1 364 /* Configure PEx pins speed to 50 MHz */
mbed_official 185:e752b4ee7de1 365 GPIOE->OSPEEDR = 0xAAAA800A;
mbed_official 185:e752b4ee7de1 366 /* Configure PEx pins Output type to push-pull */
mbed_official 185:e752b4ee7de1 367 GPIOE->OTYPER = 0x00000000;
mbed_official 185:e752b4ee7de1 368 /* No pull-up, pull-down for PEx pins */
mbed_official 185:e752b4ee7de1 369 GPIOE->PUPDR = 0x00000000;
mbed_official 185:e752b4ee7de1 370
mbed_official 185:e752b4ee7de1 371 /* Connect PFx pins to FMC Alternate function */
mbed_official 185:e752b4ee7de1 372 GPIOF->AFR[0] = 0xCCCCCCCC;
mbed_official 185:e752b4ee7de1 373 GPIOF->AFR[1] = 0xCCCCCCCC;
mbed_official 185:e752b4ee7de1 374 /* Configure PFx pins in Alternate function mode */
mbed_official 185:e752b4ee7de1 375 GPIOF->MODER = 0xAA800AAA;
mbed_official 185:e752b4ee7de1 376 /* Configure PFx pins speed to 50 MHz */
mbed_official 185:e752b4ee7de1 377 GPIOF->OSPEEDR = 0xAA800AAA;
mbed_official 185:e752b4ee7de1 378 /* Configure PFx pins Output type to push-pull */
mbed_official 185:e752b4ee7de1 379 GPIOF->OTYPER = 0x00000000;
mbed_official 185:e752b4ee7de1 380 /* No pull-up, pull-down for PFx pins */
mbed_official 185:e752b4ee7de1 381 GPIOF->PUPDR = 0x00000000;
mbed_official 185:e752b4ee7de1 382
mbed_official 185:e752b4ee7de1 383 /* Connect PGx pins to FMC Alternate function */
mbed_official 185:e752b4ee7de1 384 GPIOG->AFR[0] = 0xCCCCCCCC;
mbed_official 185:e752b4ee7de1 385 GPIOG->AFR[1] = 0xCCCCCCCC;
mbed_official 185:e752b4ee7de1 386 /* Configure PGx pins in Alternate function mode */
mbed_official 185:e752b4ee7de1 387 GPIOG->MODER = 0xAAAAAAAA;
mbed_official 185:e752b4ee7de1 388 /* Configure PGx pins speed to 50 MHz */
mbed_official 185:e752b4ee7de1 389 GPIOG->OSPEEDR = 0xAAAAAAAA;
mbed_official 185:e752b4ee7de1 390 /* Configure PGx pins Output type to push-pull */
mbed_official 185:e752b4ee7de1 391 GPIOG->OTYPER = 0x00000000;
mbed_official 185:e752b4ee7de1 392 /* No pull-up, pull-down for PGx pins */
mbed_official 185:e752b4ee7de1 393 GPIOG->PUPDR = 0x00000000;
mbed_official 185:e752b4ee7de1 394
mbed_official 185:e752b4ee7de1 395 /* Connect PHx pins to FMC Alternate function */
mbed_official 185:e752b4ee7de1 396 GPIOH->AFR[0] = 0x00C0CC00;
mbed_official 185:e752b4ee7de1 397 GPIOH->AFR[1] = 0xCCCCCCCC;
mbed_official 185:e752b4ee7de1 398 /* Configure PHx pins in Alternate function mode */
mbed_official 185:e752b4ee7de1 399 GPIOH->MODER = 0xAAAA08A0;
mbed_official 185:e752b4ee7de1 400 /* Configure PHx pins speed to 50 MHz */
mbed_official 185:e752b4ee7de1 401 GPIOH->OSPEEDR = 0xAAAA08A0;
mbed_official 185:e752b4ee7de1 402 /* Configure PHx pins Output type to push-pull */
mbed_official 185:e752b4ee7de1 403 GPIOH->OTYPER = 0x00000000;
mbed_official 185:e752b4ee7de1 404 /* No pull-up, pull-down for PHx pins */
mbed_official 185:e752b4ee7de1 405 GPIOH->PUPDR = 0x00000000;
mbed_official 185:e752b4ee7de1 406
mbed_official 185:e752b4ee7de1 407 /* Connect PIx pins to FMC Alternate function */
mbed_official 185:e752b4ee7de1 408 GPIOI->AFR[0] = 0xCCCCCCCC;
mbed_official 185:e752b4ee7de1 409 GPIOI->AFR[1] = 0x00000CC0;
mbed_official 185:e752b4ee7de1 410 /* Configure PIx pins in Alternate function mode */
mbed_official 185:e752b4ee7de1 411 GPIOI->MODER = 0x0028AAAA;
mbed_official 185:e752b4ee7de1 412 /* Configure PIx pins speed to 50 MHz */
mbed_official 185:e752b4ee7de1 413 GPIOI->OSPEEDR = 0x0028AAAA;
mbed_official 185:e752b4ee7de1 414 /* Configure PIx pins Output type to push-pull */
mbed_official 185:e752b4ee7de1 415 GPIOI->OTYPER = 0x00000000;
mbed_official 185:e752b4ee7de1 416 /* No pull-up, pull-down for PIx pins */
mbed_official 185:e752b4ee7de1 417 GPIOI->PUPDR = 0x00000000;
mbed_official 185:e752b4ee7de1 418
mbed_official 185:e752b4ee7de1 419 /*-- FMC Configuration ------------------------------------------------------*/
mbed_official 185:e752b4ee7de1 420 /* Enable the FMC interface clock */
mbed_official 185:e752b4ee7de1 421 RCC->AHB3ENR |= 0x00000001;
mbed_official 185:e752b4ee7de1 422
mbed_official 185:e752b4ee7de1 423 /* Configure and enable SDRAM bank1 */
mbed_official 185:e752b4ee7de1 424 FMC_Bank5_6->SDCR[0] = 0x000019E0;
mbed_official 185:e752b4ee7de1 425 FMC_Bank5_6->SDTR[0] = 0x01115351;
mbed_official 185:e752b4ee7de1 426
mbed_official 185:e752b4ee7de1 427 /* SDRAM initialization sequence */
mbed_official 185:e752b4ee7de1 428 /* Clock enable command */
mbed_official 185:e752b4ee7de1 429 FMC_Bank5_6->SDCMR = 0x00000011;
mbed_official 185:e752b4ee7de1 430 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 185:e752b4ee7de1 431 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 185:e752b4ee7de1 432 {
mbed_official 185:e752b4ee7de1 433 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 185:e752b4ee7de1 434 }
mbed_official 185:e752b4ee7de1 435
mbed_official 185:e752b4ee7de1 436 /* Delay */
mbed_official 185:e752b4ee7de1 437 for (index = 0; index<1000; index++);
mbed_official 185:e752b4ee7de1 438
mbed_official 185:e752b4ee7de1 439 /* PALL command */
mbed_official 185:e752b4ee7de1 440 FMC_Bank5_6->SDCMR = 0x00000012;
mbed_official 185:e752b4ee7de1 441 timeout = 0xFFFF;
mbed_official 185:e752b4ee7de1 442 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 185:e752b4ee7de1 443 {
mbed_official 185:e752b4ee7de1 444 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 185:e752b4ee7de1 445 }
mbed_official 185:e752b4ee7de1 446
mbed_official 185:e752b4ee7de1 447 /* Auto refresh command */
mbed_official 185:e752b4ee7de1 448 FMC_Bank5_6->SDCMR = 0x00000073;
mbed_official 185:e752b4ee7de1 449 timeout = 0xFFFF;
mbed_official 185:e752b4ee7de1 450 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 185:e752b4ee7de1 451 {
mbed_official 185:e752b4ee7de1 452 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 185:e752b4ee7de1 453 }
mbed_official 185:e752b4ee7de1 454
mbed_official 185:e752b4ee7de1 455 /* MRD register program */
mbed_official 185:e752b4ee7de1 456 FMC_Bank5_6->SDCMR = 0x00046014;
mbed_official 185:e752b4ee7de1 457 timeout = 0xFFFF;
mbed_official 185:e752b4ee7de1 458 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 185:e752b4ee7de1 459 {
mbed_official 185:e752b4ee7de1 460 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 185:e752b4ee7de1 461 }
mbed_official 185:e752b4ee7de1 462
mbed_official 185:e752b4ee7de1 463 /* Set refresh count */
mbed_official 185:e752b4ee7de1 464 tmpreg = FMC_Bank5_6->SDRTR;
mbed_official 185:e752b4ee7de1 465 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
mbed_official 185:e752b4ee7de1 466
mbed_official 185:e752b4ee7de1 467 /* Disable write protection */
mbed_official 185:e752b4ee7de1 468 tmpreg = FMC_Bank5_6->SDCR[0];
mbed_official 185:e752b4ee7de1 469 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
mbed_official 185:e752b4ee7de1 470 #endif /* DATA_IN_ExtSDRAM */
mbed_official 185:e752b4ee7de1 471 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 185:e752b4ee7de1 472
mbed_official 185:e752b4ee7de1 473 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 185:e752b4ee7de1 474 #if defined(DATA_IN_ExtSRAM)
mbed_official 185:e752b4ee7de1 475 /*-- GPIOs Configuration -----------------------------------------------------*/
mbed_official 185:e752b4ee7de1 476 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
mbed_official 185:e752b4ee7de1 477 RCC->AHB1ENR |= 0x00000078;
mbed_official 185:e752b4ee7de1 478
mbed_official 185:e752b4ee7de1 479 /* Connect PDx pins to FMC Alternate function */
mbed_official 185:e752b4ee7de1 480 GPIOD->AFR[0] = 0x00CCC0CC;
mbed_official 185:e752b4ee7de1 481 GPIOD->AFR[1] = 0xCCCCCCCC;
mbed_official 185:e752b4ee7de1 482 /* Configure PDx pins in Alternate function mode */
mbed_official 185:e752b4ee7de1 483 GPIOD->MODER = 0xAAAA0A8A;
mbed_official 185:e752b4ee7de1 484 /* Configure PDx pins speed to 100 MHz */
mbed_official 185:e752b4ee7de1 485 GPIOD->OSPEEDR = 0xFFFF0FCF;
mbed_official 185:e752b4ee7de1 486 /* Configure PDx pins Output type to push-pull */
mbed_official 185:e752b4ee7de1 487 GPIOD->OTYPER = 0x00000000;
mbed_official 185:e752b4ee7de1 488 /* No pull-up, pull-down for PDx pins */
mbed_official 185:e752b4ee7de1 489 GPIOD->PUPDR = 0x00000000;
mbed_official 185:e752b4ee7de1 490
mbed_official 185:e752b4ee7de1 491 /* Connect PEx pins to FMC Alternate function */
mbed_official 185:e752b4ee7de1 492 GPIOE->AFR[0] = 0xC00CC0CC;
mbed_official 185:e752b4ee7de1 493 GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official 185:e752b4ee7de1 494 /* Configure PEx pins in Alternate function mode */
mbed_official 185:e752b4ee7de1 495 GPIOE->MODER = 0xAAAA828A;
mbed_official 185:e752b4ee7de1 496 /* Configure PEx pins speed to 100 MHz */
mbed_official 185:e752b4ee7de1 497 GPIOE->OSPEEDR = 0xFFFFC3CF;
mbed_official 185:e752b4ee7de1 498 /* Configure PEx pins Output type to push-pull */
mbed_official 185:e752b4ee7de1 499 GPIOE->OTYPER = 0x00000000;
mbed_official 185:e752b4ee7de1 500 /* No pull-up, pull-down for PEx pins */
mbed_official 185:e752b4ee7de1 501 GPIOE->PUPDR = 0x00000000;
mbed_official 185:e752b4ee7de1 502
mbed_official 185:e752b4ee7de1 503 /* Connect PFx pins to FMC Alternate function */
mbed_official 185:e752b4ee7de1 504 GPIOF->AFR[0] = 0x00CCCCCC;
mbed_official 185:e752b4ee7de1 505 GPIOF->AFR[1] = 0xCCCC0000;
mbed_official 185:e752b4ee7de1 506 /* Configure PFx pins in Alternate function mode */
mbed_official 185:e752b4ee7de1 507 GPIOF->MODER = 0xAA000AAA;
mbed_official 185:e752b4ee7de1 508 /* Configure PFx pins speed to 100 MHz */
mbed_official 185:e752b4ee7de1 509 GPIOF->OSPEEDR = 0xFF000FFF;
mbed_official 185:e752b4ee7de1 510 /* Configure PFx pins Output type to push-pull */
mbed_official 185:e752b4ee7de1 511 GPIOF->OTYPER = 0x00000000;
mbed_official 185:e752b4ee7de1 512 /* No pull-up, pull-down for PFx pins */
mbed_official 185:e752b4ee7de1 513 GPIOF->PUPDR = 0x00000000;
mbed_official 185:e752b4ee7de1 514
mbed_official 185:e752b4ee7de1 515 /* Connect PGx pins to FMC Alternate function */
mbed_official 185:e752b4ee7de1 516 GPIOG->AFR[0] = 0x00CCCCCC;
mbed_official 185:e752b4ee7de1 517 GPIOG->AFR[1] = 0x000000C0;
mbed_official 185:e752b4ee7de1 518 /* Configure PGx pins in Alternate function mode */
mbed_official 185:e752b4ee7de1 519 GPIOG->MODER = 0x00085AAA;
mbed_official 185:e752b4ee7de1 520 /* Configure PGx pins speed to 100 MHz */
mbed_official 185:e752b4ee7de1 521 GPIOG->OSPEEDR = 0x000CAFFF;
mbed_official 185:e752b4ee7de1 522 /* Configure PGx pins Output type to push-pull */
mbed_official 185:e752b4ee7de1 523 GPIOG->OTYPER = 0x00000000;
mbed_official 185:e752b4ee7de1 524 /* No pull-up, pull-down for PGx pins */
mbed_official 185:e752b4ee7de1 525 GPIOG->PUPDR = 0x00000000;
mbed_official 185:e752b4ee7de1 526
mbed_official 185:e752b4ee7de1 527 /*-- FMC/FSMC Configuration --------------------------------------------------*/
mbed_official 185:e752b4ee7de1 528 /* Enable the FMC/FSMC interface clock */
mbed_official 185:e752b4ee7de1 529 RCC->AHB3ENR |= 0x00000001;
mbed_official 185:e752b4ee7de1 530
mbed_official 185:e752b4ee7de1 531 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 185:e752b4ee7de1 532 /* Configure and enable Bank1_SRAM2 */
mbed_official 185:e752b4ee7de1 533 FMC_Bank1->BTCR[2] = 0x00001011;
mbed_official 185:e752b4ee7de1 534 FMC_Bank1->BTCR[3] = 0x00000201;
mbed_official 185:e752b4ee7de1 535 FMC_Bank1E->BWTR[2] = 0x0fffffff;
mbed_official 185:e752b4ee7de1 536 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 185:e752b4ee7de1 537
mbed_official 185:e752b4ee7de1 538 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
mbed_official 185:e752b4ee7de1 539 /* Configure and enable Bank1_SRAM2 */
mbed_official 185:e752b4ee7de1 540 FSMC_Bank1->BTCR[2] = 0x00001011;
mbed_official 185:e752b4ee7de1 541 FSMC_Bank1->BTCR[3] = 0x00000201;
mbed_official 185:e752b4ee7de1 542 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
mbed_official 185:e752b4ee7de1 543 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
mbed_official 185:e752b4ee7de1 544
mbed_official 185:e752b4ee7de1 545 #endif /* DATA_IN_ExtSRAM */
mbed_official 185:e752b4ee7de1 546 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 185:e752b4ee7de1 547 }
mbed_official 185:e752b4ee7de1 548 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 185:e752b4ee7de1 549
mbed_official 185:e752b4ee7de1 550 /**
mbed_official 185:e752b4ee7de1 551 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 185:e752b4ee7de1 552 * AHB/APBx prescalers and Flash settings
mbed_official 185:e752b4ee7de1 553 * @note This function should be called only once the RCC clock configuration
mbed_official 185:e752b4ee7de1 554 * is reset to the default reset state (done in SystemInit() function).
mbed_official 185:e752b4ee7de1 555 * @param None
mbed_official 185:e752b4ee7de1 556 * @retval None
mbed_official 185:e752b4ee7de1 557 */
mbed_official 185:e752b4ee7de1 558 void SetSysClock(void)
mbed_official 185:e752b4ee7de1 559 {
mbed_official 185:e752b4ee7de1 560 /* 1- Try to start with HSE and external clock */
mbed_official 185:e752b4ee7de1 561 #if USE_PLL_HSE_EXTC != 0
mbed_official 185:e752b4ee7de1 562 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 185:e752b4ee7de1 563 #endif
mbed_official 185:e752b4ee7de1 564 {
mbed_official 185:e752b4ee7de1 565 /* 2- If fail try to start with HSE and external xtal */
mbed_official 185:e752b4ee7de1 566 #if USE_PLL_HSE_XTAL != 0
mbed_official 185:e752b4ee7de1 567 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 185:e752b4ee7de1 568 #endif
mbed_official 185:e752b4ee7de1 569 {
mbed_official 185:e752b4ee7de1 570 /* 3- If fail start with HSI clock */
mbed_official 185:e752b4ee7de1 571 if (SetSysClock_PLL_HSI() == 0)
mbed_official 185:e752b4ee7de1 572 {
mbed_official 185:e752b4ee7de1 573 while(1)
mbed_official 185:e752b4ee7de1 574 {
mbed_official 185:e752b4ee7de1 575 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 185:e752b4ee7de1 576 }
mbed_official 185:e752b4ee7de1 577 }
mbed_official 185:e752b4ee7de1 578 }
mbed_official 185:e752b4ee7de1 579 }
mbed_official 185:e752b4ee7de1 580
mbed_official 185:e752b4ee7de1 581 /* Output clock on MCO2 pin(PC9) for debugging purpose */
mbed_official 185:e752b4ee7de1 582 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_1); // 84 MHz
mbed_official 185:e752b4ee7de1 583 }
mbed_official 185:e752b4ee7de1 584
mbed_official 185:e752b4ee7de1 585 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 185:e752b4ee7de1 586 /******************************************************************************/
mbed_official 185:e752b4ee7de1 587 /* PLL (clocked by HSE) used as System clock source */
mbed_official 185:e752b4ee7de1 588 /******************************************************************************/
mbed_official 185:e752b4ee7de1 589 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 125:23cc3068a9e4 590 {
mbed_official 125:23cc3068a9e4 591 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 125:23cc3068a9e4 592 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 125:23cc3068a9e4 593
mbed_official 125:23cc3068a9e4 594 /* The voltage scaling allows optimizing the power consumption when the device is
mbed_official 125:23cc3068a9e4 595 clocked below the maximum system frequency, to update the voltage scaling value
mbed_official 125:23cc3068a9e4 596 regarding system frequency refer to product datasheet. */
mbed_official 125:23cc3068a9e4 597 __PWR_CLK_ENABLE();
mbed_official 125:23cc3068a9e4 598 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
mbed_official 125:23cc3068a9e4 599
mbed_official 185:e752b4ee7de1 600 /* Enable HSE oscillator and activate PLL with HSE as source */
mbed_official 185:e752b4ee7de1 601 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
mbed_official 185:e752b4ee7de1 602 if (bypass == 0)
mbed_official 185:e752b4ee7de1 603 {
mbed_official 185:e752b4ee7de1 604 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
mbed_official 185:e752b4ee7de1 605 }
mbed_official 185:e752b4ee7de1 606 else
mbed_official 185:e752b4ee7de1 607 {
mbed_official 185:e752b4ee7de1 608 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
mbed_official 185:e752b4ee7de1 609 }
mbed_official 125:23cc3068a9e4 610 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 185:e752b4ee7de1 611 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 185:e752b4ee7de1 612 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
mbed_official 185:e752b4ee7de1 613 RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
mbed_official 185:e752b4ee7de1 614 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
mbed_official 185:e752b4ee7de1 615 RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> OK for USB
mbed_official 125:23cc3068a9e4 616 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 125:23cc3068a9e4 617 {
mbed_official 185:e752b4ee7de1 618 return 0; // FAIL
mbed_official 125:23cc3068a9e4 619 }
mbed_official 125:23cc3068a9e4 620
mbed_official 125:23cc3068a9e4 621 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 125:23cc3068a9e4 622 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 185:e752b4ee7de1 623 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
mbed_official 185:e752b4ee7de1 624 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
mbed_official 185:e752b4ee7de1 625 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
mbed_official 185:e752b4ee7de1 626 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
mbed_official 125:23cc3068a9e4 627 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
mbed_official 125:23cc3068a9e4 628 {
mbed_official 185:e752b4ee7de1 629 return 0; // FAIL
mbed_official 125:23cc3068a9e4 630 }
mbed_official 125:23cc3068a9e4 631
mbed_official 185:e752b4ee7de1 632 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 185:e752b4ee7de1 633 /*
mbed_official 185:e752b4ee7de1 634 if (bypass == 0)
mbed_official 185:e752b4ee7de1 635 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
mbed_official 185:e752b4ee7de1 636 else
mbed_official 185:e752b4ee7de1 637 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
mbed_official 185:e752b4ee7de1 638 */
mbed_official 185:e752b4ee7de1 639
mbed_official 185:e752b4ee7de1 640 return 1; // OK
mbed_official 185:e752b4ee7de1 641 }
mbed_official 185:e752b4ee7de1 642 #endif
mbed_official 185:e752b4ee7de1 643
mbed_official 185:e752b4ee7de1 644 /******************************************************************************/
mbed_official 185:e752b4ee7de1 645 /* PLL (clocked by HSI) used as System clock source */
mbed_official 185:e752b4ee7de1 646 /******************************************************************************/
mbed_official 185:e752b4ee7de1 647 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 185:e752b4ee7de1 648 {
mbed_official 185:e752b4ee7de1 649 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 185:e752b4ee7de1 650 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 125:23cc3068a9e4 651
mbed_official 185:e752b4ee7de1 652 /* The voltage scaling allows optimizing the power consumption when the device is
mbed_official 185:e752b4ee7de1 653 clocked below the maximum system frequency, to update the voltage scaling value
mbed_official 185:e752b4ee7de1 654 regarding system frequency refer to product datasheet. */
mbed_official 185:e752b4ee7de1 655 __PWR_CLK_ENABLE();
mbed_official 185:e752b4ee7de1 656 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
mbed_official 185:e752b4ee7de1 657
mbed_official 185:e752b4ee7de1 658 /* Enable HSI oscillator and activate PLL with HSI as source */
mbed_official 185:e752b4ee7de1 659 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
mbed_official 185:e752b4ee7de1 660 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 185:e752b4ee7de1 661 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official 185:e752b4ee7de1 662 RCC_OscInitStruct.HSICalibrationValue = 16;
mbed_official 185:e752b4ee7de1 663 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 185:e752b4ee7de1 664 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
mbed_official 185:e752b4ee7de1 665 RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
mbed_official 185:e752b4ee7de1 666 RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
mbed_official 185:e752b4ee7de1 667 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
mbed_official 185:e752b4ee7de1 668 RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> freq is ok but not precise enough
mbed_official 185:e752b4ee7de1 669 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 185:e752b4ee7de1 670 {
mbed_official 185:e752b4ee7de1 671 return 0; // FAIL
mbed_official 185:e752b4ee7de1 672 }
mbed_official 185:e752b4ee7de1 673
mbed_official 185:e752b4ee7de1 674 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 185:e752b4ee7de1 675 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 185:e752b4ee7de1 676 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
mbed_official 185:e752b4ee7de1 677 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
mbed_official 185:e752b4ee7de1 678 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
mbed_official 185:e752b4ee7de1 679 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
mbed_official 185:e752b4ee7de1 680 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
mbed_official 185:e752b4ee7de1 681 {
mbed_official 185:e752b4ee7de1 682 return 0; // FAIL
mbed_official 185:e752b4ee7de1 683 }
mbed_official 185:e752b4ee7de1 684
mbed_official 185:e752b4ee7de1 685 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 185:e752b4ee7de1 686 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
mbed_official 185:e752b4ee7de1 687
mbed_official 185:e752b4ee7de1 688 return 1; // OK
mbed_official 125:23cc3068a9e4 689 }
mbed_official 125:23cc3068a9e4 690
mbed_official 87:085cde657901 691 /**
mbed_official 87:085cde657901 692 * @}
mbed_official 87:085cde657901 693 */
mbed_official 87:085cde657901 694
mbed_official 87:085cde657901 695 /**
mbed_official 87:085cde657901 696 * @}
mbed_official 87:085cde657901 697 */
mbed_official 87:085cde657901 698
mbed_official 87:085cde657901 699 /**
mbed_official 87:085cde657901 700 * @}
mbed_official 87:085cde657901 701 */
mbed_official 87:085cde657901 702 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/