shao ziyang / mbed-src-kl05

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Dependents:   frdm_kl05z_gpio_test

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targets/cmsis/TARGET_STM/TARGET_STM32F407VG/stm32f4xx_hal_sdram.c@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
296:ec1b66a3d094 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 133:d4dda5c437f0 1 /**
mbed_official 133:d4dda5c437f0 2 ******************************************************************************
mbed_official 133:d4dda5c437f0 3 * @file stm32f4xx_hal_sdram.c
mbed_official 133:d4dda5c437f0 4 * @author MCD Application Team
mbed_official 242:7074e42da0b2 5 * @version V1.1.0RC2
mbed_official 242:7074e42da0b2 6 * @date 14-May-2014
mbed_official 133:d4dda5c437f0 7 * @brief SDRAM HAL module driver.
mbed_official 133:d4dda5c437f0 8 * This file provides a generic firmware to drive SDRAM memories mounted
mbed_official 133:d4dda5c437f0 9 * as external device.
mbed_official 133:d4dda5c437f0 10 *
mbed_official 133:d4dda5c437f0 11 @verbatim
mbed_official 133:d4dda5c437f0 12 ==============================================================================
mbed_official 133:d4dda5c437f0 13 ##### How to use this driver #####
mbed_official 133:d4dda5c437f0 14 ==============================================================================
mbed_official 133:d4dda5c437f0 15 [..]
mbed_official 133:d4dda5c437f0 16 This driver is a generic layered driver which contains a set of APIs used to
mbed_official 133:d4dda5c437f0 17 control SDRAM memories. It uses the FMC layer functions to interface
mbed_official 133:d4dda5c437f0 18 with SDRAM devices.
mbed_official 133:d4dda5c437f0 19 The following sequence should be followed to configure the FMC to interface
mbed_official 133:d4dda5c437f0 20 with SDRAM memories:
mbed_official 133:d4dda5c437f0 21
mbed_official 133:d4dda5c437f0 22 (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
mbed_official 242:7074e42da0b2 23 SDRAM_HandleTypeDef hdsram
mbed_official 133:d4dda5c437f0 24
mbed_official 133:d4dda5c437f0 25 (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
mbed_official 133:d4dda5c437f0 26 values of the structure member.
mbed_official 133:d4dda5c437f0 27
mbed_official 133:d4dda5c437f0 28 (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
mbed_official 133:d4dda5c437f0 29 base register instance for NOR or SDRAM device
mbed_official 133:d4dda5c437f0 30
mbed_official 133:d4dda5c437f0 31 (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
mbed_official 133:d4dda5c437f0 32 FMC_SDRAM_TimingTypeDef Timing;
mbed_official 133:d4dda5c437f0 33 and fill its fields with the allowed values of the structure member.
mbed_official 133:d4dda5c437f0 34
mbed_official 133:d4dda5c437f0 35 (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
mbed_official 133:d4dda5c437f0 36 performs the following sequence:
mbed_official 133:d4dda5c437f0 37
mbed_official 133:d4dda5c437f0 38 (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
mbed_official 133:d4dda5c437f0 39 (##) Control register configuration using the FMC SDRAM interface function
mbed_official 133:d4dda5c437f0 40 FMC_SDRAM_Init()
mbed_official 133:d4dda5c437f0 41 (##) Timing register configuration using the FMC SDRAM interface function
mbed_official 133:d4dda5c437f0 42 FMC_SDRAM_Timing_Init()
mbed_official 133:d4dda5c437f0 43 (##) Program the SDRAM external device by applying its initialization sequence
mbed_official 133:d4dda5c437f0 44 according to the device plugged in your hardware. This step is mandatory
mbed_official 133:d4dda5c437f0 45 for accessing the SDRAM device.
mbed_official 133:d4dda5c437f0 46
mbed_official 133:d4dda5c437f0 47 (#) At this stage you can perform read/write accesses from/to the memory connected
mbed_official 133:d4dda5c437f0 48 to the SDRAM Bank. You can perform either polling or DMA transfer using the
mbed_official 133:d4dda5c437f0 49 following APIs:
mbed_official 133:d4dda5c437f0 50 (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
mbed_official 133:d4dda5c437f0 51 (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
mbed_official 133:d4dda5c437f0 52
mbed_official 133:d4dda5c437f0 53 (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
mbed_official 133:d4dda5c437f0 54 HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
mbed_official 133:d4dda5c437f0 55 the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
mbed_official 133:d4dda5c437f0 56 device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
mbed_official 133:d4dda5c437f0 57 structure.
mbed_official 133:d4dda5c437f0 58
mbed_official 133:d4dda5c437f0 59 (#) You can continuously monitor the SDRAM device HAL state by calling the function
mbed_official 133:d4dda5c437f0 60 HAL_SDRAM_GetState()
mbed_official 133:d4dda5c437f0 61
mbed_official 133:d4dda5c437f0 62 @endverbatim
mbed_official 133:d4dda5c437f0 63 ******************************************************************************
mbed_official 133:d4dda5c437f0 64 * @attention
mbed_official 133:d4dda5c437f0 65 *
mbed_official 133:d4dda5c437f0 66 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 133:d4dda5c437f0 67 *
mbed_official 133:d4dda5c437f0 68 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 133:d4dda5c437f0 69 * are permitted provided that the following conditions are met:
mbed_official 133:d4dda5c437f0 70 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 133:d4dda5c437f0 71 * this list of conditions and the following disclaimer.
mbed_official 133:d4dda5c437f0 72 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 133:d4dda5c437f0 73 * this list of conditions and the following disclaimer in the documentation
mbed_official 133:d4dda5c437f0 74 * and/or other materials provided with the distribution.
mbed_official 133:d4dda5c437f0 75 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 133:d4dda5c437f0 76 * may be used to endorse or promote products derived from this software
mbed_official 133:d4dda5c437f0 77 * without specific prior written permission.
mbed_official 133:d4dda5c437f0 78 *
mbed_official 133:d4dda5c437f0 79 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 133:d4dda5c437f0 80 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 133:d4dda5c437f0 81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 133:d4dda5c437f0 82 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 133:d4dda5c437f0 83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 133:d4dda5c437f0 84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 133:d4dda5c437f0 85 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 133:d4dda5c437f0 86 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 133:d4dda5c437f0 87 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 133:d4dda5c437f0 88 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 133:d4dda5c437f0 89 *
mbed_official 133:d4dda5c437f0 90 ******************************************************************************
mbed_official 133:d4dda5c437f0 91 */
mbed_official 133:d4dda5c437f0 92
mbed_official 133:d4dda5c437f0 93 /* Includes ------------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 94 #include "stm32f4xx_hal.h"
mbed_official 133:d4dda5c437f0 95
mbed_official 133:d4dda5c437f0 96 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 133:d4dda5c437f0 97 * @{
mbed_official 133:d4dda5c437f0 98 */
mbed_official 133:d4dda5c437f0 99
mbed_official 133:d4dda5c437f0 100 /** @defgroup SDRAM
mbed_official 133:d4dda5c437f0 101 * @brief SDRAM driver modules
mbed_official 133:d4dda5c437f0 102 * @{
mbed_official 133:d4dda5c437f0 103 */
mbed_official 133:d4dda5c437f0 104 #ifdef HAL_SDRAM_MODULE_ENABLED
mbed_official 133:d4dda5c437f0 105 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 133:d4dda5c437f0 106
mbed_official 133:d4dda5c437f0 107 /* Private typedef -----------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 108 /* Private define ------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 109 /* Private macro -------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 110 /* Private variables ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 111 /* Private function prototypes -----------------------------------------------*/
mbed_official 133:d4dda5c437f0 112
mbed_official 133:d4dda5c437f0 113 /* Private functions ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 114
mbed_official 133:d4dda5c437f0 115 /** @defgroup SDRAM_Private_Functions
mbed_official 133:d4dda5c437f0 116 * @{
mbed_official 133:d4dda5c437f0 117 */
mbed_official 133:d4dda5c437f0 118
mbed_official 133:d4dda5c437f0 119 /** @defgroup SDRAM_Group1 Initialization and de-initialization functions
mbed_official 133:d4dda5c437f0 120 * @brief Initialization and Configuration functions
mbed_official 133:d4dda5c437f0 121 *
mbed_official 133:d4dda5c437f0 122 @verbatim
mbed_official 133:d4dda5c437f0 123 ==============================================================================
mbed_official 133:d4dda5c437f0 124 ##### SDRAM Initialization and de_initialization functions #####
mbed_official 133:d4dda5c437f0 125 ==============================================================================
mbed_official 133:d4dda5c437f0 126 [..]
mbed_official 133:d4dda5c437f0 127 This section provides functions allowing to initialize/de-initialize
mbed_official 133:d4dda5c437f0 128 the SDRAM memory
mbed_official 133:d4dda5c437f0 129
mbed_official 133:d4dda5c437f0 130 @endverbatim
mbed_official 133:d4dda5c437f0 131 * @{
mbed_official 133:d4dda5c437f0 132 */
mbed_official 133:d4dda5c437f0 133
mbed_official 133:d4dda5c437f0 134 /**
mbed_official 133:d4dda5c437f0 135 * @brief Performs the SDRAM device initialization sequence.
mbed_official 242:7074e42da0b2 136 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 137 * the configuration information for SDRAM module.
mbed_official 133:d4dda5c437f0 138 * @param Timing: Pointer to SDRAM control timing structure
mbed_official 133:d4dda5c437f0 139 * @retval HAL status
mbed_official 133:d4dda5c437f0 140 */
mbed_official 133:d4dda5c437f0 141 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
mbed_official 133:d4dda5c437f0 142 {
mbed_official 133:d4dda5c437f0 143 /* Check the SDRAM handle parameter */
mbed_official 133:d4dda5c437f0 144 if(hsdram == NULL)
mbed_official 133:d4dda5c437f0 145 {
mbed_official 133:d4dda5c437f0 146 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 147 }
mbed_official 133:d4dda5c437f0 148
mbed_official 133:d4dda5c437f0 149 if(hsdram->State == HAL_SDRAM_STATE_RESET)
mbed_official 133:d4dda5c437f0 150 {
mbed_official 133:d4dda5c437f0 151 /* Initialize the low level hardware (MSP) */
mbed_official 133:d4dda5c437f0 152 HAL_SDRAM_MspInit(hsdram);
mbed_official 133:d4dda5c437f0 153 }
mbed_official 133:d4dda5c437f0 154
mbed_official 133:d4dda5c437f0 155 /* Initialize the SDRAM controller state */
mbed_official 133:d4dda5c437f0 156 hsdram->State = HAL_SDRAM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 157
mbed_official 133:d4dda5c437f0 158 /* Initialize SDRAM control Interface */
mbed_official 133:d4dda5c437f0 159 FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
mbed_official 133:d4dda5c437f0 160
mbed_official 133:d4dda5c437f0 161 /* Initialize SDRAM timing Interface */
mbed_official 133:d4dda5c437f0 162 FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
mbed_official 133:d4dda5c437f0 163
mbed_official 133:d4dda5c437f0 164 /* Update the SDRAM controller state */
mbed_official 133:d4dda5c437f0 165 hsdram->State = HAL_SDRAM_STATE_READY;
mbed_official 133:d4dda5c437f0 166
mbed_official 133:d4dda5c437f0 167 return HAL_OK;
mbed_official 133:d4dda5c437f0 168 }
mbed_official 133:d4dda5c437f0 169
mbed_official 133:d4dda5c437f0 170 /**
mbed_official 133:d4dda5c437f0 171 * @brief Perform the SDRAM device initialization sequence.
mbed_official 242:7074e42da0b2 172 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 173 * the configuration information for SDRAM module.
mbed_official 133:d4dda5c437f0 174 * @retval HAL status
mbed_official 133:d4dda5c437f0 175 */
mbed_official 133:d4dda5c437f0 176 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
mbed_official 133:d4dda5c437f0 177 {
mbed_official 133:d4dda5c437f0 178 /* Initialize the low level hardware (MSP) */
mbed_official 133:d4dda5c437f0 179 HAL_SDRAM_MspDeInit(hsdram);
mbed_official 133:d4dda5c437f0 180
mbed_official 133:d4dda5c437f0 181 /* Configure the SDRAM registers with their reset values */
mbed_official 133:d4dda5c437f0 182 FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
mbed_official 133:d4dda5c437f0 183
mbed_official 133:d4dda5c437f0 184 /* Reset the SDRAM controller state */
mbed_official 133:d4dda5c437f0 185 hsdram->State = HAL_SDRAM_STATE_RESET;
mbed_official 133:d4dda5c437f0 186
mbed_official 133:d4dda5c437f0 187 /* Release Lock */
mbed_official 133:d4dda5c437f0 188 __HAL_UNLOCK(hsdram);
mbed_official 133:d4dda5c437f0 189
mbed_official 133:d4dda5c437f0 190 return HAL_OK;
mbed_official 133:d4dda5c437f0 191 }
mbed_official 133:d4dda5c437f0 192
mbed_official 133:d4dda5c437f0 193 /**
mbed_official 133:d4dda5c437f0 194 * @brief SDRAM MSP Init.
mbed_official 242:7074e42da0b2 195 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 196 * the configuration information for SDRAM module.
mbed_official 133:d4dda5c437f0 197 * @retval None
mbed_official 133:d4dda5c437f0 198 */
mbed_official 133:d4dda5c437f0 199 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
mbed_official 133:d4dda5c437f0 200 {
mbed_official 133:d4dda5c437f0 201 /* NOTE: This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 202 the HAL_SDRAM_MspInit could be implemented in the user file
mbed_official 133:d4dda5c437f0 203 */
mbed_official 133:d4dda5c437f0 204 }
mbed_official 133:d4dda5c437f0 205
mbed_official 133:d4dda5c437f0 206 /**
mbed_official 133:d4dda5c437f0 207 * @brief SDRAM MSP DeInit.
mbed_official 242:7074e42da0b2 208 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 209 * the configuration information for SDRAM module.
mbed_official 133:d4dda5c437f0 210 * @retval None
mbed_official 133:d4dda5c437f0 211 */
mbed_official 133:d4dda5c437f0 212 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
mbed_official 133:d4dda5c437f0 213 {
mbed_official 133:d4dda5c437f0 214 /* NOTE: This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 215 the HAL_SDRAM_MspDeInit could be implemented in the user file
mbed_official 133:d4dda5c437f0 216 */
mbed_official 133:d4dda5c437f0 217 }
mbed_official 133:d4dda5c437f0 218
mbed_official 133:d4dda5c437f0 219 /**
mbed_official 133:d4dda5c437f0 220 * @brief This function handles SDRAM refresh error interrupt request.
mbed_official 242:7074e42da0b2 221 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 222 * the configuration information for SDRAM module.
mbed_official 133:d4dda5c437f0 223 * @retval HAL status
mbed_official 133:d4dda5c437f0 224 */
mbed_official 133:d4dda5c437f0 225 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
mbed_official 133:d4dda5c437f0 226 {
mbed_official 133:d4dda5c437f0 227 /* Check SDRAM interrupt Rising edge flag */
mbed_official 133:d4dda5c437f0 228 if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
mbed_official 133:d4dda5c437f0 229 {
mbed_official 133:d4dda5c437f0 230 /* SDRAM refresh error interrupt callback */
mbed_official 133:d4dda5c437f0 231 HAL_SDRAM_RefreshErrorCallback(hsdram);
mbed_official 133:d4dda5c437f0 232
mbed_official 133:d4dda5c437f0 233 /* Clear SDRAM refresh error interrupt pending bit */
mbed_official 133:d4dda5c437f0 234 __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
mbed_official 133:d4dda5c437f0 235 }
mbed_official 133:d4dda5c437f0 236 }
mbed_official 133:d4dda5c437f0 237
mbed_official 133:d4dda5c437f0 238 /**
mbed_official 133:d4dda5c437f0 239 * @brief SDRAM Refresh error callback.
mbed_official 242:7074e42da0b2 240 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 241 * the configuration information for SDRAM module.
mbed_official 133:d4dda5c437f0 242 * @retval None
mbed_official 133:d4dda5c437f0 243 */
mbed_official 133:d4dda5c437f0 244 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
mbed_official 133:d4dda5c437f0 245 {
mbed_official 133:d4dda5c437f0 246 /* NOTE: This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 247 the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
mbed_official 133:d4dda5c437f0 248 */
mbed_official 133:d4dda5c437f0 249 }
mbed_official 133:d4dda5c437f0 250
mbed_official 133:d4dda5c437f0 251 /**
mbed_official 133:d4dda5c437f0 252 * @brief DMA transfer complete callback.
mbed_official 242:7074e42da0b2 253 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 254 * the configuration information for the specified DMA module.
mbed_official 133:d4dda5c437f0 255 * @retval None
mbed_official 133:d4dda5c437f0 256 */
mbed_official 133:d4dda5c437f0 257 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 258 {
mbed_official 133:d4dda5c437f0 259 /* NOTE: This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 260 the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
mbed_official 133:d4dda5c437f0 261 */
mbed_official 133:d4dda5c437f0 262 }
mbed_official 133:d4dda5c437f0 263
mbed_official 133:d4dda5c437f0 264 /**
mbed_official 133:d4dda5c437f0 265 * @brief DMA transfer complete error callback.
mbed_official 133:d4dda5c437f0 266 * @param hdma: DMA handle
mbed_official 133:d4dda5c437f0 267 * @retval None
mbed_official 133:d4dda5c437f0 268 */
mbed_official 133:d4dda5c437f0 269 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 270 {
mbed_official 133:d4dda5c437f0 271 /* NOTE: This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 272 the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
mbed_official 133:d4dda5c437f0 273 */
mbed_official 133:d4dda5c437f0 274 }
mbed_official 133:d4dda5c437f0 275
mbed_official 133:d4dda5c437f0 276 /**
mbed_official 133:d4dda5c437f0 277 * @}
mbed_official 133:d4dda5c437f0 278 */
mbed_official 133:d4dda5c437f0 279
mbed_official 133:d4dda5c437f0 280 /** @defgroup SDRAM_Group2 Input and Output functions
mbed_official 133:d4dda5c437f0 281 * @brief Input Output and memory control functions
mbed_official 133:d4dda5c437f0 282 *
mbed_official 133:d4dda5c437f0 283 @verbatim
mbed_official 133:d4dda5c437f0 284 ==============================================================================
mbed_official 133:d4dda5c437f0 285 ##### SDRAM Input and Output functions #####
mbed_official 133:d4dda5c437f0 286 ==============================================================================
mbed_official 133:d4dda5c437f0 287 [..]
mbed_official 133:d4dda5c437f0 288 This section provides functions allowing to use and control the SDRAM memory
mbed_official 133:d4dda5c437f0 289
mbed_official 133:d4dda5c437f0 290 @endverbatim
mbed_official 133:d4dda5c437f0 291 * @{
mbed_official 133:d4dda5c437f0 292 */
mbed_official 133:d4dda5c437f0 293
mbed_official 133:d4dda5c437f0 294 /**
mbed_official 133:d4dda5c437f0 295 * @brief Reads 8-bit data buffer from the SDRAM memory.
mbed_official 242:7074e42da0b2 296 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 297 * the configuration information for SDRAM module.
mbed_official 133:d4dda5c437f0 298 * @param pAddress: Pointer to read start address
mbed_official 133:d4dda5c437f0 299 * @param pDstBuffer: Pointer to destination buffer
mbed_official 133:d4dda5c437f0 300 * @param BufferSize: Size of the buffer to read from memory
mbed_official 133:d4dda5c437f0 301 * @retval HAL status
mbed_official 133:d4dda5c437f0 302 */
mbed_official 133:d4dda5c437f0 303 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 304 {
mbed_official 133:d4dda5c437f0 305 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
mbed_official 133:d4dda5c437f0 306
mbed_official 133:d4dda5c437f0 307 /* Process Locked */
mbed_official 133:d4dda5c437f0 308 __HAL_LOCK(hsdram);
mbed_official 133:d4dda5c437f0 309
mbed_official 133:d4dda5c437f0 310 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 311 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 312 {
mbed_official 133:d4dda5c437f0 313 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 314 }
mbed_official 133:d4dda5c437f0 315 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
mbed_official 133:d4dda5c437f0 316 {
mbed_official 133:d4dda5c437f0 317 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 318 }
mbed_official 133:d4dda5c437f0 319
mbed_official 133:d4dda5c437f0 320 /* Read data from source */
mbed_official 133:d4dda5c437f0 321 for(; BufferSize != 0; BufferSize--)
mbed_official 133:d4dda5c437f0 322 {
mbed_official 133:d4dda5c437f0 323 *pDstBuffer = *(__IO uint8_t *)pSdramAddress;
mbed_official 133:d4dda5c437f0 324 pDstBuffer++;
mbed_official 133:d4dda5c437f0 325 pSdramAddress++;
mbed_official 133:d4dda5c437f0 326 }
mbed_official 133:d4dda5c437f0 327
mbed_official 133:d4dda5c437f0 328 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 329 __HAL_UNLOCK(hsdram);
mbed_official 133:d4dda5c437f0 330
mbed_official 133:d4dda5c437f0 331 return HAL_OK;
mbed_official 133:d4dda5c437f0 332 }
mbed_official 133:d4dda5c437f0 333
mbed_official 133:d4dda5c437f0 334
mbed_official 133:d4dda5c437f0 335 /**
mbed_official 133:d4dda5c437f0 336 * @brief Writes 8-bit data buffer to SDRAM memory.
mbed_official 242:7074e42da0b2 337 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 338 * the configuration information for SDRAM module.
mbed_official 133:d4dda5c437f0 339 * @param pAddress: Pointer to write start address
mbed_official 133:d4dda5c437f0 340 * @param pSrcBuffer: Pointer to source buffer to write
mbed_official 133:d4dda5c437f0 341 * @param BufferSize: Size of the buffer to write to memory
mbed_official 133:d4dda5c437f0 342 * @retval HAL status
mbed_official 133:d4dda5c437f0 343 */
mbed_official 133:d4dda5c437f0 344 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 345 {
mbed_official 133:d4dda5c437f0 346 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
mbed_official 133:d4dda5c437f0 347 uint32_t tmp = 0;
mbed_official 133:d4dda5c437f0 348
mbed_official 133:d4dda5c437f0 349 /* Process Locked */
mbed_official 133:d4dda5c437f0 350 __HAL_LOCK(hsdram);
mbed_official 133:d4dda5c437f0 351
mbed_official 133:d4dda5c437f0 352 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 353 tmp = hsdram->State;
mbed_official 133:d4dda5c437f0 354
mbed_official 133:d4dda5c437f0 355 if(tmp == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 356 {
mbed_official 133:d4dda5c437f0 357 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 358 }
mbed_official 133:d4dda5c437f0 359 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
mbed_official 133:d4dda5c437f0 360 {
mbed_official 133:d4dda5c437f0 361 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 362 }
mbed_official 133:d4dda5c437f0 363
mbed_official 133:d4dda5c437f0 364 /* Write data to memory */
mbed_official 133:d4dda5c437f0 365 for(; BufferSize != 0; BufferSize--)
mbed_official 133:d4dda5c437f0 366 {
mbed_official 133:d4dda5c437f0 367 *(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
mbed_official 133:d4dda5c437f0 368 pSrcBuffer++;
mbed_official 133:d4dda5c437f0 369 pSdramAddress++;
mbed_official 133:d4dda5c437f0 370 }
mbed_official 133:d4dda5c437f0 371
mbed_official 133:d4dda5c437f0 372 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 373 __HAL_UNLOCK(hsdram);
mbed_official 133:d4dda5c437f0 374
mbed_official 133:d4dda5c437f0 375 return HAL_OK;
mbed_official 133:d4dda5c437f0 376 }
mbed_official 133:d4dda5c437f0 377
mbed_official 133:d4dda5c437f0 378
mbed_official 133:d4dda5c437f0 379 /**
mbed_official 133:d4dda5c437f0 380 * @brief Reads 16-bit data buffer from the SDRAM memory.
mbed_official 242:7074e42da0b2 381 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 382 * the configuration information for SDRAM module.
mbed_official 133:d4dda5c437f0 383 * @param pAddress: Pointer to read start address
mbed_official 133:d4dda5c437f0 384 * @param pDstBuffer: Pointer to destination buffer
mbed_official 133:d4dda5c437f0 385 * @param BufferSize: Size of the buffer to read from memory
mbed_official 133:d4dda5c437f0 386 * @retval HAL status
mbed_official 133:d4dda5c437f0 387 */
mbed_official 133:d4dda5c437f0 388 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 389 {
mbed_official 133:d4dda5c437f0 390 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
mbed_official 133:d4dda5c437f0 391
mbed_official 133:d4dda5c437f0 392 /* Process Locked */
mbed_official 133:d4dda5c437f0 393 __HAL_LOCK(hsdram);
mbed_official 133:d4dda5c437f0 394
mbed_official 133:d4dda5c437f0 395 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 396 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 397 {
mbed_official 133:d4dda5c437f0 398 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 399 }
mbed_official 133:d4dda5c437f0 400 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
mbed_official 133:d4dda5c437f0 401 {
mbed_official 133:d4dda5c437f0 402 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 403 }
mbed_official 133:d4dda5c437f0 404
mbed_official 133:d4dda5c437f0 405 /* Read data from source */
mbed_official 133:d4dda5c437f0 406 for(; BufferSize != 0; BufferSize--)
mbed_official 133:d4dda5c437f0 407 {
mbed_official 133:d4dda5c437f0 408 *pDstBuffer = *(__IO uint16_t *)pSdramAddress;
mbed_official 133:d4dda5c437f0 409 pDstBuffer++;
mbed_official 133:d4dda5c437f0 410 pSdramAddress++;
mbed_official 133:d4dda5c437f0 411 }
mbed_official 133:d4dda5c437f0 412
mbed_official 133:d4dda5c437f0 413 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 414 __HAL_UNLOCK(hsdram);
mbed_official 133:d4dda5c437f0 415
mbed_official 133:d4dda5c437f0 416 return HAL_OK;
mbed_official 133:d4dda5c437f0 417 }
mbed_official 133:d4dda5c437f0 418
mbed_official 133:d4dda5c437f0 419 /**
mbed_official 133:d4dda5c437f0 420 * @brief Writes 16-bit data buffer to SDRAM memory.
mbed_official 242:7074e42da0b2 421 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 422 * the configuration information for SDRAM module.
mbed_official 133:d4dda5c437f0 423 * @param pAddress: Pointer to write start address
mbed_official 133:d4dda5c437f0 424 * @param pSrcBuffer: Pointer to source buffer to write
mbed_official 133:d4dda5c437f0 425 * @param BufferSize: Size of the buffer to write to memory
mbed_official 133:d4dda5c437f0 426 * @retval HAL status
mbed_official 133:d4dda5c437f0 427 */
mbed_official 133:d4dda5c437f0 428 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 429 {
mbed_official 133:d4dda5c437f0 430 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
mbed_official 133:d4dda5c437f0 431 uint32_t tmp = 0;
mbed_official 133:d4dda5c437f0 432
mbed_official 133:d4dda5c437f0 433 /* Process Locked */
mbed_official 133:d4dda5c437f0 434 __HAL_LOCK(hsdram);
mbed_official 133:d4dda5c437f0 435
mbed_official 133:d4dda5c437f0 436 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 437 tmp = hsdram->State;
mbed_official 133:d4dda5c437f0 438
mbed_official 133:d4dda5c437f0 439 if(tmp == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 440 {
mbed_official 133:d4dda5c437f0 441 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 442 }
mbed_official 133:d4dda5c437f0 443 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
mbed_official 133:d4dda5c437f0 444 {
mbed_official 133:d4dda5c437f0 445 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 446 }
mbed_official 133:d4dda5c437f0 447
mbed_official 133:d4dda5c437f0 448 /* Write data to memory */
mbed_official 133:d4dda5c437f0 449 for(; BufferSize != 0; BufferSize--)
mbed_official 133:d4dda5c437f0 450 {
mbed_official 133:d4dda5c437f0 451 *(__IO uint16_t *)pSdramAddress = *pSrcBuffer;
mbed_official 133:d4dda5c437f0 452 pSrcBuffer++;
mbed_official 133:d4dda5c437f0 453 pSdramAddress++;
mbed_official 133:d4dda5c437f0 454 }
mbed_official 133:d4dda5c437f0 455
mbed_official 133:d4dda5c437f0 456 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 457 __HAL_UNLOCK(hsdram);
mbed_official 133:d4dda5c437f0 458
mbed_official 133:d4dda5c437f0 459 return HAL_OK;
mbed_official 133:d4dda5c437f0 460 }
mbed_official 133:d4dda5c437f0 461
mbed_official 133:d4dda5c437f0 462 /**
mbed_official 133:d4dda5c437f0 463 * @brief Reads 32-bit data buffer from the SDRAM memory.
mbed_official 242:7074e42da0b2 464 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 465 * the configuration information for SDRAM module.
mbed_official 133:d4dda5c437f0 466 * @param pAddress: Pointer to read start address
mbed_official 133:d4dda5c437f0 467 * @param pDstBuffer: Pointer to destination buffer
mbed_official 133:d4dda5c437f0 468 * @param BufferSize: Size of the buffer to read from memory
mbed_official 133:d4dda5c437f0 469 * @retval HAL status
mbed_official 133:d4dda5c437f0 470 */
mbed_official 133:d4dda5c437f0 471 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 472 {
mbed_official 133:d4dda5c437f0 473 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
mbed_official 133:d4dda5c437f0 474
mbed_official 133:d4dda5c437f0 475 /* Process Locked */
mbed_official 133:d4dda5c437f0 476 __HAL_LOCK(hsdram);
mbed_official 133:d4dda5c437f0 477
mbed_official 133:d4dda5c437f0 478 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 479 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 480 {
mbed_official 133:d4dda5c437f0 481 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 482 }
mbed_official 133:d4dda5c437f0 483 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
mbed_official 133:d4dda5c437f0 484 {
mbed_official 133:d4dda5c437f0 485 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 486 }
mbed_official 133:d4dda5c437f0 487
mbed_official 133:d4dda5c437f0 488 /* Read data from source */
mbed_official 133:d4dda5c437f0 489 for(; BufferSize != 0; BufferSize--)
mbed_official 133:d4dda5c437f0 490 {
mbed_official 133:d4dda5c437f0 491 *pDstBuffer = *(__IO uint32_t *)pSdramAddress;
mbed_official 133:d4dda5c437f0 492 pDstBuffer++;
mbed_official 133:d4dda5c437f0 493 pSdramAddress++;
mbed_official 133:d4dda5c437f0 494 }
mbed_official 133:d4dda5c437f0 495
mbed_official 133:d4dda5c437f0 496 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 497 __HAL_UNLOCK(hsdram);
mbed_official 133:d4dda5c437f0 498
mbed_official 133:d4dda5c437f0 499 return HAL_OK;
mbed_official 133:d4dda5c437f0 500 }
mbed_official 133:d4dda5c437f0 501
mbed_official 133:d4dda5c437f0 502 /**
mbed_official 133:d4dda5c437f0 503 * @brief Writes 32-bit data buffer to SDRAM memory.
mbed_official 242:7074e42da0b2 504 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 505 * the configuration information for SDRAM module.
mbed_official 133:d4dda5c437f0 506 * @param pAddress: Pointer to write start address
mbed_official 133:d4dda5c437f0 507 * @param pSrcBuffer: Pointer to source buffer to write
mbed_official 133:d4dda5c437f0 508 * @param BufferSize: Size of the buffer to write to memory
mbed_official 133:d4dda5c437f0 509 * @retval HAL status
mbed_official 133:d4dda5c437f0 510 */
mbed_official 133:d4dda5c437f0 511 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 512 {
mbed_official 133:d4dda5c437f0 513 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
mbed_official 133:d4dda5c437f0 514 uint32_t tmp = 0;
mbed_official 133:d4dda5c437f0 515
mbed_official 133:d4dda5c437f0 516 /* Process Locked */
mbed_official 133:d4dda5c437f0 517 __HAL_LOCK(hsdram);
mbed_official 133:d4dda5c437f0 518
mbed_official 133:d4dda5c437f0 519 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 520 tmp = hsdram->State;
mbed_official 133:d4dda5c437f0 521
mbed_official 133:d4dda5c437f0 522 if(tmp == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 523 {
mbed_official 133:d4dda5c437f0 524 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 525 }
mbed_official 133:d4dda5c437f0 526 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
mbed_official 133:d4dda5c437f0 527 {
mbed_official 133:d4dda5c437f0 528 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 529 }
mbed_official 133:d4dda5c437f0 530
mbed_official 133:d4dda5c437f0 531 /* Write data to memory */
mbed_official 133:d4dda5c437f0 532 for(; BufferSize != 0; BufferSize--)
mbed_official 133:d4dda5c437f0 533 {
mbed_official 133:d4dda5c437f0 534 *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
mbed_official 133:d4dda5c437f0 535 pSrcBuffer++;
mbed_official 133:d4dda5c437f0 536 pSdramAddress++;
mbed_official 133:d4dda5c437f0 537 }
mbed_official 133:d4dda5c437f0 538
mbed_official 133:d4dda5c437f0 539 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 540 __HAL_UNLOCK(hsdram);
mbed_official 133:d4dda5c437f0 541
mbed_official 133:d4dda5c437f0 542 return HAL_OK;
mbed_official 133:d4dda5c437f0 543 }
mbed_official 133:d4dda5c437f0 544
mbed_official 133:d4dda5c437f0 545 /**
mbed_official 133:d4dda5c437f0 546 * @brief Reads a Words data from the SDRAM memory using DMA transfer.
mbed_official 242:7074e42da0b2 547 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 548 * the configuration information for SDRAM module.
mbed_official 133:d4dda5c437f0 549 * @param pAddress: Pointer to read start address
mbed_official 133:d4dda5c437f0 550 * @param pDstBuffer: Pointer to destination buffer
mbed_official 133:d4dda5c437f0 551 * @param BufferSize: Size of the buffer to read from memory
mbed_official 133:d4dda5c437f0 552 * @retval HAL status
mbed_official 133:d4dda5c437f0 553 */
mbed_official 133:d4dda5c437f0 554 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 555 {
mbed_official 133:d4dda5c437f0 556 uint32_t tmp = 0;
mbed_official 133:d4dda5c437f0 557
mbed_official 133:d4dda5c437f0 558 /* Process Locked */
mbed_official 133:d4dda5c437f0 559 __HAL_LOCK(hsdram);
mbed_official 133:d4dda5c437f0 560
mbed_official 133:d4dda5c437f0 561 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 562 tmp = hsdram->State;
mbed_official 133:d4dda5c437f0 563
mbed_official 133:d4dda5c437f0 564 if(tmp == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 565 {
mbed_official 133:d4dda5c437f0 566 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 567 }
mbed_official 133:d4dda5c437f0 568 else if(tmp == HAL_SDRAM_STATE_PRECHARGED)
mbed_official 133:d4dda5c437f0 569 {
mbed_official 133:d4dda5c437f0 570 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 571 }
mbed_official 133:d4dda5c437f0 572
mbed_official 133:d4dda5c437f0 573 /* Configure DMA user callbacks */
mbed_official 133:d4dda5c437f0 574 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
mbed_official 133:d4dda5c437f0 575 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
mbed_official 133:d4dda5c437f0 576
mbed_official 133:d4dda5c437f0 577 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 578 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
mbed_official 133:d4dda5c437f0 579
mbed_official 133:d4dda5c437f0 580 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 581 __HAL_UNLOCK(hsdram);
mbed_official 133:d4dda5c437f0 582
mbed_official 133:d4dda5c437f0 583 return HAL_OK;
mbed_official 133:d4dda5c437f0 584 }
mbed_official 133:d4dda5c437f0 585
mbed_official 133:d4dda5c437f0 586 /**
mbed_official 133:d4dda5c437f0 587 * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
mbed_official 242:7074e42da0b2 588 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 589 * the configuration information for SDRAM module.
mbed_official 133:d4dda5c437f0 590 * @param pAddress: Pointer to write start address
mbed_official 133:d4dda5c437f0 591 * @param pSrcBuffer: Pointer to source buffer to write
mbed_official 133:d4dda5c437f0 592 * @param BufferSize: Size of the buffer to write to memory
mbed_official 133:d4dda5c437f0 593 * @retval HAL status
mbed_official 133:d4dda5c437f0 594 */
mbed_official 133:d4dda5c437f0 595 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 596 {
mbed_official 133:d4dda5c437f0 597 uint32_t tmp = 0;
mbed_official 133:d4dda5c437f0 598
mbed_official 133:d4dda5c437f0 599 /* Process Locked */
mbed_official 133:d4dda5c437f0 600 __HAL_LOCK(hsdram);
mbed_official 133:d4dda5c437f0 601
mbed_official 133:d4dda5c437f0 602 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 603 tmp = hsdram->State;
mbed_official 133:d4dda5c437f0 604
mbed_official 133:d4dda5c437f0 605 if(tmp == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 606 {
mbed_official 133:d4dda5c437f0 607 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 608 }
mbed_official 133:d4dda5c437f0 609 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
mbed_official 133:d4dda5c437f0 610 {
mbed_official 133:d4dda5c437f0 611 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 612 }
mbed_official 133:d4dda5c437f0 613
mbed_official 133:d4dda5c437f0 614 /* Configure DMA user callbacks */
mbed_official 133:d4dda5c437f0 615 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
mbed_official 133:d4dda5c437f0 616 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
mbed_official 133:d4dda5c437f0 617
mbed_official 133:d4dda5c437f0 618 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 619 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
mbed_official 133:d4dda5c437f0 620
mbed_official 133:d4dda5c437f0 621 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 622 __HAL_UNLOCK(hsdram);
mbed_official 133:d4dda5c437f0 623
mbed_official 133:d4dda5c437f0 624 return HAL_OK;
mbed_official 133:d4dda5c437f0 625 }
mbed_official 133:d4dda5c437f0 626
mbed_official 133:d4dda5c437f0 627 /**
mbed_official 133:d4dda5c437f0 628 * @}
mbed_official 133:d4dda5c437f0 629 */
mbed_official 133:d4dda5c437f0 630
mbed_official 133:d4dda5c437f0 631 /** @defgroup SDRAM_Group3 Control functions
mbed_official 133:d4dda5c437f0 632 * @brief management functions
mbed_official 133:d4dda5c437f0 633 *
mbed_official 133:d4dda5c437f0 634 @verbatim
mbed_official 133:d4dda5c437f0 635 ==============================================================================
mbed_official 133:d4dda5c437f0 636 ##### SDRAM Control functions #####
mbed_official 133:d4dda5c437f0 637 ==============================================================================
mbed_official 133:d4dda5c437f0 638 [..]
mbed_official 133:d4dda5c437f0 639 This subsection provides a set of functions allowing to control dynamically
mbed_official 133:d4dda5c437f0 640 the SDRAM interface.
mbed_official 133:d4dda5c437f0 641
mbed_official 133:d4dda5c437f0 642 @endverbatim
mbed_official 133:d4dda5c437f0 643 * @{
mbed_official 133:d4dda5c437f0 644 */
mbed_official 133:d4dda5c437f0 645
mbed_official 133:d4dda5c437f0 646 /**
mbed_official 133:d4dda5c437f0 647 * @brief Enables dynamically SDRAM write protection.
mbed_official 242:7074e42da0b2 648 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 649 * the configuration information for SDRAM module.
mbed_official 133:d4dda5c437f0 650 * @retval HAL status
mbed_official 133:d4dda5c437f0 651 */
mbed_official 133:d4dda5c437f0 652 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
mbed_official 133:d4dda5c437f0 653 {
mbed_official 133:d4dda5c437f0 654 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 655 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 656 {
mbed_official 133:d4dda5c437f0 657 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 658 }
mbed_official 133:d4dda5c437f0 659
mbed_official 133:d4dda5c437f0 660 /* Update the SDRAM state */
mbed_official 133:d4dda5c437f0 661 hsdram->State = HAL_SDRAM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 662
mbed_official 133:d4dda5c437f0 663 /* Enable write protection */
mbed_official 133:d4dda5c437f0 664 FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
mbed_official 133:d4dda5c437f0 665
mbed_official 133:d4dda5c437f0 666 /* Update the SDRAM state */
mbed_official 133:d4dda5c437f0 667 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
mbed_official 133:d4dda5c437f0 668
mbed_official 133:d4dda5c437f0 669 return HAL_OK;
mbed_official 133:d4dda5c437f0 670 }
mbed_official 133:d4dda5c437f0 671
mbed_official 133:d4dda5c437f0 672 /**
mbed_official 133:d4dda5c437f0 673 * @brief Disables dynamically SDRAM write protection.
mbed_official 242:7074e42da0b2 674 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 675 * the configuration information for SDRAM module.
mbed_official 133:d4dda5c437f0 676 * @retval HAL status
mbed_official 133:d4dda5c437f0 677 */
mbed_official 133:d4dda5c437f0 678 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
mbed_official 133:d4dda5c437f0 679 {
mbed_official 133:d4dda5c437f0 680 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 681 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 682 {
mbed_official 133:d4dda5c437f0 683 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 684 }
mbed_official 133:d4dda5c437f0 685
mbed_official 133:d4dda5c437f0 686 /* Update the SDRAM state */
mbed_official 133:d4dda5c437f0 687 hsdram->State = HAL_SDRAM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 688
mbed_official 133:d4dda5c437f0 689 /* Disable write protection */
mbed_official 133:d4dda5c437f0 690 FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
mbed_official 133:d4dda5c437f0 691
mbed_official 133:d4dda5c437f0 692 /* Update the SDRAM state */
mbed_official 133:d4dda5c437f0 693 hsdram->State = HAL_SDRAM_STATE_READY;
mbed_official 133:d4dda5c437f0 694
mbed_official 133:d4dda5c437f0 695 return HAL_OK;
mbed_official 133:d4dda5c437f0 696 }
mbed_official 133:d4dda5c437f0 697
mbed_official 133:d4dda5c437f0 698 /**
mbed_official 133:d4dda5c437f0 699 * @brief Sends Command to the SDRAM bank.
mbed_official 242:7074e42da0b2 700 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 701 * the configuration information for SDRAM module.
mbed_official 133:d4dda5c437f0 702 * @param Command: SDRAM command structure
mbed_official 133:d4dda5c437f0 703 * @param Timeout: Timeout duration
mbed_official 242:7074e42da0b2 704 * @retval HAL status
mbed_official 133:d4dda5c437f0 705 */
mbed_official 133:d4dda5c437f0 706 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
mbed_official 133:d4dda5c437f0 707 {
mbed_official 133:d4dda5c437f0 708 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 709 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 710 {
mbed_official 133:d4dda5c437f0 711 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 712 }
mbed_official 133:d4dda5c437f0 713
mbed_official 133:d4dda5c437f0 714 /* Update the SDRAM state */
mbed_official 133:d4dda5c437f0 715 hsdram->State = HAL_SDRAM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 716
mbed_official 133:d4dda5c437f0 717 /* Send SDRAM command */
mbed_official 133:d4dda5c437f0 718 FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
mbed_official 133:d4dda5c437f0 719
mbed_official 133:d4dda5c437f0 720 /* Update the SDRAM controller state state */
mbed_official 133:d4dda5c437f0 721 if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
mbed_official 133:d4dda5c437f0 722 {
mbed_official 133:d4dda5c437f0 723 hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
mbed_official 133:d4dda5c437f0 724 }
mbed_official 133:d4dda5c437f0 725 else
mbed_official 133:d4dda5c437f0 726 {
mbed_official 133:d4dda5c437f0 727 hsdram->State = HAL_SDRAM_STATE_READY;
mbed_official 133:d4dda5c437f0 728 }
mbed_official 133:d4dda5c437f0 729
mbed_official 133:d4dda5c437f0 730 return HAL_OK;
mbed_official 133:d4dda5c437f0 731 }
mbed_official 133:d4dda5c437f0 732
mbed_official 133:d4dda5c437f0 733 /**
mbed_official 133:d4dda5c437f0 734 * @brief Programs the SDRAM Memory Refresh rate.
mbed_official 242:7074e42da0b2 735 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 736 * the configuration information for SDRAM module.
mbed_official 133:d4dda5c437f0 737 * @param RefreshRate: The SDRAM refresh rate value
mbed_official 242:7074e42da0b2 738 * @retval HAL status
mbed_official 133:d4dda5c437f0 739 */
mbed_official 133:d4dda5c437f0 740 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
mbed_official 133:d4dda5c437f0 741 {
mbed_official 133:d4dda5c437f0 742 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 743 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 744 {
mbed_official 133:d4dda5c437f0 745 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 746 }
mbed_official 133:d4dda5c437f0 747
mbed_official 133:d4dda5c437f0 748 /* Update the SDRAM state */
mbed_official 133:d4dda5c437f0 749 hsdram->State = HAL_SDRAM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 750
mbed_official 133:d4dda5c437f0 751 /* Program the refresh rate */
mbed_official 133:d4dda5c437f0 752 FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
mbed_official 133:d4dda5c437f0 753
mbed_official 133:d4dda5c437f0 754 /* Update the SDRAM state */
mbed_official 133:d4dda5c437f0 755 hsdram->State = HAL_SDRAM_STATE_READY;
mbed_official 133:d4dda5c437f0 756
mbed_official 133:d4dda5c437f0 757 return HAL_OK;
mbed_official 133:d4dda5c437f0 758 }
mbed_official 133:d4dda5c437f0 759
mbed_official 133:d4dda5c437f0 760 /**
mbed_official 133:d4dda5c437f0 761 * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
mbed_official 242:7074e42da0b2 762 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 763 * the configuration information for SDRAM module.
mbed_official 133:d4dda5c437f0 764 * @param AutoRefreshNumber: The SDRAM auto Refresh number
mbed_official 242:7074e42da0b2 765 * @retval HAL status
mbed_official 133:d4dda5c437f0 766 */
mbed_official 133:d4dda5c437f0 767 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
mbed_official 133:d4dda5c437f0 768 {
mbed_official 133:d4dda5c437f0 769 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 770 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 771 {
mbed_official 133:d4dda5c437f0 772 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 773 }
mbed_official 133:d4dda5c437f0 774
mbed_official 133:d4dda5c437f0 775 /* Update the SDRAM state */
mbed_official 133:d4dda5c437f0 776 hsdram->State = HAL_SDRAM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 777
mbed_official 133:d4dda5c437f0 778 /* Set the Auto-Refresh number */
mbed_official 133:d4dda5c437f0 779 FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);
mbed_official 133:d4dda5c437f0 780
mbed_official 133:d4dda5c437f0 781 /* Update the SDRAM state */
mbed_official 133:d4dda5c437f0 782 hsdram->State = HAL_SDRAM_STATE_READY;
mbed_official 133:d4dda5c437f0 783
mbed_official 133:d4dda5c437f0 784 return HAL_OK;
mbed_official 133:d4dda5c437f0 785 }
mbed_official 133:d4dda5c437f0 786
mbed_official 133:d4dda5c437f0 787 /**
mbed_official 133:d4dda5c437f0 788 * @brief Returns the SDRAM memory current mode.
mbed_official 242:7074e42da0b2 789 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 790 * the configuration information for SDRAM module.
mbed_official 133:d4dda5c437f0 791 * @retval The SDRAM memory mode.
mbed_official 133:d4dda5c437f0 792 */
mbed_official 133:d4dda5c437f0 793 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
mbed_official 133:d4dda5c437f0 794 {
mbed_official 133:d4dda5c437f0 795 /* Return the SDRAM memory current mode */
mbed_official 133:d4dda5c437f0 796 return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
mbed_official 133:d4dda5c437f0 797 }
mbed_official 133:d4dda5c437f0 798
mbed_official 133:d4dda5c437f0 799 /**
mbed_official 133:d4dda5c437f0 800 * @}
mbed_official 133:d4dda5c437f0 801 */
mbed_official 133:d4dda5c437f0 802
mbed_official 133:d4dda5c437f0 803 /** @defgroup SDRAM_Group4 State functions
mbed_official 133:d4dda5c437f0 804 * @brief Peripheral State functions
mbed_official 133:d4dda5c437f0 805 *
mbed_official 133:d4dda5c437f0 806 @verbatim
mbed_official 133:d4dda5c437f0 807 ==============================================================================
mbed_official 133:d4dda5c437f0 808 ##### SDRAM State functions #####
mbed_official 133:d4dda5c437f0 809 ==============================================================================
mbed_official 133:d4dda5c437f0 810 [..]
mbed_official 133:d4dda5c437f0 811 This subsection permits to get in run-time the status of the SDRAM controller
mbed_official 133:d4dda5c437f0 812 and the data flow.
mbed_official 133:d4dda5c437f0 813
mbed_official 133:d4dda5c437f0 814 @endverbatim
mbed_official 133:d4dda5c437f0 815 * @{
mbed_official 133:d4dda5c437f0 816 */
mbed_official 133:d4dda5c437f0 817
mbed_official 133:d4dda5c437f0 818 /**
mbed_official 133:d4dda5c437f0 819 * @brief Returns the SDRAM state.
mbed_official 242:7074e42da0b2 820 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 821 * the configuration information for SDRAM module.
mbed_official 133:d4dda5c437f0 822 * @retval HAL state
mbed_official 133:d4dda5c437f0 823 */
mbed_official 133:d4dda5c437f0 824 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
mbed_official 133:d4dda5c437f0 825 {
mbed_official 133:d4dda5c437f0 826 return hsdram->State;
mbed_official 133:d4dda5c437f0 827 }
mbed_official 133:d4dda5c437f0 828
mbed_official 133:d4dda5c437f0 829 /**
mbed_official 133:d4dda5c437f0 830 * @}
mbed_official 133:d4dda5c437f0 831 */
mbed_official 133:d4dda5c437f0 832
mbed_official 133:d4dda5c437f0 833 /**
mbed_official 133:d4dda5c437f0 834 * @}
mbed_official 133:d4dda5c437f0 835 */
mbed_official 133:d4dda5c437f0 836 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 133:d4dda5c437f0 837 #endif /* HAL_SDRAM_MODULE_ENABLED */
mbed_official 133:d4dda5c437f0 838 /**
mbed_official 133:d4dda5c437f0 839 * @}
mbed_official 133:d4dda5c437f0 840 */
mbed_official 133:d4dda5c437f0 841
mbed_official 133:d4dda5c437f0 842 /**
mbed_official 133:d4dda5c437f0 843 * @}
mbed_official 133:d4dda5c437f0 844 */
mbed_official 133:d4dda5c437f0 845
mbed_official 133:d4dda5c437f0 846 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/