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targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_sdram.c@133:d4dda5c437f0, 2014-03-24 (annotated)

Committer:
mbed_official
Date:
Mon Mar 24 17:45:07 2014 +0000
Revision:
133:d4dda5c437f0
Child:
242:7074e42da0b2
Synchronized with git revision 47b961246bed973fe4cb8932781ffc8025b78a61



Full URL: https://github.com/mbedmicro/mbed/commit/47b961246bed973fe4cb8932781ffc8025b78a61/



[STM32F4-Discovery (STM32F407VG)] initial port

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 133:d4dda5c437f0 1 /**
mbed_official 133:d4dda5c437f0 2 ******************************************************************************
mbed_official 133:d4dda5c437f0 3 * @file stm32f4xx_hal_sdram.c
mbed_official 133:d4dda5c437f0 4 * @author MCD Application Team
mbed_official 133:d4dda5c437f0 5 * @version V1.0.0
mbed_official 133:d4dda5c437f0 6 * @date 18-February-2014
mbed_official 133:d4dda5c437f0 7 * @brief SDRAM HAL module driver.
mbed_official 133:d4dda5c437f0 8 * This file provides a generic firmware to drive SDRAM memories mounted
mbed_official 133:d4dda5c437f0 9 * as external device.
mbed_official 133:d4dda5c437f0 10 *
mbed_official 133:d4dda5c437f0 11 @verbatim
mbed_official 133:d4dda5c437f0 12 ==============================================================================
mbed_official 133:d4dda5c437f0 13 ##### How to use this driver #####
mbed_official 133:d4dda5c437f0 14 ==============================================================================
mbed_official 133:d4dda5c437f0 15 [..]
mbed_official 133:d4dda5c437f0 16 This driver is a generic layered driver which contains a set of APIs used to
mbed_official 133:d4dda5c437f0 17 control SDRAM memories. It uses the FMC layer functions to interface
mbed_official 133:d4dda5c437f0 18 with SDRAM devices.
mbed_official 133:d4dda5c437f0 19 The following sequence should be followed to configure the FMC to interface
mbed_official 133:d4dda5c437f0 20 with SDRAM memories:
mbed_official 133:d4dda5c437f0 21
mbed_official 133:d4dda5c437f0 22 (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
mbed_official 133:d4dda5c437f0 23 SDRAM_HandleTypeDef hdsram; and:
mbed_official 133:d4dda5c437f0 24
mbed_official 133:d4dda5c437f0 25 (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
mbed_official 133:d4dda5c437f0 26 values of the structure member.
mbed_official 133:d4dda5c437f0 27
mbed_official 133:d4dda5c437f0 28 (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
mbed_official 133:d4dda5c437f0 29 base register instance for NOR or SDRAM device
mbed_official 133:d4dda5c437f0 30
mbed_official 133:d4dda5c437f0 31 (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
mbed_official 133:d4dda5c437f0 32 FMC_SDRAM_TimingTypeDef Timing;
mbed_official 133:d4dda5c437f0 33 and fill its fields with the allowed values of the structure member.
mbed_official 133:d4dda5c437f0 34
mbed_official 133:d4dda5c437f0 35 (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
mbed_official 133:d4dda5c437f0 36 performs the following sequence:
mbed_official 133:d4dda5c437f0 37
mbed_official 133:d4dda5c437f0 38 (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
mbed_official 133:d4dda5c437f0 39 (##) Control register configuration using the FMC SDRAM interface function
mbed_official 133:d4dda5c437f0 40 FMC_SDRAM_Init()
mbed_official 133:d4dda5c437f0 41 (##) Timing register configuration using the FMC SDRAM interface function
mbed_official 133:d4dda5c437f0 42 FMC_SDRAM_Timing_Init()
mbed_official 133:d4dda5c437f0 43 (##) Program the SDRAM external device by applying its initialization sequence
mbed_official 133:d4dda5c437f0 44 according to the device plugged in your hardware. This step is mandatory
mbed_official 133:d4dda5c437f0 45 for accessing the SDRAM device.
mbed_official 133:d4dda5c437f0 46
mbed_official 133:d4dda5c437f0 47 (#) At this stage you can perform read/write accesses from/to the memory connected
mbed_official 133:d4dda5c437f0 48 to the SDRAM Bank. You can perform either polling or DMA transfer using the
mbed_official 133:d4dda5c437f0 49 following APIs:
mbed_official 133:d4dda5c437f0 50 (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
mbed_official 133:d4dda5c437f0 51 (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
mbed_official 133:d4dda5c437f0 52
mbed_official 133:d4dda5c437f0 53 (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
mbed_official 133:d4dda5c437f0 54 HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
mbed_official 133:d4dda5c437f0 55 the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
mbed_official 133:d4dda5c437f0 56 device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
mbed_official 133:d4dda5c437f0 57 structure.
mbed_official 133:d4dda5c437f0 58
mbed_official 133:d4dda5c437f0 59 (#) You can continuously monitor the SDRAM device HAL state by calling the function
mbed_official 133:d4dda5c437f0 60 HAL_SDRAM_GetState()
mbed_official 133:d4dda5c437f0 61
mbed_official 133:d4dda5c437f0 62 @endverbatim
mbed_official 133:d4dda5c437f0 63 ******************************************************************************
mbed_official 133:d4dda5c437f0 64 * @attention
mbed_official 133:d4dda5c437f0 65 *
mbed_official 133:d4dda5c437f0 66 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 133:d4dda5c437f0 67 *
mbed_official 133:d4dda5c437f0 68 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 133:d4dda5c437f0 69 * are permitted provided that the following conditions are met:
mbed_official 133:d4dda5c437f0 70 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 133:d4dda5c437f0 71 * this list of conditions and the following disclaimer.
mbed_official 133:d4dda5c437f0 72 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 133:d4dda5c437f0 73 * this list of conditions and the following disclaimer in the documentation
mbed_official 133:d4dda5c437f0 74 * and/or other materials provided with the distribution.
mbed_official 133:d4dda5c437f0 75 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 133:d4dda5c437f0 76 * may be used to endorse or promote products derived from this software
mbed_official 133:d4dda5c437f0 77 * without specific prior written permission.
mbed_official 133:d4dda5c437f0 78 *
mbed_official 133:d4dda5c437f0 79 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 133:d4dda5c437f0 80 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 133:d4dda5c437f0 81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 133:d4dda5c437f0 82 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 133:d4dda5c437f0 83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 133:d4dda5c437f0 84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 133:d4dda5c437f0 85 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 133:d4dda5c437f0 86 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 133:d4dda5c437f0 87 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 133:d4dda5c437f0 88 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 133:d4dda5c437f0 89 *
mbed_official 133:d4dda5c437f0 90 ******************************************************************************
mbed_official 133:d4dda5c437f0 91 */
mbed_official 133:d4dda5c437f0 92
mbed_official 133:d4dda5c437f0 93 /* Includes ------------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 94 #include "stm32f4xx_hal.h"
mbed_official 133:d4dda5c437f0 95
mbed_official 133:d4dda5c437f0 96 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 133:d4dda5c437f0 97 * @{
mbed_official 133:d4dda5c437f0 98 */
mbed_official 133:d4dda5c437f0 99
mbed_official 133:d4dda5c437f0 100 /** @defgroup SDRAM
mbed_official 133:d4dda5c437f0 101 * @brief SDRAM driver modules
mbed_official 133:d4dda5c437f0 102 * @{
mbed_official 133:d4dda5c437f0 103 */
mbed_official 133:d4dda5c437f0 104 #ifdef HAL_SDRAM_MODULE_ENABLED
mbed_official 133:d4dda5c437f0 105 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 133:d4dda5c437f0 106
mbed_official 133:d4dda5c437f0 107 /* Private typedef -----------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 108 /* Private define ------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 109 /* Private macro -------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 110 /* Private variables ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 111 /* Private function prototypes -----------------------------------------------*/
mbed_official 133:d4dda5c437f0 112
mbed_official 133:d4dda5c437f0 113 /* Private functions ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 114
mbed_official 133:d4dda5c437f0 115 /** @defgroup SDRAM_Private_Functions
mbed_official 133:d4dda5c437f0 116 * @{
mbed_official 133:d4dda5c437f0 117 */
mbed_official 133:d4dda5c437f0 118
mbed_official 133:d4dda5c437f0 119 /** @defgroup SDRAM_Group1 Initialization and de-initialization functions
mbed_official 133:d4dda5c437f0 120 * @brief Initialization and Configuration functions
mbed_official 133:d4dda5c437f0 121 *
mbed_official 133:d4dda5c437f0 122 @verbatim
mbed_official 133:d4dda5c437f0 123 ==============================================================================
mbed_official 133:d4dda5c437f0 124 ##### SDRAM Initialization and de_initialization functions #####
mbed_official 133:d4dda5c437f0 125 ==============================================================================
mbed_official 133:d4dda5c437f0 126 [..]
mbed_official 133:d4dda5c437f0 127 This section provides functions allowing to initialize/de-initialize
mbed_official 133:d4dda5c437f0 128 the SDRAM memory
mbed_official 133:d4dda5c437f0 129
mbed_official 133:d4dda5c437f0 130 @endverbatim
mbed_official 133:d4dda5c437f0 131 * @{
mbed_official 133:d4dda5c437f0 132 */
mbed_official 133:d4dda5c437f0 133
mbed_official 133:d4dda5c437f0 134 /**
mbed_official 133:d4dda5c437f0 135 * @brief Performs the SDRAM device initialization sequence.
mbed_official 133:d4dda5c437f0 136 * @param hsdram: SDRAM handle
mbed_official 133:d4dda5c437f0 137 * @param Timing: Pointer to SDRAM control timing structure
mbed_official 133:d4dda5c437f0 138 * @retval HAL status
mbed_official 133:d4dda5c437f0 139 */
mbed_official 133:d4dda5c437f0 140 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
mbed_official 133:d4dda5c437f0 141 {
mbed_official 133:d4dda5c437f0 142 /* Check the SDRAM handle parameter */
mbed_official 133:d4dda5c437f0 143 if(hsdram == NULL)
mbed_official 133:d4dda5c437f0 144 {
mbed_official 133:d4dda5c437f0 145 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 146 }
mbed_official 133:d4dda5c437f0 147
mbed_official 133:d4dda5c437f0 148 if(hsdram->State == HAL_SDRAM_STATE_RESET)
mbed_official 133:d4dda5c437f0 149 {
mbed_official 133:d4dda5c437f0 150 /* Initialize the low level hardware (MSP) */
mbed_official 133:d4dda5c437f0 151 HAL_SDRAM_MspInit(hsdram);
mbed_official 133:d4dda5c437f0 152 }
mbed_official 133:d4dda5c437f0 153
mbed_official 133:d4dda5c437f0 154 /* Initialize the SDRAM controller state */
mbed_official 133:d4dda5c437f0 155 hsdram->State = HAL_SDRAM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 156
mbed_official 133:d4dda5c437f0 157 /* Initialize SDRAM control Interface */
mbed_official 133:d4dda5c437f0 158 FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
mbed_official 133:d4dda5c437f0 159
mbed_official 133:d4dda5c437f0 160 /* Initialize SDRAM timing Interface */
mbed_official 133:d4dda5c437f0 161 FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
mbed_official 133:d4dda5c437f0 162
mbed_official 133:d4dda5c437f0 163 /* Update the SDRAM controller state */
mbed_official 133:d4dda5c437f0 164 hsdram->State = HAL_SDRAM_STATE_READY;
mbed_official 133:d4dda5c437f0 165
mbed_official 133:d4dda5c437f0 166 return HAL_OK;
mbed_official 133:d4dda5c437f0 167 }
mbed_official 133:d4dda5c437f0 168
mbed_official 133:d4dda5c437f0 169 /**
mbed_official 133:d4dda5c437f0 170 * @brief Perform the SDRAM device initialization sequence.
mbed_official 133:d4dda5c437f0 171 * @param hsdram: SDRAM handle
mbed_official 133:d4dda5c437f0 172 * @retval HAL status
mbed_official 133:d4dda5c437f0 173 */
mbed_official 133:d4dda5c437f0 174 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
mbed_official 133:d4dda5c437f0 175 {
mbed_official 133:d4dda5c437f0 176 /* Initialize the low level hardware (MSP) */
mbed_official 133:d4dda5c437f0 177 HAL_SDRAM_MspDeInit(hsdram);
mbed_official 133:d4dda5c437f0 178
mbed_official 133:d4dda5c437f0 179 /* Configure the SDRAM registers with their reset values */
mbed_official 133:d4dda5c437f0 180 FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
mbed_official 133:d4dda5c437f0 181
mbed_official 133:d4dda5c437f0 182 /* Reset the SDRAM controller state */
mbed_official 133:d4dda5c437f0 183 hsdram->State = HAL_SDRAM_STATE_RESET;
mbed_official 133:d4dda5c437f0 184
mbed_official 133:d4dda5c437f0 185 /* Release Lock */
mbed_official 133:d4dda5c437f0 186 __HAL_UNLOCK(hsdram);
mbed_official 133:d4dda5c437f0 187
mbed_official 133:d4dda5c437f0 188 return HAL_OK;
mbed_official 133:d4dda5c437f0 189 }
mbed_official 133:d4dda5c437f0 190
mbed_official 133:d4dda5c437f0 191 /**
mbed_official 133:d4dda5c437f0 192 * @brief SDRAM MSP Init.
mbed_official 133:d4dda5c437f0 193 * @param hsdram: SDRAM handle
mbed_official 133:d4dda5c437f0 194 * @retval None
mbed_official 133:d4dda5c437f0 195 */
mbed_official 133:d4dda5c437f0 196 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
mbed_official 133:d4dda5c437f0 197 {
mbed_official 133:d4dda5c437f0 198 /* NOTE: This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 199 the HAL_SDRAM_MspInit could be implemented in the user file
mbed_official 133:d4dda5c437f0 200 */
mbed_official 133:d4dda5c437f0 201 }
mbed_official 133:d4dda5c437f0 202
mbed_official 133:d4dda5c437f0 203 /**
mbed_official 133:d4dda5c437f0 204 * @brief SDRAM MSP DeInit.
mbed_official 133:d4dda5c437f0 205 * @param hsdram: SDRAM handle
mbed_official 133:d4dda5c437f0 206 * @retval None
mbed_official 133:d4dda5c437f0 207 */
mbed_official 133:d4dda5c437f0 208 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
mbed_official 133:d4dda5c437f0 209 {
mbed_official 133:d4dda5c437f0 210 /* NOTE: This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 211 the HAL_SDRAM_MspDeInit could be implemented in the user file
mbed_official 133:d4dda5c437f0 212 */
mbed_official 133:d4dda5c437f0 213 }
mbed_official 133:d4dda5c437f0 214
mbed_official 133:d4dda5c437f0 215 /**
mbed_official 133:d4dda5c437f0 216 * @brief This function handles SDRAM refresh error interrupt request.
mbed_official 133:d4dda5c437f0 217 * @param hsdram: SDRAM handle
mbed_official 133:d4dda5c437f0 218 * @retval HAL status
mbed_official 133:d4dda5c437f0 219 */
mbed_official 133:d4dda5c437f0 220 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
mbed_official 133:d4dda5c437f0 221 {
mbed_official 133:d4dda5c437f0 222 /* Check SDRAM interrupt Rising edge flag */
mbed_official 133:d4dda5c437f0 223 if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
mbed_official 133:d4dda5c437f0 224 {
mbed_official 133:d4dda5c437f0 225 /* SDRAM refresh error interrupt callback */
mbed_official 133:d4dda5c437f0 226 HAL_SDRAM_RefreshErrorCallback(hsdram);
mbed_official 133:d4dda5c437f0 227
mbed_official 133:d4dda5c437f0 228 /* Clear SDRAM refresh error interrupt pending bit */
mbed_official 133:d4dda5c437f0 229 __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
mbed_official 133:d4dda5c437f0 230 }
mbed_official 133:d4dda5c437f0 231 }
mbed_official 133:d4dda5c437f0 232
mbed_official 133:d4dda5c437f0 233 /**
mbed_official 133:d4dda5c437f0 234 * @brief SDRAM Refresh error callback.
mbed_official 133:d4dda5c437f0 235 * @param hsdram: SDRAM handle
mbed_official 133:d4dda5c437f0 236 * @retval None
mbed_official 133:d4dda5c437f0 237 */
mbed_official 133:d4dda5c437f0 238 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
mbed_official 133:d4dda5c437f0 239 {
mbed_official 133:d4dda5c437f0 240 /* NOTE: This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 241 the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
mbed_official 133:d4dda5c437f0 242 */
mbed_official 133:d4dda5c437f0 243 }
mbed_official 133:d4dda5c437f0 244
mbed_official 133:d4dda5c437f0 245 /**
mbed_official 133:d4dda5c437f0 246 * @brief DMA transfer complete callback.
mbed_official 133:d4dda5c437f0 247 * @param hdma: DMA handle
mbed_official 133:d4dda5c437f0 248 * @retval None
mbed_official 133:d4dda5c437f0 249 */
mbed_official 133:d4dda5c437f0 250 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 251 {
mbed_official 133:d4dda5c437f0 252 /* NOTE: This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 253 the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
mbed_official 133:d4dda5c437f0 254 */
mbed_official 133:d4dda5c437f0 255 }
mbed_official 133:d4dda5c437f0 256
mbed_official 133:d4dda5c437f0 257 /**
mbed_official 133:d4dda5c437f0 258 * @brief DMA transfer complete error callback.
mbed_official 133:d4dda5c437f0 259 * @param hdma: DMA handle
mbed_official 133:d4dda5c437f0 260 * @retval None
mbed_official 133:d4dda5c437f0 261 */
mbed_official 133:d4dda5c437f0 262 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 263 {
mbed_official 133:d4dda5c437f0 264 /* NOTE: This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 265 the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
mbed_official 133:d4dda5c437f0 266 */
mbed_official 133:d4dda5c437f0 267 }
mbed_official 133:d4dda5c437f0 268
mbed_official 133:d4dda5c437f0 269 /**
mbed_official 133:d4dda5c437f0 270 * @}
mbed_official 133:d4dda5c437f0 271 */
mbed_official 133:d4dda5c437f0 272
mbed_official 133:d4dda5c437f0 273 /** @defgroup SDRAM_Group2 Input and Output functions
mbed_official 133:d4dda5c437f0 274 * @brief Input Output and memory control functions
mbed_official 133:d4dda5c437f0 275 *
mbed_official 133:d4dda5c437f0 276 @verbatim
mbed_official 133:d4dda5c437f0 277 ==============================================================================
mbed_official 133:d4dda5c437f0 278 ##### SDRAM Input and Output functions #####
mbed_official 133:d4dda5c437f0 279 ==============================================================================
mbed_official 133:d4dda5c437f0 280 [..]
mbed_official 133:d4dda5c437f0 281 This section provides functions allowing to use and control the SDRAM memory
mbed_official 133:d4dda5c437f0 282
mbed_official 133:d4dda5c437f0 283 @endverbatim
mbed_official 133:d4dda5c437f0 284 * @{
mbed_official 133:d4dda5c437f0 285 */
mbed_official 133:d4dda5c437f0 286
mbed_official 133:d4dda5c437f0 287 /**
mbed_official 133:d4dda5c437f0 288 * @brief Reads 8-bit data buffer from the SDRAM memory.
mbed_official 133:d4dda5c437f0 289 * @param hsdram: SDRAM handle
mbed_official 133:d4dda5c437f0 290 * @param pAddress: Pointer to read start address
mbed_official 133:d4dda5c437f0 291 * @param pDstBuffer: Pointer to destination buffer
mbed_official 133:d4dda5c437f0 292 * @param BufferSize: Size of the buffer to read from memory
mbed_official 133:d4dda5c437f0 293 * @retval HAL status
mbed_official 133:d4dda5c437f0 294 */
mbed_official 133:d4dda5c437f0 295 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 296 {
mbed_official 133:d4dda5c437f0 297 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
mbed_official 133:d4dda5c437f0 298
mbed_official 133:d4dda5c437f0 299 /* Process Locked */
mbed_official 133:d4dda5c437f0 300 __HAL_LOCK(hsdram);
mbed_official 133:d4dda5c437f0 301
mbed_official 133:d4dda5c437f0 302 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 303 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 304 {
mbed_official 133:d4dda5c437f0 305 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 306 }
mbed_official 133:d4dda5c437f0 307 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
mbed_official 133:d4dda5c437f0 308 {
mbed_official 133:d4dda5c437f0 309 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 310 }
mbed_official 133:d4dda5c437f0 311
mbed_official 133:d4dda5c437f0 312 /* Read data from source */
mbed_official 133:d4dda5c437f0 313 for(; BufferSize != 0; BufferSize--)
mbed_official 133:d4dda5c437f0 314 {
mbed_official 133:d4dda5c437f0 315 *pDstBuffer = *(__IO uint8_t *)pSdramAddress;
mbed_official 133:d4dda5c437f0 316 pDstBuffer++;
mbed_official 133:d4dda5c437f0 317 pSdramAddress++;
mbed_official 133:d4dda5c437f0 318 }
mbed_official 133:d4dda5c437f0 319
mbed_official 133:d4dda5c437f0 320 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 321 __HAL_UNLOCK(hsdram);
mbed_official 133:d4dda5c437f0 322
mbed_official 133:d4dda5c437f0 323 return HAL_OK;
mbed_official 133:d4dda5c437f0 324 }
mbed_official 133:d4dda5c437f0 325
mbed_official 133:d4dda5c437f0 326
mbed_official 133:d4dda5c437f0 327 /**
mbed_official 133:d4dda5c437f0 328 * @brief Writes 8-bit data buffer to SDRAM memory.
mbed_official 133:d4dda5c437f0 329 * @param hsdram: SDRAM handle
mbed_official 133:d4dda5c437f0 330 * @param pAddress: Pointer to write start address
mbed_official 133:d4dda5c437f0 331 * @param pSrcBuffer: Pointer to source buffer to write
mbed_official 133:d4dda5c437f0 332 * @param BufferSize: Size of the buffer to write to memory
mbed_official 133:d4dda5c437f0 333 * @retval HAL status
mbed_official 133:d4dda5c437f0 334 */
mbed_official 133:d4dda5c437f0 335 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 336 {
mbed_official 133:d4dda5c437f0 337 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
mbed_official 133:d4dda5c437f0 338 uint32_t tmp = 0;
mbed_official 133:d4dda5c437f0 339
mbed_official 133:d4dda5c437f0 340 /* Process Locked */
mbed_official 133:d4dda5c437f0 341 __HAL_LOCK(hsdram);
mbed_official 133:d4dda5c437f0 342
mbed_official 133:d4dda5c437f0 343 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 344 tmp = hsdram->State;
mbed_official 133:d4dda5c437f0 345
mbed_official 133:d4dda5c437f0 346 if(tmp == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 347 {
mbed_official 133:d4dda5c437f0 348 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 349 }
mbed_official 133:d4dda5c437f0 350 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
mbed_official 133:d4dda5c437f0 351 {
mbed_official 133:d4dda5c437f0 352 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 353 }
mbed_official 133:d4dda5c437f0 354
mbed_official 133:d4dda5c437f0 355 /* Write data to memory */
mbed_official 133:d4dda5c437f0 356 for(; BufferSize != 0; BufferSize--)
mbed_official 133:d4dda5c437f0 357 {
mbed_official 133:d4dda5c437f0 358 *(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
mbed_official 133:d4dda5c437f0 359 pSrcBuffer++;
mbed_official 133:d4dda5c437f0 360 pSdramAddress++;
mbed_official 133:d4dda5c437f0 361 }
mbed_official 133:d4dda5c437f0 362
mbed_official 133:d4dda5c437f0 363 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 364 __HAL_UNLOCK(hsdram);
mbed_official 133:d4dda5c437f0 365
mbed_official 133:d4dda5c437f0 366 return HAL_OK;
mbed_official 133:d4dda5c437f0 367 }
mbed_official 133:d4dda5c437f0 368
mbed_official 133:d4dda5c437f0 369
mbed_official 133:d4dda5c437f0 370 /**
mbed_official 133:d4dda5c437f0 371 * @brief Reads 16-bit data buffer from the SDRAM memory.
mbed_official 133:d4dda5c437f0 372 * @param hsdram: SDRAM handle
mbed_official 133:d4dda5c437f0 373 * @param pAddress: Pointer to read start address
mbed_official 133:d4dda5c437f0 374 * @param pDstBuffer: Pointer to destination buffer
mbed_official 133:d4dda5c437f0 375 * @param BufferSize: Size of the buffer to read from memory
mbed_official 133:d4dda5c437f0 376 * @retval HAL status
mbed_official 133:d4dda5c437f0 377 */
mbed_official 133:d4dda5c437f0 378 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 379 {
mbed_official 133:d4dda5c437f0 380 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
mbed_official 133:d4dda5c437f0 381
mbed_official 133:d4dda5c437f0 382 /* Process Locked */
mbed_official 133:d4dda5c437f0 383 __HAL_LOCK(hsdram);
mbed_official 133:d4dda5c437f0 384
mbed_official 133:d4dda5c437f0 385 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 386 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 387 {
mbed_official 133:d4dda5c437f0 388 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 389 }
mbed_official 133:d4dda5c437f0 390 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
mbed_official 133:d4dda5c437f0 391 {
mbed_official 133:d4dda5c437f0 392 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 393 }
mbed_official 133:d4dda5c437f0 394
mbed_official 133:d4dda5c437f0 395 /* Read data from source */
mbed_official 133:d4dda5c437f0 396 for(; BufferSize != 0; BufferSize--)
mbed_official 133:d4dda5c437f0 397 {
mbed_official 133:d4dda5c437f0 398 *pDstBuffer = *(__IO uint16_t *)pSdramAddress;
mbed_official 133:d4dda5c437f0 399 pDstBuffer++;
mbed_official 133:d4dda5c437f0 400 pSdramAddress++;
mbed_official 133:d4dda5c437f0 401 }
mbed_official 133:d4dda5c437f0 402
mbed_official 133:d4dda5c437f0 403 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 404 __HAL_UNLOCK(hsdram);
mbed_official 133:d4dda5c437f0 405
mbed_official 133:d4dda5c437f0 406 return HAL_OK;
mbed_official 133:d4dda5c437f0 407 }
mbed_official 133:d4dda5c437f0 408
mbed_official 133:d4dda5c437f0 409 /**
mbed_official 133:d4dda5c437f0 410 * @brief Writes 16-bit data buffer to SDRAM memory.
mbed_official 133:d4dda5c437f0 411 * @param hsdram: SDRAM handle
mbed_official 133:d4dda5c437f0 412 * @param pAddress: Pointer to write start address
mbed_official 133:d4dda5c437f0 413 * @param pSrcBuffer: Pointer to source buffer to write
mbed_official 133:d4dda5c437f0 414 * @param BufferSize: Size of the buffer to write to memory
mbed_official 133:d4dda5c437f0 415 * @retval HAL status
mbed_official 133:d4dda5c437f0 416 */
mbed_official 133:d4dda5c437f0 417 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 418 {
mbed_official 133:d4dda5c437f0 419 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
mbed_official 133:d4dda5c437f0 420 uint32_t tmp = 0;
mbed_official 133:d4dda5c437f0 421
mbed_official 133:d4dda5c437f0 422 /* Process Locked */
mbed_official 133:d4dda5c437f0 423 __HAL_LOCK(hsdram);
mbed_official 133:d4dda5c437f0 424
mbed_official 133:d4dda5c437f0 425 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 426 tmp = hsdram->State;
mbed_official 133:d4dda5c437f0 427
mbed_official 133:d4dda5c437f0 428 if(tmp == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 429 {
mbed_official 133:d4dda5c437f0 430 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 431 }
mbed_official 133:d4dda5c437f0 432 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
mbed_official 133:d4dda5c437f0 433 {
mbed_official 133:d4dda5c437f0 434 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 435 }
mbed_official 133:d4dda5c437f0 436
mbed_official 133:d4dda5c437f0 437 /* Write data to memory */
mbed_official 133:d4dda5c437f0 438 for(; BufferSize != 0; BufferSize--)
mbed_official 133:d4dda5c437f0 439 {
mbed_official 133:d4dda5c437f0 440 *(__IO uint16_t *)pSdramAddress = *pSrcBuffer;
mbed_official 133:d4dda5c437f0 441 pSrcBuffer++;
mbed_official 133:d4dda5c437f0 442 pSdramAddress++;
mbed_official 133:d4dda5c437f0 443 }
mbed_official 133:d4dda5c437f0 444
mbed_official 133:d4dda5c437f0 445 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 446 __HAL_UNLOCK(hsdram);
mbed_official 133:d4dda5c437f0 447
mbed_official 133:d4dda5c437f0 448 return HAL_OK;
mbed_official 133:d4dda5c437f0 449 }
mbed_official 133:d4dda5c437f0 450
mbed_official 133:d4dda5c437f0 451 /**
mbed_official 133:d4dda5c437f0 452 * @brief Reads 32-bit data buffer from the SDRAM memory.
mbed_official 133:d4dda5c437f0 453 * @param hsdram: SDRAM handle
mbed_official 133:d4dda5c437f0 454 * @param pAddress: Pointer to read start address
mbed_official 133:d4dda5c437f0 455 * @param pDstBuffer: Pointer to destination buffer
mbed_official 133:d4dda5c437f0 456 * @param BufferSize: Size of the buffer to read from memory
mbed_official 133:d4dda5c437f0 457 * @retval HAL status
mbed_official 133:d4dda5c437f0 458 */
mbed_official 133:d4dda5c437f0 459 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 460 {
mbed_official 133:d4dda5c437f0 461 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
mbed_official 133:d4dda5c437f0 462
mbed_official 133:d4dda5c437f0 463 /* Process Locked */
mbed_official 133:d4dda5c437f0 464 __HAL_LOCK(hsdram);
mbed_official 133:d4dda5c437f0 465
mbed_official 133:d4dda5c437f0 466 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 467 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 468 {
mbed_official 133:d4dda5c437f0 469 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 470 }
mbed_official 133:d4dda5c437f0 471 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
mbed_official 133:d4dda5c437f0 472 {
mbed_official 133:d4dda5c437f0 473 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 474 }
mbed_official 133:d4dda5c437f0 475
mbed_official 133:d4dda5c437f0 476 /* Read data from source */
mbed_official 133:d4dda5c437f0 477 for(; BufferSize != 0; BufferSize--)
mbed_official 133:d4dda5c437f0 478 {
mbed_official 133:d4dda5c437f0 479 *pDstBuffer = *(__IO uint32_t *)pSdramAddress;
mbed_official 133:d4dda5c437f0 480 pDstBuffer++;
mbed_official 133:d4dda5c437f0 481 pSdramAddress++;
mbed_official 133:d4dda5c437f0 482 }
mbed_official 133:d4dda5c437f0 483
mbed_official 133:d4dda5c437f0 484 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 485 __HAL_UNLOCK(hsdram);
mbed_official 133:d4dda5c437f0 486
mbed_official 133:d4dda5c437f0 487 return HAL_OK;
mbed_official 133:d4dda5c437f0 488 }
mbed_official 133:d4dda5c437f0 489
mbed_official 133:d4dda5c437f0 490 /**
mbed_official 133:d4dda5c437f0 491 * @brief Writes 32-bit data buffer to SDRAM memory.
mbed_official 133:d4dda5c437f0 492 * @param hsdram: SDRAM handle
mbed_official 133:d4dda5c437f0 493 * @param pAddress: Pointer to write start address
mbed_official 133:d4dda5c437f0 494 * @param pSrcBuffer: Pointer to source buffer to write
mbed_official 133:d4dda5c437f0 495 * @param BufferSize: Size of the buffer to write to memory
mbed_official 133:d4dda5c437f0 496 * @retval HAL status
mbed_official 133:d4dda5c437f0 497 */
mbed_official 133:d4dda5c437f0 498 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 499 {
mbed_official 133:d4dda5c437f0 500 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
mbed_official 133:d4dda5c437f0 501 uint32_t tmp = 0;
mbed_official 133:d4dda5c437f0 502
mbed_official 133:d4dda5c437f0 503 /* Process Locked */
mbed_official 133:d4dda5c437f0 504 __HAL_LOCK(hsdram);
mbed_official 133:d4dda5c437f0 505
mbed_official 133:d4dda5c437f0 506 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 507 tmp = hsdram->State;
mbed_official 133:d4dda5c437f0 508
mbed_official 133:d4dda5c437f0 509 if(tmp == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 510 {
mbed_official 133:d4dda5c437f0 511 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 512 }
mbed_official 133:d4dda5c437f0 513 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
mbed_official 133:d4dda5c437f0 514 {
mbed_official 133:d4dda5c437f0 515 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 516 }
mbed_official 133:d4dda5c437f0 517
mbed_official 133:d4dda5c437f0 518 /* Write data to memory */
mbed_official 133:d4dda5c437f0 519 for(; BufferSize != 0; BufferSize--)
mbed_official 133:d4dda5c437f0 520 {
mbed_official 133:d4dda5c437f0 521 *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
mbed_official 133:d4dda5c437f0 522 pSrcBuffer++;
mbed_official 133:d4dda5c437f0 523 pSdramAddress++;
mbed_official 133:d4dda5c437f0 524 }
mbed_official 133:d4dda5c437f0 525
mbed_official 133:d4dda5c437f0 526 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 527 __HAL_UNLOCK(hsdram);
mbed_official 133:d4dda5c437f0 528
mbed_official 133:d4dda5c437f0 529 return HAL_OK;
mbed_official 133:d4dda5c437f0 530 }
mbed_official 133:d4dda5c437f0 531
mbed_official 133:d4dda5c437f0 532 /**
mbed_official 133:d4dda5c437f0 533 * @brief Reads a Words data from the SDRAM memory using DMA transfer.
mbed_official 133:d4dda5c437f0 534 * @param hsdram: SDRAM handle
mbed_official 133:d4dda5c437f0 535 * @param pAddress: Pointer to read start address
mbed_official 133:d4dda5c437f0 536 * @param pDstBuffer: Pointer to destination buffer
mbed_official 133:d4dda5c437f0 537 * @param BufferSize: Size of the buffer to read from memory
mbed_official 133:d4dda5c437f0 538 * @retval HAL status
mbed_official 133:d4dda5c437f0 539 */
mbed_official 133:d4dda5c437f0 540 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 541 {
mbed_official 133:d4dda5c437f0 542 uint32_t tmp = 0;
mbed_official 133:d4dda5c437f0 543
mbed_official 133:d4dda5c437f0 544 /* Process Locked */
mbed_official 133:d4dda5c437f0 545 __HAL_LOCK(hsdram);
mbed_official 133:d4dda5c437f0 546
mbed_official 133:d4dda5c437f0 547 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 548 tmp = hsdram->State;
mbed_official 133:d4dda5c437f0 549
mbed_official 133:d4dda5c437f0 550 if(tmp == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 551 {
mbed_official 133:d4dda5c437f0 552 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 553 }
mbed_official 133:d4dda5c437f0 554 else if(tmp == HAL_SDRAM_STATE_PRECHARGED)
mbed_official 133:d4dda5c437f0 555 {
mbed_official 133:d4dda5c437f0 556 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 557 }
mbed_official 133:d4dda5c437f0 558
mbed_official 133:d4dda5c437f0 559 /* Configure DMA user callbacks */
mbed_official 133:d4dda5c437f0 560 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
mbed_official 133:d4dda5c437f0 561 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
mbed_official 133:d4dda5c437f0 562
mbed_official 133:d4dda5c437f0 563 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 564 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
mbed_official 133:d4dda5c437f0 565
mbed_official 133:d4dda5c437f0 566 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 567 __HAL_UNLOCK(hsdram);
mbed_official 133:d4dda5c437f0 568
mbed_official 133:d4dda5c437f0 569 return HAL_OK;
mbed_official 133:d4dda5c437f0 570 }
mbed_official 133:d4dda5c437f0 571
mbed_official 133:d4dda5c437f0 572 /**
mbed_official 133:d4dda5c437f0 573 * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
mbed_official 133:d4dda5c437f0 574 * @param hsdram: SDRAM handle
mbed_official 133:d4dda5c437f0 575 * @param pAddress: Pointer to write start address
mbed_official 133:d4dda5c437f0 576 * @param pSrcBuffer: Pointer to source buffer to write
mbed_official 133:d4dda5c437f0 577 * @param BufferSize: Size of the buffer to write to memory
mbed_official 133:d4dda5c437f0 578 * @retval HAL status
mbed_official 133:d4dda5c437f0 579 */
mbed_official 133:d4dda5c437f0 580 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 581 {
mbed_official 133:d4dda5c437f0 582 uint32_t tmp = 0;
mbed_official 133:d4dda5c437f0 583
mbed_official 133:d4dda5c437f0 584 /* Process Locked */
mbed_official 133:d4dda5c437f0 585 __HAL_LOCK(hsdram);
mbed_official 133:d4dda5c437f0 586
mbed_official 133:d4dda5c437f0 587 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 588 tmp = hsdram->State;
mbed_official 133:d4dda5c437f0 589
mbed_official 133:d4dda5c437f0 590 if(tmp == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 591 {
mbed_official 133:d4dda5c437f0 592 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 593 }
mbed_official 133:d4dda5c437f0 594 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
mbed_official 133:d4dda5c437f0 595 {
mbed_official 133:d4dda5c437f0 596 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 597 }
mbed_official 133:d4dda5c437f0 598
mbed_official 133:d4dda5c437f0 599 /* Configure DMA user callbacks */
mbed_official 133:d4dda5c437f0 600 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
mbed_official 133:d4dda5c437f0 601 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
mbed_official 133:d4dda5c437f0 602
mbed_official 133:d4dda5c437f0 603 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 604 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
mbed_official 133:d4dda5c437f0 605
mbed_official 133:d4dda5c437f0 606 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 607 __HAL_UNLOCK(hsdram);
mbed_official 133:d4dda5c437f0 608
mbed_official 133:d4dda5c437f0 609 return HAL_OK;
mbed_official 133:d4dda5c437f0 610 }
mbed_official 133:d4dda5c437f0 611
mbed_official 133:d4dda5c437f0 612 /**
mbed_official 133:d4dda5c437f0 613 * @}
mbed_official 133:d4dda5c437f0 614 */
mbed_official 133:d4dda5c437f0 615
mbed_official 133:d4dda5c437f0 616 /** @defgroup SDRAM_Group3 Control functions
mbed_official 133:d4dda5c437f0 617 * @brief management functions
mbed_official 133:d4dda5c437f0 618 *
mbed_official 133:d4dda5c437f0 619 @verbatim
mbed_official 133:d4dda5c437f0 620 ==============================================================================
mbed_official 133:d4dda5c437f0 621 ##### SDRAM Control functions #####
mbed_official 133:d4dda5c437f0 622 ==============================================================================
mbed_official 133:d4dda5c437f0 623 [..]
mbed_official 133:d4dda5c437f0 624 This subsection provides a set of functions allowing to control dynamically
mbed_official 133:d4dda5c437f0 625 the SDRAM interface.
mbed_official 133:d4dda5c437f0 626
mbed_official 133:d4dda5c437f0 627 @endverbatim
mbed_official 133:d4dda5c437f0 628 * @{
mbed_official 133:d4dda5c437f0 629 */
mbed_official 133:d4dda5c437f0 630
mbed_official 133:d4dda5c437f0 631 /**
mbed_official 133:d4dda5c437f0 632 * @brief Enables dynamically SDRAM write protection.
mbed_official 133:d4dda5c437f0 633 * @param hsdram: SDRAM handle
mbed_official 133:d4dda5c437f0 634 * @retval HAL status
mbed_official 133:d4dda5c437f0 635 */
mbed_official 133:d4dda5c437f0 636 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
mbed_official 133:d4dda5c437f0 637 {
mbed_official 133:d4dda5c437f0 638 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 639 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 640 {
mbed_official 133:d4dda5c437f0 641 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 642 }
mbed_official 133:d4dda5c437f0 643
mbed_official 133:d4dda5c437f0 644 /* Update the SDRAM state */
mbed_official 133:d4dda5c437f0 645 hsdram->State = HAL_SDRAM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 646
mbed_official 133:d4dda5c437f0 647 /* Enable write protection */
mbed_official 133:d4dda5c437f0 648 FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
mbed_official 133:d4dda5c437f0 649
mbed_official 133:d4dda5c437f0 650 /* Update the SDRAM state */
mbed_official 133:d4dda5c437f0 651 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
mbed_official 133:d4dda5c437f0 652
mbed_official 133:d4dda5c437f0 653 return HAL_OK;
mbed_official 133:d4dda5c437f0 654 }
mbed_official 133:d4dda5c437f0 655
mbed_official 133:d4dda5c437f0 656 /**
mbed_official 133:d4dda5c437f0 657 * @brief Disables dynamically SDRAM write protection.
mbed_official 133:d4dda5c437f0 658 * @param hsdram: SDRAM handle
mbed_official 133:d4dda5c437f0 659 * @retval HAL status
mbed_official 133:d4dda5c437f0 660 */
mbed_official 133:d4dda5c437f0 661 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
mbed_official 133:d4dda5c437f0 662 {
mbed_official 133:d4dda5c437f0 663 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 664 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 665 {
mbed_official 133:d4dda5c437f0 666 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 667 }
mbed_official 133:d4dda5c437f0 668
mbed_official 133:d4dda5c437f0 669 /* Update the SDRAM state */
mbed_official 133:d4dda5c437f0 670 hsdram->State = HAL_SDRAM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 671
mbed_official 133:d4dda5c437f0 672 /* Disable write protection */
mbed_official 133:d4dda5c437f0 673 FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
mbed_official 133:d4dda5c437f0 674
mbed_official 133:d4dda5c437f0 675 /* Update the SDRAM state */
mbed_official 133:d4dda5c437f0 676 hsdram->State = HAL_SDRAM_STATE_READY;
mbed_official 133:d4dda5c437f0 677
mbed_official 133:d4dda5c437f0 678 return HAL_OK;
mbed_official 133:d4dda5c437f0 679 }
mbed_official 133:d4dda5c437f0 680
mbed_official 133:d4dda5c437f0 681 /**
mbed_official 133:d4dda5c437f0 682 * @brief Sends Command to the SDRAM bank.
mbed_official 133:d4dda5c437f0 683 * @param hsdram: SDRAM handle
mbed_official 133:d4dda5c437f0 684 * @param Command: SDRAM command structure
mbed_official 133:d4dda5c437f0 685 * @param Timeout: Timeout duration
mbed_official 133:d4dda5c437f0 686 * @retval HAL state
mbed_official 133:d4dda5c437f0 687 */
mbed_official 133:d4dda5c437f0 688 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
mbed_official 133:d4dda5c437f0 689 {
mbed_official 133:d4dda5c437f0 690 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 691 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 692 {
mbed_official 133:d4dda5c437f0 693 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 694 }
mbed_official 133:d4dda5c437f0 695
mbed_official 133:d4dda5c437f0 696 /* Update the SDRAM state */
mbed_official 133:d4dda5c437f0 697 hsdram->State = HAL_SDRAM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 698
mbed_official 133:d4dda5c437f0 699 /* Send SDRAM command */
mbed_official 133:d4dda5c437f0 700 FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
mbed_official 133:d4dda5c437f0 701
mbed_official 133:d4dda5c437f0 702 /* Update the SDRAM controller state state */
mbed_official 133:d4dda5c437f0 703 if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
mbed_official 133:d4dda5c437f0 704 {
mbed_official 133:d4dda5c437f0 705 hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
mbed_official 133:d4dda5c437f0 706 }
mbed_official 133:d4dda5c437f0 707 else
mbed_official 133:d4dda5c437f0 708 {
mbed_official 133:d4dda5c437f0 709 hsdram->State = HAL_SDRAM_STATE_READY;
mbed_official 133:d4dda5c437f0 710 }
mbed_official 133:d4dda5c437f0 711
mbed_official 133:d4dda5c437f0 712 return HAL_OK;
mbed_official 133:d4dda5c437f0 713 }
mbed_official 133:d4dda5c437f0 714
mbed_official 133:d4dda5c437f0 715 /**
mbed_official 133:d4dda5c437f0 716 * @brief Programs the SDRAM Memory Refresh rate.
mbed_official 133:d4dda5c437f0 717 * @param hsdram: SDRAM handle
mbed_official 133:d4dda5c437f0 718 * @param RefreshRate: The SDRAM refresh rate value
mbed_official 133:d4dda5c437f0 719 * @retval HAL state
mbed_official 133:d4dda5c437f0 720 */
mbed_official 133:d4dda5c437f0 721 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
mbed_official 133:d4dda5c437f0 722 {
mbed_official 133:d4dda5c437f0 723 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 724 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 725 {
mbed_official 133:d4dda5c437f0 726 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 727 }
mbed_official 133:d4dda5c437f0 728
mbed_official 133:d4dda5c437f0 729 /* Update the SDRAM state */
mbed_official 133:d4dda5c437f0 730 hsdram->State = HAL_SDRAM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 731
mbed_official 133:d4dda5c437f0 732 /* Program the refresh rate */
mbed_official 133:d4dda5c437f0 733 FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
mbed_official 133:d4dda5c437f0 734
mbed_official 133:d4dda5c437f0 735 /* Update the SDRAM state */
mbed_official 133:d4dda5c437f0 736 hsdram->State = HAL_SDRAM_STATE_READY;
mbed_official 133:d4dda5c437f0 737
mbed_official 133:d4dda5c437f0 738 return HAL_OK;
mbed_official 133:d4dda5c437f0 739 }
mbed_official 133:d4dda5c437f0 740
mbed_official 133:d4dda5c437f0 741 /**
mbed_official 133:d4dda5c437f0 742 * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
mbed_official 133:d4dda5c437f0 743 * @param hsdram: SDRAM handle
mbed_official 133:d4dda5c437f0 744 * @param AutoRefreshNumber: The SDRAM auto Refresh number
mbed_official 133:d4dda5c437f0 745 * @retval None
mbed_official 133:d4dda5c437f0 746 */
mbed_official 133:d4dda5c437f0 747 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
mbed_official 133:d4dda5c437f0 748 {
mbed_official 133:d4dda5c437f0 749 /* Check the SDRAM controller state */
mbed_official 133:d4dda5c437f0 750 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
mbed_official 133:d4dda5c437f0 751 {
mbed_official 133:d4dda5c437f0 752 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 753 }
mbed_official 133:d4dda5c437f0 754
mbed_official 133:d4dda5c437f0 755 /* Update the SDRAM state */
mbed_official 133:d4dda5c437f0 756 hsdram->State = HAL_SDRAM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 757
mbed_official 133:d4dda5c437f0 758 /* Set the Auto-Refresh number */
mbed_official 133:d4dda5c437f0 759 FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);
mbed_official 133:d4dda5c437f0 760
mbed_official 133:d4dda5c437f0 761 /* Update the SDRAM state */
mbed_official 133:d4dda5c437f0 762 hsdram->State = HAL_SDRAM_STATE_READY;
mbed_official 133:d4dda5c437f0 763
mbed_official 133:d4dda5c437f0 764 return HAL_OK;
mbed_official 133:d4dda5c437f0 765 }
mbed_official 133:d4dda5c437f0 766
mbed_official 133:d4dda5c437f0 767 /**
mbed_official 133:d4dda5c437f0 768 * @brief Returns the SDRAM memory current mode.
mbed_official 133:d4dda5c437f0 769 * @param hsdram: SDRAM handle
mbed_official 133:d4dda5c437f0 770 * @retval The SDRAM memory mode.
mbed_official 133:d4dda5c437f0 771 */
mbed_official 133:d4dda5c437f0 772 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
mbed_official 133:d4dda5c437f0 773 {
mbed_official 133:d4dda5c437f0 774 /* Return the SDRAM memory current mode */
mbed_official 133:d4dda5c437f0 775 return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
mbed_official 133:d4dda5c437f0 776 }
mbed_official 133:d4dda5c437f0 777
mbed_official 133:d4dda5c437f0 778 /**
mbed_official 133:d4dda5c437f0 779 * @}
mbed_official 133:d4dda5c437f0 780 */
mbed_official 133:d4dda5c437f0 781
mbed_official 133:d4dda5c437f0 782 /** @defgroup SDRAM_Group4 State functions
mbed_official 133:d4dda5c437f0 783 * @brief Peripheral State functions
mbed_official 133:d4dda5c437f0 784 *
mbed_official 133:d4dda5c437f0 785 @verbatim
mbed_official 133:d4dda5c437f0 786 ==============================================================================
mbed_official 133:d4dda5c437f0 787 ##### SDRAM State functions #####
mbed_official 133:d4dda5c437f0 788 ==============================================================================
mbed_official 133:d4dda5c437f0 789 [..]
mbed_official 133:d4dda5c437f0 790 This subsection permits to get in run-time the status of the SDRAM controller
mbed_official 133:d4dda5c437f0 791 and the data flow.
mbed_official 133:d4dda5c437f0 792
mbed_official 133:d4dda5c437f0 793 @endverbatim
mbed_official 133:d4dda5c437f0 794 * @{
mbed_official 133:d4dda5c437f0 795 */
mbed_official 133:d4dda5c437f0 796
mbed_official 133:d4dda5c437f0 797 /**
mbed_official 133:d4dda5c437f0 798 * @brief Returns the SDRAM state.
mbed_official 133:d4dda5c437f0 799 * @param hsdram: SDRAM handle
mbed_official 133:d4dda5c437f0 800 * @retval HAL state
mbed_official 133:d4dda5c437f0 801 */
mbed_official 133:d4dda5c437f0 802 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
mbed_official 133:d4dda5c437f0 803 {
mbed_official 133:d4dda5c437f0 804 return hsdram->State;
mbed_official 133:d4dda5c437f0 805 }
mbed_official 133:d4dda5c437f0 806
mbed_official 133:d4dda5c437f0 807 /**
mbed_official 133:d4dda5c437f0 808 * @}
mbed_official 133:d4dda5c437f0 809 */
mbed_official 133:d4dda5c437f0 810
mbed_official 133:d4dda5c437f0 811 /**
mbed_official 133:d4dda5c437f0 812 * @}
mbed_official 133:d4dda5c437f0 813 */
mbed_official 133:d4dda5c437f0 814 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 133:d4dda5c437f0 815 #endif /* HAL_SDRAM_MODULE_ENABLED */
mbed_official 133:d4dda5c437f0 816 /**
mbed_official 133:d4dda5c437f0 817 * @}
mbed_official 133:d4dda5c437f0 818 */
mbed_official 133:d4dda5c437f0 819
mbed_official 133:d4dda5c437f0 820 /**
mbed_official 133:d4dda5c437f0 821 * @}
mbed_official 133:d4dda5c437f0 822 */
mbed_official 133:d4dda5c437f0 823
mbed_official 133:d4dda5c437f0 824 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/