shao ziyang
mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of
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mbed official
targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_fsmc.c@323:9e901b0a5aa1, 2014-09-13 (annotated)
- Committer:
- shaoziyang
- Date:
- Sat Sep 13 14:25:46 2014 +0000
- Revision:
- 323:9e901b0a5aa1
- Parent:
- 126:549ba18ddd81
test with CLOCK_SETUP = 0
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 126:549ba18ddd81 | 1 | /** |
| mbed_official | 126:549ba18ddd81 | 2 | ****************************************************************************** |
| mbed_official | 126:549ba18ddd81 | 3 | * @file stm32f10x_fsmc.c |
| mbed_official | 126:549ba18ddd81 | 4 | * @author MCD Application Team |
| mbed_official | 126:549ba18ddd81 | 5 | * @version V3.6.1 |
| mbed_official | 126:549ba18ddd81 | 6 | * @date 05-March-2012 |
| mbed_official | 126:549ba18ddd81 | 7 | * @brief This file provides all the FSMC firmware functions. |
| mbed_official | 126:549ba18ddd81 | 8 | ******************************************************************************* |
| mbed_official | 126:549ba18ddd81 | 9 | * Copyright (c) 2014, STMicroelectronics |
| mbed_official | 126:549ba18ddd81 | 10 | * All rights reserved. |
| mbed_official | 126:549ba18ddd81 | 11 | * |
| mbed_official | 126:549ba18ddd81 | 12 | * Redistribution and use in source and binary forms, with or without |
| mbed_official | 126:549ba18ddd81 | 13 | * modification, are permitted provided that the following conditions are met: |
| mbed_official | 126:549ba18ddd81 | 14 | * |
| mbed_official | 126:549ba18ddd81 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 126:549ba18ddd81 | 16 | * this list of conditions and the following disclaimer. |
| mbed_official | 126:549ba18ddd81 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 126:549ba18ddd81 | 18 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 126:549ba18ddd81 | 19 | * and/or other materials provided with the distribution. |
| mbed_official | 126:549ba18ddd81 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 126:549ba18ddd81 | 21 | * may be used to endorse or promote products derived from this software |
| mbed_official | 126:549ba18ddd81 | 22 | * without specific prior written permission. |
| mbed_official | 126:549ba18ddd81 | 23 | * |
| mbed_official | 126:549ba18ddd81 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 126:549ba18ddd81 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 126:549ba18ddd81 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 126:549ba18ddd81 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 126:549ba18ddd81 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 126:549ba18ddd81 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 126:549ba18ddd81 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 126:549ba18ddd81 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 126:549ba18ddd81 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 126:549ba18ddd81 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 126:549ba18ddd81 | 34 | ******************************************************************************* |
| mbed_official | 126:549ba18ddd81 | 35 | */ |
| mbed_official | 126:549ba18ddd81 | 36 | |
| mbed_official | 126:549ba18ddd81 | 37 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 126:549ba18ddd81 | 38 | #include "stm32f10x_fsmc.h" |
| mbed_official | 126:549ba18ddd81 | 39 | #include "stm32f10x_rcc.h" |
| mbed_official | 126:549ba18ddd81 | 40 | |
| mbed_official | 126:549ba18ddd81 | 41 | /** @addtogroup STM32F10x_StdPeriph_Driver |
| mbed_official | 126:549ba18ddd81 | 42 | * @{ |
| mbed_official | 126:549ba18ddd81 | 43 | */ |
| mbed_official | 126:549ba18ddd81 | 44 | |
| mbed_official | 126:549ba18ddd81 | 45 | /** @defgroup FSMC |
| mbed_official | 126:549ba18ddd81 | 46 | * @brief FSMC driver modules |
| mbed_official | 126:549ba18ddd81 | 47 | * @{ |
| mbed_official | 126:549ba18ddd81 | 48 | */ |
| mbed_official | 126:549ba18ddd81 | 49 | |
| mbed_official | 126:549ba18ddd81 | 50 | /** @defgroup FSMC_Private_TypesDefinitions |
| mbed_official | 126:549ba18ddd81 | 51 | * @{ |
| mbed_official | 126:549ba18ddd81 | 52 | */ |
| mbed_official | 126:549ba18ddd81 | 53 | /** |
| mbed_official | 126:549ba18ddd81 | 54 | * @} |
| mbed_official | 126:549ba18ddd81 | 55 | */ |
| mbed_official | 126:549ba18ddd81 | 56 | |
| mbed_official | 126:549ba18ddd81 | 57 | /** @defgroup FSMC_Private_Defines |
| mbed_official | 126:549ba18ddd81 | 58 | * @{ |
| mbed_official | 126:549ba18ddd81 | 59 | */ |
| mbed_official | 126:549ba18ddd81 | 60 | |
| mbed_official | 126:549ba18ddd81 | 61 | /* --------------------- FSMC registers bit mask ---------------------------- */ |
| mbed_official | 126:549ba18ddd81 | 62 | |
| mbed_official | 126:549ba18ddd81 | 63 | /* FSMC BCRx Mask */ |
| mbed_official | 126:549ba18ddd81 | 64 | #define BCR_MBKEN_Set ((uint32_t)0x00000001) |
| mbed_official | 126:549ba18ddd81 | 65 | #define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) |
| mbed_official | 126:549ba18ddd81 | 66 | #define BCR_FACCEN_Set ((uint32_t)0x00000040) |
| mbed_official | 126:549ba18ddd81 | 67 | |
| mbed_official | 126:549ba18ddd81 | 68 | /* FSMC PCRx Mask */ |
| mbed_official | 126:549ba18ddd81 | 69 | #define PCR_PBKEN_Set ((uint32_t)0x00000004) |
| mbed_official | 126:549ba18ddd81 | 70 | #define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) |
| mbed_official | 126:549ba18ddd81 | 71 | #define PCR_ECCEN_Set ((uint32_t)0x00000040) |
| mbed_official | 126:549ba18ddd81 | 72 | #define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) |
| mbed_official | 126:549ba18ddd81 | 73 | #define PCR_MemoryType_NAND ((uint32_t)0x00000008) |
| mbed_official | 126:549ba18ddd81 | 74 | /** |
| mbed_official | 126:549ba18ddd81 | 75 | * @} |
| mbed_official | 126:549ba18ddd81 | 76 | */ |
| mbed_official | 126:549ba18ddd81 | 77 | |
| mbed_official | 126:549ba18ddd81 | 78 | /** @defgroup FSMC_Private_Macros |
| mbed_official | 126:549ba18ddd81 | 79 | * @{ |
| mbed_official | 126:549ba18ddd81 | 80 | */ |
| mbed_official | 126:549ba18ddd81 | 81 | |
| mbed_official | 126:549ba18ddd81 | 82 | /** |
| mbed_official | 126:549ba18ddd81 | 83 | * @} |
| mbed_official | 126:549ba18ddd81 | 84 | */ |
| mbed_official | 126:549ba18ddd81 | 85 | |
| mbed_official | 126:549ba18ddd81 | 86 | /** @defgroup FSMC_Private_Variables |
| mbed_official | 126:549ba18ddd81 | 87 | * @{ |
| mbed_official | 126:549ba18ddd81 | 88 | */ |
| mbed_official | 126:549ba18ddd81 | 89 | |
| mbed_official | 126:549ba18ddd81 | 90 | /** |
| mbed_official | 126:549ba18ddd81 | 91 | * @} |
| mbed_official | 126:549ba18ddd81 | 92 | */ |
| mbed_official | 126:549ba18ddd81 | 93 | |
| mbed_official | 126:549ba18ddd81 | 94 | /** @defgroup FSMC_Private_FunctionPrototypes |
| mbed_official | 126:549ba18ddd81 | 95 | * @{ |
| mbed_official | 126:549ba18ddd81 | 96 | */ |
| mbed_official | 126:549ba18ddd81 | 97 | |
| mbed_official | 126:549ba18ddd81 | 98 | /** |
| mbed_official | 126:549ba18ddd81 | 99 | * @} |
| mbed_official | 126:549ba18ddd81 | 100 | */ |
| mbed_official | 126:549ba18ddd81 | 101 | |
| mbed_official | 126:549ba18ddd81 | 102 | /** @defgroup FSMC_Private_Functions |
| mbed_official | 126:549ba18ddd81 | 103 | * @{ |
| mbed_official | 126:549ba18ddd81 | 104 | */ |
| mbed_official | 126:549ba18ddd81 | 105 | |
| mbed_official | 126:549ba18ddd81 | 106 | /** |
| mbed_official | 126:549ba18ddd81 | 107 | * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default |
| mbed_official | 126:549ba18ddd81 | 108 | * reset values. |
| mbed_official | 126:549ba18ddd81 | 109 | * @param FSMC_Bank: specifies the FSMC Bank to be used |
| mbed_official | 126:549ba18ddd81 | 110 | * This parameter can be one of the following values: |
| mbed_official | 126:549ba18ddd81 | 111 | * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 |
| mbed_official | 126:549ba18ddd81 | 112 | * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 |
| mbed_official | 126:549ba18ddd81 | 113 | * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 |
| mbed_official | 126:549ba18ddd81 | 114 | * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 |
| mbed_official | 126:549ba18ddd81 | 115 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 116 | */ |
| mbed_official | 126:549ba18ddd81 | 117 | void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) |
| mbed_official | 126:549ba18ddd81 | 118 | { |
| mbed_official | 126:549ba18ddd81 | 119 | /* Check the parameter */ |
| mbed_official | 126:549ba18ddd81 | 120 | assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); |
| mbed_official | 126:549ba18ddd81 | 121 | |
| mbed_official | 126:549ba18ddd81 | 122 | /* FSMC_Bank1_NORSRAM1 */ |
| mbed_official | 126:549ba18ddd81 | 123 | if(FSMC_Bank == FSMC_Bank1_NORSRAM1) |
| mbed_official | 126:549ba18ddd81 | 124 | { |
| mbed_official | 126:549ba18ddd81 | 125 | FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; |
| mbed_official | 126:549ba18ddd81 | 126 | } |
| mbed_official | 126:549ba18ddd81 | 127 | /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ |
| mbed_official | 126:549ba18ddd81 | 128 | else |
| mbed_official | 126:549ba18ddd81 | 129 | { |
| mbed_official | 126:549ba18ddd81 | 130 | FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; |
| mbed_official | 126:549ba18ddd81 | 131 | } |
| mbed_official | 126:549ba18ddd81 | 132 | FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; |
| mbed_official | 126:549ba18ddd81 | 133 | FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; |
| mbed_official | 126:549ba18ddd81 | 134 | } |
| mbed_official | 126:549ba18ddd81 | 135 | |
| mbed_official | 126:549ba18ddd81 | 136 | /** |
| mbed_official | 126:549ba18ddd81 | 137 | * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. |
| mbed_official | 126:549ba18ddd81 | 138 | * @param FSMC_Bank: specifies the FSMC Bank to be used |
| mbed_official | 126:549ba18ddd81 | 139 | * This parameter can be one of the following values: |
| mbed_official | 126:549ba18ddd81 | 140 | * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND |
| mbed_official | 126:549ba18ddd81 | 141 | * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND |
| mbed_official | 126:549ba18ddd81 | 142 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 143 | */ |
| mbed_official | 126:549ba18ddd81 | 144 | void FSMC_NANDDeInit(uint32_t FSMC_Bank) |
| mbed_official | 126:549ba18ddd81 | 145 | { |
| mbed_official | 126:549ba18ddd81 | 146 | /* Check the parameter */ |
| mbed_official | 126:549ba18ddd81 | 147 | assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); |
| mbed_official | 126:549ba18ddd81 | 148 | |
| mbed_official | 126:549ba18ddd81 | 149 | if(FSMC_Bank == FSMC_Bank2_NAND) |
| mbed_official | 126:549ba18ddd81 | 150 | { |
| mbed_official | 126:549ba18ddd81 | 151 | /* Set the FSMC_Bank2 registers to their reset values */ |
| mbed_official | 126:549ba18ddd81 | 152 | FSMC_Bank2->PCR2 = 0x00000018; |
| mbed_official | 126:549ba18ddd81 | 153 | FSMC_Bank2->SR2 = 0x00000040; |
| mbed_official | 126:549ba18ddd81 | 154 | FSMC_Bank2->PMEM2 = 0xFCFCFCFC; |
| mbed_official | 126:549ba18ddd81 | 155 | FSMC_Bank2->PATT2 = 0xFCFCFCFC; |
| mbed_official | 126:549ba18ddd81 | 156 | } |
| mbed_official | 126:549ba18ddd81 | 157 | /* FSMC_Bank3_NAND */ |
| mbed_official | 126:549ba18ddd81 | 158 | else |
| mbed_official | 126:549ba18ddd81 | 159 | { |
| mbed_official | 126:549ba18ddd81 | 160 | /* Set the FSMC_Bank3 registers to their reset values */ |
| mbed_official | 126:549ba18ddd81 | 161 | FSMC_Bank3->PCR3 = 0x00000018; |
| mbed_official | 126:549ba18ddd81 | 162 | FSMC_Bank3->SR3 = 0x00000040; |
| mbed_official | 126:549ba18ddd81 | 163 | FSMC_Bank3->PMEM3 = 0xFCFCFCFC; |
| mbed_official | 126:549ba18ddd81 | 164 | FSMC_Bank3->PATT3 = 0xFCFCFCFC; |
| mbed_official | 126:549ba18ddd81 | 165 | } |
| mbed_official | 126:549ba18ddd81 | 166 | } |
| mbed_official | 126:549ba18ddd81 | 167 | |
| mbed_official | 126:549ba18ddd81 | 168 | /** |
| mbed_official | 126:549ba18ddd81 | 169 | * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. |
| mbed_official | 126:549ba18ddd81 | 170 | * @param None |
| mbed_official | 126:549ba18ddd81 | 171 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 172 | */ |
| mbed_official | 126:549ba18ddd81 | 173 | void FSMC_PCCARDDeInit(void) |
| mbed_official | 126:549ba18ddd81 | 174 | { |
| mbed_official | 126:549ba18ddd81 | 175 | /* Set the FSMC_Bank4 registers to their reset values */ |
| mbed_official | 126:549ba18ddd81 | 176 | FSMC_Bank4->PCR4 = 0x00000018; |
| mbed_official | 126:549ba18ddd81 | 177 | FSMC_Bank4->SR4 = 0x00000000; |
| mbed_official | 126:549ba18ddd81 | 178 | FSMC_Bank4->PMEM4 = 0xFCFCFCFC; |
| mbed_official | 126:549ba18ddd81 | 179 | FSMC_Bank4->PATT4 = 0xFCFCFCFC; |
| mbed_official | 126:549ba18ddd81 | 180 | FSMC_Bank4->PIO4 = 0xFCFCFCFC; |
| mbed_official | 126:549ba18ddd81 | 181 | } |
| mbed_official | 126:549ba18ddd81 | 182 | |
| mbed_official | 126:549ba18ddd81 | 183 | /** |
| mbed_official | 126:549ba18ddd81 | 184 | * @brief Initializes the FSMC NOR/SRAM Banks according to the specified |
| mbed_official | 126:549ba18ddd81 | 185 | * parameters in the FSMC_NORSRAMInitStruct. |
| mbed_official | 126:549ba18ddd81 | 186 | * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef |
| mbed_official | 126:549ba18ddd81 | 187 | * structure that contains the configuration information for |
| mbed_official | 126:549ba18ddd81 | 188 | * the FSMC NOR/SRAM specified Banks. |
| mbed_official | 126:549ba18ddd81 | 189 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 190 | */ |
| mbed_official | 126:549ba18ddd81 | 191 | void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) |
| mbed_official | 126:549ba18ddd81 | 192 | { |
| mbed_official | 126:549ba18ddd81 | 193 | /* Check the parameters */ |
| mbed_official | 126:549ba18ddd81 | 194 | assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); |
| mbed_official | 126:549ba18ddd81 | 195 | assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); |
| mbed_official | 126:549ba18ddd81 | 196 | assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); |
| mbed_official | 126:549ba18ddd81 | 197 | assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); |
| mbed_official | 126:549ba18ddd81 | 198 | assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); |
| mbed_official | 126:549ba18ddd81 | 199 | assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); |
| mbed_official | 126:549ba18ddd81 | 200 | assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); |
| mbed_official | 126:549ba18ddd81 | 201 | assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); |
| mbed_official | 126:549ba18ddd81 | 202 | assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); |
| mbed_official | 126:549ba18ddd81 | 203 | assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); |
| mbed_official | 126:549ba18ddd81 | 204 | assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); |
| mbed_official | 126:549ba18ddd81 | 205 | assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); |
| mbed_official | 126:549ba18ddd81 | 206 | assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); |
| mbed_official | 126:549ba18ddd81 | 207 | assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 208 | assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); |
| mbed_official | 126:549ba18ddd81 | 209 | assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 210 | assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); |
| mbed_official | 126:549ba18ddd81 | 211 | assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); |
| mbed_official | 126:549ba18ddd81 | 212 | assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); |
| mbed_official | 126:549ba18ddd81 | 213 | assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); |
| mbed_official | 126:549ba18ddd81 | 214 | |
| mbed_official | 126:549ba18ddd81 | 215 | /* Bank1 NOR/SRAM control register configuration */ |
| mbed_official | 126:549ba18ddd81 | 216 | FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = |
| mbed_official | 126:549ba18ddd81 | 217 | (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | |
| mbed_official | 126:549ba18ddd81 | 218 | FSMC_NORSRAMInitStruct->FSMC_MemoryType | |
| mbed_official | 126:549ba18ddd81 | 219 | FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | |
| mbed_official | 126:549ba18ddd81 | 220 | FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | |
| mbed_official | 126:549ba18ddd81 | 221 | FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | |
| mbed_official | 126:549ba18ddd81 | 222 | FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | |
| mbed_official | 126:549ba18ddd81 | 223 | FSMC_NORSRAMInitStruct->FSMC_WrapMode | |
| mbed_official | 126:549ba18ddd81 | 224 | FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | |
| mbed_official | 126:549ba18ddd81 | 225 | FSMC_NORSRAMInitStruct->FSMC_WriteOperation | |
| mbed_official | 126:549ba18ddd81 | 226 | FSMC_NORSRAMInitStruct->FSMC_WaitSignal | |
| mbed_official | 126:549ba18ddd81 | 227 | FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | |
| mbed_official | 126:549ba18ddd81 | 228 | FSMC_NORSRAMInitStruct->FSMC_WriteBurst; |
| mbed_official | 126:549ba18ddd81 | 229 | |
| mbed_official | 126:549ba18ddd81 | 230 | if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) |
| mbed_official | 126:549ba18ddd81 | 231 | { |
| mbed_official | 126:549ba18ddd81 | 232 | FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; |
| mbed_official | 126:549ba18ddd81 | 233 | } |
| mbed_official | 126:549ba18ddd81 | 234 | |
| mbed_official | 126:549ba18ddd81 | 235 | /* Bank1 NOR/SRAM timing register configuration */ |
| mbed_official | 126:549ba18ddd81 | 236 | FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = |
| mbed_official | 126:549ba18ddd81 | 237 | (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | |
| mbed_official | 126:549ba18ddd81 | 238 | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | |
| mbed_official | 126:549ba18ddd81 | 239 | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | |
| mbed_official | 126:549ba18ddd81 | 240 | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | |
| mbed_official | 126:549ba18ddd81 | 241 | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | |
| mbed_official | 126:549ba18ddd81 | 242 | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | |
| mbed_official | 126:549ba18ddd81 | 243 | FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; |
| mbed_official | 126:549ba18ddd81 | 244 | |
| mbed_official | 126:549ba18ddd81 | 245 | |
| mbed_official | 126:549ba18ddd81 | 246 | /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ |
| mbed_official | 126:549ba18ddd81 | 247 | if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) |
| mbed_official | 126:549ba18ddd81 | 248 | { |
| mbed_official | 126:549ba18ddd81 | 249 | assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 250 | assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); |
| mbed_official | 126:549ba18ddd81 | 251 | assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 252 | assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); |
| mbed_official | 126:549ba18ddd81 | 253 | assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); |
| mbed_official | 126:549ba18ddd81 | 254 | assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); |
| mbed_official | 126:549ba18ddd81 | 255 | FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = |
| mbed_official | 126:549ba18ddd81 | 256 | (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | |
| mbed_official | 126:549ba18ddd81 | 257 | (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| |
| mbed_official | 126:549ba18ddd81 | 258 | (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | |
| mbed_official | 126:549ba18ddd81 | 259 | (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | |
| mbed_official | 126:549ba18ddd81 | 260 | (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | |
| mbed_official | 126:549ba18ddd81 | 261 | FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; |
| mbed_official | 126:549ba18ddd81 | 262 | } |
| mbed_official | 126:549ba18ddd81 | 263 | else |
| mbed_official | 126:549ba18ddd81 | 264 | { |
| mbed_official | 126:549ba18ddd81 | 265 | FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; |
| mbed_official | 126:549ba18ddd81 | 266 | } |
| mbed_official | 126:549ba18ddd81 | 267 | } |
| mbed_official | 126:549ba18ddd81 | 268 | |
| mbed_official | 126:549ba18ddd81 | 269 | /** |
| mbed_official | 126:549ba18ddd81 | 270 | * @brief Initializes the FSMC NAND Banks according to the specified |
| mbed_official | 126:549ba18ddd81 | 271 | * parameters in the FSMC_NANDInitStruct. |
| mbed_official | 126:549ba18ddd81 | 272 | * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef |
| mbed_official | 126:549ba18ddd81 | 273 | * structure that contains the configuration information for the FSMC |
| mbed_official | 126:549ba18ddd81 | 274 | * NAND specified Banks. |
| mbed_official | 126:549ba18ddd81 | 275 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 276 | */ |
| mbed_official | 126:549ba18ddd81 | 277 | void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) |
| mbed_official | 126:549ba18ddd81 | 278 | { |
| mbed_official | 126:549ba18ddd81 | 279 | uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; |
| mbed_official | 126:549ba18ddd81 | 280 | |
| mbed_official | 126:549ba18ddd81 | 281 | /* Check the parameters */ |
| mbed_official | 126:549ba18ddd81 | 282 | assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); |
| mbed_official | 126:549ba18ddd81 | 283 | assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); |
| mbed_official | 126:549ba18ddd81 | 284 | assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); |
| mbed_official | 126:549ba18ddd81 | 285 | assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); |
| mbed_official | 126:549ba18ddd81 | 286 | assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); |
| mbed_official | 126:549ba18ddd81 | 287 | assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 288 | assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 289 | assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); |
| mbed_official | 126:549ba18ddd81 | 290 | assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 291 | assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 292 | assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 293 | assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); |
| mbed_official | 126:549ba18ddd81 | 294 | assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 295 | assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 296 | assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 297 | |
| mbed_official | 126:549ba18ddd81 | 298 | /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ |
| mbed_official | 126:549ba18ddd81 | 299 | tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | |
| mbed_official | 126:549ba18ddd81 | 300 | PCR_MemoryType_NAND | |
| mbed_official | 126:549ba18ddd81 | 301 | FSMC_NANDInitStruct->FSMC_MemoryDataWidth | |
| mbed_official | 126:549ba18ddd81 | 302 | FSMC_NANDInitStruct->FSMC_ECC | |
| mbed_official | 126:549ba18ddd81 | 303 | FSMC_NANDInitStruct->FSMC_ECCPageSize | |
| mbed_official | 126:549ba18ddd81 | 304 | (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| |
| mbed_official | 126:549ba18ddd81 | 305 | (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); |
| mbed_official | 126:549ba18ddd81 | 306 | |
| mbed_official | 126:549ba18ddd81 | 307 | /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ |
| mbed_official | 126:549ba18ddd81 | 308 | tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | |
| mbed_official | 126:549ba18ddd81 | 309 | (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | |
| mbed_official | 126:549ba18ddd81 | 310 | (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| |
| mbed_official | 126:549ba18ddd81 | 311 | (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); |
| mbed_official | 126:549ba18ddd81 | 312 | |
| mbed_official | 126:549ba18ddd81 | 313 | /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ |
| mbed_official | 126:549ba18ddd81 | 314 | tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | |
| mbed_official | 126:549ba18ddd81 | 315 | (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | |
| mbed_official | 126:549ba18ddd81 | 316 | (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| |
| mbed_official | 126:549ba18ddd81 | 317 | (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); |
| mbed_official | 126:549ba18ddd81 | 318 | |
| mbed_official | 126:549ba18ddd81 | 319 | if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) |
| mbed_official | 126:549ba18ddd81 | 320 | { |
| mbed_official | 126:549ba18ddd81 | 321 | /* FSMC_Bank2_NAND registers configuration */ |
| mbed_official | 126:549ba18ddd81 | 322 | FSMC_Bank2->PCR2 = tmppcr; |
| mbed_official | 126:549ba18ddd81 | 323 | FSMC_Bank2->PMEM2 = tmppmem; |
| mbed_official | 126:549ba18ddd81 | 324 | FSMC_Bank2->PATT2 = tmppatt; |
| mbed_official | 126:549ba18ddd81 | 325 | } |
| mbed_official | 126:549ba18ddd81 | 326 | else |
| mbed_official | 126:549ba18ddd81 | 327 | { |
| mbed_official | 126:549ba18ddd81 | 328 | /* FSMC_Bank3_NAND registers configuration */ |
| mbed_official | 126:549ba18ddd81 | 329 | FSMC_Bank3->PCR3 = tmppcr; |
| mbed_official | 126:549ba18ddd81 | 330 | FSMC_Bank3->PMEM3 = tmppmem; |
| mbed_official | 126:549ba18ddd81 | 331 | FSMC_Bank3->PATT3 = tmppatt; |
| mbed_official | 126:549ba18ddd81 | 332 | } |
| mbed_official | 126:549ba18ddd81 | 333 | } |
| mbed_official | 126:549ba18ddd81 | 334 | |
| mbed_official | 126:549ba18ddd81 | 335 | /** |
| mbed_official | 126:549ba18ddd81 | 336 | * @brief Initializes the FSMC PCCARD Bank according to the specified |
| mbed_official | 126:549ba18ddd81 | 337 | * parameters in the FSMC_PCCARDInitStruct. |
| mbed_official | 126:549ba18ddd81 | 338 | * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef |
| mbed_official | 126:549ba18ddd81 | 339 | * structure that contains the configuration information for the FSMC |
| mbed_official | 126:549ba18ddd81 | 340 | * PCCARD Bank. |
| mbed_official | 126:549ba18ddd81 | 341 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 342 | */ |
| mbed_official | 126:549ba18ddd81 | 343 | void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) |
| mbed_official | 126:549ba18ddd81 | 344 | { |
| mbed_official | 126:549ba18ddd81 | 345 | /* Check the parameters */ |
| mbed_official | 126:549ba18ddd81 | 346 | assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); |
| mbed_official | 126:549ba18ddd81 | 347 | assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 348 | assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 349 | |
| mbed_official | 126:549ba18ddd81 | 350 | assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); |
| mbed_official | 126:549ba18ddd81 | 351 | assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 352 | assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 353 | assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 354 | |
| mbed_official | 126:549ba18ddd81 | 355 | assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); |
| mbed_official | 126:549ba18ddd81 | 356 | assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 357 | assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 358 | assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 359 | assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); |
| mbed_official | 126:549ba18ddd81 | 360 | assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 361 | assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 362 | assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); |
| mbed_official | 126:549ba18ddd81 | 363 | |
| mbed_official | 126:549ba18ddd81 | 364 | /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ |
| mbed_official | 126:549ba18ddd81 | 365 | FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | |
| mbed_official | 126:549ba18ddd81 | 366 | FSMC_MemoryDataWidth_16b | |
| mbed_official | 126:549ba18ddd81 | 367 | (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | |
| mbed_official | 126:549ba18ddd81 | 368 | (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); |
| mbed_official | 126:549ba18ddd81 | 369 | |
| mbed_official | 126:549ba18ddd81 | 370 | /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ |
| mbed_official | 126:549ba18ddd81 | 371 | FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | |
| mbed_official | 126:549ba18ddd81 | 372 | (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | |
| mbed_official | 126:549ba18ddd81 | 373 | (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| |
| mbed_official | 126:549ba18ddd81 | 374 | (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); |
| mbed_official | 126:549ba18ddd81 | 375 | |
| mbed_official | 126:549ba18ddd81 | 376 | /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ |
| mbed_official | 126:549ba18ddd81 | 377 | FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | |
| mbed_official | 126:549ba18ddd81 | 378 | (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | |
| mbed_official | 126:549ba18ddd81 | 379 | (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| |
| mbed_official | 126:549ba18ddd81 | 380 | (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); |
| mbed_official | 126:549ba18ddd81 | 381 | |
| mbed_official | 126:549ba18ddd81 | 382 | /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ |
| mbed_official | 126:549ba18ddd81 | 383 | FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | |
| mbed_official | 126:549ba18ddd81 | 384 | (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | |
| mbed_official | 126:549ba18ddd81 | 385 | (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| |
| mbed_official | 126:549ba18ddd81 | 386 | (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); |
| mbed_official | 126:549ba18ddd81 | 387 | } |
| mbed_official | 126:549ba18ddd81 | 388 | |
| mbed_official | 126:549ba18ddd81 | 389 | /** |
| mbed_official | 126:549ba18ddd81 | 390 | * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. |
| mbed_official | 126:549ba18ddd81 | 391 | * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef |
| mbed_official | 126:549ba18ddd81 | 392 | * structure which will be initialized. |
| mbed_official | 126:549ba18ddd81 | 393 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 394 | */ |
| mbed_official | 126:549ba18ddd81 | 395 | void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) |
| mbed_official | 126:549ba18ddd81 | 396 | { |
| mbed_official | 126:549ba18ddd81 | 397 | /* Reset NOR/SRAM Init structure parameters values */ |
| mbed_official | 126:549ba18ddd81 | 398 | FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; |
| mbed_official | 126:549ba18ddd81 | 399 | FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; |
| mbed_official | 126:549ba18ddd81 | 400 | FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; |
| mbed_official | 126:549ba18ddd81 | 401 | FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; |
| mbed_official | 126:549ba18ddd81 | 402 | FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; |
| mbed_official | 126:549ba18ddd81 | 403 | FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; |
| mbed_official | 126:549ba18ddd81 | 404 | FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; |
| mbed_official | 126:549ba18ddd81 | 405 | FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; |
| mbed_official | 126:549ba18ddd81 | 406 | FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; |
| mbed_official | 126:549ba18ddd81 | 407 | FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; |
| mbed_official | 126:549ba18ddd81 | 408 | FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; |
| mbed_official | 126:549ba18ddd81 | 409 | FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; |
| mbed_official | 126:549ba18ddd81 | 410 | FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; |
| mbed_official | 126:549ba18ddd81 | 411 | FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; |
| mbed_official | 126:549ba18ddd81 | 412 | FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; |
| mbed_official | 126:549ba18ddd81 | 413 | FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; |
| mbed_official | 126:549ba18ddd81 | 414 | FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; |
| mbed_official | 126:549ba18ddd81 | 415 | FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; |
| mbed_official | 126:549ba18ddd81 | 416 | FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; |
| mbed_official | 126:549ba18ddd81 | 417 | FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; |
| mbed_official | 126:549ba18ddd81 | 418 | FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; |
| mbed_official | 126:549ba18ddd81 | 419 | FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; |
| mbed_official | 126:549ba18ddd81 | 420 | FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; |
| mbed_official | 126:549ba18ddd81 | 421 | FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; |
| mbed_official | 126:549ba18ddd81 | 422 | FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; |
| mbed_official | 126:549ba18ddd81 | 423 | FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; |
| mbed_official | 126:549ba18ddd81 | 424 | FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; |
| mbed_official | 126:549ba18ddd81 | 425 | } |
| mbed_official | 126:549ba18ddd81 | 426 | |
| mbed_official | 126:549ba18ddd81 | 427 | /** |
| mbed_official | 126:549ba18ddd81 | 428 | * @brief Fills each FSMC_NANDInitStruct member with its default value. |
| mbed_official | 126:549ba18ddd81 | 429 | * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef |
| mbed_official | 126:549ba18ddd81 | 430 | * structure which will be initialized. |
| mbed_official | 126:549ba18ddd81 | 431 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 432 | */ |
| mbed_official | 126:549ba18ddd81 | 433 | void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) |
| mbed_official | 126:549ba18ddd81 | 434 | { |
| mbed_official | 126:549ba18ddd81 | 435 | /* Reset NAND Init structure parameters values */ |
| mbed_official | 126:549ba18ddd81 | 436 | FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; |
| mbed_official | 126:549ba18ddd81 | 437 | FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; |
| mbed_official | 126:549ba18ddd81 | 438 | FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; |
| mbed_official | 126:549ba18ddd81 | 439 | FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; |
| mbed_official | 126:549ba18ddd81 | 440 | FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; |
| mbed_official | 126:549ba18ddd81 | 441 | FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; |
| mbed_official | 126:549ba18ddd81 | 442 | FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; |
| mbed_official | 126:549ba18ddd81 | 443 | FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; |
| mbed_official | 126:549ba18ddd81 | 444 | FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; |
| mbed_official | 126:549ba18ddd81 | 445 | FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; |
| mbed_official | 126:549ba18ddd81 | 446 | FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; |
| mbed_official | 126:549ba18ddd81 | 447 | FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; |
| mbed_official | 126:549ba18ddd81 | 448 | FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; |
| mbed_official | 126:549ba18ddd81 | 449 | FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; |
| mbed_official | 126:549ba18ddd81 | 450 | FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; |
| mbed_official | 126:549ba18ddd81 | 451 | } |
| mbed_official | 126:549ba18ddd81 | 452 | |
| mbed_official | 126:549ba18ddd81 | 453 | /** |
| mbed_official | 126:549ba18ddd81 | 454 | * @brief Fills each FSMC_PCCARDInitStruct member with its default value. |
| mbed_official | 126:549ba18ddd81 | 455 | * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef |
| mbed_official | 126:549ba18ddd81 | 456 | * structure which will be initialized. |
| mbed_official | 126:549ba18ddd81 | 457 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 458 | */ |
| mbed_official | 126:549ba18ddd81 | 459 | void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) |
| mbed_official | 126:549ba18ddd81 | 460 | { |
| mbed_official | 126:549ba18ddd81 | 461 | /* Reset PCCARD Init structure parameters values */ |
| mbed_official | 126:549ba18ddd81 | 462 | FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; |
| mbed_official | 126:549ba18ddd81 | 463 | FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; |
| mbed_official | 126:549ba18ddd81 | 464 | FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; |
| mbed_official | 126:549ba18ddd81 | 465 | FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; |
| mbed_official | 126:549ba18ddd81 | 466 | FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; |
| mbed_official | 126:549ba18ddd81 | 467 | FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; |
| mbed_official | 126:549ba18ddd81 | 468 | FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; |
| mbed_official | 126:549ba18ddd81 | 469 | FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; |
| mbed_official | 126:549ba18ddd81 | 470 | FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; |
| mbed_official | 126:549ba18ddd81 | 471 | FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; |
| mbed_official | 126:549ba18ddd81 | 472 | FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; |
| mbed_official | 126:549ba18ddd81 | 473 | FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; |
| mbed_official | 126:549ba18ddd81 | 474 | FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; |
| mbed_official | 126:549ba18ddd81 | 475 | FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; |
| mbed_official | 126:549ba18ddd81 | 476 | FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; |
| mbed_official | 126:549ba18ddd81 | 477 | } |
| mbed_official | 126:549ba18ddd81 | 478 | |
| mbed_official | 126:549ba18ddd81 | 479 | /** |
| mbed_official | 126:549ba18ddd81 | 480 | * @brief Enables or disables the specified NOR/SRAM Memory Bank. |
| mbed_official | 126:549ba18ddd81 | 481 | * @param FSMC_Bank: specifies the FSMC Bank to be used |
| mbed_official | 126:549ba18ddd81 | 482 | * This parameter can be one of the following values: |
| mbed_official | 126:549ba18ddd81 | 483 | * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 |
| mbed_official | 126:549ba18ddd81 | 484 | * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 |
| mbed_official | 126:549ba18ddd81 | 485 | * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 |
| mbed_official | 126:549ba18ddd81 | 486 | * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 |
| mbed_official | 126:549ba18ddd81 | 487 | * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. |
| mbed_official | 126:549ba18ddd81 | 488 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 489 | */ |
| mbed_official | 126:549ba18ddd81 | 490 | void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) |
| mbed_official | 126:549ba18ddd81 | 491 | { |
| mbed_official | 126:549ba18ddd81 | 492 | assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); |
| mbed_official | 126:549ba18ddd81 | 493 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
| mbed_official | 126:549ba18ddd81 | 494 | |
| mbed_official | 126:549ba18ddd81 | 495 | if (NewState != DISABLE) |
| mbed_official | 126:549ba18ddd81 | 496 | { |
| mbed_official | 126:549ba18ddd81 | 497 | /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ |
| mbed_official | 126:549ba18ddd81 | 498 | FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; |
| mbed_official | 126:549ba18ddd81 | 499 | } |
| mbed_official | 126:549ba18ddd81 | 500 | else |
| mbed_official | 126:549ba18ddd81 | 501 | { |
| mbed_official | 126:549ba18ddd81 | 502 | /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ |
| mbed_official | 126:549ba18ddd81 | 503 | FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; |
| mbed_official | 126:549ba18ddd81 | 504 | } |
| mbed_official | 126:549ba18ddd81 | 505 | } |
| mbed_official | 126:549ba18ddd81 | 506 | |
| mbed_official | 126:549ba18ddd81 | 507 | /** |
| mbed_official | 126:549ba18ddd81 | 508 | * @brief Enables or disables the specified NAND Memory Bank. |
| mbed_official | 126:549ba18ddd81 | 509 | * @param FSMC_Bank: specifies the FSMC Bank to be used |
| mbed_official | 126:549ba18ddd81 | 510 | * This parameter can be one of the following values: |
| mbed_official | 126:549ba18ddd81 | 511 | * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND |
| mbed_official | 126:549ba18ddd81 | 512 | * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND |
| mbed_official | 126:549ba18ddd81 | 513 | * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. |
| mbed_official | 126:549ba18ddd81 | 514 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 515 | */ |
| mbed_official | 126:549ba18ddd81 | 516 | void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) |
| mbed_official | 126:549ba18ddd81 | 517 | { |
| mbed_official | 126:549ba18ddd81 | 518 | assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); |
| mbed_official | 126:549ba18ddd81 | 519 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
| mbed_official | 126:549ba18ddd81 | 520 | |
| mbed_official | 126:549ba18ddd81 | 521 | if (NewState != DISABLE) |
| mbed_official | 126:549ba18ddd81 | 522 | { |
| mbed_official | 126:549ba18ddd81 | 523 | /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ |
| mbed_official | 126:549ba18ddd81 | 524 | if(FSMC_Bank == FSMC_Bank2_NAND) |
| mbed_official | 126:549ba18ddd81 | 525 | { |
| mbed_official | 126:549ba18ddd81 | 526 | FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; |
| mbed_official | 126:549ba18ddd81 | 527 | } |
| mbed_official | 126:549ba18ddd81 | 528 | else |
| mbed_official | 126:549ba18ddd81 | 529 | { |
| mbed_official | 126:549ba18ddd81 | 530 | FSMC_Bank3->PCR3 |= PCR_PBKEN_Set; |
| mbed_official | 126:549ba18ddd81 | 531 | } |
| mbed_official | 126:549ba18ddd81 | 532 | } |
| mbed_official | 126:549ba18ddd81 | 533 | else |
| mbed_official | 126:549ba18ddd81 | 534 | { |
| mbed_official | 126:549ba18ddd81 | 535 | /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ |
| mbed_official | 126:549ba18ddd81 | 536 | if(FSMC_Bank == FSMC_Bank2_NAND) |
| mbed_official | 126:549ba18ddd81 | 537 | { |
| mbed_official | 126:549ba18ddd81 | 538 | FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; |
| mbed_official | 126:549ba18ddd81 | 539 | } |
| mbed_official | 126:549ba18ddd81 | 540 | else |
| mbed_official | 126:549ba18ddd81 | 541 | { |
| mbed_official | 126:549ba18ddd81 | 542 | FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset; |
| mbed_official | 126:549ba18ddd81 | 543 | } |
| mbed_official | 126:549ba18ddd81 | 544 | } |
| mbed_official | 126:549ba18ddd81 | 545 | } |
| mbed_official | 126:549ba18ddd81 | 546 | |
| mbed_official | 126:549ba18ddd81 | 547 | /** |
| mbed_official | 126:549ba18ddd81 | 548 | * @brief Enables or disables the PCCARD Memory Bank. |
| mbed_official | 126:549ba18ddd81 | 549 | * @param NewState: new state of the PCCARD Memory Bank. |
| mbed_official | 126:549ba18ddd81 | 550 | * This parameter can be: ENABLE or DISABLE. |
| mbed_official | 126:549ba18ddd81 | 551 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 552 | */ |
| mbed_official | 126:549ba18ddd81 | 553 | void FSMC_PCCARDCmd(FunctionalState NewState) |
| mbed_official | 126:549ba18ddd81 | 554 | { |
| mbed_official | 126:549ba18ddd81 | 555 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
| mbed_official | 126:549ba18ddd81 | 556 | |
| mbed_official | 126:549ba18ddd81 | 557 | if (NewState != DISABLE) |
| mbed_official | 126:549ba18ddd81 | 558 | { |
| mbed_official | 126:549ba18ddd81 | 559 | /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ |
| mbed_official | 126:549ba18ddd81 | 560 | FSMC_Bank4->PCR4 |= PCR_PBKEN_Set; |
| mbed_official | 126:549ba18ddd81 | 561 | } |
| mbed_official | 126:549ba18ddd81 | 562 | else |
| mbed_official | 126:549ba18ddd81 | 563 | { |
| mbed_official | 126:549ba18ddd81 | 564 | /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ |
| mbed_official | 126:549ba18ddd81 | 565 | FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset; |
| mbed_official | 126:549ba18ddd81 | 566 | } |
| mbed_official | 126:549ba18ddd81 | 567 | } |
| mbed_official | 126:549ba18ddd81 | 568 | |
| mbed_official | 126:549ba18ddd81 | 569 | /** |
| mbed_official | 126:549ba18ddd81 | 570 | * @brief Enables or disables the FSMC NAND ECC feature. |
| mbed_official | 126:549ba18ddd81 | 571 | * @param FSMC_Bank: specifies the FSMC Bank to be used |
| mbed_official | 126:549ba18ddd81 | 572 | * This parameter can be one of the following values: |
| mbed_official | 126:549ba18ddd81 | 573 | * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND |
| mbed_official | 126:549ba18ddd81 | 574 | * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND |
| mbed_official | 126:549ba18ddd81 | 575 | * @param NewState: new state of the FSMC NAND ECC feature. |
| mbed_official | 126:549ba18ddd81 | 576 | * This parameter can be: ENABLE or DISABLE. |
| mbed_official | 126:549ba18ddd81 | 577 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 578 | */ |
| mbed_official | 126:549ba18ddd81 | 579 | void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) |
| mbed_official | 126:549ba18ddd81 | 580 | { |
| mbed_official | 126:549ba18ddd81 | 581 | assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); |
| mbed_official | 126:549ba18ddd81 | 582 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
| mbed_official | 126:549ba18ddd81 | 583 | |
| mbed_official | 126:549ba18ddd81 | 584 | if (NewState != DISABLE) |
| mbed_official | 126:549ba18ddd81 | 585 | { |
| mbed_official | 126:549ba18ddd81 | 586 | /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ |
| mbed_official | 126:549ba18ddd81 | 587 | if(FSMC_Bank == FSMC_Bank2_NAND) |
| mbed_official | 126:549ba18ddd81 | 588 | { |
| mbed_official | 126:549ba18ddd81 | 589 | FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; |
| mbed_official | 126:549ba18ddd81 | 590 | } |
| mbed_official | 126:549ba18ddd81 | 591 | else |
| mbed_official | 126:549ba18ddd81 | 592 | { |
| mbed_official | 126:549ba18ddd81 | 593 | FSMC_Bank3->PCR3 |= PCR_ECCEN_Set; |
| mbed_official | 126:549ba18ddd81 | 594 | } |
| mbed_official | 126:549ba18ddd81 | 595 | } |
| mbed_official | 126:549ba18ddd81 | 596 | else |
| mbed_official | 126:549ba18ddd81 | 597 | { |
| mbed_official | 126:549ba18ddd81 | 598 | /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ |
| mbed_official | 126:549ba18ddd81 | 599 | if(FSMC_Bank == FSMC_Bank2_NAND) |
| mbed_official | 126:549ba18ddd81 | 600 | { |
| mbed_official | 126:549ba18ddd81 | 601 | FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; |
| mbed_official | 126:549ba18ddd81 | 602 | } |
| mbed_official | 126:549ba18ddd81 | 603 | else |
| mbed_official | 126:549ba18ddd81 | 604 | { |
| mbed_official | 126:549ba18ddd81 | 605 | FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset; |
| mbed_official | 126:549ba18ddd81 | 606 | } |
| mbed_official | 126:549ba18ddd81 | 607 | } |
| mbed_official | 126:549ba18ddd81 | 608 | } |
| mbed_official | 126:549ba18ddd81 | 609 | |
| mbed_official | 126:549ba18ddd81 | 610 | /** |
| mbed_official | 126:549ba18ddd81 | 611 | * @brief Returns the error correction code register value. |
| mbed_official | 126:549ba18ddd81 | 612 | * @param FSMC_Bank: specifies the FSMC Bank to be used |
| mbed_official | 126:549ba18ddd81 | 613 | * This parameter can be one of the following values: |
| mbed_official | 126:549ba18ddd81 | 614 | * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND |
| mbed_official | 126:549ba18ddd81 | 615 | * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND |
| mbed_official | 126:549ba18ddd81 | 616 | * @retval The Error Correction Code (ECC) value. |
| mbed_official | 126:549ba18ddd81 | 617 | */ |
| mbed_official | 126:549ba18ddd81 | 618 | uint32_t FSMC_GetECC(uint32_t FSMC_Bank) |
| mbed_official | 126:549ba18ddd81 | 619 | { |
| mbed_official | 126:549ba18ddd81 | 620 | uint32_t eccval = 0x00000000; |
| mbed_official | 126:549ba18ddd81 | 621 | |
| mbed_official | 126:549ba18ddd81 | 622 | if(FSMC_Bank == FSMC_Bank2_NAND) |
| mbed_official | 126:549ba18ddd81 | 623 | { |
| mbed_official | 126:549ba18ddd81 | 624 | /* Get the ECCR2 register value */ |
| mbed_official | 126:549ba18ddd81 | 625 | eccval = FSMC_Bank2->ECCR2; |
| mbed_official | 126:549ba18ddd81 | 626 | } |
| mbed_official | 126:549ba18ddd81 | 627 | else |
| mbed_official | 126:549ba18ddd81 | 628 | { |
| mbed_official | 126:549ba18ddd81 | 629 | /* Get the ECCR3 register value */ |
| mbed_official | 126:549ba18ddd81 | 630 | eccval = FSMC_Bank3->ECCR3; |
| mbed_official | 126:549ba18ddd81 | 631 | } |
| mbed_official | 126:549ba18ddd81 | 632 | /* Return the error correction code value */ |
| mbed_official | 126:549ba18ddd81 | 633 | return(eccval); |
| mbed_official | 126:549ba18ddd81 | 634 | } |
| mbed_official | 126:549ba18ddd81 | 635 | |
| mbed_official | 126:549ba18ddd81 | 636 | /** |
| mbed_official | 126:549ba18ddd81 | 637 | * @brief Enables or disables the specified FSMC interrupts. |
| mbed_official | 126:549ba18ddd81 | 638 | * @param FSMC_Bank: specifies the FSMC Bank to be used |
| mbed_official | 126:549ba18ddd81 | 639 | * This parameter can be one of the following values: |
| mbed_official | 126:549ba18ddd81 | 640 | * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND |
| mbed_official | 126:549ba18ddd81 | 641 | * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND |
| mbed_official | 126:549ba18ddd81 | 642 | * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD |
| mbed_official | 126:549ba18ddd81 | 643 | * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. |
| mbed_official | 126:549ba18ddd81 | 644 | * This parameter can be any combination of the following values: |
| mbed_official | 126:549ba18ddd81 | 645 | * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. |
| mbed_official | 126:549ba18ddd81 | 646 | * @arg FSMC_IT_Level: Level edge detection interrupt. |
| mbed_official | 126:549ba18ddd81 | 647 | * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. |
| mbed_official | 126:549ba18ddd81 | 648 | * @param NewState: new state of the specified FSMC interrupts. |
| mbed_official | 126:549ba18ddd81 | 649 | * This parameter can be: ENABLE or DISABLE. |
| mbed_official | 126:549ba18ddd81 | 650 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 651 | */ |
| mbed_official | 126:549ba18ddd81 | 652 | void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) |
| mbed_official | 126:549ba18ddd81 | 653 | { |
| mbed_official | 126:549ba18ddd81 | 654 | assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); |
| mbed_official | 126:549ba18ddd81 | 655 | assert_param(IS_FSMC_IT(FSMC_IT)); |
| mbed_official | 126:549ba18ddd81 | 656 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
| mbed_official | 126:549ba18ddd81 | 657 | |
| mbed_official | 126:549ba18ddd81 | 658 | if (NewState != DISABLE) |
| mbed_official | 126:549ba18ddd81 | 659 | { |
| mbed_official | 126:549ba18ddd81 | 660 | /* Enable the selected FSMC_Bank2 interrupts */ |
| mbed_official | 126:549ba18ddd81 | 661 | if(FSMC_Bank == FSMC_Bank2_NAND) |
| mbed_official | 126:549ba18ddd81 | 662 | { |
| mbed_official | 126:549ba18ddd81 | 663 | FSMC_Bank2->SR2 |= FSMC_IT; |
| mbed_official | 126:549ba18ddd81 | 664 | } |
| mbed_official | 126:549ba18ddd81 | 665 | /* Enable the selected FSMC_Bank3 interrupts */ |
| mbed_official | 126:549ba18ddd81 | 666 | else if (FSMC_Bank == FSMC_Bank3_NAND) |
| mbed_official | 126:549ba18ddd81 | 667 | { |
| mbed_official | 126:549ba18ddd81 | 668 | FSMC_Bank3->SR3 |= FSMC_IT; |
| mbed_official | 126:549ba18ddd81 | 669 | } |
| mbed_official | 126:549ba18ddd81 | 670 | /* Enable the selected FSMC_Bank4 interrupts */ |
| mbed_official | 126:549ba18ddd81 | 671 | else |
| mbed_official | 126:549ba18ddd81 | 672 | { |
| mbed_official | 126:549ba18ddd81 | 673 | FSMC_Bank4->SR4 |= FSMC_IT; |
| mbed_official | 126:549ba18ddd81 | 674 | } |
| mbed_official | 126:549ba18ddd81 | 675 | } |
| mbed_official | 126:549ba18ddd81 | 676 | else |
| mbed_official | 126:549ba18ddd81 | 677 | { |
| mbed_official | 126:549ba18ddd81 | 678 | /* Disable the selected FSMC_Bank2 interrupts */ |
| mbed_official | 126:549ba18ddd81 | 679 | if(FSMC_Bank == FSMC_Bank2_NAND) |
| mbed_official | 126:549ba18ddd81 | 680 | { |
| mbed_official | 126:549ba18ddd81 | 681 | |
| mbed_official | 126:549ba18ddd81 | 682 | FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; |
| mbed_official | 126:549ba18ddd81 | 683 | } |
| mbed_official | 126:549ba18ddd81 | 684 | /* Disable the selected FSMC_Bank3 interrupts */ |
| mbed_official | 126:549ba18ddd81 | 685 | else if (FSMC_Bank == FSMC_Bank3_NAND) |
| mbed_official | 126:549ba18ddd81 | 686 | { |
| mbed_official | 126:549ba18ddd81 | 687 | FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; |
| mbed_official | 126:549ba18ddd81 | 688 | } |
| mbed_official | 126:549ba18ddd81 | 689 | /* Disable the selected FSMC_Bank4 interrupts */ |
| mbed_official | 126:549ba18ddd81 | 690 | else |
| mbed_official | 126:549ba18ddd81 | 691 | { |
| mbed_official | 126:549ba18ddd81 | 692 | FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; |
| mbed_official | 126:549ba18ddd81 | 693 | } |
| mbed_official | 126:549ba18ddd81 | 694 | } |
| mbed_official | 126:549ba18ddd81 | 695 | } |
| mbed_official | 126:549ba18ddd81 | 696 | |
| mbed_official | 126:549ba18ddd81 | 697 | /** |
| mbed_official | 126:549ba18ddd81 | 698 | * @brief Checks whether the specified FSMC flag is set or not. |
| mbed_official | 126:549ba18ddd81 | 699 | * @param FSMC_Bank: specifies the FSMC Bank to be used |
| mbed_official | 126:549ba18ddd81 | 700 | * This parameter can be one of the following values: |
| mbed_official | 126:549ba18ddd81 | 701 | * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND |
| mbed_official | 126:549ba18ddd81 | 702 | * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND |
| mbed_official | 126:549ba18ddd81 | 703 | * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD |
| mbed_official | 126:549ba18ddd81 | 704 | * @param FSMC_FLAG: specifies the flag to check. |
| mbed_official | 126:549ba18ddd81 | 705 | * This parameter can be one of the following values: |
| mbed_official | 126:549ba18ddd81 | 706 | * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. |
| mbed_official | 126:549ba18ddd81 | 707 | * @arg FSMC_FLAG_Level: Level detection Flag. |
| mbed_official | 126:549ba18ddd81 | 708 | * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. |
| mbed_official | 126:549ba18ddd81 | 709 | * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. |
| mbed_official | 126:549ba18ddd81 | 710 | * @retval The new state of FSMC_FLAG (SET or RESET). |
| mbed_official | 126:549ba18ddd81 | 711 | */ |
| mbed_official | 126:549ba18ddd81 | 712 | FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) |
| mbed_official | 126:549ba18ddd81 | 713 | { |
| mbed_official | 126:549ba18ddd81 | 714 | FlagStatus bitstatus = RESET; |
| mbed_official | 126:549ba18ddd81 | 715 | uint32_t tmpsr = 0x00000000; |
| mbed_official | 126:549ba18ddd81 | 716 | |
| mbed_official | 126:549ba18ddd81 | 717 | /* Check the parameters */ |
| mbed_official | 126:549ba18ddd81 | 718 | assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); |
| mbed_official | 126:549ba18ddd81 | 719 | assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); |
| mbed_official | 126:549ba18ddd81 | 720 | |
| mbed_official | 126:549ba18ddd81 | 721 | if(FSMC_Bank == FSMC_Bank2_NAND) |
| mbed_official | 126:549ba18ddd81 | 722 | { |
| mbed_official | 126:549ba18ddd81 | 723 | tmpsr = FSMC_Bank2->SR2; |
| mbed_official | 126:549ba18ddd81 | 724 | } |
| mbed_official | 126:549ba18ddd81 | 725 | else if(FSMC_Bank == FSMC_Bank3_NAND) |
| mbed_official | 126:549ba18ddd81 | 726 | { |
| mbed_official | 126:549ba18ddd81 | 727 | tmpsr = FSMC_Bank3->SR3; |
| mbed_official | 126:549ba18ddd81 | 728 | } |
| mbed_official | 126:549ba18ddd81 | 729 | /* FSMC_Bank4_PCCARD*/ |
| mbed_official | 126:549ba18ddd81 | 730 | else |
| mbed_official | 126:549ba18ddd81 | 731 | { |
| mbed_official | 126:549ba18ddd81 | 732 | tmpsr = FSMC_Bank4->SR4; |
| mbed_official | 126:549ba18ddd81 | 733 | } |
| mbed_official | 126:549ba18ddd81 | 734 | |
| mbed_official | 126:549ba18ddd81 | 735 | /* Get the flag status */ |
| mbed_official | 126:549ba18ddd81 | 736 | if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) |
| mbed_official | 126:549ba18ddd81 | 737 | { |
| mbed_official | 126:549ba18ddd81 | 738 | bitstatus = SET; |
| mbed_official | 126:549ba18ddd81 | 739 | } |
| mbed_official | 126:549ba18ddd81 | 740 | else |
| mbed_official | 126:549ba18ddd81 | 741 | { |
| mbed_official | 126:549ba18ddd81 | 742 | bitstatus = RESET; |
| mbed_official | 126:549ba18ddd81 | 743 | } |
| mbed_official | 126:549ba18ddd81 | 744 | /* Return the flag status */ |
| mbed_official | 126:549ba18ddd81 | 745 | return bitstatus; |
| mbed_official | 126:549ba18ddd81 | 746 | } |
| mbed_official | 126:549ba18ddd81 | 747 | |
| mbed_official | 126:549ba18ddd81 | 748 | /** |
| mbed_official | 126:549ba18ddd81 | 749 | * @brief Clears the FSMC's pending flags. |
| mbed_official | 126:549ba18ddd81 | 750 | * @param FSMC_Bank: specifies the FSMC Bank to be used |
| mbed_official | 126:549ba18ddd81 | 751 | * This parameter can be one of the following values: |
| mbed_official | 126:549ba18ddd81 | 752 | * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND |
| mbed_official | 126:549ba18ddd81 | 753 | * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND |
| mbed_official | 126:549ba18ddd81 | 754 | * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD |
| mbed_official | 126:549ba18ddd81 | 755 | * @param FSMC_FLAG: specifies the flag to clear. |
| mbed_official | 126:549ba18ddd81 | 756 | * This parameter can be any combination of the following values: |
| mbed_official | 126:549ba18ddd81 | 757 | * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. |
| mbed_official | 126:549ba18ddd81 | 758 | * @arg FSMC_FLAG_Level: Level detection Flag. |
| mbed_official | 126:549ba18ddd81 | 759 | * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. |
| mbed_official | 126:549ba18ddd81 | 760 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 761 | */ |
| mbed_official | 126:549ba18ddd81 | 762 | void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) |
| mbed_official | 126:549ba18ddd81 | 763 | { |
| mbed_official | 126:549ba18ddd81 | 764 | /* Check the parameters */ |
| mbed_official | 126:549ba18ddd81 | 765 | assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); |
| mbed_official | 126:549ba18ddd81 | 766 | assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; |
| mbed_official | 126:549ba18ddd81 | 767 | |
| mbed_official | 126:549ba18ddd81 | 768 | if(FSMC_Bank == FSMC_Bank2_NAND) |
| mbed_official | 126:549ba18ddd81 | 769 | { |
| mbed_official | 126:549ba18ddd81 | 770 | FSMC_Bank2->SR2 &= ~FSMC_FLAG; |
| mbed_official | 126:549ba18ddd81 | 771 | } |
| mbed_official | 126:549ba18ddd81 | 772 | else if(FSMC_Bank == FSMC_Bank3_NAND) |
| mbed_official | 126:549ba18ddd81 | 773 | { |
| mbed_official | 126:549ba18ddd81 | 774 | FSMC_Bank3->SR3 &= ~FSMC_FLAG; |
| mbed_official | 126:549ba18ddd81 | 775 | } |
| mbed_official | 126:549ba18ddd81 | 776 | /* FSMC_Bank4_PCCARD*/ |
| mbed_official | 126:549ba18ddd81 | 777 | else |
| mbed_official | 126:549ba18ddd81 | 778 | { |
| mbed_official | 126:549ba18ddd81 | 779 | FSMC_Bank4->SR4 &= ~FSMC_FLAG; |
| mbed_official | 126:549ba18ddd81 | 780 | } |
| mbed_official | 126:549ba18ddd81 | 781 | } |
| mbed_official | 126:549ba18ddd81 | 782 | |
| mbed_official | 126:549ba18ddd81 | 783 | /** |
| mbed_official | 126:549ba18ddd81 | 784 | * @brief Checks whether the specified FSMC interrupt has occurred or not. |
| mbed_official | 126:549ba18ddd81 | 785 | * @param FSMC_Bank: specifies the FSMC Bank to be used |
| mbed_official | 126:549ba18ddd81 | 786 | * This parameter can be one of the following values: |
| mbed_official | 126:549ba18ddd81 | 787 | * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND |
| mbed_official | 126:549ba18ddd81 | 788 | * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND |
| mbed_official | 126:549ba18ddd81 | 789 | * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD |
| mbed_official | 126:549ba18ddd81 | 790 | * @param FSMC_IT: specifies the FSMC interrupt source to check. |
| mbed_official | 126:549ba18ddd81 | 791 | * This parameter can be one of the following values: |
| mbed_official | 126:549ba18ddd81 | 792 | * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. |
| mbed_official | 126:549ba18ddd81 | 793 | * @arg FSMC_IT_Level: Level edge detection interrupt. |
| mbed_official | 126:549ba18ddd81 | 794 | * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. |
| mbed_official | 126:549ba18ddd81 | 795 | * @retval The new state of FSMC_IT (SET or RESET). |
| mbed_official | 126:549ba18ddd81 | 796 | */ |
| mbed_official | 126:549ba18ddd81 | 797 | ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) |
| mbed_official | 126:549ba18ddd81 | 798 | { |
| mbed_official | 126:549ba18ddd81 | 799 | ITStatus bitstatus = RESET; |
| mbed_official | 126:549ba18ddd81 | 800 | uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; |
| mbed_official | 126:549ba18ddd81 | 801 | |
| mbed_official | 126:549ba18ddd81 | 802 | /* Check the parameters */ |
| mbed_official | 126:549ba18ddd81 | 803 | assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); |
| mbed_official | 126:549ba18ddd81 | 804 | assert_param(IS_FSMC_GET_IT(FSMC_IT)); |
| mbed_official | 126:549ba18ddd81 | 805 | |
| mbed_official | 126:549ba18ddd81 | 806 | if(FSMC_Bank == FSMC_Bank2_NAND) |
| mbed_official | 126:549ba18ddd81 | 807 | { |
| mbed_official | 126:549ba18ddd81 | 808 | tmpsr = FSMC_Bank2->SR2; |
| mbed_official | 126:549ba18ddd81 | 809 | } |
| mbed_official | 126:549ba18ddd81 | 810 | else if(FSMC_Bank == FSMC_Bank3_NAND) |
| mbed_official | 126:549ba18ddd81 | 811 | { |
| mbed_official | 126:549ba18ddd81 | 812 | tmpsr = FSMC_Bank3->SR3; |
| mbed_official | 126:549ba18ddd81 | 813 | } |
| mbed_official | 126:549ba18ddd81 | 814 | /* FSMC_Bank4_PCCARD*/ |
| mbed_official | 126:549ba18ddd81 | 815 | else |
| mbed_official | 126:549ba18ddd81 | 816 | { |
| mbed_official | 126:549ba18ddd81 | 817 | tmpsr = FSMC_Bank4->SR4; |
| mbed_official | 126:549ba18ddd81 | 818 | } |
| mbed_official | 126:549ba18ddd81 | 819 | |
| mbed_official | 126:549ba18ddd81 | 820 | itstatus = tmpsr & FSMC_IT; |
| mbed_official | 126:549ba18ddd81 | 821 | |
| mbed_official | 126:549ba18ddd81 | 822 | itenable = tmpsr & (FSMC_IT >> 3); |
| mbed_official | 126:549ba18ddd81 | 823 | if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) |
| mbed_official | 126:549ba18ddd81 | 824 | { |
| mbed_official | 126:549ba18ddd81 | 825 | bitstatus = SET; |
| mbed_official | 126:549ba18ddd81 | 826 | } |
| mbed_official | 126:549ba18ddd81 | 827 | else |
| mbed_official | 126:549ba18ddd81 | 828 | { |
| mbed_official | 126:549ba18ddd81 | 829 | bitstatus = RESET; |
| mbed_official | 126:549ba18ddd81 | 830 | } |
| mbed_official | 126:549ba18ddd81 | 831 | return bitstatus; |
| mbed_official | 126:549ba18ddd81 | 832 | } |
| mbed_official | 126:549ba18ddd81 | 833 | |
| mbed_official | 126:549ba18ddd81 | 834 | /** |
| mbed_official | 126:549ba18ddd81 | 835 | * @brief Clears the FSMC's interrupt pending bits. |
| mbed_official | 126:549ba18ddd81 | 836 | * @param FSMC_Bank: specifies the FSMC Bank to be used |
| mbed_official | 126:549ba18ddd81 | 837 | * This parameter can be one of the following values: |
| mbed_official | 126:549ba18ddd81 | 838 | * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND |
| mbed_official | 126:549ba18ddd81 | 839 | * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND |
| mbed_official | 126:549ba18ddd81 | 840 | * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD |
| mbed_official | 126:549ba18ddd81 | 841 | * @param FSMC_IT: specifies the interrupt pending bit to clear. |
| mbed_official | 126:549ba18ddd81 | 842 | * This parameter can be any combination of the following values: |
| mbed_official | 126:549ba18ddd81 | 843 | * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. |
| mbed_official | 126:549ba18ddd81 | 844 | * @arg FSMC_IT_Level: Level edge detection interrupt. |
| mbed_official | 126:549ba18ddd81 | 845 | * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. |
| mbed_official | 126:549ba18ddd81 | 846 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 847 | */ |
| mbed_official | 126:549ba18ddd81 | 848 | void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) |
| mbed_official | 126:549ba18ddd81 | 849 | { |
| mbed_official | 126:549ba18ddd81 | 850 | /* Check the parameters */ |
| mbed_official | 126:549ba18ddd81 | 851 | assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); |
| mbed_official | 126:549ba18ddd81 | 852 | assert_param(IS_FSMC_IT(FSMC_IT)); |
| mbed_official | 126:549ba18ddd81 | 853 | |
| mbed_official | 126:549ba18ddd81 | 854 | if(FSMC_Bank == FSMC_Bank2_NAND) |
| mbed_official | 126:549ba18ddd81 | 855 | { |
| mbed_official | 126:549ba18ddd81 | 856 | FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); |
| mbed_official | 126:549ba18ddd81 | 857 | } |
| mbed_official | 126:549ba18ddd81 | 858 | else if(FSMC_Bank == FSMC_Bank3_NAND) |
| mbed_official | 126:549ba18ddd81 | 859 | { |
| mbed_official | 126:549ba18ddd81 | 860 | FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); |
| mbed_official | 126:549ba18ddd81 | 861 | } |
| mbed_official | 126:549ba18ddd81 | 862 | /* FSMC_Bank4_PCCARD*/ |
| mbed_official | 126:549ba18ddd81 | 863 | else |
| mbed_official | 126:549ba18ddd81 | 864 | { |
| mbed_official | 126:549ba18ddd81 | 865 | FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); |
| mbed_official | 126:549ba18ddd81 | 866 | } |
| mbed_official | 126:549ba18ddd81 | 867 | } |
| mbed_official | 126:549ba18ddd81 | 868 | |
| mbed_official | 126:549ba18ddd81 | 869 | /** |
| mbed_official | 126:549ba18ddd81 | 870 | * @} |
| mbed_official | 126:549ba18ddd81 | 871 | */ |
| mbed_official | 126:549ba18ddd81 | 872 | |
| mbed_official | 126:549ba18ddd81 | 873 | /** |
| mbed_official | 126:549ba18ddd81 | 874 | * @} |
| mbed_official | 126:549ba18ddd81 | 875 | */ |
| mbed_official | 126:549ba18ddd81 | 876 | |
| mbed_official | 126:549ba18ddd81 | 877 | /** |
| mbed_official | 126:549ba18ddd81 | 878 | * @} |
| mbed_official | 126:549ba18ddd81 | 879 | */ |
| mbed_official | 126:549ba18ddd81 | 880 | |
| mbed_official | 126:549ba18ddd81 | 881 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |