mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_fsmc.c
- Committer:
- shaoziyang
- Date:
- 2014-09-13
- Revision:
- 323:9e901b0a5aa1
- Parent:
- 126:549ba18ddd81
File content as of revision 323:9e901b0a5aa1:
/** ****************************************************************************** * @file stm32f10x_fsmc.c * @author MCD Application Team * @version V3.6.1 * @date 05-March-2012 * @brief This file provides all the FSMC firmware functions. ******************************************************************************* * Copyright (c) 2014, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_fsmc.h" #include "stm32f10x_rcc.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @defgroup FSMC * @brief FSMC driver modules * @{ */ /** @defgroup FSMC_Private_TypesDefinitions * @{ */ /** * @} */ /** @defgroup FSMC_Private_Defines * @{ */ /* --------------------- FSMC registers bit mask ---------------------------- */ /* FSMC BCRx Mask */ #define BCR_MBKEN_Set ((uint32_t)0x00000001) #define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) #define BCR_FACCEN_Set ((uint32_t)0x00000040) /* FSMC PCRx Mask */ #define PCR_PBKEN_Set ((uint32_t)0x00000004) #define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) #define PCR_ECCEN_Set ((uint32_t)0x00000040) #define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) #define PCR_MemoryType_NAND ((uint32_t)0x00000008) /** * @} */ /** @defgroup FSMC_Private_Macros * @{ */ /** * @} */ /** @defgroup FSMC_Private_Variables * @{ */ /** * @} */ /** @defgroup FSMC_Private_FunctionPrototypes * @{ */ /** * @} */ /** @defgroup FSMC_Private_Functions * @{ */ /** * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default * reset values. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 * @retval None */ void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) { /* Check the parameter */ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); /* FSMC_Bank1_NORSRAM1 */ if(FSMC_Bank == FSMC_Bank1_NORSRAM1) { FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; } /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ else { FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; } FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; } /** * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @retval None */ void FSMC_NANDDeInit(uint32_t FSMC_Bank) { /* Check the parameter */ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); if(FSMC_Bank == FSMC_Bank2_NAND) { /* Set the FSMC_Bank2 registers to their reset values */ FSMC_Bank2->PCR2 = 0x00000018; FSMC_Bank2->SR2 = 0x00000040; FSMC_Bank2->PMEM2 = 0xFCFCFCFC; FSMC_Bank2->PATT2 = 0xFCFCFCFC; } /* FSMC_Bank3_NAND */ else { /* Set the FSMC_Bank3 registers to their reset values */ FSMC_Bank3->PCR3 = 0x00000018; FSMC_Bank3->SR3 = 0x00000040; FSMC_Bank3->PMEM3 = 0xFCFCFCFC; FSMC_Bank3->PATT3 = 0xFCFCFCFC; } } /** * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. * @param None * @retval None */ void FSMC_PCCARDDeInit(void) { /* Set the FSMC_Bank4 registers to their reset values */ FSMC_Bank4->PCR4 = 0x00000018; FSMC_Bank4->SR4 = 0x00000000; FSMC_Bank4->PMEM4 = 0xFCFCFCFC; FSMC_Bank4->PATT4 = 0xFCFCFCFC; FSMC_Bank4->PIO4 = 0xFCFCFCFC; } /** * @brief Initializes the FSMC NOR/SRAM Banks according to the specified * parameters in the FSMC_NORSRAMInitStruct. * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef * structure that contains the configuration information for * the FSMC NOR/SRAM specified Banks. * @retval None */ void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) { /* Check the parameters */ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); /* Bank1 NOR/SRAM control register configuration */ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | FSMC_NORSRAMInitStruct->FSMC_MemoryType | FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | FSMC_NORSRAMInitStruct->FSMC_WrapMode | FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | FSMC_NORSRAMInitStruct->FSMC_WriteOperation | FSMC_NORSRAMInitStruct->FSMC_WaitSignal | FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | FSMC_NORSRAMInitStruct->FSMC_WriteBurst; if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) { FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; } /* Bank1 NOR/SRAM timing register configuration */ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) { assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; } else { FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; } } /** * @brief Initializes the FSMC NAND Banks according to the specified * parameters in the FSMC_NANDInitStruct. * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef * structure that contains the configuration information for the FSMC * NAND specified Banks. * @retval None */ void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) { uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; /* Check the parameters */ assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | PCR_MemoryType_NAND | FSMC_NANDInitStruct->FSMC_MemoryDataWidth | FSMC_NANDInitStruct->FSMC_ECC | FSMC_NANDInitStruct->FSMC_ECCPageSize | (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) { /* FSMC_Bank2_NAND registers configuration */ FSMC_Bank2->PCR2 = tmppcr; FSMC_Bank2->PMEM2 = tmppmem; FSMC_Bank2->PATT2 = tmppatt; } else { /* FSMC_Bank3_NAND registers configuration */ FSMC_Bank3->PCR3 = tmppcr; FSMC_Bank3->PMEM3 = tmppmem; FSMC_Bank3->PATT3 = tmppatt; } } /** * @brief Initializes the FSMC PCCARD Bank according to the specified * parameters in the FSMC_PCCARDInitStruct. * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef * structure that contains the configuration information for the FSMC * PCCARD Bank. * @retval None */ void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) { /* Check the parameters */ assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | FSMC_MemoryDataWidth_16b | (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); } /** * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef * structure which will be initialized. * @retval None */ void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) { /* Reset NOR/SRAM Init structure parameters values */ FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; } /** * @brief Fills each FSMC_NANDInitStruct member with its default value. * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef * structure which will be initialized. * @retval None */ void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) { /* Reset NAND Init structure parameters values */ FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; } /** * @brief Fills each FSMC_PCCARDInitStruct member with its default value. * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef * structure which will be initialized. * @retval None */ void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) { /* Reset PCCARD Init structure parameters values */ FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; } /** * @brief Enables or disables the specified NOR/SRAM Memory Bank. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. * @retval None */ void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) { assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; } else { /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; } } /** * @brief Enables or disables the specified NAND Memory Bank. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. * @retval None */ void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) { assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; } else { FSMC_Bank3->PCR3 |= PCR_PBKEN_Set; } } else { /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; } else { FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset; } } } /** * @brief Enables or disables the PCCARD Memory Bank. * @param NewState: new state of the PCCARD Memory Bank. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FSMC_PCCARDCmd(FunctionalState NewState) { assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ FSMC_Bank4->PCR4 |= PCR_PBKEN_Set; } else { /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset; } } /** * @brief Enables or disables the FSMC NAND ECC feature. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @param NewState: new state of the FSMC NAND ECC feature. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) { assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; } else { FSMC_Bank3->PCR3 |= PCR_ECCEN_Set; } } else { /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; } else { FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset; } } } /** * @brief Returns the error correction code register value. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @retval The Error Correction Code (ECC) value. */ uint32_t FSMC_GetECC(uint32_t FSMC_Bank) { uint32_t eccval = 0x00000000; if(FSMC_Bank == FSMC_Bank2_NAND) { /* Get the ECCR2 register value */ eccval = FSMC_Bank2->ECCR2; } else { /* Get the ECCR3 register value */ eccval = FSMC_Bank3->ECCR3; } /* Return the error correction code value */ return(eccval); } /** * @brief Enables or disables the specified FSMC interrupts. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. * @arg FSMC_IT_Level: Level edge detection interrupt. * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. * @param NewState: new state of the specified FSMC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) { assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); assert_param(IS_FSMC_IT(FSMC_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected FSMC_Bank2 interrupts */ if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->SR2 |= FSMC_IT; } /* Enable the selected FSMC_Bank3 interrupts */ else if (FSMC_Bank == FSMC_Bank3_NAND) { FSMC_Bank3->SR3 |= FSMC_IT; } /* Enable the selected FSMC_Bank4 interrupts */ else { FSMC_Bank4->SR4 |= FSMC_IT; } } else { /* Disable the selected FSMC_Bank2 interrupts */ if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; } /* Disable the selected FSMC_Bank3 interrupts */ else if (FSMC_Bank == FSMC_Bank3_NAND) { FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; } /* Disable the selected FSMC_Bank4 interrupts */ else { FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; } } } /** * @brief Checks whether the specified FSMC flag is set or not. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD * @param FSMC_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. * @arg FSMC_FLAG_Level: Level detection Flag. * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. * @retval The new state of FSMC_FLAG (SET or RESET). */ FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) { FlagStatus bitstatus = RESET; uint32_t tmpsr = 0x00000000; /* Check the parameters */ assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); if(FSMC_Bank == FSMC_Bank2_NAND) { tmpsr = FSMC_Bank2->SR2; } else if(FSMC_Bank == FSMC_Bank3_NAND) { tmpsr = FSMC_Bank3->SR3; } /* FSMC_Bank4_PCCARD*/ else { tmpsr = FSMC_Bank4->SR4; } /* Get the flag status */ if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) { bitstatus = SET; } else { bitstatus = RESET; } /* Return the flag status */ return bitstatus; } /** * @brief Clears the FSMC's pending flags. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD * @param FSMC_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. * @arg FSMC_FLAG_Level: Level detection Flag. * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. * @retval None */ void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) { /* Check the parameters */ assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->SR2 &= ~FSMC_FLAG; } else if(FSMC_Bank == FSMC_Bank3_NAND) { FSMC_Bank3->SR3 &= ~FSMC_FLAG; } /* FSMC_Bank4_PCCARD*/ else { FSMC_Bank4->SR4 &= ~FSMC_FLAG; } } /** * @brief Checks whether the specified FSMC interrupt has occurred or not. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD * @param FSMC_IT: specifies the FSMC interrupt source to check. * This parameter can be one of the following values: * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. * @arg FSMC_IT_Level: Level edge detection interrupt. * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. * @retval The new state of FSMC_IT (SET or RESET). */ ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) { ITStatus bitstatus = RESET; uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; /* Check the parameters */ assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); assert_param(IS_FSMC_GET_IT(FSMC_IT)); if(FSMC_Bank == FSMC_Bank2_NAND) { tmpsr = FSMC_Bank2->SR2; } else if(FSMC_Bank == FSMC_Bank3_NAND) { tmpsr = FSMC_Bank3->SR3; } /* FSMC_Bank4_PCCARD*/ else { tmpsr = FSMC_Bank4->SR4; } itstatus = tmpsr & FSMC_IT; itenable = tmpsr & (FSMC_IT >> 3); if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the FSMC's interrupt pending bits. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD * @param FSMC_IT: specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. * @arg FSMC_IT_Level: Level edge detection interrupt. * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. * @retval None */ void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) { /* Check the parameters */ assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); assert_param(IS_FSMC_IT(FSMC_IT)); if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); } else if(FSMC_Bank == FSMC_Bank3_NAND) { FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); } /* FSMC_Bank4_PCCARD*/ else { FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); } } /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/