shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

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targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/system_stm32f0xx.c@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
240:9a7c54113eaf 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 130:1dec54e4aec3 1 /**
mbed_official 130:1dec54e4aec3 2 ******************************************************************************
mbed_official 130:1dec54e4aec3 3 * @file system_stm32f0xx.c
mbed_official 130:1dec54e4aec3 4 * @author MCD Application Team
mbed_official 130:1dec54e4aec3 5 * @version V1.0.1
mbed_official 240:9a7c54113eaf 6 * @date 12-January-2014
mbed_official 130:1dec54e4aec3 7 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
mbed_official 130:1dec54e4aec3 8 * This file contains the system clock configuration for STM32F0xx devices,
mbed_official 130:1dec54e4aec3 9 * and is generated by the clock configuration tool
mbed_official 240:9a7c54113eaf 10 * STM32F0xx_Clock_Configuration_V1.0.1.xls
mbed_official 130:1dec54e4aec3 11 *
mbed_official 130:1dec54e4aec3 12 * 1. This file provides two functions and one global variable to be called from
mbed_official 130:1dec54e4aec3 13 * user application:
mbed_official 130:1dec54e4aec3 14 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
mbed_official 130:1dec54e4aec3 15 * and Divider factors, AHB/APBx prescalers and Flash settings),
mbed_official 130:1dec54e4aec3 16 * depending on the configuration made in the clock xls tool.
mbed_official 130:1dec54e4aec3 17 * This function is called at startup just after reset and
mbed_official 130:1dec54e4aec3 18 * before branch to main program. This call is made inside
mbed_official 130:1dec54e4aec3 19 * the "startup_stm32f0xx.s" file.
mbed_official 130:1dec54e4aec3 20 *
mbed_official 130:1dec54e4aec3 21 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 130:1dec54e4aec3 22 * by the user application to setup the SysTick
mbed_official 130:1dec54e4aec3 23 * timer or configure other parameters.
mbed_official 130:1dec54e4aec3 24 *
mbed_official 130:1dec54e4aec3 25 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 130:1dec54e4aec3 26 * be called whenever the core clock is changed
mbed_official 130:1dec54e4aec3 27 * during program execution.
mbed_official 130:1dec54e4aec3 28 *
mbed_official 130:1dec54e4aec3 29 * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
mbed_official 130:1dec54e4aec3 30 * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
mbed_official 130:1dec54e4aec3 31 * configure the system clock before to branch to main program.
mbed_official 130:1dec54e4aec3 32 *
mbed_official 130:1dec54e4aec3 33 * 3. If the system clock source selected by user fails to startup, the SystemInit()
mbed_official 130:1dec54e4aec3 34 * function will do nothing and HSI still used as system clock source. User can
mbed_official 130:1dec54e4aec3 35 * add some code to deal with this issue inside the SetSysClock() function.
mbed_official 130:1dec54e4aec3 36 *
mbed_official 130:1dec54e4aec3 37 * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
mbed_official 130:1dec54e4aec3 38 * in "stm32f0xx.h" file. When HSE is used as system clock source, directly or
mbed_official 130:1dec54e4aec3 39 * through PLL, and you are using different crystal you have to adapt the HSE
mbed_official 130:1dec54e4aec3 40 * value to your own configuration.
mbed_official 130:1dec54e4aec3 41 *
mbed_official 130:1dec54e4aec3 42 * 5. This file configures the system clock as follows:
mbed_official 130:1dec54e4aec3 43 *-----------------------------------------------------------------------------
mbed_official 240:9a7c54113eaf 44 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 240:9a7c54113eaf 45 * | (external 8 MHz clock) | (internal 8 MHz)
mbed_official 240:9a7c54113eaf 46 * | 2- PLL_HSE_XTAL |
mbed_official 240:9a7c54113eaf 47 * | (external 8 MHz xtal) |
mbed_official 130:1dec54e4aec3 48 *-----------------------------------------------------------------------------
mbed_official 240:9a7c54113eaf 49 * SYSCLK(MHz) | 48 | 48
mbed_official 130:1dec54e4aec3 50 *-----------------------------------------------------------------------------
mbed_official 240:9a7c54113eaf 51 * AHBCLK (MHz) | 48 | 48
mbed_official 130:1dec54e4aec3 52 *-----------------------------------------------------------------------------
mbed_official 240:9a7c54113eaf 53 * APBCLK (MHz) | 48 | 48
mbed_official 130:1dec54e4aec3 54 *-----------------------------------------------------------------------------
mbed_official 130:1dec54e4aec3 55 ******************************************************************************
mbed_official 130:1dec54e4aec3 56 * @attention
mbed_official 130:1dec54e4aec3 57 *
mbed_official 240:9a7c54113eaf 58 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 130:1dec54e4aec3 59 *
mbed_official 240:9a7c54113eaf 60 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 240:9a7c54113eaf 61 * are permitted provided that the following conditions are met:
mbed_official 240:9a7c54113eaf 62 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 240:9a7c54113eaf 63 * this list of conditions and the following disclaimer.
mbed_official 240:9a7c54113eaf 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 240:9a7c54113eaf 65 * this list of conditions and the following disclaimer in the documentation
mbed_official 240:9a7c54113eaf 66 * and/or other materials provided with the distribution.
mbed_official 240:9a7c54113eaf 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 240:9a7c54113eaf 68 * may be used to endorse or promote products derived from this software
mbed_official 240:9a7c54113eaf 69 * without specific prior written permission.
mbed_official 130:1dec54e4aec3 70 *
mbed_official 240:9a7c54113eaf 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 240:9a7c54113eaf 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 240:9a7c54113eaf 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 240:9a7c54113eaf 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 240:9a7c54113eaf 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 240:9a7c54113eaf 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 240:9a7c54113eaf 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 240:9a7c54113eaf 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 240:9a7c54113eaf 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 240:9a7c54113eaf 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 130:1dec54e4aec3 81 *
mbed_official 130:1dec54e4aec3 82 ******************************************************************************
mbed_official 130:1dec54e4aec3 83 */
mbed_official 130:1dec54e4aec3 84
mbed_official 130:1dec54e4aec3 85 /** @addtogroup CMSIS
mbed_official 130:1dec54e4aec3 86 * @{
mbed_official 130:1dec54e4aec3 87 */
mbed_official 130:1dec54e4aec3 88
mbed_official 130:1dec54e4aec3 89 /** @addtogroup stm32f0xx_system
mbed_official 130:1dec54e4aec3 90 * @{
mbed_official 130:1dec54e4aec3 91 */
mbed_official 130:1dec54e4aec3 92
mbed_official 130:1dec54e4aec3 93 /** @addtogroup STM32F0xx_System_Private_Includes
mbed_official 130:1dec54e4aec3 94 * @{
mbed_official 130:1dec54e4aec3 95 */
mbed_official 130:1dec54e4aec3 96
mbed_official 130:1dec54e4aec3 97 #include "stm32f0xx.h"
mbed_official 130:1dec54e4aec3 98
mbed_official 130:1dec54e4aec3 99 /**
mbed_official 130:1dec54e4aec3 100 * @}
mbed_official 130:1dec54e4aec3 101 */
mbed_official 130:1dec54e4aec3 102
mbed_official 130:1dec54e4aec3 103 /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
mbed_official 130:1dec54e4aec3 104 * @{
mbed_official 130:1dec54e4aec3 105 */
mbed_official 130:1dec54e4aec3 106
mbed_official 130:1dec54e4aec3 107 /**
mbed_official 130:1dec54e4aec3 108 * @}
mbed_official 130:1dec54e4aec3 109 */
mbed_official 130:1dec54e4aec3 110
mbed_official 130:1dec54e4aec3 111 /** @addtogroup STM32F0xx_System_Private_Defines
mbed_official 130:1dec54e4aec3 112 * @{
mbed_official 130:1dec54e4aec3 113 */
mbed_official 130:1dec54e4aec3 114 /**
mbed_official 130:1dec54e4aec3 115 * @}
mbed_official 130:1dec54e4aec3 116 */
mbed_official 130:1dec54e4aec3 117
mbed_official 130:1dec54e4aec3 118 /** @addtogroup STM32F0xx_System_Private_Macros
mbed_official 130:1dec54e4aec3 119 * @{
mbed_official 130:1dec54e4aec3 120 */
mbed_official 130:1dec54e4aec3 121
mbed_official 240:9a7c54113eaf 122 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 240:9a7c54113eaf 123 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 240:9a7c54113eaf 124 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 240:9a7c54113eaf 125
mbed_official 130:1dec54e4aec3 126 /**
mbed_official 130:1dec54e4aec3 127 * @}
mbed_official 130:1dec54e4aec3 128 */
mbed_official 130:1dec54e4aec3 129
mbed_official 130:1dec54e4aec3 130 /** @addtogroup STM32F0xx_System_Private_Variables
mbed_official 130:1dec54e4aec3 131 * @{
mbed_official 130:1dec54e4aec3 132 */
mbed_official 130:1dec54e4aec3 133 uint32_t SystemCoreClock = 48000000;
mbed_official 130:1dec54e4aec3 134 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 130:1dec54e4aec3 135
mbed_official 130:1dec54e4aec3 136 /**
mbed_official 130:1dec54e4aec3 137 * @}
mbed_official 130:1dec54e4aec3 138 */
mbed_official 130:1dec54e4aec3 139
mbed_official 130:1dec54e4aec3 140 /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
mbed_official 130:1dec54e4aec3 141 * @{
mbed_official 130:1dec54e4aec3 142 */
mbed_official 130:1dec54e4aec3 143
mbed_official 240:9a7c54113eaf 144 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 240:9a7c54113eaf 145 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 240:9a7c54113eaf 146 #endif
mbed_official 240:9a7c54113eaf 147
mbed_official 240:9a7c54113eaf 148 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 130:1dec54e4aec3 149
mbed_official 130:1dec54e4aec3 150 /**
mbed_official 130:1dec54e4aec3 151 * @}
mbed_official 130:1dec54e4aec3 152 */
mbed_official 130:1dec54e4aec3 153
mbed_official 130:1dec54e4aec3 154 /** @addtogroup STM32F0xx_System_Private_Functions
mbed_official 130:1dec54e4aec3 155 * @{
mbed_official 130:1dec54e4aec3 156 */
mbed_official 130:1dec54e4aec3 157
mbed_official 130:1dec54e4aec3 158 /**
mbed_official 130:1dec54e4aec3 159 * @brief Setup the microcontroller system.
mbed_official 130:1dec54e4aec3 160 * Initialize the Embedded Flash Interface, the PLL and update the
mbed_official 130:1dec54e4aec3 161 * SystemCoreClock variable.
mbed_official 130:1dec54e4aec3 162 * @param None
mbed_official 130:1dec54e4aec3 163 * @retval None
mbed_official 130:1dec54e4aec3 164 */
mbed_official 130:1dec54e4aec3 165 void SystemInit (void)
mbed_official 130:1dec54e4aec3 166 {
mbed_official 130:1dec54e4aec3 167 /* Set HSION bit */
mbed_official 130:1dec54e4aec3 168 RCC->CR |= (uint32_t)0x00000001;
mbed_official 130:1dec54e4aec3 169
mbed_official 130:1dec54e4aec3 170 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
mbed_official 130:1dec54e4aec3 171 RCC->CFGR &= (uint32_t)0xF8FFB80C;
mbed_official 130:1dec54e4aec3 172
mbed_official 130:1dec54e4aec3 173 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 130:1dec54e4aec3 174 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 130:1dec54e4aec3 175
mbed_official 130:1dec54e4aec3 176 /* Reset HSEBYP bit */
mbed_official 130:1dec54e4aec3 177 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 130:1dec54e4aec3 178
mbed_official 130:1dec54e4aec3 179 /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
mbed_official 130:1dec54e4aec3 180 RCC->CFGR &= (uint32_t)0xFFC0FFFF;
mbed_official 130:1dec54e4aec3 181
mbed_official 130:1dec54e4aec3 182 /* Reset PREDIV1[3:0] bits */
mbed_official 130:1dec54e4aec3 183 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
mbed_official 130:1dec54e4aec3 184
mbed_official 130:1dec54e4aec3 185 /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
mbed_official 130:1dec54e4aec3 186 RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
mbed_official 130:1dec54e4aec3 187
mbed_official 130:1dec54e4aec3 188 /* Reset HSI14 bit */
mbed_official 130:1dec54e4aec3 189 RCC->CR2 &= (uint32_t)0xFFFFFFFE;
mbed_official 130:1dec54e4aec3 190
mbed_official 130:1dec54e4aec3 191 /* Disable all interrupts */
mbed_official 130:1dec54e4aec3 192 RCC->CIR = 0x00000000;
mbed_official 130:1dec54e4aec3 193
mbed_official 240:9a7c54113eaf 194 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 240:9a7c54113eaf 195 AHB/APBx prescalers and Flash settings */
mbed_official 130:1dec54e4aec3 196 SetSysClock();
mbed_official 130:1dec54e4aec3 197 }
mbed_official 130:1dec54e4aec3 198
mbed_official 130:1dec54e4aec3 199 /**
mbed_official 130:1dec54e4aec3 200 * @brief Update SystemCoreClock according to Clock Register Values
mbed_official 130:1dec54e4aec3 201 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 130:1dec54e4aec3 202 * be used by the user application to setup the SysTick timer or configure
mbed_official 130:1dec54e4aec3 203 * other parameters.
mbed_official 130:1dec54e4aec3 204 *
mbed_official 130:1dec54e4aec3 205 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 130:1dec54e4aec3 206 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 130:1dec54e4aec3 207 * based on this variable will be incorrect.
mbed_official 130:1dec54e4aec3 208 *
mbed_official 130:1dec54e4aec3 209 * @note - The system frequency computed by this function is not the real
mbed_official 130:1dec54e4aec3 210 * frequency in the chip. It is calculated based on the predefined
mbed_official 130:1dec54e4aec3 211 * constant and the selected clock source:
mbed_official 130:1dec54e4aec3 212 *
mbed_official 130:1dec54e4aec3 213 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 130:1dec54e4aec3 214 *
mbed_official 130:1dec54e4aec3 215 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 130:1dec54e4aec3 216 *
mbed_official 130:1dec54e4aec3 217 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 130:1dec54e4aec3 218 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 130:1dec54e4aec3 219 *
mbed_official 130:1dec54e4aec3 220 * (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
mbed_official 130:1dec54e4aec3 221 * 8 MHz) but the real value may vary depending on the variations
mbed_official 130:1dec54e4aec3 222 * in voltage and temperature.
mbed_official 130:1dec54e4aec3 223 *
mbed_official 130:1dec54e4aec3 224 * (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
mbed_official 130:1dec54e4aec3 225 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 130:1dec54e4aec3 226 * frequency of the crystal used. Otherwise, this function may
mbed_official 130:1dec54e4aec3 227 * have wrong result.
mbed_official 130:1dec54e4aec3 228 *
mbed_official 130:1dec54e4aec3 229 * - The result of this function could be not correct when using fractional
mbed_official 130:1dec54e4aec3 230 * value for HSE crystal.
mbed_official 130:1dec54e4aec3 231 * @param None
mbed_official 130:1dec54e4aec3 232 * @retval None
mbed_official 130:1dec54e4aec3 233 */
mbed_official 130:1dec54e4aec3 234 void SystemCoreClockUpdate (void)
mbed_official 130:1dec54e4aec3 235 {
mbed_official 130:1dec54e4aec3 236 uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
mbed_official 130:1dec54e4aec3 237
mbed_official 130:1dec54e4aec3 238 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 130:1dec54e4aec3 239 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 130:1dec54e4aec3 240
mbed_official 130:1dec54e4aec3 241 switch (tmp)
mbed_official 130:1dec54e4aec3 242 {
mbed_official 130:1dec54e4aec3 243 case 0x00: /* HSI used as system clock */
mbed_official 130:1dec54e4aec3 244 SystemCoreClock = HSI_VALUE;
mbed_official 130:1dec54e4aec3 245 break;
mbed_official 130:1dec54e4aec3 246 case 0x04: /* HSE used as system clock */
mbed_official 130:1dec54e4aec3 247 SystemCoreClock = HSE_VALUE;
mbed_official 130:1dec54e4aec3 248 break;
mbed_official 130:1dec54e4aec3 249 case 0x08: /* PLL used as system clock */
mbed_official 130:1dec54e4aec3 250 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 130:1dec54e4aec3 251 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
mbed_official 130:1dec54e4aec3 252 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 130:1dec54e4aec3 253 pllmull = ( pllmull >> 18) + 2;
mbed_official 130:1dec54e4aec3 254
mbed_official 130:1dec54e4aec3 255 if (pllsource == 0x00)
mbed_official 130:1dec54e4aec3 256 {
mbed_official 130:1dec54e4aec3 257 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official 130:1dec54e4aec3 258 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official 130:1dec54e4aec3 259 }
mbed_official 130:1dec54e4aec3 260 else
mbed_official 130:1dec54e4aec3 261 {
mbed_official 130:1dec54e4aec3 262 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
mbed_official 130:1dec54e4aec3 263 /* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official 130:1dec54e4aec3 264 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
mbed_official 130:1dec54e4aec3 265 }
mbed_official 130:1dec54e4aec3 266 break;
mbed_official 130:1dec54e4aec3 267 default: /* HSI used as system clock */
mbed_official 130:1dec54e4aec3 268 SystemCoreClock = HSI_VALUE;
mbed_official 130:1dec54e4aec3 269 break;
mbed_official 130:1dec54e4aec3 270 }
mbed_official 130:1dec54e4aec3 271 /* Compute HCLK clock frequency ----------------*/
mbed_official 130:1dec54e4aec3 272 /* Get HCLK prescaler */
mbed_official 130:1dec54e4aec3 273 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 130:1dec54e4aec3 274 /* HCLK clock frequency */
mbed_official 130:1dec54e4aec3 275 SystemCoreClock >>= tmp;
mbed_official 130:1dec54e4aec3 276 }
mbed_official 130:1dec54e4aec3 277
mbed_official 130:1dec54e4aec3 278 /**
mbed_official 240:9a7c54113eaf 279 * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
mbed_official 130:1dec54e4aec3 280 * @param None
mbed_official 130:1dec54e4aec3 281 * @retval None
mbed_official 130:1dec54e4aec3 282 */
mbed_official 240:9a7c54113eaf 283 void SetSysClock(void)
mbed_official 130:1dec54e4aec3 284 {
mbed_official 240:9a7c54113eaf 285 /* 1- Try to start with HSE and external clock */
mbed_official 240:9a7c54113eaf 286 #if USE_PLL_HSE_EXTC != 0
mbed_official 240:9a7c54113eaf 287 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 240:9a7c54113eaf 288 #endif
mbed_official 240:9a7c54113eaf 289 {
mbed_official 240:9a7c54113eaf 290 /* 2- If fail try to start with HSE and external xtal */
mbed_official 240:9a7c54113eaf 291 #if USE_PLL_HSE_XTAL != 0
mbed_official 240:9a7c54113eaf 292 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 240:9a7c54113eaf 293 #endif
mbed_official 240:9a7c54113eaf 294 {
mbed_official 240:9a7c54113eaf 295 /* 3- If fail start with HSI clock */
mbed_official 240:9a7c54113eaf 296 if (SetSysClock_PLL_HSI() == 0)
mbed_official 240:9a7c54113eaf 297 {
mbed_official 240:9a7c54113eaf 298 while(1)
mbed_official 240:9a7c54113eaf 299 {
mbed_official 240:9a7c54113eaf 300 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 240:9a7c54113eaf 301 }
mbed_official 240:9a7c54113eaf 302 }
mbed_official 240:9a7c54113eaf 303 }
mbed_official 240:9a7c54113eaf 304 }
mbed_official 240:9a7c54113eaf 305
mbed_official 240:9a7c54113eaf 306 // Output clock on MCO pin (PA8) for debugging purpose
mbed_official 240:9a7c54113eaf 307 /*
mbed_official 240:9a7c54113eaf 308 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
mbed_official 240:9a7c54113eaf 309 GPIO_InitTypeDef GPIO_InitStructure;
mbed_official 240:9a7c54113eaf 310 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
mbed_official 240:9a7c54113eaf 311 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
mbed_official 240:9a7c54113eaf 312 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
mbed_official 240:9a7c54113eaf 313 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
mbed_official 240:9a7c54113eaf 314 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
mbed_official 240:9a7c54113eaf 315 GPIO_Init(GPIOA, &GPIO_InitStructure);
mbed_official 240:9a7c54113eaf 316 GPIO_PinAFConfig(GPIOA, GPIO_PinSource8, GPIO_AF_0);
mbed_official 240:9a7c54113eaf 317 // Output clock on MCO pin
mbed_official 240:9a7c54113eaf 318 // Warning: only RCC_MCOPrescaler_1 is available on STM32F030x8 devices
mbed_official 240:9a7c54113eaf 319 RCC_MCOConfig(RCC_MCOSource_SYSCLK, RCC_MCOPrescaler_1);
mbed_official 240:9a7c54113eaf 320 */
mbed_official 240:9a7c54113eaf 321 }
mbed_official 240:9a7c54113eaf 322
mbed_official 240:9a7c54113eaf 323 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 130:1dec54e4aec3 324 /******************************************************************************/
mbed_official 240:9a7c54113eaf 325 /* PLL (clocked by HSE) used as System clock source */
mbed_official 240:9a7c54113eaf 326 /******************************************************************************/
mbed_official 240:9a7c54113eaf 327 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 240:9a7c54113eaf 328 {
mbed_official 240:9a7c54113eaf 329 __IO uint32_t StartUpCounter = 0;
mbed_official 240:9a7c54113eaf 330 __IO uint32_t HSEStatus = 0;
mbed_official 130:1dec54e4aec3 331
mbed_official 240:9a7c54113eaf 332 /* Bypass HSE: can be done only if HSE is OFF */
mbed_official 240:9a7c54113eaf 333 RCC->CR &= ((uint32_t)~RCC_CR_HSEON); /* To be sure HSE is OFF */
mbed_official 240:9a7c54113eaf 334 if (bypass != 0)
mbed_official 240:9a7c54113eaf 335 {
mbed_official 240:9a7c54113eaf 336 RCC->CR |= ((uint32_t)RCC_CR_HSEBYP);
mbed_official 240:9a7c54113eaf 337 }
mbed_official 240:9a7c54113eaf 338 else
mbed_official 240:9a7c54113eaf 339 {
mbed_official 240:9a7c54113eaf 340 RCC->CR &= ((uint32_t)~RCC_CR_HSEBYP);
mbed_official 240:9a7c54113eaf 341 }
mbed_official 130:1dec54e4aec3 342
mbed_official 240:9a7c54113eaf 343 /* Enable HSE */
mbed_official 240:9a7c54113eaf 344 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
mbed_official 240:9a7c54113eaf 345
mbed_official 240:9a7c54113eaf 346 /* Wait till HSE is ready */
mbed_official 240:9a7c54113eaf 347 do
mbed_official 240:9a7c54113eaf 348 {
mbed_official 240:9a7c54113eaf 349 HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official 240:9a7c54113eaf 350 StartUpCounter++;
mbed_official 240:9a7c54113eaf 351 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official 240:9a7c54113eaf 352
mbed_official 240:9a7c54113eaf 353 /* Check if HSE has started correctly */
mbed_official 240:9a7c54113eaf 354 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official 240:9a7c54113eaf 355 {
mbed_official 240:9a7c54113eaf 356 /* Enable Prefetch Buffer */
mbed_official 240:9a7c54113eaf 357 FLASH->ACR |= FLASH_ACR_PRFTBE;
mbed_official 130:1dec54e4aec3 358
mbed_official 130:1dec54e4aec3 359 /* Enable Prefetch Buffer and set Flash Latency */
mbed_official 130:1dec54e4aec3 360 FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
mbed_official 130:1dec54e4aec3 361
mbed_official 240:9a7c54113eaf 362 /* PLL configuration
mbed_official 240:9a7c54113eaf 363 PLLCLK = 48 MHz (xtal 8 MHz * 6) */
mbed_official 240:9a7c54113eaf 364 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
mbed_official 240:9a7c54113eaf 365 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6
mbed_official 240:9a7c54113eaf 366 | RCC_CFGR_HPRE_DIV1 /* HCLK = 48 MHz */
mbed_official 240:9a7c54113eaf 367 | RCC_CFGR_PPRE_DIV1); /* PCLK = 48 MHz */
mbed_official 240:9a7c54113eaf 368
mbed_official 240:9a7c54113eaf 369 /* Enable PLL */
mbed_official 240:9a7c54113eaf 370 RCC->CR |= RCC_CR_PLLON;
mbed_official 240:9a7c54113eaf 371
mbed_official 240:9a7c54113eaf 372 /* Wait till PLL is ready */
mbed_official 240:9a7c54113eaf 373 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 240:9a7c54113eaf 374 {
mbed_official 240:9a7c54113eaf 375 }
mbed_official 130:1dec54e4aec3 376
mbed_official 240:9a7c54113eaf 377 /* Select PLL as system clock source */
mbed_official 240:9a7c54113eaf 378 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 240:9a7c54113eaf 379 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 240:9a7c54113eaf 380
mbed_official 240:9a7c54113eaf 381 /* Wait till PLL is used as system clock source */
mbed_official 240:9a7c54113eaf 382 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
mbed_official 240:9a7c54113eaf 383 {
mbed_official 240:9a7c54113eaf 384 }
mbed_official 130:1dec54e4aec3 385
mbed_official 240:9a7c54113eaf 386 return 1; // OK
mbed_official 240:9a7c54113eaf 387 }
mbed_official 240:9a7c54113eaf 388 else
mbed_official 240:9a7c54113eaf 389 {
mbed_official 240:9a7c54113eaf 390 return 0; // FAIL
mbed_official 240:9a7c54113eaf 391 }
mbed_official 240:9a7c54113eaf 392 }
mbed_official 240:9a7c54113eaf 393 #endif
mbed_official 240:9a7c54113eaf 394
mbed_official 240:9a7c54113eaf 395 /******************************************************************************/
mbed_official 240:9a7c54113eaf 396 /* PLL (clocked by HSI) used as System clock source */
mbed_official 240:9a7c54113eaf 397 /******************************************************************************/
mbed_official 240:9a7c54113eaf 398 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 240:9a7c54113eaf 399 {
mbed_official 240:9a7c54113eaf 400 /* Enable Prefetch Buffer and set Flash Latency */
mbed_official 240:9a7c54113eaf 401 FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
mbed_official 240:9a7c54113eaf 402
mbed_official 240:9a7c54113eaf 403 /* PLL configuration
mbed_official 240:9a7c54113eaf 404 PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12) */
mbed_official 130:1dec54e4aec3 405 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
mbed_official 240:9a7c54113eaf 406 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL12
mbed_official 240:9a7c54113eaf 407 | RCC_CFGR_HPRE_DIV1 /* HCLK = 48 MHz */
mbed_official 240:9a7c54113eaf 408 | RCC_CFGR_PPRE_DIV1); /* PCLK = 48 MHz */
mbed_official 130:1dec54e4aec3 409
mbed_official 130:1dec54e4aec3 410 /* Enable PLL */
mbed_official 130:1dec54e4aec3 411 RCC->CR |= RCC_CR_PLLON;
mbed_official 130:1dec54e4aec3 412
mbed_official 130:1dec54e4aec3 413 /* Wait till PLL is ready */
mbed_official 130:1dec54e4aec3 414 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 130:1dec54e4aec3 415 {
mbed_official 130:1dec54e4aec3 416 }
mbed_official 130:1dec54e4aec3 417
mbed_official 130:1dec54e4aec3 418 /* Select PLL as system clock source */
mbed_official 130:1dec54e4aec3 419 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 130:1dec54e4aec3 420 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 130:1dec54e4aec3 421
mbed_official 130:1dec54e4aec3 422 /* Wait till PLL is used as system clock source */
mbed_official 130:1dec54e4aec3 423 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
mbed_official 130:1dec54e4aec3 424 {
mbed_official 130:1dec54e4aec3 425 }
mbed_official 240:9a7c54113eaf 426
mbed_official 240:9a7c54113eaf 427 return 1; // OK
mbed_official 130:1dec54e4aec3 428 }
mbed_official 130:1dec54e4aec3 429
mbed_official 130:1dec54e4aec3 430 /**
mbed_official 130:1dec54e4aec3 431 * @}
mbed_official 130:1dec54e4aec3 432 */
mbed_official 130:1dec54e4aec3 433
mbed_official 130:1dec54e4aec3 434 /**
mbed_official 130:1dec54e4aec3 435 * @}
mbed_official 130:1dec54e4aec3 436 */
mbed_official 130:1dec54e4aec3 437
mbed_official 130:1dec54e4aec3 438 /**
mbed_official 130:1dec54e4aec3 439 * @}
mbed_official 130:1dec54e4aec3 440 */
mbed_official 130:1dec54e4aec3 441
mbed_official 130:1dec54e4aec3 442 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
mbed_official 130:1dec54e4aec3 443