shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/system_stm32f0xx.c@130:1dec54e4aec3, 2014-03-21 (annotated)

Committer:
mbed_official
Date:
Fri Mar 21 11:45:09 2014 +0000
Revision:
130:1dec54e4aec3
Child:
240:9a7c54113eaf
Synchronized with git revision e5c9ff6781a4e277a5a454e5a0b037f76e31739d



Full URL: https://github.com/mbedmicro/mbed/commit/e5c9ff6781a4e277a5a454e5a0b037f76e31739d/



STM32F0-Discovery (STM32F051R8) initial port

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 130:1dec54e4aec3 1 /**
mbed_official 130:1dec54e4aec3 2 ******************************************************************************
mbed_official 130:1dec54e4aec3 3 * @file system_stm32f0xx.c
mbed_official 130:1dec54e4aec3 4 * @author MCD Application Team
mbed_official 130:1dec54e4aec3 5 * @version V1.0.1
mbed_official 130:1dec54e4aec3 6 * @date 29-May-2012
mbed_official 130:1dec54e4aec3 7 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
mbed_official 130:1dec54e4aec3 8 * This file contains the system clock configuration for STM32F0xx devices,
mbed_official 130:1dec54e4aec3 9 * and is generated by the clock configuration tool
mbed_official 130:1dec54e4aec3 10 * STM32f0xx_Clock_Configuration_V1.0.1.xls
mbed_official 130:1dec54e4aec3 11 *
mbed_official 130:1dec54e4aec3 12 * 1. This file provides two functions and one global variable to be called from
mbed_official 130:1dec54e4aec3 13 * user application:
mbed_official 130:1dec54e4aec3 14 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
mbed_official 130:1dec54e4aec3 15 * and Divider factors, AHB/APBx prescalers and Flash settings),
mbed_official 130:1dec54e4aec3 16 * depending on the configuration made in the clock xls tool.
mbed_official 130:1dec54e4aec3 17 * This function is called at startup just after reset and
mbed_official 130:1dec54e4aec3 18 * before branch to main program. This call is made inside
mbed_official 130:1dec54e4aec3 19 * the "startup_stm32f0xx.s" file.
mbed_official 130:1dec54e4aec3 20 *
mbed_official 130:1dec54e4aec3 21 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 130:1dec54e4aec3 22 * by the user application to setup the SysTick
mbed_official 130:1dec54e4aec3 23 * timer or configure other parameters.
mbed_official 130:1dec54e4aec3 24 *
mbed_official 130:1dec54e4aec3 25 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 130:1dec54e4aec3 26 * be called whenever the core clock is changed
mbed_official 130:1dec54e4aec3 27 * during program execution.
mbed_official 130:1dec54e4aec3 28 *
mbed_official 130:1dec54e4aec3 29 * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
mbed_official 130:1dec54e4aec3 30 * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
mbed_official 130:1dec54e4aec3 31 * configure the system clock before to branch to main program.
mbed_official 130:1dec54e4aec3 32 *
mbed_official 130:1dec54e4aec3 33 * 3. If the system clock source selected by user fails to startup, the SystemInit()
mbed_official 130:1dec54e4aec3 34 * function will do nothing and HSI still used as system clock source. User can
mbed_official 130:1dec54e4aec3 35 * add some code to deal with this issue inside the SetSysClock() function.
mbed_official 130:1dec54e4aec3 36 *
mbed_official 130:1dec54e4aec3 37 * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
mbed_official 130:1dec54e4aec3 38 * in "stm32f0xx.h" file. When HSE is used as system clock source, directly or
mbed_official 130:1dec54e4aec3 39 * through PLL, and you are using different crystal you have to adapt the HSE
mbed_official 130:1dec54e4aec3 40 * value to your own configuration.
mbed_official 130:1dec54e4aec3 41 *
mbed_official 130:1dec54e4aec3 42 * 5. This file configures the system clock as follows:
mbed_official 130:1dec54e4aec3 43 *=============================================================================
mbed_official 130:1dec54e4aec3 44 *=============================================================================
mbed_official 130:1dec54e4aec3 45 * System Clock source | PLL(HSI)
mbed_official 130:1dec54e4aec3 46 *-----------------------------------------------------------------------------
mbed_official 130:1dec54e4aec3 47 * SYSCLK(Hz) | 48000000
mbed_official 130:1dec54e4aec3 48 *-----------------------------------------------------------------------------
mbed_official 130:1dec54e4aec3 49 * HCLK(Hz) | 48000000
mbed_official 130:1dec54e4aec3 50 *-----------------------------------------------------------------------------
mbed_official 130:1dec54e4aec3 51 * AHB Prescaler | 1
mbed_official 130:1dec54e4aec3 52 *-----------------------------------------------------------------------------
mbed_official 130:1dec54e4aec3 53 * APB Prescaler | 1
mbed_official 130:1dec54e4aec3 54 *-----------------------------------------------------------------------------
mbed_official 130:1dec54e4aec3 55 * HSE Frequency(Hz) | NA
mbed_official 130:1dec54e4aec3 56 *----------------------------------------------------------------------------
mbed_official 130:1dec54e4aec3 57 * PLLMUL | 12
mbed_official 130:1dec54e4aec3 58 *-----------------------------------------------------------------------------
mbed_official 130:1dec54e4aec3 59 * PREDIV | 2
mbed_official 130:1dec54e4aec3 60 *-----------------------------------------------------------------------------
mbed_official 130:1dec54e4aec3 61 * I2S input clock(Hz) | 48000000
mbed_official 130:1dec54e4aec3 62 * |
mbed_official 130:1dec54e4aec3 63 * To achieve the following I2S config: |
mbed_official 130:1dec54e4aec3 64 * - Master clock output (MCKO): OFF |
mbed_official 130:1dec54e4aec3 65 * - Frame wide : 16bit |
mbed_official 130:1dec54e4aec3 66 * - Audio sampling freq (KHz) : 44.1 |
mbed_official 130:1dec54e4aec3 67 * - Error % : 0.2674 |
mbed_official 130:1dec54e4aec3 68 *-----------------------------------------------------------------------------
mbed_official 130:1dec54e4aec3 69 * Flash Latency(WS) | 1
mbed_official 130:1dec54e4aec3 70 *-----------------------------------------------------------------------------
mbed_official 130:1dec54e4aec3 71 * Prefetch Buffer | ON
mbed_official 130:1dec54e4aec3 72 *-----------------------------------------------------------------------------
mbed_official 130:1dec54e4aec3 73 ******************************************************************************
mbed_official 130:1dec54e4aec3 74 * @attention
mbed_official 130:1dec54e4aec3 75 *
mbed_official 130:1dec54e4aec3 76 * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
mbed_official 130:1dec54e4aec3 77 *
mbed_official 130:1dec54e4aec3 78 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
mbed_official 130:1dec54e4aec3 79 * You may not use this file except in compliance with the License.
mbed_official 130:1dec54e4aec3 80 * You may obtain a copy of the License at:
mbed_official 130:1dec54e4aec3 81 *
mbed_official 130:1dec54e4aec3 82 * http://www.st.com/software_license_agreement_liberty_v2
mbed_official 130:1dec54e4aec3 83 *
mbed_official 130:1dec54e4aec3 84 * Unless required by applicable law or agreed to in writing, software
mbed_official 130:1dec54e4aec3 85 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 130:1dec54e4aec3 86 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 130:1dec54e4aec3 87 * See the License for the specific language governing permissions and
mbed_official 130:1dec54e4aec3 88 * limitations under the License.
mbed_official 130:1dec54e4aec3 89 *
mbed_official 130:1dec54e4aec3 90 ******************************************************************************
mbed_official 130:1dec54e4aec3 91 */
mbed_official 130:1dec54e4aec3 92
mbed_official 130:1dec54e4aec3 93 /** @addtogroup CMSIS
mbed_official 130:1dec54e4aec3 94 * @{
mbed_official 130:1dec54e4aec3 95 */
mbed_official 130:1dec54e4aec3 96
mbed_official 130:1dec54e4aec3 97 /** @addtogroup stm32f0xx_system
mbed_official 130:1dec54e4aec3 98 * @{
mbed_official 130:1dec54e4aec3 99 */
mbed_official 130:1dec54e4aec3 100
mbed_official 130:1dec54e4aec3 101 /** @addtogroup STM32F0xx_System_Private_Includes
mbed_official 130:1dec54e4aec3 102 * @{
mbed_official 130:1dec54e4aec3 103 */
mbed_official 130:1dec54e4aec3 104
mbed_official 130:1dec54e4aec3 105 #include "stm32f0xx.h"
mbed_official 130:1dec54e4aec3 106
mbed_official 130:1dec54e4aec3 107 /**
mbed_official 130:1dec54e4aec3 108 * @}
mbed_official 130:1dec54e4aec3 109 */
mbed_official 130:1dec54e4aec3 110
mbed_official 130:1dec54e4aec3 111 /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
mbed_official 130:1dec54e4aec3 112 * @{
mbed_official 130:1dec54e4aec3 113 */
mbed_official 130:1dec54e4aec3 114
mbed_official 130:1dec54e4aec3 115 /**
mbed_official 130:1dec54e4aec3 116 * @}
mbed_official 130:1dec54e4aec3 117 */
mbed_official 130:1dec54e4aec3 118
mbed_official 130:1dec54e4aec3 119 /** @addtogroup STM32F0xx_System_Private_Defines
mbed_official 130:1dec54e4aec3 120 * @{
mbed_official 130:1dec54e4aec3 121 */
mbed_official 130:1dec54e4aec3 122 /**
mbed_official 130:1dec54e4aec3 123 * @}
mbed_official 130:1dec54e4aec3 124 */
mbed_official 130:1dec54e4aec3 125
mbed_official 130:1dec54e4aec3 126 /** @addtogroup STM32F0xx_System_Private_Macros
mbed_official 130:1dec54e4aec3 127 * @{
mbed_official 130:1dec54e4aec3 128 */
mbed_official 130:1dec54e4aec3 129
mbed_official 130:1dec54e4aec3 130 /**
mbed_official 130:1dec54e4aec3 131 * @}
mbed_official 130:1dec54e4aec3 132 */
mbed_official 130:1dec54e4aec3 133
mbed_official 130:1dec54e4aec3 134 /** @addtogroup STM32F0xx_System_Private_Variables
mbed_official 130:1dec54e4aec3 135 * @{
mbed_official 130:1dec54e4aec3 136 */
mbed_official 130:1dec54e4aec3 137 uint32_t SystemCoreClock = 48000000;
mbed_official 130:1dec54e4aec3 138 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 130:1dec54e4aec3 139
mbed_official 130:1dec54e4aec3 140 /**
mbed_official 130:1dec54e4aec3 141 * @}
mbed_official 130:1dec54e4aec3 142 */
mbed_official 130:1dec54e4aec3 143
mbed_official 130:1dec54e4aec3 144 /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
mbed_official 130:1dec54e4aec3 145 * @{
mbed_official 130:1dec54e4aec3 146 */
mbed_official 130:1dec54e4aec3 147
mbed_official 130:1dec54e4aec3 148 static void SetSysClock(void);
mbed_official 130:1dec54e4aec3 149
mbed_official 130:1dec54e4aec3 150 /**
mbed_official 130:1dec54e4aec3 151 * @}
mbed_official 130:1dec54e4aec3 152 */
mbed_official 130:1dec54e4aec3 153
mbed_official 130:1dec54e4aec3 154 /** @addtogroup STM32F0xx_System_Private_Functions
mbed_official 130:1dec54e4aec3 155 * @{
mbed_official 130:1dec54e4aec3 156 */
mbed_official 130:1dec54e4aec3 157
mbed_official 130:1dec54e4aec3 158 /**
mbed_official 130:1dec54e4aec3 159 * @brief Setup the microcontroller system.
mbed_official 130:1dec54e4aec3 160 * Initialize the Embedded Flash Interface, the PLL and update the
mbed_official 130:1dec54e4aec3 161 * SystemCoreClock variable.
mbed_official 130:1dec54e4aec3 162 * @param None
mbed_official 130:1dec54e4aec3 163 * @retval None
mbed_official 130:1dec54e4aec3 164 */
mbed_official 130:1dec54e4aec3 165 void SystemInit (void)
mbed_official 130:1dec54e4aec3 166 {
mbed_official 130:1dec54e4aec3 167 /* Set HSION bit */
mbed_official 130:1dec54e4aec3 168 RCC->CR |= (uint32_t)0x00000001;
mbed_official 130:1dec54e4aec3 169
mbed_official 130:1dec54e4aec3 170 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
mbed_official 130:1dec54e4aec3 171 RCC->CFGR &= (uint32_t)0xF8FFB80C;
mbed_official 130:1dec54e4aec3 172
mbed_official 130:1dec54e4aec3 173 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 130:1dec54e4aec3 174 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 130:1dec54e4aec3 175
mbed_official 130:1dec54e4aec3 176 /* Reset HSEBYP bit */
mbed_official 130:1dec54e4aec3 177 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 130:1dec54e4aec3 178
mbed_official 130:1dec54e4aec3 179 /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
mbed_official 130:1dec54e4aec3 180 RCC->CFGR &= (uint32_t)0xFFC0FFFF;
mbed_official 130:1dec54e4aec3 181
mbed_official 130:1dec54e4aec3 182 /* Reset PREDIV1[3:0] bits */
mbed_official 130:1dec54e4aec3 183 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
mbed_official 130:1dec54e4aec3 184
mbed_official 130:1dec54e4aec3 185 /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
mbed_official 130:1dec54e4aec3 186 RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
mbed_official 130:1dec54e4aec3 187
mbed_official 130:1dec54e4aec3 188 /* Reset HSI14 bit */
mbed_official 130:1dec54e4aec3 189 RCC->CR2 &= (uint32_t)0xFFFFFFFE;
mbed_official 130:1dec54e4aec3 190
mbed_official 130:1dec54e4aec3 191 /* Disable all interrupts */
mbed_official 130:1dec54e4aec3 192 RCC->CIR = 0x00000000;
mbed_official 130:1dec54e4aec3 193
mbed_official 130:1dec54e4aec3 194 /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
mbed_official 130:1dec54e4aec3 195 SetSysClock();
mbed_official 130:1dec54e4aec3 196 }
mbed_official 130:1dec54e4aec3 197
mbed_official 130:1dec54e4aec3 198 /**
mbed_official 130:1dec54e4aec3 199 * @brief Update SystemCoreClock according to Clock Register Values
mbed_official 130:1dec54e4aec3 200 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 130:1dec54e4aec3 201 * be used by the user application to setup the SysTick timer or configure
mbed_official 130:1dec54e4aec3 202 * other parameters.
mbed_official 130:1dec54e4aec3 203 *
mbed_official 130:1dec54e4aec3 204 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 130:1dec54e4aec3 205 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 130:1dec54e4aec3 206 * based on this variable will be incorrect.
mbed_official 130:1dec54e4aec3 207 *
mbed_official 130:1dec54e4aec3 208 * @note - The system frequency computed by this function is not the real
mbed_official 130:1dec54e4aec3 209 * frequency in the chip. It is calculated based on the predefined
mbed_official 130:1dec54e4aec3 210 * constant and the selected clock source:
mbed_official 130:1dec54e4aec3 211 *
mbed_official 130:1dec54e4aec3 212 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 130:1dec54e4aec3 213 *
mbed_official 130:1dec54e4aec3 214 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 130:1dec54e4aec3 215 *
mbed_official 130:1dec54e4aec3 216 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 130:1dec54e4aec3 217 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 130:1dec54e4aec3 218 *
mbed_official 130:1dec54e4aec3 219 * (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
mbed_official 130:1dec54e4aec3 220 * 8 MHz) but the real value may vary depending on the variations
mbed_official 130:1dec54e4aec3 221 * in voltage and temperature.
mbed_official 130:1dec54e4aec3 222 *
mbed_official 130:1dec54e4aec3 223 * (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
mbed_official 130:1dec54e4aec3 224 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 130:1dec54e4aec3 225 * frequency of the crystal used. Otherwise, this function may
mbed_official 130:1dec54e4aec3 226 * have wrong result.
mbed_official 130:1dec54e4aec3 227 *
mbed_official 130:1dec54e4aec3 228 * - The result of this function could be not correct when using fractional
mbed_official 130:1dec54e4aec3 229 * value for HSE crystal.
mbed_official 130:1dec54e4aec3 230 * @param None
mbed_official 130:1dec54e4aec3 231 * @retval None
mbed_official 130:1dec54e4aec3 232 */
mbed_official 130:1dec54e4aec3 233 void SystemCoreClockUpdate (void)
mbed_official 130:1dec54e4aec3 234 {
mbed_official 130:1dec54e4aec3 235 uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
mbed_official 130:1dec54e4aec3 236
mbed_official 130:1dec54e4aec3 237 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 130:1dec54e4aec3 238 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 130:1dec54e4aec3 239
mbed_official 130:1dec54e4aec3 240 switch (tmp)
mbed_official 130:1dec54e4aec3 241 {
mbed_official 130:1dec54e4aec3 242 case 0x00: /* HSI used as system clock */
mbed_official 130:1dec54e4aec3 243 SystemCoreClock = HSI_VALUE;
mbed_official 130:1dec54e4aec3 244 break;
mbed_official 130:1dec54e4aec3 245 case 0x04: /* HSE used as system clock */
mbed_official 130:1dec54e4aec3 246 SystemCoreClock = HSE_VALUE;
mbed_official 130:1dec54e4aec3 247 break;
mbed_official 130:1dec54e4aec3 248 case 0x08: /* PLL used as system clock */
mbed_official 130:1dec54e4aec3 249 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 130:1dec54e4aec3 250 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
mbed_official 130:1dec54e4aec3 251 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 130:1dec54e4aec3 252 pllmull = ( pllmull >> 18) + 2;
mbed_official 130:1dec54e4aec3 253
mbed_official 130:1dec54e4aec3 254 if (pllsource == 0x00)
mbed_official 130:1dec54e4aec3 255 {
mbed_official 130:1dec54e4aec3 256 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official 130:1dec54e4aec3 257 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official 130:1dec54e4aec3 258 }
mbed_official 130:1dec54e4aec3 259 else
mbed_official 130:1dec54e4aec3 260 {
mbed_official 130:1dec54e4aec3 261 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
mbed_official 130:1dec54e4aec3 262 /* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official 130:1dec54e4aec3 263 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
mbed_official 130:1dec54e4aec3 264 }
mbed_official 130:1dec54e4aec3 265 break;
mbed_official 130:1dec54e4aec3 266 default: /* HSI used as system clock */
mbed_official 130:1dec54e4aec3 267 SystemCoreClock = HSI_VALUE;
mbed_official 130:1dec54e4aec3 268 break;
mbed_official 130:1dec54e4aec3 269 }
mbed_official 130:1dec54e4aec3 270 /* Compute HCLK clock frequency ----------------*/
mbed_official 130:1dec54e4aec3 271 /* Get HCLK prescaler */
mbed_official 130:1dec54e4aec3 272 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 130:1dec54e4aec3 273 /* HCLK clock frequency */
mbed_official 130:1dec54e4aec3 274 SystemCoreClock >>= tmp;
mbed_official 130:1dec54e4aec3 275 }
mbed_official 130:1dec54e4aec3 276
mbed_official 130:1dec54e4aec3 277 /**
mbed_official 130:1dec54e4aec3 278 * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash
mbed_official 130:1dec54e4aec3 279 * settings.
mbed_official 130:1dec54e4aec3 280 * @note This function should be called only once the RCC clock configuration
mbed_official 130:1dec54e4aec3 281 * is reset to the default reset state (done in SystemInit() function).
mbed_official 130:1dec54e4aec3 282 * @param None
mbed_official 130:1dec54e4aec3 283 * @retval None
mbed_official 130:1dec54e4aec3 284 */
mbed_official 130:1dec54e4aec3 285 static void SetSysClock(void)
mbed_official 130:1dec54e4aec3 286 {
mbed_official 130:1dec54e4aec3 287 /******************************************************************************/
mbed_official 130:1dec54e4aec3 288 /* PLL (clocked by HSI) used as System clock source */
mbed_official 130:1dec54e4aec3 289 /******************************************************************************/
mbed_official 130:1dec54e4aec3 290
mbed_official 130:1dec54e4aec3 291 /* At this stage the HSI is already enabled and used as System clock source */
mbed_official 130:1dec54e4aec3 292
mbed_official 130:1dec54e4aec3 293 /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
mbed_official 130:1dec54e4aec3 294
mbed_official 130:1dec54e4aec3 295 /* Enable Prefetch Buffer and set Flash Latency */
mbed_official 130:1dec54e4aec3 296 FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
mbed_official 130:1dec54e4aec3 297
mbed_official 130:1dec54e4aec3 298 /* HCLK = SYSCLK / 1 */
mbed_official 130:1dec54e4aec3 299 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
mbed_official 130:1dec54e4aec3 300
mbed_official 130:1dec54e4aec3 301 /* PCLK = HCLK / 1 */
mbed_official 130:1dec54e4aec3 302 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
mbed_official 130:1dec54e4aec3 303
mbed_official 130:1dec54e4aec3 304 /* PLL configuration */
mbed_official 130:1dec54e4aec3 305 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
mbed_official 130:1dec54e4aec3 306 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL12);
mbed_official 130:1dec54e4aec3 307
mbed_official 130:1dec54e4aec3 308 /* Enable PLL */
mbed_official 130:1dec54e4aec3 309 RCC->CR |= RCC_CR_PLLON;
mbed_official 130:1dec54e4aec3 310
mbed_official 130:1dec54e4aec3 311 /* Wait till PLL is ready */
mbed_official 130:1dec54e4aec3 312 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 130:1dec54e4aec3 313 {
mbed_official 130:1dec54e4aec3 314 }
mbed_official 130:1dec54e4aec3 315
mbed_official 130:1dec54e4aec3 316 /* Select PLL as system clock source */
mbed_official 130:1dec54e4aec3 317 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 130:1dec54e4aec3 318 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 130:1dec54e4aec3 319
mbed_official 130:1dec54e4aec3 320 /* Wait till PLL is used as system clock source */
mbed_official 130:1dec54e4aec3 321 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
mbed_official 130:1dec54e4aec3 322 {
mbed_official 130:1dec54e4aec3 323 }
mbed_official 130:1dec54e4aec3 324 }
mbed_official 130:1dec54e4aec3 325
mbed_official 130:1dec54e4aec3 326 /**
mbed_official 130:1dec54e4aec3 327 * @}
mbed_official 130:1dec54e4aec3 328 */
mbed_official 130:1dec54e4aec3 329
mbed_official 130:1dec54e4aec3 330 /**
mbed_official 130:1dec54e4aec3 331 * @}
mbed_official 130:1dec54e4aec3 332 */
mbed_official 130:1dec54e4aec3 333
mbed_official 130:1dec54e4aec3 334 /**
mbed_official 130:1dec54e4aec3 335 * @}
mbed_official 130:1dec54e4aec3 336 */
mbed_official 130:1dec54e4aec3 337
mbed_official 130:1dec54e4aec3 338 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
mbed_official 130:1dec54e4aec3 339