mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/system_stm32f30x.c@162:937d965048d3, 2014-04-22 (annotated)
- Committer:
- mbed_official
- Date:
- Tue Apr 22 13:30:06 2014 +0100
- Revision:
- 162:937d965048d3
- Parent:
- 138:ec7ee4660c49
- Child:
- 167:d5744491c362
Synchronized with git revision 6b9fca177ab428a93a520d666ca5b4aeb921da51
Full URL: https://github.com/mbedmicro/mbed/commit/6b9fca177ab428a93a520d666ca5b4aeb921da51/
Update gpio_irq_api.c
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 125:23cc3068a9e4 | 1 | /** |
mbed_official | 125:23cc3068a9e4 | 2 | ****************************************************************************** |
mbed_official | 125:23cc3068a9e4 | 3 | * @file system_stm32f30x.c |
mbed_official | 125:23cc3068a9e4 | 4 | * @author MCD Application Team |
mbed_official | 125:23cc3068a9e4 | 5 | * @version V1.0.0 |
mbed_official | 125:23cc3068a9e4 | 6 | * @date 05-March-2014 |
mbed_official | 125:23cc3068a9e4 | 7 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. |
mbed_official | 125:23cc3068a9e4 | 8 | * This file contains the system clock configuration for STM32F30x devices, |
mbed_official | 125:23cc3068a9e4 | 9 | * and is generated by the clock configuration tool |
mbed_official | 125:23cc3068a9e4 | 10 | * stm32f30x_Clock_Configuration_V1.0.0.xls |
mbed_official | 125:23cc3068a9e4 | 11 | * |
mbed_official | 125:23cc3068a9e4 | 12 | * 1. This file provides two functions and one global variable to be called from |
mbed_official | 125:23cc3068a9e4 | 13 | * user application: |
mbed_official | 125:23cc3068a9e4 | 14 | * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier |
mbed_official | 125:23cc3068a9e4 | 15 | * and Divider factors, AHB/APBx prescalers and Flash settings), |
mbed_official | 125:23cc3068a9e4 | 16 | * depending on the configuration made in the clock xls tool. |
mbed_official | 125:23cc3068a9e4 | 17 | * This function is called at startup just after reset and |
mbed_official | 125:23cc3068a9e4 | 18 | * before branch to main program. This call is made inside |
mbed_official | 125:23cc3068a9e4 | 19 | * the "startup_stm32f30x.s" file. |
mbed_official | 125:23cc3068a9e4 | 20 | * |
mbed_official | 125:23cc3068a9e4 | 21 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
mbed_official | 125:23cc3068a9e4 | 22 | * by the user application to setup the SysTick |
mbed_official | 125:23cc3068a9e4 | 23 | * timer or configure other parameters. |
mbed_official | 125:23cc3068a9e4 | 24 | * |
mbed_official | 125:23cc3068a9e4 | 25 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
mbed_official | 125:23cc3068a9e4 | 26 | * be called whenever the core clock is changed |
mbed_official | 125:23cc3068a9e4 | 27 | * during program execution. |
mbed_official | 125:23cc3068a9e4 | 28 | * |
mbed_official | 125:23cc3068a9e4 | 29 | * 2. After each device reset the HSI (8 MHz) is used as system clock source. |
mbed_official | 125:23cc3068a9e4 | 30 | * Then SystemInit() function is called, in "startup_stm32f30x.s" file, to |
mbed_official | 125:23cc3068a9e4 | 31 | * configure the system clock before to branch to main program. |
mbed_official | 125:23cc3068a9e4 | 32 | * |
mbed_official | 125:23cc3068a9e4 | 33 | * 3. If the system clock source selected by user fails to startup, the SystemInit() |
mbed_official | 125:23cc3068a9e4 | 34 | * function will do nothing and HSI still used as system clock source. User can |
mbed_official | 125:23cc3068a9e4 | 35 | * add some code to deal with this issue inside the SetSysClock() function. |
mbed_official | 125:23cc3068a9e4 | 36 | * |
mbed_official | 125:23cc3068a9e4 | 37 | * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define |
mbed_official | 125:23cc3068a9e4 | 38 | * in "stm32f30x.h" file. When HSE is used as system clock source, directly or |
mbed_official | 125:23cc3068a9e4 | 39 | * through PLL, and you are using different crystal you have to adapt the HSE |
mbed_official | 125:23cc3068a9e4 | 40 | * value to your own configuration. |
mbed_official | 125:23cc3068a9e4 | 41 | * |
mbed_official | 125:23cc3068a9e4 | 42 | * 5. This file configures the system clock as follows: |
mbed_official | 125:23cc3068a9e4 | 43 | *----------------------------------------------------------------------------- |
mbed_official | 135:067cc8ba23da | 44 | * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI |
mbed_official | 135:067cc8ba23da | 45 | * | (external 8 MHz clock) | (internal 8 MHz) |
mbed_official | 135:067cc8ba23da | 46 | * | 2- PLL_HSE_XTAL | |
mbed_official | 135:067cc8ba23da | 47 | * | (external 8 MHz xtal) | |
mbed_official | 125:23cc3068a9e4 | 48 | *----------------------------------------------------------------------------- |
mbed_official | 135:067cc8ba23da | 49 | * SYSCLK(MHz) | 72 | 64 |
mbed_official | 125:23cc3068a9e4 | 50 | *----------------------------------------------------------------------------- |
mbed_official | 135:067cc8ba23da | 51 | * AHBCLK (MHz) | 72 | 64 |
mbed_official | 125:23cc3068a9e4 | 52 | *----------------------------------------------------------------------------- |
mbed_official | 135:067cc8ba23da | 53 | * APB1CLK (MHz) | 36 | 32 |
mbed_official | 125:23cc3068a9e4 | 54 | *----------------------------------------------------------------------------- |
mbed_official | 135:067cc8ba23da | 55 | * APB2CLK (MHz) | 72 | 64 |
mbed_official | 125:23cc3068a9e4 | 56 | *----------------------------------------------------------------------------- |
mbed_official | 135:067cc8ba23da | 57 | * USB capable (48 MHz precise clock) | YES | NO |
mbed_official | 135:067cc8ba23da | 58 | *----------------------------------------------------------------------------- |
mbed_official | 125:23cc3068a9e4 | 59 | ****************************************************************************** |
mbed_official | 125:23cc3068a9e4 | 60 | * @attention |
mbed_official | 125:23cc3068a9e4 | 61 | * |
mbed_official | 125:23cc3068a9e4 | 62 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 125:23cc3068a9e4 | 63 | * |
mbed_official | 125:23cc3068a9e4 | 64 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 125:23cc3068a9e4 | 65 | * are permitted provided that the following conditions are met: |
mbed_official | 125:23cc3068a9e4 | 66 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 125:23cc3068a9e4 | 67 | * this list of conditions and the following disclaimer. |
mbed_official | 125:23cc3068a9e4 | 68 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 125:23cc3068a9e4 | 69 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 125:23cc3068a9e4 | 70 | * and/or other materials provided with the distribution. |
mbed_official | 125:23cc3068a9e4 | 71 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 125:23cc3068a9e4 | 72 | * may be used to endorse or promote products derived from this software |
mbed_official | 125:23cc3068a9e4 | 73 | * without specific prior written permission. |
mbed_official | 125:23cc3068a9e4 | 74 | * |
mbed_official | 125:23cc3068a9e4 | 75 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 125:23cc3068a9e4 | 76 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 125:23cc3068a9e4 | 77 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 125:23cc3068a9e4 | 78 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 125:23cc3068a9e4 | 79 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 125:23cc3068a9e4 | 80 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 125:23cc3068a9e4 | 81 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 125:23cc3068a9e4 | 82 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 125:23cc3068a9e4 | 83 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 125:23cc3068a9e4 | 84 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 125:23cc3068a9e4 | 85 | * |
mbed_official | 125:23cc3068a9e4 | 86 | ****************************************************************************** |
mbed_official | 125:23cc3068a9e4 | 87 | */ |
mbed_official | 135:067cc8ba23da | 88 | |
mbed_official | 125:23cc3068a9e4 | 89 | /** @addtogroup CMSIS |
mbed_official | 125:23cc3068a9e4 | 90 | * @{ |
mbed_official | 125:23cc3068a9e4 | 91 | */ |
mbed_official | 125:23cc3068a9e4 | 92 | |
mbed_official | 125:23cc3068a9e4 | 93 | /** @addtogroup stm32f30x_system |
mbed_official | 125:23cc3068a9e4 | 94 | * @{ |
mbed_official | 125:23cc3068a9e4 | 95 | */ |
mbed_official | 125:23cc3068a9e4 | 96 | |
mbed_official | 125:23cc3068a9e4 | 97 | /** @addtogroup STM32F30x_System_Private_Includes |
mbed_official | 125:23cc3068a9e4 | 98 | * @{ |
mbed_official | 125:23cc3068a9e4 | 99 | */ |
mbed_official | 125:23cc3068a9e4 | 100 | |
mbed_official | 125:23cc3068a9e4 | 101 | #include "stm32f30x.h" |
mbed_official | 125:23cc3068a9e4 | 102 | |
mbed_official | 125:23cc3068a9e4 | 103 | /** |
mbed_official | 125:23cc3068a9e4 | 104 | * @} |
mbed_official | 125:23cc3068a9e4 | 105 | */ |
mbed_official | 125:23cc3068a9e4 | 106 | |
mbed_official | 125:23cc3068a9e4 | 107 | /** @addtogroup STM32F30x_System_Private_TypesDefinitions |
mbed_official | 125:23cc3068a9e4 | 108 | * @{ |
mbed_official | 125:23cc3068a9e4 | 109 | */ |
mbed_official | 125:23cc3068a9e4 | 110 | |
mbed_official | 125:23cc3068a9e4 | 111 | /** |
mbed_official | 125:23cc3068a9e4 | 112 | * @} |
mbed_official | 125:23cc3068a9e4 | 113 | */ |
mbed_official | 125:23cc3068a9e4 | 114 | |
mbed_official | 125:23cc3068a9e4 | 115 | /** @addtogroup STM32F30x_System_Private_Defines |
mbed_official | 125:23cc3068a9e4 | 116 | * @{ |
mbed_official | 125:23cc3068a9e4 | 117 | */ |
mbed_official | 135:067cc8ba23da | 118 | |
mbed_official | 125:23cc3068a9e4 | 119 | /*!< Uncomment the following line if you need to relocate your vector Table in |
mbed_official | 125:23cc3068a9e4 | 120 | Internal SRAM. */ |
mbed_official | 125:23cc3068a9e4 | 121 | /* #define VECT_TAB_SRAM */ |
mbed_official | 125:23cc3068a9e4 | 122 | #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. |
mbed_official | 125:23cc3068a9e4 | 123 | This value must be a multiple of 0x200. */ |
mbed_official | 125:23cc3068a9e4 | 124 | /** |
mbed_official | 125:23cc3068a9e4 | 125 | * @} |
mbed_official | 125:23cc3068a9e4 | 126 | */ |
mbed_official | 125:23cc3068a9e4 | 127 | |
mbed_official | 125:23cc3068a9e4 | 128 | /** @addtogroup STM32F30x_System_Private_Macros |
mbed_official | 125:23cc3068a9e4 | 129 | * @{ |
mbed_official | 125:23cc3068a9e4 | 130 | */ |
mbed_official | 125:23cc3068a9e4 | 131 | |
mbed_official | 135:067cc8ba23da | 132 | /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ |
mbed_official | 135:067cc8ba23da | 133 | #define USE_PLL_HSE_EXTC (1) /* Use external clock */ |
mbed_official | 135:067cc8ba23da | 134 | #define USE_PLL_HSE_XTAL (1) /* Use external xtal */ |
mbed_official | 135:067cc8ba23da | 135 | |
mbed_official | 125:23cc3068a9e4 | 136 | /** |
mbed_official | 125:23cc3068a9e4 | 137 | * @} |
mbed_official | 125:23cc3068a9e4 | 138 | */ |
mbed_official | 125:23cc3068a9e4 | 139 | |
mbed_official | 125:23cc3068a9e4 | 140 | /** @addtogroup STM32F30x_System_Private_Variables |
mbed_official | 125:23cc3068a9e4 | 141 | * @{ |
mbed_official | 125:23cc3068a9e4 | 142 | */ |
mbed_official | 125:23cc3068a9e4 | 143 | |
mbed_official | 138:ec7ee4660c49 | 144 | uint32_t SystemCoreClock = 64000000; /* Default with HSI. Will be updated if HSE is used */ |
mbed_official | 125:23cc3068a9e4 | 145 | |
mbed_official | 135:067cc8ba23da | 146 | __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
mbed_official | 125:23cc3068a9e4 | 147 | |
mbed_official | 125:23cc3068a9e4 | 148 | /** |
mbed_official | 125:23cc3068a9e4 | 149 | * @} |
mbed_official | 125:23cc3068a9e4 | 150 | */ |
mbed_official | 125:23cc3068a9e4 | 151 | |
mbed_official | 125:23cc3068a9e4 | 152 | /** @addtogroup STM32F30x_System_Private_FunctionPrototypes |
mbed_official | 125:23cc3068a9e4 | 153 | * @{ |
mbed_official | 125:23cc3068a9e4 | 154 | */ |
mbed_official | 125:23cc3068a9e4 | 155 | |
mbed_official | 135:067cc8ba23da | 156 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
mbed_official | 135:067cc8ba23da | 157 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
mbed_official | 135:067cc8ba23da | 158 | #endif |
mbed_official | 135:067cc8ba23da | 159 | |
mbed_official | 135:067cc8ba23da | 160 | uint8_t SetSysClock_PLL_HSI(void); |
mbed_official | 135:067cc8ba23da | 161 | |
mbed_official | 125:23cc3068a9e4 | 162 | /** |
mbed_official | 125:23cc3068a9e4 | 163 | * @} |
mbed_official | 125:23cc3068a9e4 | 164 | */ |
mbed_official | 125:23cc3068a9e4 | 165 | |
mbed_official | 125:23cc3068a9e4 | 166 | /** @addtogroup STM32F30x_System_Private_Functions |
mbed_official | 125:23cc3068a9e4 | 167 | * @{ |
mbed_official | 125:23cc3068a9e4 | 168 | */ |
mbed_official | 125:23cc3068a9e4 | 169 | |
mbed_official | 125:23cc3068a9e4 | 170 | /** |
mbed_official | 125:23cc3068a9e4 | 171 | * @brief Setup the microcontroller system |
mbed_official | 125:23cc3068a9e4 | 172 | * Initialize the Embedded Flash Interface, the PLL and update the |
mbed_official | 125:23cc3068a9e4 | 173 | * SystemFrequency variable. |
mbed_official | 125:23cc3068a9e4 | 174 | * @param None |
mbed_official | 125:23cc3068a9e4 | 175 | * @retval None |
mbed_official | 125:23cc3068a9e4 | 176 | */ |
mbed_official | 125:23cc3068a9e4 | 177 | void SystemInit(void) |
mbed_official | 125:23cc3068a9e4 | 178 | { |
mbed_official | 125:23cc3068a9e4 | 179 | /* FPU settings ------------------------------------------------------------*/ |
mbed_official | 125:23cc3068a9e4 | 180 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
mbed_official | 125:23cc3068a9e4 | 181 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ |
mbed_official | 125:23cc3068a9e4 | 182 | #endif |
mbed_official | 125:23cc3068a9e4 | 183 | |
mbed_official | 125:23cc3068a9e4 | 184 | /* Reset the RCC clock configuration to the default reset state ------------*/ |
mbed_official | 125:23cc3068a9e4 | 185 | /* Set HSION bit */ |
mbed_official | 125:23cc3068a9e4 | 186 | RCC->CR |= (uint32_t)0x00000001; |
mbed_official | 125:23cc3068a9e4 | 187 | |
mbed_official | 125:23cc3068a9e4 | 188 | /* Reset CFGR register */ |
mbed_official | 125:23cc3068a9e4 | 189 | RCC->CFGR &= 0xF87FC00C; |
mbed_official | 125:23cc3068a9e4 | 190 | |
mbed_official | 125:23cc3068a9e4 | 191 | /* Reset HSEON, CSSON and PLLON bits */ |
mbed_official | 125:23cc3068a9e4 | 192 | RCC->CR &= (uint32_t)0xFEF6FFFF; |
mbed_official | 125:23cc3068a9e4 | 193 | |
mbed_official | 125:23cc3068a9e4 | 194 | /* Reset HSEBYP bit */ |
mbed_official | 125:23cc3068a9e4 | 195 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
mbed_official | 125:23cc3068a9e4 | 196 | |
mbed_official | 125:23cc3068a9e4 | 197 | /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */ |
mbed_official | 125:23cc3068a9e4 | 198 | RCC->CFGR &= (uint32_t)0xFF80FFFF; |
mbed_official | 125:23cc3068a9e4 | 199 | |
mbed_official | 125:23cc3068a9e4 | 200 | /* Reset PREDIV1[3:0] bits */ |
mbed_official | 125:23cc3068a9e4 | 201 | RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; |
mbed_official | 125:23cc3068a9e4 | 202 | |
mbed_official | 125:23cc3068a9e4 | 203 | /* Reset USARTSW[1:0], I2CSW and TIMs bits */ |
mbed_official | 125:23cc3068a9e4 | 204 | RCC->CFGR3 &= (uint32_t)0xFF00FCCC; |
mbed_official | 125:23cc3068a9e4 | 205 | |
mbed_official | 125:23cc3068a9e4 | 206 | /* Disable all interrupts */ |
mbed_official | 125:23cc3068a9e4 | 207 | RCC->CIR = 0x00000000; |
mbed_official | 125:23cc3068a9e4 | 208 | |
mbed_official | 135:067cc8ba23da | 209 | /* Configure the Vector Table location add offset address ------------------*/ |
mbed_official | 125:23cc3068a9e4 | 210 | #ifdef VECT_TAB_SRAM |
mbed_official | 135:067cc8ba23da | 211 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
mbed_official | 125:23cc3068a9e4 | 212 | #else |
mbed_official | 135:067cc8ba23da | 213 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ |
mbed_official | 125:23cc3068a9e4 | 214 | #endif |
mbed_official | 125:23cc3068a9e4 | 215 | } |
mbed_official | 125:23cc3068a9e4 | 216 | |
mbed_official | 125:23cc3068a9e4 | 217 | /** |
mbed_official | 125:23cc3068a9e4 | 218 | * @brief Update SystemCoreClock variable according to Clock Register Values. |
mbed_official | 125:23cc3068a9e4 | 219 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
mbed_official | 125:23cc3068a9e4 | 220 | * be used by the user application to setup the SysTick timer or configure |
mbed_official | 125:23cc3068a9e4 | 221 | * other parameters. |
mbed_official | 125:23cc3068a9e4 | 222 | * |
mbed_official | 125:23cc3068a9e4 | 223 | * @note Each time the core clock (HCLK) changes, this function must be called |
mbed_official | 125:23cc3068a9e4 | 224 | * to update SystemCoreClock variable value. Otherwise, any configuration |
mbed_official | 125:23cc3068a9e4 | 225 | * based on this variable will be incorrect. |
mbed_official | 125:23cc3068a9e4 | 226 | * |
mbed_official | 125:23cc3068a9e4 | 227 | * @note - The system frequency computed by this function is not the real |
mbed_official | 125:23cc3068a9e4 | 228 | * frequency in the chip. It is calculated based on the predefined |
mbed_official | 125:23cc3068a9e4 | 229 | * constant and the selected clock source: |
mbed_official | 125:23cc3068a9e4 | 230 | * |
mbed_official | 125:23cc3068a9e4 | 231 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
mbed_official | 125:23cc3068a9e4 | 232 | * |
mbed_official | 125:23cc3068a9e4 | 233 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
mbed_official | 125:23cc3068a9e4 | 234 | * |
mbed_official | 125:23cc3068a9e4 | 235 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
mbed_official | 125:23cc3068a9e4 | 236 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
mbed_official | 125:23cc3068a9e4 | 237 | * |
mbed_official | 125:23cc3068a9e4 | 238 | * (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value |
mbed_official | 125:23cc3068a9e4 | 239 | * 8 MHz) but the real value may vary depending on the variations |
mbed_official | 125:23cc3068a9e4 | 240 | * in voltage and temperature. |
mbed_official | 125:23cc3068a9e4 | 241 | * |
mbed_official | 125:23cc3068a9e4 | 242 | * (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value |
mbed_official | 125:23cc3068a9e4 | 243 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real |
mbed_official | 125:23cc3068a9e4 | 244 | * frequency of the crystal used. Otherwise, this function may |
mbed_official | 125:23cc3068a9e4 | 245 | * have wrong result. |
mbed_official | 125:23cc3068a9e4 | 246 | * |
mbed_official | 125:23cc3068a9e4 | 247 | * - The result of this function could be not correct when using fractional |
mbed_official | 125:23cc3068a9e4 | 248 | * value for HSE crystal. |
mbed_official | 125:23cc3068a9e4 | 249 | * |
mbed_official | 125:23cc3068a9e4 | 250 | * @param None |
mbed_official | 125:23cc3068a9e4 | 251 | * @retval None |
mbed_official | 125:23cc3068a9e4 | 252 | */ |
mbed_official | 125:23cc3068a9e4 | 253 | void SystemCoreClockUpdate (void) |
mbed_official | 125:23cc3068a9e4 | 254 | { |
mbed_official | 125:23cc3068a9e4 | 255 | uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0; |
mbed_official | 125:23cc3068a9e4 | 256 | |
mbed_official | 125:23cc3068a9e4 | 257 | /* Get SYSCLK source -------------------------------------------------------*/ |
mbed_official | 125:23cc3068a9e4 | 258 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
mbed_official | 125:23cc3068a9e4 | 259 | |
mbed_official | 125:23cc3068a9e4 | 260 | switch (tmp) |
mbed_official | 125:23cc3068a9e4 | 261 | { |
mbed_official | 125:23cc3068a9e4 | 262 | case 0x00: /* HSI used as system clock */ |
mbed_official | 125:23cc3068a9e4 | 263 | SystemCoreClock = HSI_VALUE; |
mbed_official | 125:23cc3068a9e4 | 264 | break; |
mbed_official | 125:23cc3068a9e4 | 265 | case 0x04: /* HSE used as system clock */ |
mbed_official | 125:23cc3068a9e4 | 266 | SystemCoreClock = HSE_VALUE; |
mbed_official | 125:23cc3068a9e4 | 267 | break; |
mbed_official | 125:23cc3068a9e4 | 268 | case 0x08: /* PLL used as system clock */ |
mbed_official | 125:23cc3068a9e4 | 269 | /* Get PLL clock source and multiplication factor ----------------------*/ |
mbed_official | 125:23cc3068a9e4 | 270 | pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; |
mbed_official | 125:23cc3068a9e4 | 271 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
mbed_official | 125:23cc3068a9e4 | 272 | pllmull = ( pllmull >> 18) + 2; |
mbed_official | 125:23cc3068a9e4 | 273 | |
mbed_official | 125:23cc3068a9e4 | 274 | if (pllsource == 0x00) |
mbed_official | 125:23cc3068a9e4 | 275 | { |
mbed_official | 125:23cc3068a9e4 | 276 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */ |
mbed_official | 125:23cc3068a9e4 | 277 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; |
mbed_official | 125:23cc3068a9e4 | 278 | } |
mbed_official | 125:23cc3068a9e4 | 279 | else |
mbed_official | 125:23cc3068a9e4 | 280 | { |
mbed_official | 125:23cc3068a9e4 | 281 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; |
mbed_official | 125:23cc3068a9e4 | 282 | /* HSE oscillator clock selected as PREDIV1 clock entry */ |
mbed_official | 125:23cc3068a9e4 | 283 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; |
mbed_official | 125:23cc3068a9e4 | 284 | } |
mbed_official | 125:23cc3068a9e4 | 285 | break; |
mbed_official | 125:23cc3068a9e4 | 286 | default: /* HSI used as system clock */ |
mbed_official | 125:23cc3068a9e4 | 287 | SystemCoreClock = HSI_VALUE; |
mbed_official | 125:23cc3068a9e4 | 288 | break; |
mbed_official | 125:23cc3068a9e4 | 289 | } |
mbed_official | 125:23cc3068a9e4 | 290 | /* Compute HCLK clock frequency ----------------*/ |
mbed_official | 125:23cc3068a9e4 | 291 | /* Get HCLK prescaler */ |
mbed_official | 125:23cc3068a9e4 | 292 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
mbed_official | 125:23cc3068a9e4 | 293 | /* HCLK clock frequency */ |
mbed_official | 125:23cc3068a9e4 | 294 | SystemCoreClock >>= tmp; |
mbed_official | 125:23cc3068a9e4 | 295 | } |
mbed_official | 125:23cc3068a9e4 | 296 | |
mbed_official | 125:23cc3068a9e4 | 297 | /** |
mbed_official | 125:23cc3068a9e4 | 298 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
mbed_official | 125:23cc3068a9e4 | 299 | * AHB/APBx prescalers and Flash settings |
mbed_official | 125:23cc3068a9e4 | 300 | * @note This function should be called only once the RCC clock configuration |
mbed_official | 125:23cc3068a9e4 | 301 | * is reset to the default reset state (done in SystemInit() function). |
mbed_official | 125:23cc3068a9e4 | 302 | * @param None |
mbed_official | 125:23cc3068a9e4 | 303 | * @retval None |
mbed_official | 125:23cc3068a9e4 | 304 | */ |
mbed_official | 125:23cc3068a9e4 | 305 | void SetSysClock(void) |
mbed_official | 125:23cc3068a9e4 | 306 | { |
mbed_official | 135:067cc8ba23da | 307 | /* 1- Try to start with HSE and external clock */ |
mbed_official | 135:067cc8ba23da | 308 | #if USE_PLL_HSE_EXTC != 0 |
mbed_official | 135:067cc8ba23da | 309 | if (SetSysClock_PLL_HSE(1) == 0) |
mbed_official | 135:067cc8ba23da | 310 | #endif |
mbed_official | 135:067cc8ba23da | 311 | { |
mbed_official | 135:067cc8ba23da | 312 | /* 2- If fail try to start with HSE and external xtal */ |
mbed_official | 135:067cc8ba23da | 313 | #if USE_PLL_HSE_XTAL != 0 |
mbed_official | 135:067cc8ba23da | 314 | if (SetSysClock_PLL_HSE(0) == 0) |
mbed_official | 135:067cc8ba23da | 315 | #endif |
mbed_official | 135:067cc8ba23da | 316 | { |
mbed_official | 135:067cc8ba23da | 317 | /* 3- If fail start with HSI clock */ |
mbed_official | 135:067cc8ba23da | 318 | if (SetSysClock_PLL_HSI() == 0) |
mbed_official | 135:067cc8ba23da | 319 | { |
mbed_official | 135:067cc8ba23da | 320 | while(1) |
mbed_official | 135:067cc8ba23da | 321 | { |
mbed_official | 135:067cc8ba23da | 322 | // [TODO] Put something here to tell the user that a problem occured... |
mbed_official | 135:067cc8ba23da | 323 | } |
mbed_official | 135:067cc8ba23da | 324 | } |
mbed_official | 135:067cc8ba23da | 325 | } |
mbed_official | 135:067cc8ba23da | 326 | } |
mbed_official | 135:067cc8ba23da | 327 | |
mbed_official | 135:067cc8ba23da | 328 | /* Output SYSCLK on MCO pin(PA8) for debugging purpose */ |
mbed_official | 135:067cc8ba23da | 329 | /* |
mbed_official | 135:067cc8ba23da | 330 | // Enable GPIOA clock |
mbed_official | 135:067cc8ba23da | 331 | RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); |
mbed_official | 135:067cc8ba23da | 332 | // Configure MCO pin (PA8) |
mbed_official | 135:067cc8ba23da | 333 | GPIO_InitTypeDef GPIO_InitStructure; |
mbed_official | 135:067cc8ba23da | 334 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; |
mbed_official | 135:067cc8ba23da | 335 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
mbed_official | 135:067cc8ba23da | 336 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; |
mbed_official | 135:067cc8ba23da | 337 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; |
mbed_official | 135:067cc8ba23da | 338 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; |
mbed_official | 135:067cc8ba23da | 339 | GPIO_Init(GPIOA, &GPIO_InitStructure); |
mbed_official | 135:067cc8ba23da | 340 | // Select the clock to output |
mbed_official | 135:067cc8ba23da | 341 | RCC_MCOConfig(RCC_MCOSource_SYSCLK, RCC_MCOPrescaler_1); |
mbed_official | 135:067cc8ba23da | 342 | */ |
mbed_official | 135:067cc8ba23da | 343 | } |
mbed_official | 135:067cc8ba23da | 344 | |
mbed_official | 135:067cc8ba23da | 345 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
mbed_official | 135:067cc8ba23da | 346 | /******************************************************************************/ |
mbed_official | 135:067cc8ba23da | 347 | /* PLL (clocked by HSE) used as System clock source */ |
mbed_official | 135:067cc8ba23da | 348 | /******************************************************************************/ |
mbed_official | 135:067cc8ba23da | 349 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
mbed_official | 135:067cc8ba23da | 350 | { |
mbed_official | 135:067cc8ba23da | 351 | __IO uint32_t StartUpCounter = 0; |
mbed_official | 135:067cc8ba23da | 352 | __IO uint32_t HSEStatus = 0; |
mbed_official | 135:067cc8ba23da | 353 | |
mbed_official | 135:067cc8ba23da | 354 | /* Bypass HSE: can be done only if HSE is OFF */ |
mbed_official | 138:ec7ee4660c49 | 355 | RCC->CR &= ((uint32_t)~RCC_CR_HSEON); /* To be sure HSE is OFF */ |
mbed_official | 135:067cc8ba23da | 356 | if (bypass != 0) |
mbed_official | 135:067cc8ba23da | 357 | { |
mbed_official | 135:067cc8ba23da | 358 | RCC->CR |= ((uint32_t)RCC_CR_HSEBYP); |
mbed_official | 135:067cc8ba23da | 359 | } |
mbed_official | 138:ec7ee4660c49 | 360 | else |
mbed_official | 138:ec7ee4660c49 | 361 | { |
mbed_official | 138:ec7ee4660c49 | 362 | RCC->CR &= ((uint32_t)~RCC_CR_HSEBYP); |
mbed_official | 138:ec7ee4660c49 | 363 | } |
mbed_official | 135:067cc8ba23da | 364 | |
mbed_official | 135:067cc8ba23da | 365 | /* Enable HSE */ |
mbed_official | 135:067cc8ba23da | 366 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); |
mbed_official | 135:067cc8ba23da | 367 | |
mbed_official | 135:067cc8ba23da | 368 | /* Wait till HSE is ready */ |
mbed_official | 135:067cc8ba23da | 369 | do |
mbed_official | 135:067cc8ba23da | 370 | { |
mbed_official | 135:067cc8ba23da | 371 | HSEStatus = RCC->CR & RCC_CR_HSERDY; |
mbed_official | 135:067cc8ba23da | 372 | StartUpCounter++; |
mbed_official | 135:067cc8ba23da | 373 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); |
mbed_official | 135:067cc8ba23da | 374 | |
mbed_official | 135:067cc8ba23da | 375 | /* Check if HSE has started correctly */ |
mbed_official | 135:067cc8ba23da | 376 | if ((RCC->CR & RCC_CR_HSERDY) != RESET) |
mbed_official | 135:067cc8ba23da | 377 | { |
mbed_official | 135:067cc8ba23da | 378 | /* Enable prefetch buffer and set flash latency |
mbed_official | 135:067cc8ba23da | 379 | 0WS for 0 < SYSCLK <= 24 MHz |
mbed_official | 135:067cc8ba23da | 380 | 1WS for 24 < SYSCLK <= 48 MHz |
mbed_official | 135:067cc8ba23da | 381 | 2WS for 48 < SYSCLK <= 72 MHz */ |
mbed_official | 135:067cc8ba23da | 382 | FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; /* 2 WS */ |
mbed_official | 135:067cc8ba23da | 383 | |
mbed_official | 135:067cc8ba23da | 384 | /* Warning: values are obtained with external xtal or clock = 8 MHz */ |
mbed_official | 135:067cc8ba23da | 385 | /* SYSCLK = 72 MHz (8 MHz * 9) */ |
mbed_official | 135:067cc8ba23da | 386 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); |
mbed_official | 135:067cc8ba23da | 387 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9 |
mbed_official | 135:067cc8ba23da | 388 | | RCC_CFGR_HPRE_DIV1 /* HCLK = 72 MHz */ |
mbed_official | 135:067cc8ba23da | 389 | | RCC_CFGR_PPRE2_DIV1 /* PCLK2 = 72 MHz */ |
mbed_official | 135:067cc8ba23da | 390 | | RCC_CFGR_PPRE1_DIV2); /* PCLK1 = 36 MHz */ |
mbed_official | 135:067cc8ba23da | 391 | /* USBCLK = 48 MHz (72 MHz / 1.5) --> USB OK */ |
mbed_official | 135:067cc8ba23da | 392 | |
mbed_official | 135:067cc8ba23da | 393 | /* Enable PLL */ |
mbed_official | 135:067cc8ba23da | 394 | RCC->CR |= RCC_CR_PLLON; |
mbed_official | 135:067cc8ba23da | 395 | |
mbed_official | 135:067cc8ba23da | 396 | /* Wait till PLL is ready */ |
mbed_official | 135:067cc8ba23da | 397 | while((RCC->CR & RCC_CR_PLLRDY) == 0) |
mbed_official | 135:067cc8ba23da | 398 | { |
mbed_official | 135:067cc8ba23da | 399 | } |
mbed_official | 135:067cc8ba23da | 400 | |
mbed_official | 135:067cc8ba23da | 401 | /* Select PLL as system clock source */ |
mbed_official | 135:067cc8ba23da | 402 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
mbed_official | 135:067cc8ba23da | 403 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; |
mbed_official | 135:067cc8ba23da | 404 | |
mbed_official | 135:067cc8ba23da | 405 | /* Wait till PLL is used as system clock source */ |
mbed_official | 135:067cc8ba23da | 406 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) |
mbed_official | 135:067cc8ba23da | 407 | { |
mbed_official | 135:067cc8ba23da | 408 | } |
mbed_official | 137:f9a97811e98c | 409 | |
mbed_official | 135:067cc8ba23da | 410 | return 1; // OK |
mbed_official | 135:067cc8ba23da | 411 | } |
mbed_official | 135:067cc8ba23da | 412 | else |
mbed_official | 135:067cc8ba23da | 413 | { |
mbed_official | 135:067cc8ba23da | 414 | return 0; // FAIL |
mbed_official | 135:067cc8ba23da | 415 | } |
mbed_official | 135:067cc8ba23da | 416 | } |
mbed_official | 135:067cc8ba23da | 417 | #endif |
mbed_official | 135:067cc8ba23da | 418 | |
mbed_official | 125:23cc3068a9e4 | 419 | /******************************************************************************/ |
mbed_official | 125:23cc3068a9e4 | 420 | /* PLL (clocked by HSI) used as System clock source */ |
mbed_official | 125:23cc3068a9e4 | 421 | /******************************************************************************/ |
mbed_official | 135:067cc8ba23da | 422 | uint8_t SetSysClock_PLL_HSI(void) |
mbed_official | 135:067cc8ba23da | 423 | { |
mbed_official | 125:23cc3068a9e4 | 424 | /* At this stage the HSI is already enabled and used as System clock source */ |
mbed_official | 125:23cc3068a9e4 | 425 | |
mbed_official | 135:067cc8ba23da | 426 | /* Enable prefetch buffer and set flash latency |
mbed_official | 135:067cc8ba23da | 427 | 0WS for 0 < SYSCLK <= 24 MHz |
mbed_official | 135:067cc8ba23da | 428 | 1WS for 24 < SYSCLK <= 48 MHz |
mbed_official | 135:067cc8ba23da | 429 | 2WS for 48 < SYSCLK <= 72 MHz */ |
mbed_official | 135:067cc8ba23da | 430 | FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; /* 2 WS */ |
mbed_official | 135:067cc8ba23da | 431 | |
mbed_official | 135:067cc8ba23da | 432 | /* SYSCLK = 64 MHz (8 MHz / 2 * 16) */ |
mbed_official | 125:23cc3068a9e4 | 433 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); |
mbed_official | 135:067cc8ba23da | 434 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL16 |
mbed_official | 135:067cc8ba23da | 435 | | RCC_CFGR_HPRE_DIV1 /* HCLK = 64 MHz */ |
mbed_official | 135:067cc8ba23da | 436 | | RCC_CFGR_PPRE2_DIV1 /* PCLK2 = 64 MHz */ |
mbed_official | 135:067cc8ba23da | 437 | | RCC_CFGR_PPRE1_DIV2); /* PCLK1 = 32 MHz */ |
mbed_official | 135:067cc8ba23da | 438 | /* USBCLK = 42.667 MHz (64 MHz / 1.5) --> USB NOT POSSIBLE */ |
mbed_official | 125:23cc3068a9e4 | 439 | |
mbed_official | 125:23cc3068a9e4 | 440 | /* Enable PLL */ |
mbed_official | 125:23cc3068a9e4 | 441 | RCC->CR |= RCC_CR_PLLON; |
mbed_official | 125:23cc3068a9e4 | 442 | |
mbed_official | 125:23cc3068a9e4 | 443 | /* Wait till PLL is ready */ |
mbed_official | 125:23cc3068a9e4 | 444 | while((RCC->CR & RCC_CR_PLLRDY) == 0) |
mbed_official | 125:23cc3068a9e4 | 445 | { |
mbed_official | 125:23cc3068a9e4 | 446 | } |
mbed_official | 125:23cc3068a9e4 | 447 | |
mbed_official | 125:23cc3068a9e4 | 448 | /* Select PLL as system clock source */ |
mbed_official | 125:23cc3068a9e4 | 449 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
mbed_official | 125:23cc3068a9e4 | 450 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; |
mbed_official | 125:23cc3068a9e4 | 451 | |
mbed_official | 125:23cc3068a9e4 | 452 | /* Wait till PLL is used as system clock source */ |
mbed_official | 125:23cc3068a9e4 | 453 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) |
mbed_official | 125:23cc3068a9e4 | 454 | { |
mbed_official | 125:23cc3068a9e4 | 455 | } |
mbed_official | 135:067cc8ba23da | 456 | |
mbed_official | 135:067cc8ba23da | 457 | return 1; // OK |
mbed_official | 125:23cc3068a9e4 | 458 | } |
mbed_official | 125:23cc3068a9e4 | 459 | |
mbed_official | 125:23cc3068a9e4 | 460 | /** |
mbed_official | 125:23cc3068a9e4 | 461 | * @} |
mbed_official | 125:23cc3068a9e4 | 462 | */ |
mbed_official | 125:23cc3068a9e4 | 463 | |
mbed_official | 125:23cc3068a9e4 | 464 | /** |
mbed_official | 125:23cc3068a9e4 | 465 | * @} |
mbed_official | 125:23cc3068a9e4 | 466 | */ |
mbed_official | 125:23cc3068a9e4 | 467 | |
mbed_official | 125:23cc3068a9e4 | 468 | /** |
mbed_official | 125:23cc3068a9e4 | 469 | * @} |
mbed_official | 125:23cc3068a9e4 | 470 | */ |
mbed_official | 125:23cc3068a9e4 | 471 | |
mbed_official | 125:23cc3068a9e4 | 472 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |