mbed-src-kl05 - mbed library sources

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mbed library sources

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targets/cmsis/TARGET_STM/TARGET_STM32F407VG/stm32f4xx_hal_cryp_ex.c@296:ec1b66a3d094, 2014-08-21 (annotated)

Committer:: mbed_official
Date:: Thu Aug 21 15:00:08 2014 +0100
Revision:: 296:ec1b66a3d094
Parent:: targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_cryp_ex.c@242:7074e42da0b2

Synchronized with git revision bbc120c4786e99dfa586e7a13f8638064f1e5938

Full URL: https://github.com/mbedmicro/mbed/commit/bbc120c4786e99dfa586e7a13f8638064f1e5938/

DISCO_F407VG - add USBDevice support and a variant - ARCH_MAX

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	133:d4dda5c437f0	1	/**
mbed_official	133:d4dda5c437f0	2	******************************************************************************
mbed_official	133:d4dda5c437f0	3	* @file stm32f4xx_hal_cryp_ex.c
mbed_official	133:d4dda5c437f0	4	* @author MCD Application Team
mbed_official	242:7074e42da0b2	5	* @version V1.1.0RC2
mbed_official	242:7074e42da0b2	6	* @date 14-May-2014
mbed_official	133:d4dda5c437f0	7	* @brief Extended CRYP HAL module driver
mbed_official	133:d4dda5c437f0	8	* This file provides firmware functions to manage the following
mbed_official	133:d4dda5c437f0	9	* functionalities of CRYP extension peripheral:
mbed_official	133:d4dda5c437f0	10	* + Extended AES processing functions
mbed_official	133:d4dda5c437f0	11	*
mbed_official	133:d4dda5c437f0	12	@verbatim
mbed_official	133:d4dda5c437f0	13	==============================================================================
mbed_official	133:d4dda5c437f0	14	##### How to use this driver #####
mbed_official	133:d4dda5c437f0	15	==============================================================================
mbed_official	133:d4dda5c437f0	16	[..]
mbed_official	133:d4dda5c437f0	17	The CRYP Extension HAL driver can be used as follows:
mbed_official	133:d4dda5c437f0	18	(#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
mbed_official	133:d4dda5c437f0	19	(##) Enable the CRYP interface clock using __CRYP_CLK_ENABLE()
mbed_official	133:d4dda5c437f0	20	(##) In case of using interrupts (e.g. HAL_CRYPEx_AESGCM_Encrypt_IT())
mbed_official	133:d4dda5c437f0	21	(+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
mbed_official	133:d4dda5c437f0	22	(+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
mbed_official	133:d4dda5c437f0	23	(+) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
mbed_official	133:d4dda5c437f0	24	(##) In case of using DMA to control data transfer (e.g. HAL_AES_ECB_Encrypt_DMA())
mbed_official	133:d4dda5c437f0	25	(+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
mbed_official	133:d4dda5c437f0	26	(+++) Configure and enable two DMA streams one for managing data transfer from
mbed_official	133:d4dda5c437f0	27	memory to peripheral (input stream) and another stream for managing data
mbed_official	133:d4dda5c437f0	28	transfer from peripheral to memory (output stream)
mbed_official	133:d4dda5c437f0	29	(+++) Associate the initilalized DMA handle to the CRYP DMA handle
mbed_official	133:d4dda5c437f0	30	using __HAL_LINKDMA()
mbed_official	133:d4dda5c437f0	31	(+++) Configure the priority and enable the NVIC for the transfer complete
mbed_official	133:d4dda5c437f0	32	interrupt on the two DMA Streams. The output stream should have higher
mbed_official	133:d4dda5c437f0	33	priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
mbed_official	133:d4dda5c437f0	34	(#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
mbed_official	133:d4dda5c437f0	35	(##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
mbed_official	133:d4dda5c437f0	36	(##) The key size: 128, 192 and 256. This parameter is relevant only for AES
mbed_official	133:d4dda5c437f0	37	(##) The encryption/decryption key. Its size depends on the algorithm
mbed_official	133:d4dda5c437f0	38	used for encryption/decryption
mbed_official	133:d4dda5c437f0	39	(##) The initialization vector (counter). It is not used ECB mode.
mbed_official	133:d4dda5c437f0	40	(#)Three processing (encryption/decryption) functions are available:
mbed_official	133:d4dda5c437f0	41	(##) Polling mode: encryption and decryption APIs are blocking functions
mbed_official	133:d4dda5c437f0	42	i.e. they process the data and wait till the processing is finished
mbed_official	133:d4dda5c437f0	43	e.g. HAL_CRYPEx_AESGCM_Encrypt()
mbed_official	133:d4dda5c437f0	44	(##) Interrupt mode: encryption and decryption APIs are not blocking functions
mbed_official	133:d4dda5c437f0	45	i.e. they process the data under interrupt
mbed_official	133:d4dda5c437f0	46	e.g. HAL_CRYPEx_AESGCM_Encrypt_IT()
mbed_official	133:d4dda5c437f0	47	(##) DMA mode: encryption and decryption APIs are not blocking functions
mbed_official	133:d4dda5c437f0	48	i.e. the data transfer is ensured by DMA
mbed_official	133:d4dda5c437f0	49	e.g. HAL_CRYPEx_AESGCM_Encrypt_DMA()
mbed_official	133:d4dda5c437f0	50	(#)When the processing function is called at first time after HAL_CRYP_Init()
mbed_official	133:d4dda5c437f0	51	the CRYP peripheral is initialized and processes the buffer in input.
mbed_official	133:d4dda5c437f0	52	At second call, the processing function performs an append of the already
mbed_official	133:d4dda5c437f0	53	processed buffer.
mbed_official	133:d4dda5c437f0	54	When a new data block is to be processed, call HAL_CRYP_Init() then the
mbed_official	133:d4dda5c437f0	55	processing function.
mbed_official	133:d4dda5c437f0	56	(#)In AES-GCM and AES-CCM modes are an authenticated encryption algorithms
mbed_official	133:d4dda5c437f0	57	which provide authentication messages.
mbed_official	133:d4dda5c437f0	58	HAL_AES_GCM_Finish() and HAL_AES_CCM_Finish() are used to provide those
mbed_official	133:d4dda5c437f0	59	authentication messages.
mbed_official	133:d4dda5c437f0	60	Call those functions after the processing ones (polling, interrupt or DMA).
mbed_official	133:d4dda5c437f0	61	e.g. in AES-CCM mode call HAL_CRYPEx_AESCCM_Encrypt() to encrypt the plain data
mbed_official	133:d4dda5c437f0	62	then call HAL_CRYPEx_AESCCM_Finish() to get the authentication message
mbed_official	133:d4dda5c437f0	63	(#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
mbed_official	133:d4dda5c437f0	64
mbed_official	133:d4dda5c437f0	65	@endverbatim
mbed_official	133:d4dda5c437f0	66	******************************************************************************
mbed_official	133:d4dda5c437f0	67	* @attention
mbed_official	133:d4dda5c437f0	68	*
mbed_official	133:d4dda5c437f0	69	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	133:d4dda5c437f0	70	*
mbed_official	133:d4dda5c437f0	71	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	133:d4dda5c437f0	72	* are permitted provided that the following conditions are met:
mbed_official	133:d4dda5c437f0	73	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	133:d4dda5c437f0	74	* this list of conditions and the following disclaimer.
mbed_official	133:d4dda5c437f0	75	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	133:d4dda5c437f0	76	* this list of conditions and the following disclaimer in the documentation
mbed_official	133:d4dda5c437f0	77	* and/or other materials provided with the distribution.
mbed_official	133:d4dda5c437f0	78	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	133:d4dda5c437f0	79	* may be used to endorse or promote products derived from this software
mbed_official	133:d4dda5c437f0	80	* without specific prior written permission.
mbed_official	133:d4dda5c437f0	81	*
mbed_official	133:d4dda5c437f0	82	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	133:d4dda5c437f0	83	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	133:d4dda5c437f0	84	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	133:d4dda5c437f0	85	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	133:d4dda5c437f0	86	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	133:d4dda5c437f0	87	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	133:d4dda5c437f0	88	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	133:d4dda5c437f0	89	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	133:d4dda5c437f0	90	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	133:d4dda5c437f0	91	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	133:d4dda5c437f0	92	*
mbed_official	133:d4dda5c437f0	93	******************************************************************************
mbed_official	133:d4dda5c437f0	94	*/
mbed_official	133:d4dda5c437f0	95
mbed_official	133:d4dda5c437f0	96	/* Includes ------------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	97	#include "stm32f4xx_hal.h"
mbed_official	133:d4dda5c437f0	98
mbed_official	133:d4dda5c437f0	99	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	133:d4dda5c437f0	100	* @{
mbed_official	133:d4dda5c437f0	101	*/
mbed_official	133:d4dda5c437f0	102
mbed_official	133:d4dda5c437f0	103	/** @defgroup CRYPEx
mbed_official	133:d4dda5c437f0	104	* @brief CRYP Extension HAL module driver.
mbed_official	133:d4dda5c437f0	105	* @{
mbed_official	133:d4dda5c437f0	106	*/
mbed_official	133:d4dda5c437f0	107
mbed_official	133:d4dda5c437f0	108	#ifdef HAL_CRYP_MODULE_ENABLED
mbed_official	133:d4dda5c437f0	109
mbed_official	133:d4dda5c437f0	110	#if defined(STM32F437xx) \|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	111
mbed_official	133:d4dda5c437f0	112	/* Private typedef -----------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	113	/* Private define ------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	114	/* Private macro -------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	115	/* Private variables ---------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	116	/* Private function prototypes -----------------------------------------------*/
mbed_official	133:d4dda5c437f0	117	static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef hcryp, uint8_t InitVector, uint32_t IVSize);
mbed_official	133:d4dda5c437f0	118	static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef hcryp, uint8_t Key, uint32_t KeySize);
mbed_official	133:d4dda5c437f0	119	static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef hcryp, uint8_t Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout);
mbed_official	133:d4dda5c437f0	120	static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef hcryp, uint8_t Input, uint16_t Ilength, uint32_t Timeout);
mbed_official	133:d4dda5c437f0	121	static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma);
mbed_official	133:d4dda5c437f0	122	static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma);
mbed_official	133:d4dda5c437f0	123	static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma);
mbed_official	133:d4dda5c437f0	124	static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
mbed_official	133:d4dda5c437f0	125
mbed_official	133:d4dda5c437f0	126	/* Private functions ---------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	127
mbed_official	133:d4dda5c437f0	128	/** @defgroup CRYPEx_Private_Functions
mbed_official	133:d4dda5c437f0	129	* @{
mbed_official	133:d4dda5c437f0	130	*/
mbed_official	133:d4dda5c437f0	131
mbed_official	133:d4dda5c437f0	132	/** @defgroup CRYPEx_Group1 Extended AES processing functions
mbed_official	133:d4dda5c437f0	133	* @brief Extended processing functions.
mbed_official	133:d4dda5c437f0	134	*
mbed_official	133:d4dda5c437f0	135	@verbatim
mbed_official	133:d4dda5c437f0	136	==============================================================================
mbed_official	133:d4dda5c437f0	137	##### Extended AES processing functions #####
mbed_official	133:d4dda5c437f0	138	==============================================================================
mbed_official	133:d4dda5c437f0	139	[..] This section provides functions allowing to:
mbed_official	133:d4dda5c437f0	140	(+) Encrypt plaintext using AES-128/192/256 using GCM and CCM chaining modes
mbed_official	133:d4dda5c437f0	141	(+) Decrypt cyphertext using AES-128/192/256 using GCM and CCM chaining modes
mbed_official	133:d4dda5c437f0	142	(+) Finish the processing. This function is available only for GCM and CCM
mbed_official	133:d4dda5c437f0	143	[..] Three processing methods are available:
mbed_official	133:d4dda5c437f0	144	(+) Polling mode
mbed_official	133:d4dda5c437f0	145	(+) Interrupt mode
mbed_official	133:d4dda5c437f0	146	(+) DMA mode
mbed_official	133:d4dda5c437f0	147
mbed_official	133:d4dda5c437f0	148	@endverbatim
mbed_official	133:d4dda5c437f0	149	* @{
mbed_official	133:d4dda5c437f0	150	*/
mbed_official	133:d4dda5c437f0	151
mbed_official	133:d4dda5c437f0	152
mbed_official	133:d4dda5c437f0	153	/**
mbed_official	133:d4dda5c437f0	154	* @brief Initializes the CRYP peripheral in AES CCM encryption mode then
mbed_official	133:d4dda5c437f0	155	* encrypt pPlainData. The cypher data are available in pCypherData.
mbed_official	242:7074e42da0b2	156	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
mbed_official	242:7074e42da0b2	157	* the configuration information for CRYP module
mbed_official	133:d4dda5c437f0	158	* @param pPlainData: Pointer to the plaintext buffer
mbed_official	133:d4dda5c437f0	159	* @param Size: Length of the plaintext buffer, must be a multiple of 16
mbed_official	133:d4dda5c437f0	160	* @param pCypherData: Pointer to the cyphertext buffer
mbed_official	133:d4dda5c437f0	161	* @param Timeout: Timeout duration
mbed_official	133:d4dda5c437f0	162	* @retval HAL status
mbed_official	133:d4dda5c437f0	163	*/
mbed_official	133:d4dda5c437f0	164	HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef hcryp, uint8_t pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
mbed_official	133:d4dda5c437f0	165	{
mbed_official	133:d4dda5c437f0	166	uint32_t timeout = 0;
mbed_official	133:d4dda5c437f0	167	uint32_t headersize = hcryp->Init.HeaderSize;
mbed_official	133:d4dda5c437f0	168	uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
mbed_official	133:d4dda5c437f0	169	uint32_t loopcounter = 0;
mbed_official	133:d4dda5c437f0	170	uint32_t bufferidx = 0;
mbed_official	133:d4dda5c437f0	171	uint8_t blockb0[16] = {0};/* Block B0 */
mbed_official	133:d4dda5c437f0	172	uint8_t ctr[16] = {0}; /* Counter */
mbed_official	133:d4dda5c437f0	173	uint32_t b0addr = (uint32_t)blockb0;
mbed_official	133:d4dda5c437f0	174
mbed_official	133:d4dda5c437f0	175	/* Process Locked */
mbed_official	133:d4dda5c437f0	176	__HAL_LOCK(hcryp);
mbed_official	133:d4dda5c437f0	177
mbed_official	133:d4dda5c437f0	178	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	179	hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official	133:d4dda5c437f0	180
mbed_official	133:d4dda5c437f0	181	/* Check if initialization phase has already been performed */
mbed_official	133:d4dda5c437f0	182	if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official	133:d4dda5c437f0	183	{
mbed_official	133:d4dda5c437f0	184	/********************** Formatting the header block *******************/
mbed_official	133:d4dda5c437f0	185	if(headersize != 0)
mbed_official	133:d4dda5c437f0	186	{
mbed_official	133:d4dda5c437f0	187	/* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
mbed_official	133:d4dda5c437f0	188	if(headersize < 65280)
mbed_official	133:d4dda5c437f0	189	{
mbed_official	133:d4dda5c437f0	190	hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
mbed_official	133:d4dda5c437f0	191	hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
mbed_official	133:d4dda5c437f0	192	headersize += 2;
mbed_official	133:d4dda5c437f0	193	}
mbed_official	133:d4dda5c437f0	194	else
mbed_official	133:d4dda5c437f0	195	{
mbed_official	133:d4dda5c437f0	196	/* Header is encoded as 0xff \|\| 0xfe \|\| [headersize]32, i.e., six octets */
mbed_official	133:d4dda5c437f0	197	hcryp->Init.pScratch[bufferidx++] = 0xFF;
mbed_official	133:d4dda5c437f0	198	hcryp->Init.pScratch[bufferidx++] = 0xFE;
mbed_official	133:d4dda5c437f0	199	hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
mbed_official	133:d4dda5c437f0	200	hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
mbed_official	133:d4dda5c437f0	201	hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
mbed_official	133:d4dda5c437f0	202	hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
mbed_official	133:d4dda5c437f0	203	headersize += 6;
mbed_official	133:d4dda5c437f0	204	}
mbed_official	133:d4dda5c437f0	205	/* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
mbed_official	133:d4dda5c437f0	206	for(loopcounter = 0; loopcounter < headersize; loopcounter++)
mbed_official	133:d4dda5c437f0	207	{
mbed_official	133:d4dda5c437f0	208	hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
mbed_official	133:d4dda5c437f0	209	}
mbed_official	133:d4dda5c437f0	210	/* Check if the header size is modulo 16 */
mbed_official	133:d4dda5c437f0	211	if ((headersize % 16) != 0)
mbed_official	133:d4dda5c437f0	212	{
mbed_official	133:d4dda5c437f0	213	/* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
mbed_official	133:d4dda5c437f0	214	for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
mbed_official	133:d4dda5c437f0	215	{
mbed_official	133:d4dda5c437f0	216	hcryp->Init.pScratch[loopcounter] = 0;
mbed_official	133:d4dda5c437f0	217	}
mbed_official	133:d4dda5c437f0	218	/* Set the header size to modulo 16 */
mbed_official	133:d4dda5c437f0	219	headersize = ((headersize/16) + 1) * 16;
mbed_official	133:d4dda5c437f0	220	}
mbed_official	133:d4dda5c437f0	221	/* Set the pointer headeraddr to hcryp->Init.pScratch */
mbed_official	133:d4dda5c437f0	222	headeraddr = (uint32_t)hcryp->Init.pScratch;
mbed_official	133:d4dda5c437f0	223	}
mbed_official	133:d4dda5c437f0	224	/********************* Formatting the block B0 ************************/
mbed_official	133:d4dda5c437f0	225	if(headersize != 0)
mbed_official	133:d4dda5c437f0	226	{
mbed_official	133:d4dda5c437f0	227	blockb0[0] = 0x40;
mbed_official	133:d4dda5c437f0	228	}
mbed_official	133:d4dda5c437f0	229	/* Flags byte */
mbed_official	133:d4dda5c437f0	230	/* blockb0[0] \|= 0u \| (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) \| ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
mbed_official	133:d4dda5c437f0	231	blockb0[0] \|= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
mbed_official	133:d4dda5c437f0	232	blockb0[0] \|= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
mbed_official	133:d4dda5c437f0	233
mbed_official	133:d4dda5c437f0	234	for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
mbed_official	133:d4dda5c437f0	235	{
mbed_official	133:d4dda5c437f0	236	blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
mbed_official	133:d4dda5c437f0	237	}
mbed_official	133:d4dda5c437f0	238	for ( ; loopcounter < 13; loopcounter++)
mbed_official	133:d4dda5c437f0	239	{
mbed_official	133:d4dda5c437f0	240	blockb0[loopcounter+1] = 0;
mbed_official	133:d4dda5c437f0	241	}
mbed_official	133:d4dda5c437f0	242
mbed_official	133:d4dda5c437f0	243	blockb0[14] = (Size >> 8);
mbed_official	133:d4dda5c437f0	244	blockb0[15] = (Size & 0xFF);
mbed_official	133:d4dda5c437f0	245
mbed_official	133:d4dda5c437f0	246	/*********************** Formatting the initial counter ***************/
mbed_official	133:d4dda5c437f0	247	/* Byte 0:
mbed_official	133:d4dda5c437f0	248	Bits 7 and 6 are reserved and shall be set to 0
mbed_official	133:d4dda5c437f0	249	Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter blocks
mbed_official	133:d4dda5c437f0	250	are distinct from B0
mbed_official	133:d4dda5c437f0	251	Bits 0, 1, and 2 contain the same encoding of q as in B0
mbed_official	133:d4dda5c437f0	252	*/
mbed_official	133:d4dda5c437f0	253	ctr[0] = blockb0[0] & 0x07;
mbed_official	133:d4dda5c437f0	254	/* byte 1 to NonceSize is the IV (Nonce) */
mbed_official	133:d4dda5c437f0	255	for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
mbed_official	133:d4dda5c437f0	256	{
mbed_official	133:d4dda5c437f0	257	ctr[loopcounter] = blockb0[loopcounter];
mbed_official	133:d4dda5c437f0	258	}
mbed_official	133:d4dda5c437f0	259	/* Set the LSB to 1 */
mbed_official	133:d4dda5c437f0	260	ctr[15] \|= 0x01;
mbed_official	133:d4dda5c437f0	261
mbed_official	133:d4dda5c437f0	262	/* Set the key */
mbed_official	133:d4dda5c437f0	263	CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official	133:d4dda5c437f0	264
mbed_official	133:d4dda5c437f0	265	/* Set the CRYP peripheral in AES CCM mode */
mbed_official	133:d4dda5c437f0	266	__HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
mbed_official	133:d4dda5c437f0	267
mbed_official	133:d4dda5c437f0	268	/* Set the Initialization Vector */
mbed_official	133:d4dda5c437f0	269	CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, CRYP_KEYSIZE_128B);
mbed_official	133:d4dda5c437f0	270
mbed_official	133:d4dda5c437f0	271	/* Select init phase */
mbed_official	133:d4dda5c437f0	272	__HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
mbed_official	133:d4dda5c437f0	273
mbed_official	133:d4dda5c437f0	274	b0addr = (uint32_t)blockb0;
mbed_official	133:d4dda5c437f0	275	/* Write the blockb0 block in the IN FIFO */
mbed_official	133:d4dda5c437f0	276	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	277	b0addr+=4;
mbed_official	133:d4dda5c437f0	278	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	279	b0addr+=4;
mbed_official	133:d4dda5c437f0	280	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	281	b0addr+=4;
mbed_official	133:d4dda5c437f0	282	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	283
mbed_official	133:d4dda5c437f0	284	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	285	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	286
mbed_official	133:d4dda5c437f0	287	/* Get timeout */
mbed_official	133:d4dda5c437f0	288	timeout = HAL_GetTick() + Timeout;
mbed_official	133:d4dda5c437f0	289
mbed_official	133:d4dda5c437f0	290	while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official	133:d4dda5c437f0	291	{
mbed_official	133:d4dda5c437f0	292	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	293	if(Timeout != HAL_MAX_DELAY)
mbed_official	133:d4dda5c437f0	294	{
mbed_official	133:d4dda5c437f0	295	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	296	{
mbed_official	133:d4dda5c437f0	297	/* Change state */
mbed_official	133:d4dda5c437f0	298	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	299
mbed_official	133:d4dda5c437f0	300	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	301	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	302
mbed_official	133:d4dda5c437f0	303	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	304	}
mbed_official	133:d4dda5c437f0	305	}
mbed_official	133:d4dda5c437f0	306	}
mbed_official	133:d4dda5c437f0	307	/*************************** Header phase *****************************/
mbed_official	133:d4dda5c437f0	308	if(headersize != 0)
mbed_official	133:d4dda5c437f0	309	{
mbed_official	133:d4dda5c437f0	310	/* Select header phase */
mbed_official	133:d4dda5c437f0	311	__HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
mbed_official	133:d4dda5c437f0	312
mbed_official	133:d4dda5c437f0	313	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	314	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	315
mbed_official	133:d4dda5c437f0	316	for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
mbed_official	133:d4dda5c437f0	317	{
mbed_official	133:d4dda5c437f0	318	/* Get timeout */
mbed_official	133:d4dda5c437f0	319	timeout = HAL_GetTick() + Timeout;
mbed_official	133:d4dda5c437f0	320	while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
mbed_official	133:d4dda5c437f0	321	{
mbed_official	133:d4dda5c437f0	322	{
mbed_official	133:d4dda5c437f0	323	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	324	if(Timeout != HAL_MAX_DELAY)
mbed_official	133:d4dda5c437f0	325	{
mbed_official	133:d4dda5c437f0	326	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	327	{
mbed_official	133:d4dda5c437f0	328	/* Change state */
mbed_official	133:d4dda5c437f0	329	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	330
mbed_official	133:d4dda5c437f0	331	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	332	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	333
mbed_official	133:d4dda5c437f0	334	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	335	}
mbed_official	133:d4dda5c437f0	336	}
mbed_official	133:d4dda5c437f0	337	}
mbed_official	133:d4dda5c437f0	338	}
mbed_official	133:d4dda5c437f0	339	/* Write the header block in the IN FIFO */
mbed_official	133:d4dda5c437f0	340	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	341	headeraddr+=4;
mbed_official	133:d4dda5c437f0	342	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	343	headeraddr+=4;
mbed_official	133:d4dda5c437f0	344	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	345	headeraddr+=4;
mbed_official	133:d4dda5c437f0	346	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	347	headeraddr+=4;
mbed_official	133:d4dda5c437f0	348	}
mbed_official	133:d4dda5c437f0	349
mbed_official	133:d4dda5c437f0	350	/* Get timeout */
mbed_official	133:d4dda5c437f0	351	timeout = HAL_GetTick() + Timeout;
mbed_official	133:d4dda5c437f0	352
mbed_official	133:d4dda5c437f0	353	while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
mbed_official	133:d4dda5c437f0	354	{
mbed_official	133:d4dda5c437f0	355	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	356	if(Timeout != HAL_MAX_DELAY)
mbed_official	133:d4dda5c437f0	357	{
mbed_official	133:d4dda5c437f0	358	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	359	{
mbed_official	133:d4dda5c437f0	360	/* Change state */
mbed_official	133:d4dda5c437f0	361	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	362
mbed_official	133:d4dda5c437f0	363	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	364	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	365
mbed_official	133:d4dda5c437f0	366	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	367	}
mbed_official	133:d4dda5c437f0	368	}
mbed_official	133:d4dda5c437f0	369	}
mbed_official	133:d4dda5c437f0	370	}
mbed_official	133:d4dda5c437f0	371	/* Save formatted counter into the scratch buffer pScratch */
mbed_official	133:d4dda5c437f0	372	for(loopcounter = 0; (loopcounter < 16); loopcounter++)
mbed_official	133:d4dda5c437f0	373	{
mbed_official	133:d4dda5c437f0	374	hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
mbed_official	133:d4dda5c437f0	375	}
mbed_official	133:d4dda5c437f0	376	/* Reset bit 0 */
mbed_official	133:d4dda5c437f0	377	hcryp->Init.pScratch[15] &= 0xfe;
mbed_official	133:d4dda5c437f0	378
mbed_official	133:d4dda5c437f0	379	/* Select payload phase once the header phase is performed */
mbed_official	133:d4dda5c437f0	380	__HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official	133:d4dda5c437f0	381
mbed_official	133:d4dda5c437f0	382	/* Flush FIFO */
mbed_official	133:d4dda5c437f0	383	__HAL_CRYP_FIFO_FLUSH();
mbed_official	133:d4dda5c437f0	384
mbed_official	133:d4dda5c437f0	385	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	386	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	387
mbed_official	133:d4dda5c437f0	388	/* Set the phase */
mbed_official	133:d4dda5c437f0	389	hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official	133:d4dda5c437f0	390	}
mbed_official	133:d4dda5c437f0	391
mbed_official	133:d4dda5c437f0	392	/* Write Plain Data and Get Cypher Data */
mbed_official	133:d4dda5c437f0	393	if(CRYPEx_GCMCCM_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
mbed_official	133:d4dda5c437f0	394	{
mbed_official	133:d4dda5c437f0	395	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	396	}
mbed_official	133:d4dda5c437f0	397
mbed_official	133:d4dda5c437f0	398	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	399	hcryp->State = HAL_CRYP_STATE_READY;
mbed_official	133:d4dda5c437f0	400
mbed_official	133:d4dda5c437f0	401	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	402	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	403
mbed_official	133:d4dda5c437f0	404	/* Return function status */
mbed_official	133:d4dda5c437f0	405	return HAL_OK;
mbed_official	133:d4dda5c437f0	406	}
mbed_official	133:d4dda5c437f0	407
mbed_official	133:d4dda5c437f0	408	/**
mbed_official	133:d4dda5c437f0	409	* @brief Initializes the CRYP peripheral in AES GCM encryption mode then
mbed_official	133:d4dda5c437f0	410	* encrypt pPlainData. The cypher data are available in pCypherData.
mbed_official	242:7074e42da0b2	411	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
mbed_official	242:7074e42da0b2	412	* the configuration information for CRYP module
mbed_official	133:d4dda5c437f0	413	* @param pPlainData: Pointer to the plaintext buffer
mbed_official	133:d4dda5c437f0	414	* @param Size: Length of the plaintext buffer, must be a multiple of 16
mbed_official	133:d4dda5c437f0	415	* @param pCypherData: Pointer to the cyphertext buffer
mbed_official	133:d4dda5c437f0	416	* @param Timeout: Timeout duration
mbed_official	133:d4dda5c437f0	417	* @retval HAL status
mbed_official	133:d4dda5c437f0	418	*/
mbed_official	133:d4dda5c437f0	419	HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef hcryp, uint8_t pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
mbed_official	133:d4dda5c437f0	420	{
mbed_official	133:d4dda5c437f0	421	uint32_t timeout = 0;
mbed_official	133:d4dda5c437f0	422
mbed_official	133:d4dda5c437f0	423	/* Process Locked */
mbed_official	133:d4dda5c437f0	424	__HAL_LOCK(hcryp);
mbed_official	133:d4dda5c437f0	425
mbed_official	133:d4dda5c437f0	426	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	427	hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official	133:d4dda5c437f0	428
mbed_official	133:d4dda5c437f0	429	/* Check if initialization phase has already been performed */
mbed_official	133:d4dda5c437f0	430	if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official	133:d4dda5c437f0	431	{
mbed_official	133:d4dda5c437f0	432	/* Set the key */
mbed_official	133:d4dda5c437f0	433	CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official	133:d4dda5c437f0	434
mbed_official	133:d4dda5c437f0	435	/* Set the CRYP peripheral in AES GCM mode */
mbed_official	133:d4dda5c437f0	436	__HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
mbed_official	133:d4dda5c437f0	437
mbed_official	133:d4dda5c437f0	438	/* Set the Initialization Vector */
mbed_official	133:d4dda5c437f0	439	CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
mbed_official	133:d4dda5c437f0	440
mbed_official	133:d4dda5c437f0	441	/* Flush FIFO */
mbed_official	133:d4dda5c437f0	442	__HAL_CRYP_FIFO_FLUSH();
mbed_official	133:d4dda5c437f0	443
mbed_official	133:d4dda5c437f0	444	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	445	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	446
mbed_official	133:d4dda5c437f0	447	/* Get timeout */
mbed_official	133:d4dda5c437f0	448	timeout = HAL_GetTick() + Timeout;
mbed_official	133:d4dda5c437f0	449
mbed_official	133:d4dda5c437f0	450	while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official	133:d4dda5c437f0	451	{
mbed_official	133:d4dda5c437f0	452	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	453	if(Timeout != HAL_MAX_DELAY)
mbed_official	133:d4dda5c437f0	454	{
mbed_official	133:d4dda5c437f0	455	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	456	{
mbed_official	133:d4dda5c437f0	457	/* Change state */
mbed_official	133:d4dda5c437f0	458	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	459
mbed_official	133:d4dda5c437f0	460	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	461	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	462
mbed_official	133:d4dda5c437f0	463	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	464	}
mbed_official	133:d4dda5c437f0	465	}
mbed_official	133:d4dda5c437f0	466	}
mbed_official	133:d4dda5c437f0	467
mbed_official	133:d4dda5c437f0	468	/* Set the header phase */
mbed_official	133:d4dda5c437f0	469	if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)
mbed_official	133:d4dda5c437f0	470	{
mbed_official	133:d4dda5c437f0	471	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	472	}
mbed_official	133:d4dda5c437f0	473
mbed_official	133:d4dda5c437f0	474	/* Disable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	475	__HAL_CRYP_DISABLE();
mbed_official	133:d4dda5c437f0	476
mbed_official	133:d4dda5c437f0	477	/* Select payload phase once the header phase is performed */
mbed_official	133:d4dda5c437f0	478	__HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official	133:d4dda5c437f0	479
mbed_official	133:d4dda5c437f0	480	/* Flush FIFO */
mbed_official	133:d4dda5c437f0	481	__HAL_CRYP_FIFO_FLUSH();
mbed_official	133:d4dda5c437f0	482
mbed_official	133:d4dda5c437f0	483	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	484	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	485
mbed_official	133:d4dda5c437f0	486	/* Set the phase */
mbed_official	133:d4dda5c437f0	487	hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official	133:d4dda5c437f0	488	}
mbed_official	133:d4dda5c437f0	489
mbed_official	133:d4dda5c437f0	490	/* Write Plain Data and Get Cypher Data */
mbed_official	133:d4dda5c437f0	491	if(CRYPEx_GCMCCM_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
mbed_official	133:d4dda5c437f0	492	{
mbed_official	133:d4dda5c437f0	493	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	494	}
mbed_official	133:d4dda5c437f0	495
mbed_official	133:d4dda5c437f0	496	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	497	hcryp->State = HAL_CRYP_STATE_READY;
mbed_official	133:d4dda5c437f0	498
mbed_official	133:d4dda5c437f0	499	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	500	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	501
mbed_official	133:d4dda5c437f0	502	/* Return function status */
mbed_official	133:d4dda5c437f0	503	return HAL_OK;
mbed_official	133:d4dda5c437f0	504	}
mbed_official	133:d4dda5c437f0	505
mbed_official	133:d4dda5c437f0	506	/**
mbed_official	133:d4dda5c437f0	507	* @brief Initializes the CRYP peripheral in AES GCM decryption mode then
mbed_official	133:d4dda5c437f0	508	* decrypted pCypherData. The cypher data are available in pPlainData.
mbed_official	242:7074e42da0b2	509	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
mbed_official	242:7074e42da0b2	510	* the configuration information for CRYP module
mbed_official	133:d4dda5c437f0	511	* @param pCypherData: Pointer to the cyphertext buffer
mbed_official	133:d4dda5c437f0	512	* @param Size: Length of the cyphertext buffer, must be a multiple of 16
mbed_official	133:d4dda5c437f0	513	* @param pPlainData: Pointer to the plaintext buffer
mbed_official	133:d4dda5c437f0	514	* @param Timeout: Timeout duration
mbed_official	133:d4dda5c437f0	515	* @retval HAL status
mbed_official	133:d4dda5c437f0	516	*/
mbed_official	133:d4dda5c437f0	517	HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef hcryp, uint8_t pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
mbed_official	133:d4dda5c437f0	518	{
mbed_official	133:d4dda5c437f0	519	uint32_t timeout = 0;
mbed_official	133:d4dda5c437f0	520
mbed_official	133:d4dda5c437f0	521	/* Process Locked */
mbed_official	133:d4dda5c437f0	522	__HAL_LOCK(hcryp);
mbed_official	133:d4dda5c437f0	523
mbed_official	133:d4dda5c437f0	524	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	525	hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official	133:d4dda5c437f0	526
mbed_official	133:d4dda5c437f0	527	/* Check if initialization phase has already been performed */
mbed_official	133:d4dda5c437f0	528	if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official	133:d4dda5c437f0	529	{
mbed_official	133:d4dda5c437f0	530	/* Set the key */
mbed_official	133:d4dda5c437f0	531	CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official	133:d4dda5c437f0	532
mbed_official	133:d4dda5c437f0	533	/* Set the CRYP peripheral in AES GCM decryption mode */
mbed_official	133:d4dda5c437f0	534	__HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
mbed_official	133:d4dda5c437f0	535
mbed_official	133:d4dda5c437f0	536	/* Set the Initialization Vector */
mbed_official	133:d4dda5c437f0	537	CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
mbed_official	133:d4dda5c437f0	538
mbed_official	133:d4dda5c437f0	539	/* Flush FIFO */
mbed_official	133:d4dda5c437f0	540	__HAL_CRYP_FIFO_FLUSH();
mbed_official	133:d4dda5c437f0	541
mbed_official	133:d4dda5c437f0	542	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	543	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	544
mbed_official	133:d4dda5c437f0	545	/* Get the timeout */
mbed_official	133:d4dda5c437f0	546	timeout = HAL_GetTick() + Timeout;
mbed_official	133:d4dda5c437f0	547
mbed_official	133:d4dda5c437f0	548	while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official	133:d4dda5c437f0	549	{
mbed_official	133:d4dda5c437f0	550	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	551	if(Timeout != HAL_MAX_DELAY)
mbed_official	133:d4dda5c437f0	552	{
mbed_official	133:d4dda5c437f0	553	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	554	{
mbed_official	133:d4dda5c437f0	555	/* Change state */
mbed_official	133:d4dda5c437f0	556	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	557
mbed_official	133:d4dda5c437f0	558	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	559	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	560
mbed_official	133:d4dda5c437f0	561	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	562	}
mbed_official	133:d4dda5c437f0	563	}
mbed_official	133:d4dda5c437f0	564	}
mbed_official	133:d4dda5c437f0	565
mbed_official	133:d4dda5c437f0	566	/* Set the header phase */
mbed_official	133:d4dda5c437f0	567	if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)
mbed_official	133:d4dda5c437f0	568	{
mbed_official	133:d4dda5c437f0	569	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	570	}
mbed_official	133:d4dda5c437f0	571	/* Disable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	572	__HAL_CRYP_DISABLE();
mbed_official	133:d4dda5c437f0	573
mbed_official	133:d4dda5c437f0	574	/* Select payload phase once the header phase is performed */
mbed_official	133:d4dda5c437f0	575	__HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official	133:d4dda5c437f0	576
mbed_official	133:d4dda5c437f0	577	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	578	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	579
mbed_official	133:d4dda5c437f0	580	/* Set the phase */
mbed_official	133:d4dda5c437f0	581	hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official	133:d4dda5c437f0	582	}
mbed_official	133:d4dda5c437f0	583
mbed_official	133:d4dda5c437f0	584	/* Write Plain Data and Get Cypher Data */
mbed_official	133:d4dda5c437f0	585	if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
mbed_official	133:d4dda5c437f0	586	{
mbed_official	133:d4dda5c437f0	587	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	588	}
mbed_official	133:d4dda5c437f0	589
mbed_official	133:d4dda5c437f0	590	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	591	hcryp->State = HAL_CRYP_STATE_READY;
mbed_official	133:d4dda5c437f0	592
mbed_official	133:d4dda5c437f0	593	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	594	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	595
mbed_official	133:d4dda5c437f0	596	/* Return function status */
mbed_official	133:d4dda5c437f0	597	return HAL_OK;
mbed_official	133:d4dda5c437f0	598	}
mbed_official	133:d4dda5c437f0	599
mbed_official	133:d4dda5c437f0	600	/**
mbed_official	133:d4dda5c437f0	601	* @brief Computes the authentication TAG.
mbed_official	242:7074e42da0b2	602	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
mbed_official	242:7074e42da0b2	603	* the configuration information for CRYP module
mbed_official	133:d4dda5c437f0	604	* @param Size: Total length of the plain/cyphertext buffer
mbed_official	133:d4dda5c437f0	605	* @param AuthTag: Pointer to the authentication buffer
mbed_official	133:d4dda5c437f0	606	* @param Timeout: Timeout duration
mbed_official	133:d4dda5c437f0	607	* @retval HAL status
mbed_official	133:d4dda5c437f0	608	*/
mbed_official	133:d4dda5c437f0	609	HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef hcryp, uint16_t Size, uint8_t AuthTag, uint32_t Timeout)
mbed_official	133:d4dda5c437f0	610	{
mbed_official	133:d4dda5c437f0	611	uint32_t timeout = 0;
mbed_official	133:d4dda5c437f0	612	uint32_t headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */
mbed_official	133:d4dda5c437f0	613	uint32_t inputlength = Size * 8; /* input length in bits */
mbed_official	133:d4dda5c437f0	614	uint32_t tagaddr = (uint32_t)AuthTag;
mbed_official	133:d4dda5c437f0	615
mbed_official	133:d4dda5c437f0	616	/* Process Locked */
mbed_official	133:d4dda5c437f0	617	__HAL_LOCK(hcryp);
mbed_official	133:d4dda5c437f0	618
mbed_official	133:d4dda5c437f0	619	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	620	hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official	133:d4dda5c437f0	621
mbed_official	133:d4dda5c437f0	622	/* Check if initialization phase has already been performed */
mbed_official	133:d4dda5c437f0	623	if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)
mbed_official	133:d4dda5c437f0	624	{
mbed_official	133:d4dda5c437f0	625	/* Change the CRYP phase */
mbed_official	133:d4dda5c437f0	626	hcryp->Phase = HAL_CRYP_PHASE_FINAL;
mbed_official	133:d4dda5c437f0	627
mbed_official	133:d4dda5c437f0	628	/* Disable CRYP to start the final phase */
mbed_official	133:d4dda5c437f0	629	__HAL_CRYP_DISABLE();
mbed_official	133:d4dda5c437f0	630
mbed_official	133:d4dda5c437f0	631	/* Select final phase */
mbed_official	133:d4dda5c437f0	632	__HAL_CRYP_SET_PHASE(CRYP_PHASE_FINAL);
mbed_official	133:d4dda5c437f0	633
mbed_official	133:d4dda5c437f0	634	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	635	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	636
mbed_official	133:d4dda5c437f0	637	/* Write the number of bits in header (64 bits) followed by the number of bits
mbed_official	133:d4dda5c437f0	638	in the payload */
mbed_official	133:d4dda5c437f0	639	if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
mbed_official	133:d4dda5c437f0	640	{
mbed_official	133:d4dda5c437f0	641	CRYP->DR = 0;
mbed_official	133:d4dda5c437f0	642	CRYP->DR = __RBIT(headerlength);
mbed_official	133:d4dda5c437f0	643	CRYP->DR = 0;
mbed_official	133:d4dda5c437f0	644	CRYP->DR = __RBIT(inputlength);
mbed_official	133:d4dda5c437f0	645	}
mbed_official	133:d4dda5c437f0	646	else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
mbed_official	133:d4dda5c437f0	647	{
mbed_official	133:d4dda5c437f0	648	CRYP->DR = 0;
mbed_official	133:d4dda5c437f0	649	CRYP->DR = __REV(headerlength);
mbed_official	133:d4dda5c437f0	650	CRYP->DR = 0;
mbed_official	133:d4dda5c437f0	651	CRYP->DR = __REV(inputlength);
mbed_official	133:d4dda5c437f0	652	}
mbed_official	133:d4dda5c437f0	653	else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
mbed_official	133:d4dda5c437f0	654	{
mbed_official	133:d4dda5c437f0	655	CRYP->DR = 0;
mbed_official	133:d4dda5c437f0	656	CRYP->DR = __REV16(headerlength);
mbed_official	133:d4dda5c437f0	657	CRYP->DR = 0;
mbed_official	133:d4dda5c437f0	658	CRYP->DR = __REV16(inputlength);
mbed_official	133:d4dda5c437f0	659	}
mbed_official	133:d4dda5c437f0	660	else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
mbed_official	133:d4dda5c437f0	661	{
mbed_official	133:d4dda5c437f0	662	CRYP->DR = 0;
mbed_official	133:d4dda5c437f0	663	CRYP->DR = (uint32_t)(headerlength);
mbed_official	133:d4dda5c437f0	664	CRYP->DR = 0;
mbed_official	133:d4dda5c437f0	665	CRYP->DR = (uint32_t)(inputlength);
mbed_official	133:d4dda5c437f0	666	}
mbed_official	133:d4dda5c437f0	667	/* Get timeout */
mbed_official	133:d4dda5c437f0	668	timeout = HAL_GetTick() + Timeout;
mbed_official	133:d4dda5c437f0	669
mbed_official	133:d4dda5c437f0	670	while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
mbed_official	133:d4dda5c437f0	671	{
mbed_official	133:d4dda5c437f0	672	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	673	if(Timeout != HAL_MAX_DELAY)
mbed_official	133:d4dda5c437f0	674	{
mbed_official	133:d4dda5c437f0	675	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	676	{
mbed_official	133:d4dda5c437f0	677	/* Change state */
mbed_official	133:d4dda5c437f0	678	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	679
mbed_official	133:d4dda5c437f0	680	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	681	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	682
mbed_official	133:d4dda5c437f0	683	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	684	}
mbed_official	133:d4dda5c437f0	685	}
mbed_official	133:d4dda5c437f0	686	}
mbed_official	133:d4dda5c437f0	687
mbed_official	133:d4dda5c437f0	688	/* Read the Auth TAG in the IN FIFO */
mbed_official	133:d4dda5c437f0	689	(uint32_t)(tagaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	690	tagaddr+=4;
mbed_official	133:d4dda5c437f0	691	(uint32_t)(tagaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	692	tagaddr+=4;
mbed_official	133:d4dda5c437f0	693	(uint32_t)(tagaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	694	tagaddr+=4;
mbed_official	133:d4dda5c437f0	695	(uint32_t)(tagaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	696	}
mbed_official	133:d4dda5c437f0	697
mbed_official	133:d4dda5c437f0	698	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	699	hcryp->State = HAL_CRYP_STATE_READY;
mbed_official	133:d4dda5c437f0	700
mbed_official	133:d4dda5c437f0	701	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	702	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	703
mbed_official	133:d4dda5c437f0	704	/* Return function status */
mbed_official	133:d4dda5c437f0	705	return HAL_OK;
mbed_official	133:d4dda5c437f0	706	}
mbed_official	133:d4dda5c437f0	707
mbed_official	133:d4dda5c437f0	708	/**
mbed_official	133:d4dda5c437f0	709	* @brief Computes the authentication TAG for AES CCM mode.
mbed_official	133:d4dda5c437f0	710	* @note This API is called after HAL_AES_CCM_Encrypt()/HAL_AES_CCM_Decrypt()
mbed_official	242:7074e42da0b2	711	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
mbed_official	242:7074e42da0b2	712	* the configuration information for CRYP module
mbed_official	133:d4dda5c437f0	713	* @param AuthTag: Pointer to the authentication buffer
mbed_official	133:d4dda5c437f0	714	* @param Timeout: Timeout duration
mbed_official	133:d4dda5c437f0	715	* @retval HAL status
mbed_official	133:d4dda5c437f0	716	*/
mbed_official	133:d4dda5c437f0	717	HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef hcryp, uint8_t AuthTag, uint32_t Timeout)
mbed_official	133:d4dda5c437f0	718	{
mbed_official	133:d4dda5c437f0	719	uint32_t timeout = 0;
mbed_official	133:d4dda5c437f0	720	uint32_t tagaddr = (uint32_t)AuthTag;
mbed_official	133:d4dda5c437f0	721	uint32_t ctraddr = (uint32_t)hcryp->Init.pScratch;
mbed_official	133:d4dda5c437f0	722	uint32_t temptag[4] = {0}; /* Temporary TAG (MAC) */
mbed_official	133:d4dda5c437f0	723	uint32_t loopcounter;
mbed_official	133:d4dda5c437f0	724
mbed_official	133:d4dda5c437f0	725	/* Process Locked */
mbed_official	133:d4dda5c437f0	726	__HAL_LOCK(hcryp);
mbed_official	133:d4dda5c437f0	727
mbed_official	133:d4dda5c437f0	728	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	729	hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official	133:d4dda5c437f0	730
mbed_official	133:d4dda5c437f0	731	/* Check if initialization phase has already been performed */
mbed_official	133:d4dda5c437f0	732	if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)
mbed_official	133:d4dda5c437f0	733	{
mbed_official	133:d4dda5c437f0	734	/* Change the CRYP phase */
mbed_official	133:d4dda5c437f0	735	hcryp->Phase = HAL_CRYP_PHASE_FINAL;
mbed_official	133:d4dda5c437f0	736
mbed_official	133:d4dda5c437f0	737	/* Disable CRYP to start the final phase */
mbed_official	133:d4dda5c437f0	738	__HAL_CRYP_DISABLE();
mbed_official	133:d4dda5c437f0	739
mbed_official	133:d4dda5c437f0	740	/* Select final phase */
mbed_official	133:d4dda5c437f0	741	__HAL_CRYP_SET_PHASE(CRYP_PHASE_FINAL);
mbed_official	133:d4dda5c437f0	742
mbed_official	133:d4dda5c437f0	743	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	744	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	745
mbed_official	133:d4dda5c437f0	746	/* Write the counter block in the IN FIFO */
mbed_official	133:d4dda5c437f0	747	CRYP->DR = (uint32_t)ctraddr;
mbed_official	133:d4dda5c437f0	748	ctraddr+=4;
mbed_official	133:d4dda5c437f0	749	CRYP->DR = (uint32_t)ctraddr;
mbed_official	133:d4dda5c437f0	750	ctraddr+=4;
mbed_official	133:d4dda5c437f0	751	CRYP->DR = (uint32_t)ctraddr;
mbed_official	133:d4dda5c437f0	752	ctraddr+=4;
mbed_official	133:d4dda5c437f0	753	CRYP->DR = (uint32_t)ctraddr;
mbed_official	133:d4dda5c437f0	754
mbed_official	133:d4dda5c437f0	755	/* Get timeout */
mbed_official	133:d4dda5c437f0	756	timeout = HAL_GetTick() + Timeout;
mbed_official	133:d4dda5c437f0	757
mbed_official	133:d4dda5c437f0	758	while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
mbed_official	133:d4dda5c437f0	759	{
mbed_official	133:d4dda5c437f0	760	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	761	if(Timeout != HAL_MAX_DELAY)
mbed_official	133:d4dda5c437f0	762	{
mbed_official	133:d4dda5c437f0	763	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	764	{
mbed_official	133:d4dda5c437f0	765	/* Change state */
mbed_official	133:d4dda5c437f0	766	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	767
mbed_official	133:d4dda5c437f0	768	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	769	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	770
mbed_official	133:d4dda5c437f0	771	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	772	}
mbed_official	133:d4dda5c437f0	773	}
mbed_official	133:d4dda5c437f0	774	}
mbed_official	133:d4dda5c437f0	775
mbed_official	133:d4dda5c437f0	776	/* Read the Auth TAG in the IN FIFO */
mbed_official	133:d4dda5c437f0	777	temptag[0] = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	778	temptag[1] = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	779	temptag[2] = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	780	temptag[3] = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	781	}
mbed_official	133:d4dda5c437f0	782
mbed_official	133:d4dda5c437f0	783	/* Copy temporary authentication TAG in user TAG buffer */
mbed_official	133:d4dda5c437f0	784	for(loopcounter = 0; loopcounter < hcryp->Init.TagSize ; loopcounter++)
mbed_official	133:d4dda5c437f0	785	{
mbed_official	133:d4dda5c437f0	786	/* Set the authentication TAG buffer */
mbed_official	133:d4dda5c437f0	787	((uint8_t)tagaddr+loopcounter) = ((uint8_t)temptag+loopcounter);
mbed_official	133:d4dda5c437f0	788	}
mbed_official	133:d4dda5c437f0	789
mbed_official	133:d4dda5c437f0	790	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	791	hcryp->State = HAL_CRYP_STATE_READY;
mbed_official	133:d4dda5c437f0	792
mbed_official	133:d4dda5c437f0	793	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	794	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	795
mbed_official	133:d4dda5c437f0	796	/* Return function status */
mbed_official	133:d4dda5c437f0	797	return HAL_OK;
mbed_official	133:d4dda5c437f0	798	}
mbed_official	133:d4dda5c437f0	799
mbed_official	133:d4dda5c437f0	800	/**
mbed_official	133:d4dda5c437f0	801	* @brief Initializes the CRYP peripheral in AES CCM decryption mode then
mbed_official	133:d4dda5c437f0	802	* decrypted pCypherData. The cypher data are available in pPlainData.
mbed_official	242:7074e42da0b2	803	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
mbed_official	242:7074e42da0b2	804	* the configuration information for CRYP module
mbed_official	133:d4dda5c437f0	805	* @param pPlainData: Pointer to the plaintext buffer
mbed_official	133:d4dda5c437f0	806	* @param Size: Length of the plaintext buffer, must be a multiple of 16
mbed_official	133:d4dda5c437f0	807	* @param pCypherData: Pointer to the cyphertext buffer
mbed_official	133:d4dda5c437f0	808	* @param Timeout: Timeout duration
mbed_official	133:d4dda5c437f0	809	* @retval HAL status
mbed_official	133:d4dda5c437f0	810	*/
mbed_official	133:d4dda5c437f0	811	HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef hcryp, uint8_t pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
mbed_official	133:d4dda5c437f0	812	{
mbed_official	133:d4dda5c437f0	813	uint32_t timeout = 0;
mbed_official	133:d4dda5c437f0	814	uint32_t headersize = hcryp->Init.HeaderSize;
mbed_official	133:d4dda5c437f0	815	uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
mbed_official	133:d4dda5c437f0	816	uint32_t loopcounter = 0;
mbed_official	133:d4dda5c437f0	817	uint32_t bufferidx = 0;
mbed_official	133:d4dda5c437f0	818	uint8_t blockb0[16] = {0};/* Block B0 */
mbed_official	133:d4dda5c437f0	819	uint8_t ctr[16] = {0}; /* Counter */
mbed_official	133:d4dda5c437f0	820	uint32_t b0addr = (uint32_t)blockb0;
mbed_official	133:d4dda5c437f0	821
mbed_official	133:d4dda5c437f0	822	/* Process Locked */
mbed_official	133:d4dda5c437f0	823	__HAL_LOCK(hcryp);
mbed_official	133:d4dda5c437f0	824
mbed_official	133:d4dda5c437f0	825	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	826	hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official	133:d4dda5c437f0	827
mbed_official	133:d4dda5c437f0	828	/* Check if initialization phase has already been performed */
mbed_official	133:d4dda5c437f0	829	if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official	133:d4dda5c437f0	830	{
mbed_official	133:d4dda5c437f0	831	/********************** Formatting the header block *******************/
mbed_official	133:d4dda5c437f0	832	if(headersize != 0)
mbed_official	133:d4dda5c437f0	833	{
mbed_official	133:d4dda5c437f0	834	/* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
mbed_official	133:d4dda5c437f0	835	if(headersize < 65280)
mbed_official	133:d4dda5c437f0	836	{
mbed_official	133:d4dda5c437f0	837	hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
mbed_official	133:d4dda5c437f0	838	hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
mbed_official	133:d4dda5c437f0	839	headersize += 2;
mbed_official	133:d4dda5c437f0	840	}
mbed_official	133:d4dda5c437f0	841	else
mbed_official	133:d4dda5c437f0	842	{
mbed_official	133:d4dda5c437f0	843	/* Header is encoded as 0xff \|\| 0xfe \|\| [headersize]32, i.e., six octets */
mbed_official	133:d4dda5c437f0	844	hcryp->Init.pScratch[bufferidx++] = 0xFF;
mbed_official	133:d4dda5c437f0	845	hcryp->Init.pScratch[bufferidx++] = 0xFE;
mbed_official	133:d4dda5c437f0	846	hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
mbed_official	133:d4dda5c437f0	847	hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
mbed_official	133:d4dda5c437f0	848	hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
mbed_official	133:d4dda5c437f0	849	hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
mbed_official	133:d4dda5c437f0	850	headersize += 6;
mbed_official	133:d4dda5c437f0	851	}
mbed_official	133:d4dda5c437f0	852	/* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
mbed_official	133:d4dda5c437f0	853	for(loopcounter = 0; loopcounter < headersize; loopcounter++)
mbed_official	133:d4dda5c437f0	854	{
mbed_official	133:d4dda5c437f0	855	hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
mbed_official	133:d4dda5c437f0	856	}
mbed_official	133:d4dda5c437f0	857	/* Check if the header size is modulo 16 */
mbed_official	133:d4dda5c437f0	858	if ((headersize % 16) != 0)
mbed_official	133:d4dda5c437f0	859	{
mbed_official	133:d4dda5c437f0	860	/* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
mbed_official	133:d4dda5c437f0	861	for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
mbed_official	133:d4dda5c437f0	862	{
mbed_official	133:d4dda5c437f0	863	hcryp->Init.pScratch[loopcounter] = 0;
mbed_official	133:d4dda5c437f0	864	}
mbed_official	133:d4dda5c437f0	865	/* Set the header size to modulo 16 */
mbed_official	133:d4dda5c437f0	866	headersize = ((headersize/16) + 1) * 16;
mbed_official	133:d4dda5c437f0	867	}
mbed_official	133:d4dda5c437f0	868	/* Set the pointer headeraddr to hcryp->Init.pScratch */
mbed_official	133:d4dda5c437f0	869	headeraddr = (uint32_t)hcryp->Init.pScratch;
mbed_official	133:d4dda5c437f0	870	}
mbed_official	133:d4dda5c437f0	871	/********************* Formatting the block B0 ************************/
mbed_official	133:d4dda5c437f0	872	if(headersize != 0)
mbed_official	133:d4dda5c437f0	873	{
mbed_official	133:d4dda5c437f0	874	blockb0[0] = 0x40;
mbed_official	133:d4dda5c437f0	875	}
mbed_official	133:d4dda5c437f0	876	/* Flags byte */
mbed_official	133:d4dda5c437f0	877	/* blockb0[0] \|= 0u \| (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) \| ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
mbed_official	133:d4dda5c437f0	878	blockb0[0] \|= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
mbed_official	133:d4dda5c437f0	879	blockb0[0] \|= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
mbed_official	133:d4dda5c437f0	880
mbed_official	133:d4dda5c437f0	881	for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
mbed_official	133:d4dda5c437f0	882	{
mbed_official	133:d4dda5c437f0	883	blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
mbed_official	133:d4dda5c437f0	884	}
mbed_official	133:d4dda5c437f0	885	for ( ; loopcounter < 13; loopcounter++)
mbed_official	133:d4dda5c437f0	886	{
mbed_official	133:d4dda5c437f0	887	blockb0[loopcounter+1] = 0;
mbed_official	133:d4dda5c437f0	888	}
mbed_official	133:d4dda5c437f0	889
mbed_official	133:d4dda5c437f0	890	blockb0[14] = (Size >> 8);
mbed_official	133:d4dda5c437f0	891	blockb0[15] = (Size & 0xFF);
mbed_official	133:d4dda5c437f0	892
mbed_official	133:d4dda5c437f0	893	/*********************** Formatting the initial counter ***************/
mbed_official	133:d4dda5c437f0	894	/* Byte 0:
mbed_official	133:d4dda5c437f0	895	Bits 7 and 6 are reserved and shall be set to 0
mbed_official	133:d4dda5c437f0	896	Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
mbed_official	133:d4dda5c437f0	897	blocks are distinct from B0
mbed_official	133:d4dda5c437f0	898	Bits 0, 1, and 2 contain the same encoding of q as in B0
mbed_official	133:d4dda5c437f0	899	*/
mbed_official	133:d4dda5c437f0	900	ctr[0] = blockb0[0] & 0x07;
mbed_official	133:d4dda5c437f0	901	/* byte 1 to NonceSize is the IV (Nonce) */
mbed_official	133:d4dda5c437f0	902	for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
mbed_official	133:d4dda5c437f0	903	{
mbed_official	133:d4dda5c437f0	904	ctr[loopcounter] = blockb0[loopcounter];
mbed_official	133:d4dda5c437f0	905	}
mbed_official	133:d4dda5c437f0	906	/* Set the LSB to 1 */
mbed_official	133:d4dda5c437f0	907	ctr[15] \|= 0x01;
mbed_official	133:d4dda5c437f0	908
mbed_official	133:d4dda5c437f0	909	/* Set the key */
mbed_official	133:d4dda5c437f0	910	CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official	133:d4dda5c437f0	911
mbed_official	133:d4dda5c437f0	912	/* Set the CRYP peripheral in AES CCM mode */
mbed_official	133:d4dda5c437f0	913	__HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
mbed_official	133:d4dda5c437f0	914
mbed_official	133:d4dda5c437f0	915	/* Set the Initialization Vector */
mbed_official	133:d4dda5c437f0	916	CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, CRYP_KEYSIZE_128B);
mbed_official	133:d4dda5c437f0	917
mbed_official	133:d4dda5c437f0	918	/* Select init phase */
mbed_official	133:d4dda5c437f0	919	__HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
mbed_official	133:d4dda5c437f0	920
mbed_official	133:d4dda5c437f0	921	b0addr = (uint32_t)blockb0;
mbed_official	133:d4dda5c437f0	922	/* Write the blockb0 block in the IN FIFO */
mbed_official	133:d4dda5c437f0	923	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	924	b0addr+=4;
mbed_official	133:d4dda5c437f0	925	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	926	b0addr+=4;
mbed_official	133:d4dda5c437f0	927	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	928	b0addr+=4;
mbed_official	133:d4dda5c437f0	929	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	930
mbed_official	133:d4dda5c437f0	931	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	932	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	933
mbed_official	133:d4dda5c437f0	934	/* Get timeout */
mbed_official	133:d4dda5c437f0	935	timeout = HAL_GetTick() + Timeout;
mbed_official	133:d4dda5c437f0	936
mbed_official	133:d4dda5c437f0	937	while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official	133:d4dda5c437f0	938	{
mbed_official	133:d4dda5c437f0	939	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	940	if(Timeout != HAL_MAX_DELAY)
mbed_official	133:d4dda5c437f0	941	{
mbed_official	133:d4dda5c437f0	942	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	943	{
mbed_official	133:d4dda5c437f0	944	/* Change state */
mbed_official	133:d4dda5c437f0	945	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	946
mbed_official	133:d4dda5c437f0	947	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	948	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	949
mbed_official	133:d4dda5c437f0	950	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	951	}
mbed_official	133:d4dda5c437f0	952	}
mbed_official	133:d4dda5c437f0	953	}
mbed_official	133:d4dda5c437f0	954	/*************************** Header phase *****************************/
mbed_official	133:d4dda5c437f0	955	if(headersize != 0)
mbed_official	133:d4dda5c437f0	956	{
mbed_official	133:d4dda5c437f0	957	/* Select header phase */
mbed_official	133:d4dda5c437f0	958	__HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
mbed_official	133:d4dda5c437f0	959
mbed_official	133:d4dda5c437f0	960	/* Enable Crypto processor */
mbed_official	133:d4dda5c437f0	961	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	962
mbed_official	133:d4dda5c437f0	963	for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
mbed_official	133:d4dda5c437f0	964	{
mbed_official	133:d4dda5c437f0	965	/* Get timeout */
mbed_official	133:d4dda5c437f0	966	timeout = HAL_GetTick() + Timeout;
mbed_official	133:d4dda5c437f0	967
mbed_official	133:d4dda5c437f0	968	while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
mbed_official	133:d4dda5c437f0	969	{
mbed_official	133:d4dda5c437f0	970	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	971	if(Timeout != HAL_MAX_DELAY)
mbed_official	133:d4dda5c437f0	972	{
mbed_official	133:d4dda5c437f0	973	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	974	{
mbed_official	133:d4dda5c437f0	975	/* Change state */
mbed_official	133:d4dda5c437f0	976	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	977
mbed_official	133:d4dda5c437f0	978	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	979	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	980
mbed_official	133:d4dda5c437f0	981	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	982	}
mbed_official	133:d4dda5c437f0	983	}
mbed_official	133:d4dda5c437f0	984	}
mbed_official	133:d4dda5c437f0	985	/* Write the header block in the IN FIFO */
mbed_official	133:d4dda5c437f0	986	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	987	headeraddr+=4;
mbed_official	133:d4dda5c437f0	988	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	989	headeraddr+=4;
mbed_official	133:d4dda5c437f0	990	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	991	headeraddr+=4;
mbed_official	133:d4dda5c437f0	992	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	993	headeraddr+=4;
mbed_official	133:d4dda5c437f0	994	}
mbed_official	133:d4dda5c437f0	995
mbed_official	133:d4dda5c437f0	996	/* Get timeout */
mbed_official	133:d4dda5c437f0	997	timeout = HAL_GetTick() + Timeout;
mbed_official	133:d4dda5c437f0	998
mbed_official	133:d4dda5c437f0	999	while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
mbed_official	133:d4dda5c437f0	1000	{
mbed_official	133:d4dda5c437f0	1001	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	1002	if(Timeout != HAL_MAX_DELAY)
mbed_official	133:d4dda5c437f0	1003	{
mbed_official	133:d4dda5c437f0	1004	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	1005	{
mbed_official	133:d4dda5c437f0	1006	/* Change state */
mbed_official	133:d4dda5c437f0	1007	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	1008
mbed_official	133:d4dda5c437f0	1009	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	1010	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	1011
mbed_official	133:d4dda5c437f0	1012	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	1013	}
mbed_official	133:d4dda5c437f0	1014	}
mbed_official	133:d4dda5c437f0	1015	}
mbed_official	133:d4dda5c437f0	1016	}
mbed_official	133:d4dda5c437f0	1017	/* Save formatted counter into the scratch buffer pScratch */
mbed_official	133:d4dda5c437f0	1018	for(loopcounter = 0; (loopcounter < 16); loopcounter++)
mbed_official	133:d4dda5c437f0	1019	{
mbed_official	133:d4dda5c437f0	1020	hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
mbed_official	133:d4dda5c437f0	1021	}
mbed_official	133:d4dda5c437f0	1022	/* Reset bit 0 */
mbed_official	133:d4dda5c437f0	1023	hcryp->Init.pScratch[15] &= 0xfe;
mbed_official	133:d4dda5c437f0	1024	/* Select payload phase once the header phase is performed */
mbed_official	133:d4dda5c437f0	1025	__HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official	133:d4dda5c437f0	1026
mbed_official	133:d4dda5c437f0	1027	/* Flush FIFO */
mbed_official	133:d4dda5c437f0	1028	__HAL_CRYP_FIFO_FLUSH();
mbed_official	133:d4dda5c437f0	1029
mbed_official	133:d4dda5c437f0	1030	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	1031	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	1032
mbed_official	133:d4dda5c437f0	1033	/* Set the phase */
mbed_official	133:d4dda5c437f0	1034	hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official	133:d4dda5c437f0	1035	}
mbed_official	133:d4dda5c437f0	1036
mbed_official	133:d4dda5c437f0	1037	/* Write Plain Data and Get Cypher Data */
mbed_official	133:d4dda5c437f0	1038	if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
mbed_official	133:d4dda5c437f0	1039	{
mbed_official	133:d4dda5c437f0	1040	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	1041	}
mbed_official	133:d4dda5c437f0	1042
mbed_official	133:d4dda5c437f0	1043	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	1044	hcryp->State = HAL_CRYP_STATE_READY;
mbed_official	133:d4dda5c437f0	1045
mbed_official	133:d4dda5c437f0	1046	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	1047	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	1048
mbed_official	133:d4dda5c437f0	1049	/* Return function status */
mbed_official	133:d4dda5c437f0	1050	return HAL_OK;
mbed_official	133:d4dda5c437f0	1051	}
mbed_official	133:d4dda5c437f0	1052
mbed_official	133:d4dda5c437f0	1053	/**
mbed_official	133:d4dda5c437f0	1054	* @brief Initializes the CRYP peripheral in AES GCM encryption mode using IT.
mbed_official	242:7074e42da0b2	1055	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
mbed_official	242:7074e42da0b2	1056	* the configuration information for CRYP module
mbed_official	133:d4dda5c437f0	1057	* @param pPlainData: Pointer to the plaintext buffer
mbed_official	133:d4dda5c437f0	1058	* @param Size: Length of the plaintext buffer, must be a multiple of 16
mbed_official	133:d4dda5c437f0	1059	* @param pCypherData: Pointer to the cyphertext buffer
mbed_official	133:d4dda5c437f0	1060	* @retval HAL status
mbed_official	133:d4dda5c437f0	1061	*/
mbed_official	133:d4dda5c437f0	1062	HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef hcryp, uint8_t pPlainData, uint16_t Size, uint8_t *pCypherData)
mbed_official	133:d4dda5c437f0	1063	{
mbed_official	133:d4dda5c437f0	1064	uint32_t timeout = 0;
mbed_official	133:d4dda5c437f0	1065	uint32_t inputaddr;
mbed_official	133:d4dda5c437f0	1066	uint32_t outputaddr;
mbed_official	133:d4dda5c437f0	1067
mbed_official	133:d4dda5c437f0	1068	if(hcryp->State == HAL_CRYP_STATE_READY)
mbed_official	133:d4dda5c437f0	1069	{
mbed_official	133:d4dda5c437f0	1070	/* Process Locked */
mbed_official	133:d4dda5c437f0	1071	__HAL_LOCK(hcryp);
mbed_official	133:d4dda5c437f0	1072
mbed_official	133:d4dda5c437f0	1073	/* Get the buffer addresses and sizes */
mbed_official	133:d4dda5c437f0	1074	hcryp->CrypInCount = Size;
mbed_official	133:d4dda5c437f0	1075	hcryp->pCrypInBuffPtr = pPlainData;
mbed_official	133:d4dda5c437f0	1076	hcryp->pCrypOutBuffPtr = pCypherData;
mbed_official	133:d4dda5c437f0	1077	hcryp->CrypOutCount = Size;
mbed_official	133:d4dda5c437f0	1078
mbed_official	133:d4dda5c437f0	1079	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	1080	hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official	133:d4dda5c437f0	1081
mbed_official	133:d4dda5c437f0	1082	/* Check if initialization phase has already been performed */
mbed_official	133:d4dda5c437f0	1083	if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official	133:d4dda5c437f0	1084	{
mbed_official	133:d4dda5c437f0	1085	/* Set the key */
mbed_official	133:d4dda5c437f0	1086	CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official	133:d4dda5c437f0	1087
mbed_official	133:d4dda5c437f0	1088	/* Set the CRYP peripheral in AES GCM mode */
mbed_official	133:d4dda5c437f0	1089	__HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
mbed_official	133:d4dda5c437f0	1090
mbed_official	133:d4dda5c437f0	1091	/* Set the Initialization Vector */
mbed_official	133:d4dda5c437f0	1092	CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
mbed_official	133:d4dda5c437f0	1093
mbed_official	133:d4dda5c437f0	1094	/* Flush FIFO */
mbed_official	133:d4dda5c437f0	1095	__HAL_CRYP_FIFO_FLUSH();
mbed_official	133:d4dda5c437f0	1096
mbed_official	133:d4dda5c437f0	1097	/* Enable CRYP to start the init phase */
mbed_official	133:d4dda5c437f0	1098	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	1099
mbed_official	133:d4dda5c437f0	1100	/* Get timeout */
mbed_official	133:d4dda5c437f0	1101	timeout = HAL_GetTick() + 1;
mbed_official	133:d4dda5c437f0	1102
mbed_official	133:d4dda5c437f0	1103	while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official	133:d4dda5c437f0	1104	{
mbed_official	133:d4dda5c437f0	1105	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	1106
mbed_official	133:d4dda5c437f0	1107	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	1108	{
mbed_official	133:d4dda5c437f0	1109	/* Change state */
mbed_official	133:d4dda5c437f0	1110	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	1111
mbed_official	133:d4dda5c437f0	1112	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	1113	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	1114
mbed_official	133:d4dda5c437f0	1115	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	1116
mbed_official	133:d4dda5c437f0	1117	}
mbed_official	133:d4dda5c437f0	1118	}
mbed_official	133:d4dda5c437f0	1119
mbed_official	133:d4dda5c437f0	1120	/* Set the header phase */
mbed_official	133:d4dda5c437f0	1121	if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
mbed_official	133:d4dda5c437f0	1122	{
mbed_official	133:d4dda5c437f0	1123	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	1124	}
mbed_official	133:d4dda5c437f0	1125	/* Disable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	1126	__HAL_CRYP_DISABLE();
mbed_official	133:d4dda5c437f0	1127
mbed_official	133:d4dda5c437f0	1128	/* Select payload phase once the header phase is performed */
mbed_official	133:d4dda5c437f0	1129	__HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official	133:d4dda5c437f0	1130
mbed_official	133:d4dda5c437f0	1131	/* Flush FIFO */
mbed_official	133:d4dda5c437f0	1132	__HAL_CRYP_FIFO_FLUSH();
mbed_official	133:d4dda5c437f0	1133
mbed_official	133:d4dda5c437f0	1134	/* Set the phase */
mbed_official	133:d4dda5c437f0	1135	hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official	133:d4dda5c437f0	1136	}
mbed_official	133:d4dda5c437f0	1137
mbed_official	133:d4dda5c437f0	1138	if(Size != 0)
mbed_official	133:d4dda5c437f0	1139	{
mbed_official	133:d4dda5c437f0	1140	/* Enable Interrupts */
mbed_official	133:d4dda5c437f0	1141	__HAL_CRYP_ENABLE_IT(CRYP_IT_INI \| CRYP_IT_OUTI);
mbed_official	133:d4dda5c437f0	1142	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	1143	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	1144	}
mbed_official	133:d4dda5c437f0	1145	else
mbed_official	133:d4dda5c437f0	1146	{
mbed_official	133:d4dda5c437f0	1147	/* Process Locked */
mbed_official	133:d4dda5c437f0	1148	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	1149	/* Change the CRYP state and phase */
mbed_official	133:d4dda5c437f0	1150	hcryp->State = HAL_CRYP_STATE_READY;
mbed_official	133:d4dda5c437f0	1151	}
mbed_official	133:d4dda5c437f0	1152	/* Return function status */
mbed_official	133:d4dda5c437f0	1153	return HAL_OK;
mbed_official	133:d4dda5c437f0	1154	}
mbed_official	133:d4dda5c437f0	1155	else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
mbed_official	133:d4dda5c437f0	1156	{
mbed_official	133:d4dda5c437f0	1157	inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
mbed_official	133:d4dda5c437f0	1158	/* Write the Input block in the IN FIFO */
mbed_official	133:d4dda5c437f0	1159	CRYP->DR = (uint32_t)(inputaddr);
mbed_official	133:d4dda5c437f0	1160	inputaddr+=4;
mbed_official	133:d4dda5c437f0	1161	CRYP->DR = (uint32_t)(inputaddr);
mbed_official	133:d4dda5c437f0	1162	inputaddr+=4;
mbed_official	133:d4dda5c437f0	1163	CRYP->DR = (uint32_t)(inputaddr);
mbed_official	133:d4dda5c437f0	1164	inputaddr+=4;
mbed_official	133:d4dda5c437f0	1165	CRYP->DR = (uint32_t)(inputaddr);
mbed_official	133:d4dda5c437f0	1166	hcryp->pCrypInBuffPtr += 16;
mbed_official	133:d4dda5c437f0	1167	hcryp->CrypInCount -= 16;
mbed_official	133:d4dda5c437f0	1168	if(hcryp->CrypInCount == 0)
mbed_official	133:d4dda5c437f0	1169	{
mbed_official	133:d4dda5c437f0	1170	__HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
mbed_official	133:d4dda5c437f0	1171	/* Call the Input data transfer complete callback */
mbed_official	133:d4dda5c437f0	1172	HAL_CRYP_InCpltCallback(hcryp);
mbed_official	133:d4dda5c437f0	1173	}
mbed_official	133:d4dda5c437f0	1174	}
mbed_official	133:d4dda5c437f0	1175	else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
mbed_official	133:d4dda5c437f0	1176	{
mbed_official	133:d4dda5c437f0	1177	outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
mbed_official	133:d4dda5c437f0	1178	/* Read the Output block from the Output FIFO */
mbed_official	133:d4dda5c437f0	1179	(uint32_t)(outputaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	1180	outputaddr+=4;
mbed_official	133:d4dda5c437f0	1181	(uint32_t)(outputaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	1182	outputaddr+=4;
mbed_official	133:d4dda5c437f0	1183	(uint32_t)(outputaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	1184	outputaddr+=4;
mbed_official	133:d4dda5c437f0	1185	(uint32_t)(outputaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	1186	hcryp->pCrypOutBuffPtr += 16;
mbed_official	133:d4dda5c437f0	1187	hcryp->CrypOutCount -= 16;
mbed_official	133:d4dda5c437f0	1188	if(hcryp->CrypOutCount == 0)
mbed_official	133:d4dda5c437f0	1189	{
mbed_official	133:d4dda5c437f0	1190	__HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
mbed_official	133:d4dda5c437f0	1191	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	1192	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	1193	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	1194	hcryp->State = HAL_CRYP_STATE_READY;
mbed_official	133:d4dda5c437f0	1195	/* Call Input transfer complete callback */
mbed_official	133:d4dda5c437f0	1196	HAL_CRYP_OutCpltCallback(hcryp);
mbed_official	133:d4dda5c437f0	1197	}
mbed_official	133:d4dda5c437f0	1198	}
mbed_official	133:d4dda5c437f0	1199
mbed_official	133:d4dda5c437f0	1200	/* Return function status */
mbed_official	133:d4dda5c437f0	1201	return HAL_OK;
mbed_official	133:d4dda5c437f0	1202	}
mbed_official	133:d4dda5c437f0	1203
mbed_official	133:d4dda5c437f0	1204	/**
mbed_official	133:d4dda5c437f0	1205	* @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.
mbed_official	242:7074e42da0b2	1206	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
mbed_official	242:7074e42da0b2	1207	* the configuration information for CRYP module
mbed_official	133:d4dda5c437f0	1208	* @param pPlainData: Pointer to the plaintext buffer
mbed_official	133:d4dda5c437f0	1209	* @param Size: Length of the plaintext buffer, must be a multiple of 16
mbed_official	133:d4dda5c437f0	1210	* @param pCypherData: Pointer to the cyphertext buffer
mbed_official	133:d4dda5c437f0	1211	* @retval HAL status
mbed_official	133:d4dda5c437f0	1212	*/
mbed_official	133:d4dda5c437f0	1213	HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef hcryp, uint8_t pPlainData, uint16_t Size, uint8_t *pCypherData)
mbed_official	133:d4dda5c437f0	1214	{
mbed_official	133:d4dda5c437f0	1215	uint32_t timeout = 0;
mbed_official	133:d4dda5c437f0	1216	uint32_t inputaddr;
mbed_official	133:d4dda5c437f0	1217	uint32_t outputaddr;
mbed_official	133:d4dda5c437f0	1218
mbed_official	133:d4dda5c437f0	1219	uint32_t headersize = hcryp->Init.HeaderSize;
mbed_official	133:d4dda5c437f0	1220	uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
mbed_official	133:d4dda5c437f0	1221	uint32_t loopcounter = 0;
mbed_official	133:d4dda5c437f0	1222	uint32_t bufferidx = 0;
mbed_official	133:d4dda5c437f0	1223	uint8_t blockb0[16] = {0};/* Block B0 */
mbed_official	133:d4dda5c437f0	1224	uint8_t ctr[16] = {0}; /* Counter */
mbed_official	133:d4dda5c437f0	1225	uint32_t b0addr = (uint32_t)blockb0;
mbed_official	133:d4dda5c437f0	1226
mbed_official	133:d4dda5c437f0	1227	if(hcryp->State == HAL_CRYP_STATE_READY)
mbed_official	133:d4dda5c437f0	1228	{
mbed_official	133:d4dda5c437f0	1229	/* Process Locked */
mbed_official	133:d4dda5c437f0	1230	__HAL_LOCK(hcryp);
mbed_official	133:d4dda5c437f0	1231
mbed_official	133:d4dda5c437f0	1232	hcryp->CrypInCount = Size;
mbed_official	133:d4dda5c437f0	1233	hcryp->pCrypInBuffPtr = pPlainData;
mbed_official	133:d4dda5c437f0	1234	hcryp->pCrypOutBuffPtr = pCypherData;
mbed_official	133:d4dda5c437f0	1235	hcryp->CrypOutCount = Size;
mbed_official	133:d4dda5c437f0	1236
mbed_official	133:d4dda5c437f0	1237	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	1238	hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official	133:d4dda5c437f0	1239
mbed_official	133:d4dda5c437f0	1240	/* Check if initialization phase has already been performed */
mbed_official	133:d4dda5c437f0	1241	if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official	133:d4dda5c437f0	1242	{
mbed_official	133:d4dda5c437f0	1243	/********************** Formatting the header block *****************/
mbed_official	133:d4dda5c437f0	1244	if(headersize != 0)
mbed_official	133:d4dda5c437f0	1245	{
mbed_official	133:d4dda5c437f0	1246	/* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
mbed_official	133:d4dda5c437f0	1247	if(headersize < 65280)
mbed_official	133:d4dda5c437f0	1248	{
mbed_official	133:d4dda5c437f0	1249	hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
mbed_official	133:d4dda5c437f0	1250	hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
mbed_official	133:d4dda5c437f0	1251	headersize += 2;
mbed_official	133:d4dda5c437f0	1252	}
mbed_official	133:d4dda5c437f0	1253	else
mbed_official	133:d4dda5c437f0	1254	{
mbed_official	133:d4dda5c437f0	1255	/* Header is encoded as 0xff \|\| 0xfe \|\| [headersize]32, i.e., six octets */
mbed_official	133:d4dda5c437f0	1256	hcryp->Init.pScratch[bufferidx++] = 0xFF;
mbed_official	133:d4dda5c437f0	1257	hcryp->Init.pScratch[bufferidx++] = 0xFE;
mbed_official	133:d4dda5c437f0	1258	hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
mbed_official	133:d4dda5c437f0	1259	hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
mbed_official	133:d4dda5c437f0	1260	hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
mbed_official	133:d4dda5c437f0	1261	hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
mbed_official	133:d4dda5c437f0	1262	headersize += 6;
mbed_official	133:d4dda5c437f0	1263	}
mbed_official	133:d4dda5c437f0	1264	/* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
mbed_official	133:d4dda5c437f0	1265	for(loopcounter = 0; loopcounter < headersize; loopcounter++)
mbed_official	133:d4dda5c437f0	1266	{
mbed_official	133:d4dda5c437f0	1267	hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
mbed_official	133:d4dda5c437f0	1268	}
mbed_official	133:d4dda5c437f0	1269	/* Check if the header size is modulo 16 */
mbed_official	133:d4dda5c437f0	1270	if ((headersize % 16) != 0)
mbed_official	133:d4dda5c437f0	1271	{
mbed_official	133:d4dda5c437f0	1272	/* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
mbed_official	133:d4dda5c437f0	1273	for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
mbed_official	133:d4dda5c437f0	1274	{
mbed_official	133:d4dda5c437f0	1275	hcryp->Init.pScratch[loopcounter] = 0;
mbed_official	133:d4dda5c437f0	1276	}
mbed_official	133:d4dda5c437f0	1277	/* Set the header size to modulo 16 */
mbed_official	133:d4dda5c437f0	1278	headersize = ((headersize/16) + 1) * 16;
mbed_official	133:d4dda5c437f0	1279	}
mbed_official	133:d4dda5c437f0	1280	/* Set the pointer headeraddr to hcryp->Init.pScratch */
mbed_official	133:d4dda5c437f0	1281	headeraddr = (uint32_t)hcryp->Init.pScratch;
mbed_official	133:d4dda5c437f0	1282	}
mbed_official	133:d4dda5c437f0	1283	/********************* Formatting the block B0 **********************/
mbed_official	133:d4dda5c437f0	1284	if(headersize != 0)
mbed_official	133:d4dda5c437f0	1285	{
mbed_official	133:d4dda5c437f0	1286	blockb0[0] = 0x40;
mbed_official	133:d4dda5c437f0	1287	}
mbed_official	133:d4dda5c437f0	1288	/* Flags byte */
mbed_official	133:d4dda5c437f0	1289	/* blockb0[0] \|= 0u \| (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) \| ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
mbed_official	133:d4dda5c437f0	1290	blockb0[0] \|= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
mbed_official	133:d4dda5c437f0	1291	blockb0[0] \|= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
mbed_official	133:d4dda5c437f0	1292
mbed_official	133:d4dda5c437f0	1293	for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
mbed_official	133:d4dda5c437f0	1294	{
mbed_official	133:d4dda5c437f0	1295	blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
mbed_official	133:d4dda5c437f0	1296	}
mbed_official	133:d4dda5c437f0	1297	for ( ; loopcounter < 13; loopcounter++)
mbed_official	133:d4dda5c437f0	1298	{
mbed_official	133:d4dda5c437f0	1299	blockb0[loopcounter+1] = 0;
mbed_official	133:d4dda5c437f0	1300	}
mbed_official	133:d4dda5c437f0	1301
mbed_official	133:d4dda5c437f0	1302	blockb0[14] = (Size >> 8);
mbed_official	133:d4dda5c437f0	1303	blockb0[15] = (Size & 0xFF);
mbed_official	133:d4dda5c437f0	1304
mbed_official	133:d4dda5c437f0	1305	/*********************** Formatting the initial counter *************/
mbed_official	133:d4dda5c437f0	1306	/* Byte 0:
mbed_official	133:d4dda5c437f0	1307	Bits 7 and 6 are reserved and shall be set to 0
mbed_official	133:d4dda5c437f0	1308	Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
mbed_official	133:d4dda5c437f0	1309	blocks are distinct from B0
mbed_official	133:d4dda5c437f0	1310	Bits 0, 1, and 2 contain the same encoding of q as in B0
mbed_official	133:d4dda5c437f0	1311	*/
mbed_official	133:d4dda5c437f0	1312	ctr[0] = blockb0[0] & 0x07;
mbed_official	133:d4dda5c437f0	1313	/* byte 1 to NonceSize is the IV (Nonce) */
mbed_official	133:d4dda5c437f0	1314	for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
mbed_official	133:d4dda5c437f0	1315	{
mbed_official	133:d4dda5c437f0	1316	ctr[loopcounter] = blockb0[loopcounter];
mbed_official	133:d4dda5c437f0	1317	}
mbed_official	133:d4dda5c437f0	1318	/* Set the LSB to 1 */
mbed_official	133:d4dda5c437f0	1319	ctr[15] \|= 0x01;
mbed_official	133:d4dda5c437f0	1320
mbed_official	133:d4dda5c437f0	1321	/* Set the key */
mbed_official	133:d4dda5c437f0	1322	CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official	133:d4dda5c437f0	1323
mbed_official	133:d4dda5c437f0	1324	/* Set the CRYP peripheral in AES CCM mode */
mbed_official	133:d4dda5c437f0	1325	__HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
mbed_official	133:d4dda5c437f0	1326
mbed_official	133:d4dda5c437f0	1327	/* Set the Initialization Vector */
mbed_official	133:d4dda5c437f0	1328	CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, hcryp->Init.KeySize);
mbed_official	133:d4dda5c437f0	1329
mbed_official	133:d4dda5c437f0	1330	/* Select init phase */
mbed_official	133:d4dda5c437f0	1331	__HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
mbed_official	133:d4dda5c437f0	1332
mbed_official	133:d4dda5c437f0	1333	b0addr = (uint32_t)blockb0;
mbed_official	133:d4dda5c437f0	1334	/* Write the blockb0 block in the IN FIFO */
mbed_official	133:d4dda5c437f0	1335	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	1336	b0addr+=4;
mbed_official	133:d4dda5c437f0	1337	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	1338	b0addr+=4;
mbed_official	133:d4dda5c437f0	1339	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	1340	b0addr+=4;
mbed_official	133:d4dda5c437f0	1341	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	1342
mbed_official	133:d4dda5c437f0	1343	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	1344	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	1345
mbed_official	133:d4dda5c437f0	1346	/* Get timeout */
mbed_official	133:d4dda5c437f0	1347	timeout = HAL_GetTick() + 1;
mbed_official	133:d4dda5c437f0	1348
mbed_official	133:d4dda5c437f0	1349	while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official	133:d4dda5c437f0	1350	{
mbed_official	133:d4dda5c437f0	1351	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	1352	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	1353	{
mbed_official	133:d4dda5c437f0	1354	/* Change state */
mbed_official	133:d4dda5c437f0	1355	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	1356
mbed_official	133:d4dda5c437f0	1357	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	1358	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	1359
mbed_official	133:d4dda5c437f0	1360	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	1361	}
mbed_official	133:d4dda5c437f0	1362	}
mbed_official	133:d4dda5c437f0	1363	/*************************** Header phase ***************************/
mbed_official	133:d4dda5c437f0	1364	if(headersize != 0)
mbed_official	133:d4dda5c437f0	1365	{
mbed_official	133:d4dda5c437f0	1366	/* Select header phase */
mbed_official	133:d4dda5c437f0	1367	__HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
mbed_official	133:d4dda5c437f0	1368
mbed_official	133:d4dda5c437f0	1369	/* Enable Crypto processor */
mbed_official	133:d4dda5c437f0	1370	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	1371
mbed_official	133:d4dda5c437f0	1372	for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
mbed_official	133:d4dda5c437f0	1373	{
mbed_official	133:d4dda5c437f0	1374	/* Get timeout */
mbed_official	133:d4dda5c437f0	1375	timeout = HAL_GetTick() + 1;
mbed_official	133:d4dda5c437f0	1376
mbed_official	133:d4dda5c437f0	1377	while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
mbed_official	133:d4dda5c437f0	1378	{
mbed_official	133:d4dda5c437f0	1379	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	1380	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	1381	{
mbed_official	133:d4dda5c437f0	1382	/* Change state */
mbed_official	133:d4dda5c437f0	1383	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	1384
mbed_official	133:d4dda5c437f0	1385	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	1386	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	1387
mbed_official	133:d4dda5c437f0	1388	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	1389	}
mbed_official	133:d4dda5c437f0	1390	}
mbed_official	133:d4dda5c437f0	1391	/* Write the header block in the IN FIFO */
mbed_official	133:d4dda5c437f0	1392	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	1393	headeraddr+=4;
mbed_official	133:d4dda5c437f0	1394	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	1395	headeraddr+=4;
mbed_official	133:d4dda5c437f0	1396	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	1397	headeraddr+=4;
mbed_official	133:d4dda5c437f0	1398	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	1399	headeraddr+=4;
mbed_official	133:d4dda5c437f0	1400	}
mbed_official	133:d4dda5c437f0	1401
mbed_official	133:d4dda5c437f0	1402	/* Get timeout */
mbed_official	133:d4dda5c437f0	1403	timeout = HAL_GetTick() + 1;
mbed_official	133:d4dda5c437f0	1404
mbed_official	133:d4dda5c437f0	1405	while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
mbed_official	133:d4dda5c437f0	1406	{
mbed_official	133:d4dda5c437f0	1407	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	1408	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	1409	{
mbed_official	133:d4dda5c437f0	1410	/* Change state */
mbed_official	133:d4dda5c437f0	1411	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	1412
mbed_official	133:d4dda5c437f0	1413	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	1414	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	1415
mbed_official	133:d4dda5c437f0	1416	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	1417	}
mbed_official	133:d4dda5c437f0	1418	}
mbed_official	133:d4dda5c437f0	1419	}
mbed_official	133:d4dda5c437f0	1420	/* Save formatted counter into the scratch buffer pScratch */
mbed_official	133:d4dda5c437f0	1421	for(loopcounter = 0; (loopcounter < 16); loopcounter++)
mbed_official	133:d4dda5c437f0	1422	{
mbed_official	133:d4dda5c437f0	1423	hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
mbed_official	133:d4dda5c437f0	1424	}
mbed_official	133:d4dda5c437f0	1425	/* Reset bit 0 */
mbed_official	133:d4dda5c437f0	1426	hcryp->Init.pScratch[15] &= 0xfe;
mbed_official	133:d4dda5c437f0	1427
mbed_official	133:d4dda5c437f0	1428	/* Select payload phase once the header phase is performed */
mbed_official	133:d4dda5c437f0	1429	__HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official	133:d4dda5c437f0	1430
mbed_official	133:d4dda5c437f0	1431	/* Flush FIFO */
mbed_official	133:d4dda5c437f0	1432	__HAL_CRYP_FIFO_FLUSH();
mbed_official	133:d4dda5c437f0	1433
mbed_official	133:d4dda5c437f0	1434	/* Set the phase */
mbed_official	133:d4dda5c437f0	1435	hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official	133:d4dda5c437f0	1436	}
mbed_official	133:d4dda5c437f0	1437
mbed_official	133:d4dda5c437f0	1438	if(Size != 0)
mbed_official	133:d4dda5c437f0	1439	{
mbed_official	133:d4dda5c437f0	1440	/* Enable Interrupts */
mbed_official	133:d4dda5c437f0	1441	__HAL_CRYP_ENABLE_IT(CRYP_IT_INI \| CRYP_IT_OUTI);
mbed_official	133:d4dda5c437f0	1442	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	1443	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	1444	}
mbed_official	133:d4dda5c437f0	1445	else
mbed_official	133:d4dda5c437f0	1446	{
mbed_official	133:d4dda5c437f0	1447	/* Change the CRYP state and phase */
mbed_official	133:d4dda5c437f0	1448	hcryp->State = HAL_CRYP_STATE_READY;
mbed_official	133:d4dda5c437f0	1449	}
mbed_official	133:d4dda5c437f0	1450
mbed_official	133:d4dda5c437f0	1451	/* Return function status */
mbed_official	133:d4dda5c437f0	1452	return HAL_OK;
mbed_official	133:d4dda5c437f0	1453	}
mbed_official	133:d4dda5c437f0	1454	else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
mbed_official	133:d4dda5c437f0	1455	{
mbed_official	133:d4dda5c437f0	1456	inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
mbed_official	133:d4dda5c437f0	1457	/* Write the Input block in the IN FIFO */
mbed_official	133:d4dda5c437f0	1458	CRYP->DR = (uint32_t)(inputaddr);
mbed_official	133:d4dda5c437f0	1459	inputaddr+=4;
mbed_official	133:d4dda5c437f0	1460	CRYP->DR = (uint32_t)(inputaddr);
mbed_official	133:d4dda5c437f0	1461	inputaddr+=4;
mbed_official	133:d4dda5c437f0	1462	CRYP->DR = (uint32_t)(inputaddr);
mbed_official	133:d4dda5c437f0	1463	inputaddr+=4;
mbed_official	133:d4dda5c437f0	1464	CRYP->DR = (uint32_t)(inputaddr);
mbed_official	133:d4dda5c437f0	1465	hcryp->pCrypInBuffPtr += 16;
mbed_official	133:d4dda5c437f0	1466	hcryp->CrypInCount -= 16;
mbed_official	133:d4dda5c437f0	1467	if(hcryp->CrypInCount == 0)
mbed_official	133:d4dda5c437f0	1468	{
mbed_official	133:d4dda5c437f0	1469	__HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
mbed_official	133:d4dda5c437f0	1470	/* Call Input transfer complete callback */
mbed_official	133:d4dda5c437f0	1471	HAL_CRYP_InCpltCallback(hcryp);
mbed_official	133:d4dda5c437f0	1472	}
mbed_official	133:d4dda5c437f0	1473	}
mbed_official	133:d4dda5c437f0	1474	else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
mbed_official	133:d4dda5c437f0	1475	{
mbed_official	133:d4dda5c437f0	1476	outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
mbed_official	133:d4dda5c437f0	1477	/* Read the Output block from the Output FIFO */
mbed_official	133:d4dda5c437f0	1478	(uint32_t)(outputaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	1479	outputaddr+=4;
mbed_official	133:d4dda5c437f0	1480	(uint32_t)(outputaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	1481	outputaddr+=4;
mbed_official	133:d4dda5c437f0	1482	(uint32_t)(outputaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	1483	outputaddr+=4;
mbed_official	133:d4dda5c437f0	1484	(uint32_t)(outputaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	1485	hcryp->pCrypOutBuffPtr += 16;
mbed_official	133:d4dda5c437f0	1486	hcryp->CrypOutCount -= 16;
mbed_official	133:d4dda5c437f0	1487	if(hcryp->CrypOutCount == 0)
mbed_official	133:d4dda5c437f0	1488	{
mbed_official	133:d4dda5c437f0	1489	__HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
mbed_official	133:d4dda5c437f0	1490	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	1491	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	1492	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	1493	hcryp->State = HAL_CRYP_STATE_READY;
mbed_official	133:d4dda5c437f0	1494	/* Call Input transfer complete callback */
mbed_official	133:d4dda5c437f0	1495	HAL_CRYP_OutCpltCallback(hcryp);
mbed_official	133:d4dda5c437f0	1496	}
mbed_official	133:d4dda5c437f0	1497	}
mbed_official	133:d4dda5c437f0	1498
mbed_official	133:d4dda5c437f0	1499	/* Return function status */
mbed_official	133:d4dda5c437f0	1500	return HAL_OK;
mbed_official	133:d4dda5c437f0	1501	}
mbed_official	133:d4dda5c437f0	1502
mbed_official	133:d4dda5c437f0	1503	/**
mbed_official	133:d4dda5c437f0	1504	* @brief Initializes the CRYP peripheral in AES GCM decryption mode using IT.
mbed_official	242:7074e42da0b2	1505	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
mbed_official	242:7074e42da0b2	1506	* the configuration information for CRYP module
mbed_official	133:d4dda5c437f0	1507	* @param pCypherData: Pointer to the cyphertext buffer
mbed_official	133:d4dda5c437f0	1508	* @param Size: Length of the cyphertext buffer, must be a multiple of 16
mbed_official	133:d4dda5c437f0	1509	* @param pPlainData: Pointer to the plaintext buffer
mbed_official	133:d4dda5c437f0	1510	* @retval HAL status
mbed_official	133:d4dda5c437f0	1511	*/
mbed_official	133:d4dda5c437f0	1512	HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef hcryp, uint8_t pCypherData, uint16_t Size, uint8_t *pPlainData)
mbed_official	133:d4dda5c437f0	1513	{
mbed_official	133:d4dda5c437f0	1514	uint32_t timeout = 0;
mbed_official	133:d4dda5c437f0	1515	uint32_t inputaddr;
mbed_official	133:d4dda5c437f0	1516	uint32_t outputaddr;
mbed_official	133:d4dda5c437f0	1517
mbed_official	133:d4dda5c437f0	1518	if(hcryp->State == HAL_CRYP_STATE_READY)
mbed_official	133:d4dda5c437f0	1519	{
mbed_official	133:d4dda5c437f0	1520	/* Process Locked */
mbed_official	133:d4dda5c437f0	1521	__HAL_LOCK(hcryp);
mbed_official	133:d4dda5c437f0	1522
mbed_official	133:d4dda5c437f0	1523	/* Get the buffer addresses and sizes */
mbed_official	133:d4dda5c437f0	1524	hcryp->CrypInCount = Size;
mbed_official	133:d4dda5c437f0	1525	hcryp->pCrypInBuffPtr = pCypherData;
mbed_official	133:d4dda5c437f0	1526	hcryp->pCrypOutBuffPtr = pPlainData;
mbed_official	133:d4dda5c437f0	1527	hcryp->CrypOutCount = Size;
mbed_official	133:d4dda5c437f0	1528
mbed_official	133:d4dda5c437f0	1529	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	1530	hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official	133:d4dda5c437f0	1531
mbed_official	133:d4dda5c437f0	1532	/* Check if initialization phase has already been performed */
mbed_official	133:d4dda5c437f0	1533	if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official	133:d4dda5c437f0	1534	{
mbed_official	133:d4dda5c437f0	1535	/* Set the key */
mbed_official	133:d4dda5c437f0	1536	CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official	133:d4dda5c437f0	1537
mbed_official	133:d4dda5c437f0	1538	/* Set the CRYP peripheral in AES GCM decryption mode */
mbed_official	133:d4dda5c437f0	1539	__HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
mbed_official	133:d4dda5c437f0	1540
mbed_official	133:d4dda5c437f0	1541	/* Set the Initialization Vector */
mbed_official	133:d4dda5c437f0	1542	CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
mbed_official	133:d4dda5c437f0	1543
mbed_official	133:d4dda5c437f0	1544	/* Flush FIFO */
mbed_official	133:d4dda5c437f0	1545	__HAL_CRYP_FIFO_FLUSH();
mbed_official	133:d4dda5c437f0	1546
mbed_official	133:d4dda5c437f0	1547	/* Enable CRYP to start the init phase */
mbed_official	133:d4dda5c437f0	1548	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	1549
mbed_official	133:d4dda5c437f0	1550	/* Get timeout */
mbed_official	133:d4dda5c437f0	1551	timeout = HAL_GetTick() + 1;
mbed_official	133:d4dda5c437f0	1552
mbed_official	133:d4dda5c437f0	1553	while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official	133:d4dda5c437f0	1554	{
mbed_official	133:d4dda5c437f0	1555	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	1556	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	1557	{
mbed_official	133:d4dda5c437f0	1558	/* Change state */
mbed_official	133:d4dda5c437f0	1559	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	1560
mbed_official	133:d4dda5c437f0	1561	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	1562	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	1563
mbed_official	133:d4dda5c437f0	1564	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	1565	}
mbed_official	133:d4dda5c437f0	1566	}
mbed_official	133:d4dda5c437f0	1567
mbed_official	133:d4dda5c437f0	1568	/* Set the header phase */
mbed_official	133:d4dda5c437f0	1569	if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
mbed_official	133:d4dda5c437f0	1570	{
mbed_official	133:d4dda5c437f0	1571	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	1572	}
mbed_official	133:d4dda5c437f0	1573	/* Disable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	1574	__HAL_CRYP_DISABLE();
mbed_official	133:d4dda5c437f0	1575
mbed_official	133:d4dda5c437f0	1576	/* Select payload phase once the header phase is performed */
mbed_official	133:d4dda5c437f0	1577	__HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official	133:d4dda5c437f0	1578
mbed_official	133:d4dda5c437f0	1579	/* Set the phase */
mbed_official	133:d4dda5c437f0	1580	hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official	133:d4dda5c437f0	1581	}
mbed_official	133:d4dda5c437f0	1582
mbed_official	133:d4dda5c437f0	1583	if(Size != 0)
mbed_official	133:d4dda5c437f0	1584	{
mbed_official	133:d4dda5c437f0	1585	/* Enable Interrupts */
mbed_official	133:d4dda5c437f0	1586	__HAL_CRYP_ENABLE_IT(CRYP_IT_INI \| CRYP_IT_OUTI);
mbed_official	133:d4dda5c437f0	1587	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	1588	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	1589	}
mbed_official	133:d4dda5c437f0	1590	else
mbed_official	133:d4dda5c437f0	1591	{
mbed_official	133:d4dda5c437f0	1592	/* Process Locked */
mbed_official	133:d4dda5c437f0	1593	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	1594	/* Change the CRYP state and phase */
mbed_official	133:d4dda5c437f0	1595	hcryp->State = HAL_CRYP_STATE_READY;
mbed_official	133:d4dda5c437f0	1596	}
mbed_official	133:d4dda5c437f0	1597
mbed_official	133:d4dda5c437f0	1598	/* Return function status */
mbed_official	133:d4dda5c437f0	1599	return HAL_OK;
mbed_official	133:d4dda5c437f0	1600	}
mbed_official	133:d4dda5c437f0	1601	else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
mbed_official	133:d4dda5c437f0	1602	{
mbed_official	133:d4dda5c437f0	1603	inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
mbed_official	133:d4dda5c437f0	1604	/* Write the Input block in the IN FIFO */
mbed_official	133:d4dda5c437f0	1605	CRYP->DR = (uint32_t)(inputaddr);
mbed_official	133:d4dda5c437f0	1606	inputaddr+=4;
mbed_official	133:d4dda5c437f0	1607	CRYP->DR = (uint32_t)(inputaddr);
mbed_official	133:d4dda5c437f0	1608	inputaddr+=4;
mbed_official	133:d4dda5c437f0	1609	CRYP->DR = (uint32_t)(inputaddr);
mbed_official	133:d4dda5c437f0	1610	inputaddr+=4;
mbed_official	133:d4dda5c437f0	1611	CRYP->DR = (uint32_t)(inputaddr);
mbed_official	133:d4dda5c437f0	1612	hcryp->pCrypInBuffPtr += 16;
mbed_official	133:d4dda5c437f0	1613	hcryp->CrypInCount -= 16;
mbed_official	133:d4dda5c437f0	1614	if(hcryp->CrypInCount == 0)
mbed_official	133:d4dda5c437f0	1615	{
mbed_official	133:d4dda5c437f0	1616	__HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
mbed_official	133:d4dda5c437f0	1617	/* Call the Input data transfer complete callback */
mbed_official	133:d4dda5c437f0	1618	HAL_CRYP_InCpltCallback(hcryp);
mbed_official	133:d4dda5c437f0	1619	}
mbed_official	133:d4dda5c437f0	1620	}
mbed_official	133:d4dda5c437f0	1621	else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
mbed_official	133:d4dda5c437f0	1622	{
mbed_official	133:d4dda5c437f0	1623	outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
mbed_official	133:d4dda5c437f0	1624	/* Read the Output block from the Output FIFO */
mbed_official	133:d4dda5c437f0	1625	(uint32_t)(outputaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	1626	outputaddr+=4;
mbed_official	133:d4dda5c437f0	1627	(uint32_t)(outputaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	1628	outputaddr+=4;
mbed_official	133:d4dda5c437f0	1629	(uint32_t)(outputaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	1630	outputaddr+=4;
mbed_official	133:d4dda5c437f0	1631	(uint32_t)(outputaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	1632	hcryp->pCrypOutBuffPtr += 16;
mbed_official	133:d4dda5c437f0	1633	hcryp->CrypOutCount -= 16;
mbed_official	133:d4dda5c437f0	1634	if(hcryp->CrypOutCount == 0)
mbed_official	133:d4dda5c437f0	1635	{
mbed_official	133:d4dda5c437f0	1636	__HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
mbed_official	133:d4dda5c437f0	1637	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	1638	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	1639	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	1640	hcryp->State = HAL_CRYP_STATE_READY;
mbed_official	133:d4dda5c437f0	1641	/* Call Input transfer complete callback */
mbed_official	133:d4dda5c437f0	1642	HAL_CRYP_OutCpltCallback(hcryp);
mbed_official	133:d4dda5c437f0	1643	}
mbed_official	133:d4dda5c437f0	1644	}
mbed_official	133:d4dda5c437f0	1645
mbed_official	133:d4dda5c437f0	1646	/* Return function status */
mbed_official	133:d4dda5c437f0	1647	return HAL_OK;
mbed_official	133:d4dda5c437f0	1648	}
mbed_official	133:d4dda5c437f0	1649
mbed_official	133:d4dda5c437f0	1650	/**
mbed_official	133:d4dda5c437f0	1651	* @brief Initializes the CRYP peripheral in AES CCM decryption mode using interrupt
mbed_official	133:d4dda5c437f0	1652	* then decrypted pCypherData. The cypher data are available in pPlainData.
mbed_official	242:7074e42da0b2	1653	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
mbed_official	242:7074e42da0b2	1654	* the configuration information for CRYP module
mbed_official	133:d4dda5c437f0	1655	* @param pCypherData: Pointer to the cyphertext buffer
mbed_official	133:d4dda5c437f0	1656	* @param Size: Length of the plaintext buffer, must be a multiple of 16
mbed_official	133:d4dda5c437f0	1657	* @param pPlainData: Pointer to the plaintext buffer
mbed_official	133:d4dda5c437f0	1658	* @retval HAL status
mbed_official	133:d4dda5c437f0	1659	*/
mbed_official	133:d4dda5c437f0	1660	HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef hcryp, uint8_t pCypherData, uint16_t Size, uint8_t *pPlainData)
mbed_official	133:d4dda5c437f0	1661	{
mbed_official	133:d4dda5c437f0	1662	uint32_t inputaddr;
mbed_official	133:d4dda5c437f0	1663	uint32_t outputaddr;
mbed_official	133:d4dda5c437f0	1664	uint32_t timeout = 0;
mbed_official	133:d4dda5c437f0	1665	uint32_t headersize = hcryp->Init.HeaderSize;
mbed_official	133:d4dda5c437f0	1666	uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
mbed_official	133:d4dda5c437f0	1667	uint32_t loopcounter = 0;
mbed_official	133:d4dda5c437f0	1668	uint32_t bufferidx = 0;
mbed_official	133:d4dda5c437f0	1669	uint8_t blockb0[16] = {0};/* Block B0 */
mbed_official	133:d4dda5c437f0	1670	uint8_t ctr[16] = {0}; /* Counter */
mbed_official	133:d4dda5c437f0	1671	uint32_t b0addr = (uint32_t)blockb0;
mbed_official	133:d4dda5c437f0	1672
mbed_official	133:d4dda5c437f0	1673	if(hcryp->State == HAL_CRYP_STATE_READY)
mbed_official	133:d4dda5c437f0	1674	{
mbed_official	133:d4dda5c437f0	1675	/* Process Locked */
mbed_official	133:d4dda5c437f0	1676	__HAL_LOCK(hcryp);
mbed_official	133:d4dda5c437f0	1677
mbed_official	133:d4dda5c437f0	1678	hcryp->CrypInCount = Size;
mbed_official	133:d4dda5c437f0	1679	hcryp->pCrypInBuffPtr = pCypherData;
mbed_official	133:d4dda5c437f0	1680	hcryp->pCrypOutBuffPtr = pPlainData;
mbed_official	133:d4dda5c437f0	1681	hcryp->CrypOutCount = Size;
mbed_official	133:d4dda5c437f0	1682
mbed_official	133:d4dda5c437f0	1683	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	1684	hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official	133:d4dda5c437f0	1685
mbed_official	133:d4dda5c437f0	1686	/* Check if initialization phase has already been performed */
mbed_official	133:d4dda5c437f0	1687	if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official	133:d4dda5c437f0	1688	{
mbed_official	133:d4dda5c437f0	1689	/********************** Formatting the header block *****************/
mbed_official	133:d4dda5c437f0	1690	if(headersize != 0)
mbed_official	133:d4dda5c437f0	1691	{
mbed_official	133:d4dda5c437f0	1692	/* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
mbed_official	133:d4dda5c437f0	1693	if(headersize < 65280)
mbed_official	133:d4dda5c437f0	1694	{
mbed_official	133:d4dda5c437f0	1695	hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
mbed_official	133:d4dda5c437f0	1696	hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
mbed_official	133:d4dda5c437f0	1697	headersize += 2;
mbed_official	133:d4dda5c437f0	1698	}
mbed_official	133:d4dda5c437f0	1699	else
mbed_official	133:d4dda5c437f0	1700	{
mbed_official	133:d4dda5c437f0	1701	/* Header is encoded as 0xff \|\| 0xfe \|\| [headersize]32, i.e., six octets */
mbed_official	133:d4dda5c437f0	1702	hcryp->Init.pScratch[bufferidx++] = 0xFF;
mbed_official	133:d4dda5c437f0	1703	hcryp->Init.pScratch[bufferidx++] = 0xFE;
mbed_official	133:d4dda5c437f0	1704	hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
mbed_official	133:d4dda5c437f0	1705	hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
mbed_official	133:d4dda5c437f0	1706	hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
mbed_official	133:d4dda5c437f0	1707	hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
mbed_official	133:d4dda5c437f0	1708	headersize += 6;
mbed_official	133:d4dda5c437f0	1709	}
mbed_official	133:d4dda5c437f0	1710	/* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
mbed_official	133:d4dda5c437f0	1711	for(loopcounter = 0; loopcounter < headersize; loopcounter++)
mbed_official	133:d4dda5c437f0	1712	{
mbed_official	133:d4dda5c437f0	1713	hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
mbed_official	133:d4dda5c437f0	1714	}
mbed_official	133:d4dda5c437f0	1715	/* Check if the header size is modulo 16 */
mbed_official	133:d4dda5c437f0	1716	if ((headersize % 16) != 0)
mbed_official	133:d4dda5c437f0	1717	{
mbed_official	133:d4dda5c437f0	1718	/* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
mbed_official	133:d4dda5c437f0	1719	for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
mbed_official	133:d4dda5c437f0	1720	{
mbed_official	133:d4dda5c437f0	1721	hcryp->Init.pScratch[loopcounter] = 0;
mbed_official	133:d4dda5c437f0	1722	}
mbed_official	133:d4dda5c437f0	1723	/* Set the header size to modulo 16 */
mbed_official	133:d4dda5c437f0	1724	headersize = ((headersize/16) + 1) * 16;
mbed_official	133:d4dda5c437f0	1725	}
mbed_official	133:d4dda5c437f0	1726	/* Set the pointer headeraddr to hcryp->Init.pScratch */
mbed_official	133:d4dda5c437f0	1727	headeraddr = (uint32_t)hcryp->Init.pScratch;
mbed_official	133:d4dda5c437f0	1728	}
mbed_official	133:d4dda5c437f0	1729	/********************* Formatting the block B0 **********************/
mbed_official	133:d4dda5c437f0	1730	if(headersize != 0)
mbed_official	133:d4dda5c437f0	1731	{
mbed_official	133:d4dda5c437f0	1732	blockb0[0] = 0x40;
mbed_official	133:d4dda5c437f0	1733	}
mbed_official	133:d4dda5c437f0	1734	/* Flags byte */
mbed_official	133:d4dda5c437f0	1735	/* blockb0[0] \|= 0u \| (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) \| ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
mbed_official	133:d4dda5c437f0	1736	blockb0[0] \|= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
mbed_official	133:d4dda5c437f0	1737	blockb0[0] \|= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
mbed_official	133:d4dda5c437f0	1738
mbed_official	133:d4dda5c437f0	1739	for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
mbed_official	133:d4dda5c437f0	1740	{
mbed_official	133:d4dda5c437f0	1741	blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
mbed_official	133:d4dda5c437f0	1742	}
mbed_official	133:d4dda5c437f0	1743	for ( ; loopcounter < 13; loopcounter++)
mbed_official	133:d4dda5c437f0	1744	{
mbed_official	133:d4dda5c437f0	1745	blockb0[loopcounter+1] = 0;
mbed_official	133:d4dda5c437f0	1746	}
mbed_official	133:d4dda5c437f0	1747
mbed_official	133:d4dda5c437f0	1748	blockb0[14] = (Size >> 8);
mbed_official	133:d4dda5c437f0	1749	blockb0[15] = (Size & 0xFF);
mbed_official	133:d4dda5c437f0	1750
mbed_official	133:d4dda5c437f0	1751	/*********************** Formatting the initial counter *************/
mbed_official	133:d4dda5c437f0	1752	/* Byte 0:
mbed_official	133:d4dda5c437f0	1753	Bits 7 and 6 are reserved and shall be set to 0
mbed_official	133:d4dda5c437f0	1754	Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
mbed_official	133:d4dda5c437f0	1755	blocks are distinct from B0
mbed_official	133:d4dda5c437f0	1756	Bits 0, 1, and 2 contain the same encoding of q as in B0
mbed_official	133:d4dda5c437f0	1757	*/
mbed_official	133:d4dda5c437f0	1758	ctr[0] = blockb0[0] & 0x07;
mbed_official	133:d4dda5c437f0	1759	/* byte 1 to NonceSize is the IV (Nonce) */
mbed_official	133:d4dda5c437f0	1760	for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
mbed_official	133:d4dda5c437f0	1761	{
mbed_official	133:d4dda5c437f0	1762	ctr[loopcounter] = blockb0[loopcounter];
mbed_official	133:d4dda5c437f0	1763	}
mbed_official	133:d4dda5c437f0	1764	/* Set the LSB to 1 */
mbed_official	133:d4dda5c437f0	1765	ctr[15] \|= 0x01;
mbed_official	133:d4dda5c437f0	1766
mbed_official	133:d4dda5c437f0	1767	/* Set the key */
mbed_official	133:d4dda5c437f0	1768	CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official	133:d4dda5c437f0	1769
mbed_official	133:d4dda5c437f0	1770	/* Set the CRYP peripheral in AES CCM mode */
mbed_official	133:d4dda5c437f0	1771	__HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
mbed_official	133:d4dda5c437f0	1772
mbed_official	133:d4dda5c437f0	1773	/* Set the Initialization Vector */
mbed_official	133:d4dda5c437f0	1774	CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, hcryp->Init.KeySize);
mbed_official	133:d4dda5c437f0	1775
mbed_official	133:d4dda5c437f0	1776	/* Select init phase */
mbed_official	133:d4dda5c437f0	1777	__HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
mbed_official	133:d4dda5c437f0	1778
mbed_official	133:d4dda5c437f0	1779	b0addr = (uint32_t)blockb0;
mbed_official	133:d4dda5c437f0	1780	/* Write the blockb0 block in the IN FIFO */
mbed_official	133:d4dda5c437f0	1781	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	1782	b0addr+=4;
mbed_official	133:d4dda5c437f0	1783	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	1784	b0addr+=4;
mbed_official	133:d4dda5c437f0	1785	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	1786	b0addr+=4;
mbed_official	133:d4dda5c437f0	1787	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	1788
mbed_official	133:d4dda5c437f0	1789	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	1790	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	1791
mbed_official	133:d4dda5c437f0	1792	/* Get timeout */
mbed_official	133:d4dda5c437f0	1793	timeout = HAL_GetTick() + 1;
mbed_official	133:d4dda5c437f0	1794
mbed_official	133:d4dda5c437f0	1795	while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official	133:d4dda5c437f0	1796	{
mbed_official	133:d4dda5c437f0	1797	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	1798	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	1799	{
mbed_official	133:d4dda5c437f0	1800	/* Change state */
mbed_official	133:d4dda5c437f0	1801	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	1802
mbed_official	133:d4dda5c437f0	1803	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	1804	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	1805
mbed_official	133:d4dda5c437f0	1806	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	1807	}
mbed_official	133:d4dda5c437f0	1808	}
mbed_official	133:d4dda5c437f0	1809	/*************************** Header phase ***************************/
mbed_official	133:d4dda5c437f0	1810	if(headersize != 0)
mbed_official	133:d4dda5c437f0	1811	{
mbed_official	133:d4dda5c437f0	1812	/* Select header phase */
mbed_official	133:d4dda5c437f0	1813	__HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
mbed_official	133:d4dda5c437f0	1814
mbed_official	133:d4dda5c437f0	1815	/* Enable Crypto processor */
mbed_official	133:d4dda5c437f0	1816	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	1817
mbed_official	133:d4dda5c437f0	1818	for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
mbed_official	133:d4dda5c437f0	1819	{
mbed_official	133:d4dda5c437f0	1820	/* Get timeout */
mbed_official	133:d4dda5c437f0	1821	timeout = HAL_GetTick() + 1;
mbed_official	133:d4dda5c437f0	1822
mbed_official	133:d4dda5c437f0	1823	while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
mbed_official	133:d4dda5c437f0	1824	{
mbed_official	133:d4dda5c437f0	1825	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	1826	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	1827	{
mbed_official	133:d4dda5c437f0	1828	/* Change state */
mbed_official	133:d4dda5c437f0	1829	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	1830
mbed_official	133:d4dda5c437f0	1831	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	1832	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	1833
mbed_official	133:d4dda5c437f0	1834	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	1835	}
mbed_official	133:d4dda5c437f0	1836	}
mbed_official	133:d4dda5c437f0	1837	/* Write the header block in the IN FIFO */
mbed_official	133:d4dda5c437f0	1838	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	1839	headeraddr+=4;
mbed_official	133:d4dda5c437f0	1840	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	1841	headeraddr+=4;
mbed_official	133:d4dda5c437f0	1842	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	1843	headeraddr+=4;
mbed_official	133:d4dda5c437f0	1844	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	1845	headeraddr+=4;
mbed_official	133:d4dda5c437f0	1846	}
mbed_official	133:d4dda5c437f0	1847
mbed_official	133:d4dda5c437f0	1848	/* Get timeout */
mbed_official	133:d4dda5c437f0	1849	timeout = HAL_GetTick() + 1;
mbed_official	133:d4dda5c437f0	1850
mbed_official	133:d4dda5c437f0	1851	while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
mbed_official	133:d4dda5c437f0	1852	{
mbed_official	133:d4dda5c437f0	1853	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	1854	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	1855	{
mbed_official	133:d4dda5c437f0	1856	/* Change state */
mbed_official	133:d4dda5c437f0	1857	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	1858
mbed_official	133:d4dda5c437f0	1859	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	1860	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	1861
mbed_official	133:d4dda5c437f0	1862	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	1863	}
mbed_official	133:d4dda5c437f0	1864	}
mbed_official	133:d4dda5c437f0	1865	}
mbed_official	133:d4dda5c437f0	1866	/* Save formatted counter into the scratch buffer pScratch */
mbed_official	133:d4dda5c437f0	1867	for(loopcounter = 0; (loopcounter < 16); loopcounter++)
mbed_official	133:d4dda5c437f0	1868	{
mbed_official	133:d4dda5c437f0	1869	hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
mbed_official	133:d4dda5c437f0	1870	}
mbed_official	133:d4dda5c437f0	1871	/* Reset bit 0 */
mbed_official	133:d4dda5c437f0	1872	hcryp->Init.pScratch[15] &= 0xfe;
mbed_official	133:d4dda5c437f0	1873	/* Select payload phase once the header phase is performed */
mbed_official	133:d4dda5c437f0	1874	__HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official	133:d4dda5c437f0	1875
mbed_official	133:d4dda5c437f0	1876	/* Flush FIFO */
mbed_official	133:d4dda5c437f0	1877	__HAL_CRYP_FIFO_FLUSH();
mbed_official	133:d4dda5c437f0	1878
mbed_official	133:d4dda5c437f0	1879	/* Set the phase */
mbed_official	133:d4dda5c437f0	1880	hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official	133:d4dda5c437f0	1881	}
mbed_official	133:d4dda5c437f0	1882
mbed_official	133:d4dda5c437f0	1883	/* Enable Interrupts */
mbed_official	133:d4dda5c437f0	1884	__HAL_CRYP_ENABLE_IT(CRYP_IT_INI \| CRYP_IT_OUTI);
mbed_official	133:d4dda5c437f0	1885
mbed_official	133:d4dda5c437f0	1886	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	1887	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	1888
mbed_official	133:d4dda5c437f0	1889	/* Return function status */
mbed_official	133:d4dda5c437f0	1890	return HAL_OK;
mbed_official	133:d4dda5c437f0	1891	}
mbed_official	133:d4dda5c437f0	1892	else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
mbed_official	133:d4dda5c437f0	1893	{
mbed_official	133:d4dda5c437f0	1894	inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
mbed_official	133:d4dda5c437f0	1895	/* Write the Input block in the IN FIFO */
mbed_official	133:d4dda5c437f0	1896	CRYP->DR = (uint32_t)(inputaddr);
mbed_official	133:d4dda5c437f0	1897	inputaddr+=4;
mbed_official	133:d4dda5c437f0	1898	CRYP->DR = (uint32_t)(inputaddr);
mbed_official	133:d4dda5c437f0	1899	inputaddr+=4;
mbed_official	133:d4dda5c437f0	1900	CRYP->DR = (uint32_t)(inputaddr);
mbed_official	133:d4dda5c437f0	1901	inputaddr+=4;
mbed_official	133:d4dda5c437f0	1902	CRYP->DR = (uint32_t)(inputaddr);
mbed_official	133:d4dda5c437f0	1903	hcryp->pCrypInBuffPtr += 16;
mbed_official	133:d4dda5c437f0	1904	hcryp->CrypInCount -= 16;
mbed_official	133:d4dda5c437f0	1905	if(hcryp->CrypInCount == 0)
mbed_official	133:d4dda5c437f0	1906	{
mbed_official	133:d4dda5c437f0	1907	__HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
mbed_official	133:d4dda5c437f0	1908	/* Call the Input data transfer complete callback */
mbed_official	133:d4dda5c437f0	1909	HAL_CRYP_InCpltCallback(hcryp);
mbed_official	133:d4dda5c437f0	1910	}
mbed_official	133:d4dda5c437f0	1911	}
mbed_official	133:d4dda5c437f0	1912	else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
mbed_official	133:d4dda5c437f0	1913	{
mbed_official	133:d4dda5c437f0	1914	outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
mbed_official	133:d4dda5c437f0	1915	/* Read the Output block from the Output FIFO */
mbed_official	133:d4dda5c437f0	1916	(uint32_t)(outputaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	1917	outputaddr+=4;
mbed_official	133:d4dda5c437f0	1918	(uint32_t)(outputaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	1919	outputaddr+=4;
mbed_official	133:d4dda5c437f0	1920	(uint32_t)(outputaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	1921	outputaddr+=4;
mbed_official	133:d4dda5c437f0	1922	(uint32_t)(outputaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	1923	hcryp->pCrypOutBuffPtr += 16;
mbed_official	133:d4dda5c437f0	1924	hcryp->CrypOutCount -= 16;
mbed_official	133:d4dda5c437f0	1925	if(hcryp->CrypOutCount == 0)
mbed_official	133:d4dda5c437f0	1926	{
mbed_official	133:d4dda5c437f0	1927	__HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
mbed_official	133:d4dda5c437f0	1928	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	1929	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	1930	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	1931	hcryp->State = HAL_CRYP_STATE_READY;
mbed_official	133:d4dda5c437f0	1932	/* Call Input transfer complete callback */
mbed_official	133:d4dda5c437f0	1933	HAL_CRYP_OutCpltCallback(hcryp);
mbed_official	133:d4dda5c437f0	1934	}
mbed_official	133:d4dda5c437f0	1935	}
mbed_official	133:d4dda5c437f0	1936
mbed_official	133:d4dda5c437f0	1937	/* Return function status */
mbed_official	133:d4dda5c437f0	1938	return HAL_OK;
mbed_official	133:d4dda5c437f0	1939	}
mbed_official	133:d4dda5c437f0	1940
mbed_official	133:d4dda5c437f0	1941	/**
mbed_official	133:d4dda5c437f0	1942	* @brief Initializes the CRYP peripheral in AES GCM encryption mode using DMA.
mbed_official	242:7074e42da0b2	1943	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
mbed_official	242:7074e42da0b2	1944	* the configuration information for CRYP module
mbed_official	133:d4dda5c437f0	1945	* @param pPlainData: Pointer to the plaintext buffer
mbed_official	133:d4dda5c437f0	1946	* @param Size: Length of the plaintext buffer, must be a multiple of 16
mbed_official	133:d4dda5c437f0	1947	* @param pCypherData: Pointer to the cyphertext buffer
mbed_official	133:d4dda5c437f0	1948	* @retval HAL status
mbed_official	133:d4dda5c437f0	1949	*/
mbed_official	133:d4dda5c437f0	1950	HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef hcryp, uint8_t pPlainData, uint16_t Size, uint8_t *pCypherData)
mbed_official	133:d4dda5c437f0	1951	{
mbed_official	133:d4dda5c437f0	1952	uint32_t timeout = 0;
mbed_official	133:d4dda5c437f0	1953	uint32_t inputaddr;
mbed_official	133:d4dda5c437f0	1954	uint32_t outputaddr;
mbed_official	133:d4dda5c437f0	1955
mbed_official	133:d4dda5c437f0	1956	if((hcryp->State == HAL_CRYP_STATE_READY) \|\| (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
mbed_official	133:d4dda5c437f0	1957	{
mbed_official	133:d4dda5c437f0	1958	/* Process Locked */
mbed_official	133:d4dda5c437f0	1959	__HAL_LOCK(hcryp);
mbed_official	133:d4dda5c437f0	1960
mbed_official	133:d4dda5c437f0	1961	inputaddr = (uint32_t)pPlainData;
mbed_official	133:d4dda5c437f0	1962	outputaddr = (uint32_t)pCypherData;
mbed_official	133:d4dda5c437f0	1963
mbed_official	133:d4dda5c437f0	1964	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	1965	hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official	133:d4dda5c437f0	1966
mbed_official	133:d4dda5c437f0	1967	/* Check if initialization phase has already been performed */
mbed_official	133:d4dda5c437f0	1968	if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official	133:d4dda5c437f0	1969	{
mbed_official	133:d4dda5c437f0	1970	/* Set the key */
mbed_official	133:d4dda5c437f0	1971	CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official	133:d4dda5c437f0	1972
mbed_official	133:d4dda5c437f0	1973	/* Set the CRYP peripheral in AES GCM mode */
mbed_official	133:d4dda5c437f0	1974	__HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
mbed_official	133:d4dda5c437f0	1975
mbed_official	133:d4dda5c437f0	1976	/* Set the Initialization Vector */
mbed_official	133:d4dda5c437f0	1977	CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
mbed_official	133:d4dda5c437f0	1978
mbed_official	133:d4dda5c437f0	1979	/* Flush FIFO */
mbed_official	133:d4dda5c437f0	1980	__HAL_CRYP_FIFO_FLUSH();
mbed_official	133:d4dda5c437f0	1981
mbed_official	133:d4dda5c437f0	1982	/* Enable CRYP to start the init phase */
mbed_official	133:d4dda5c437f0	1983	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	1984
mbed_official	133:d4dda5c437f0	1985	/* Get timeout */
mbed_official	133:d4dda5c437f0	1986	timeout = HAL_GetTick() + 1;
mbed_official	133:d4dda5c437f0	1987
mbed_official	133:d4dda5c437f0	1988	while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official	133:d4dda5c437f0	1989	{
mbed_official	133:d4dda5c437f0	1990	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	1991	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	1992	{
mbed_official	133:d4dda5c437f0	1993	/* Change state */
mbed_official	133:d4dda5c437f0	1994	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	1995
mbed_official	133:d4dda5c437f0	1996	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	1997	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	1998
mbed_official	133:d4dda5c437f0	1999	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	2000	}
mbed_official	133:d4dda5c437f0	2001	}
mbed_official	133:d4dda5c437f0	2002	/* Flush FIFO */
mbed_official	133:d4dda5c437f0	2003	__HAL_CRYP_FIFO_FLUSH();
mbed_official	133:d4dda5c437f0	2004
mbed_official	133:d4dda5c437f0	2005	/* Set the header phase */
mbed_official	133:d4dda5c437f0	2006	if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
mbed_official	133:d4dda5c437f0	2007	{
mbed_official	133:d4dda5c437f0	2008	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	2009	}
mbed_official	133:d4dda5c437f0	2010	/* Disable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	2011	__HAL_CRYP_DISABLE();
mbed_official	133:d4dda5c437f0	2012
mbed_official	133:d4dda5c437f0	2013	/* Select payload phase once the header phase is performed */
mbed_official	133:d4dda5c437f0	2014	__HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official	133:d4dda5c437f0	2015
mbed_official	133:d4dda5c437f0	2016	/* Flush FIFO */
mbed_official	133:d4dda5c437f0	2017	__HAL_CRYP_FIFO_FLUSH();
mbed_official	133:d4dda5c437f0	2018
mbed_official	133:d4dda5c437f0	2019	/* Set the phase */
mbed_official	133:d4dda5c437f0	2020	hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official	133:d4dda5c437f0	2021	}
mbed_official	133:d4dda5c437f0	2022
mbed_official	133:d4dda5c437f0	2023	/* Set the input and output addresses and start DMA transfer */
mbed_official	133:d4dda5c437f0	2024	CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
mbed_official	133:d4dda5c437f0	2025
mbed_official	133:d4dda5c437f0	2026	/* Unlock process */
mbed_official	133:d4dda5c437f0	2027	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	2028
mbed_official	133:d4dda5c437f0	2029	/* Return function status */
mbed_official	133:d4dda5c437f0	2030	return HAL_OK;
mbed_official	133:d4dda5c437f0	2031	}
mbed_official	133:d4dda5c437f0	2032	else
mbed_official	133:d4dda5c437f0	2033	{
mbed_official	133:d4dda5c437f0	2034	return HAL_ERROR;
mbed_official	133:d4dda5c437f0	2035	}
mbed_official	133:d4dda5c437f0	2036	}
mbed_official	133:d4dda5c437f0	2037
mbed_official	133:d4dda5c437f0	2038	/**
mbed_official	133:d4dda5c437f0	2039	* @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.
mbed_official	242:7074e42da0b2	2040	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
mbed_official	242:7074e42da0b2	2041	* the configuration information for CRYP module
mbed_official	133:d4dda5c437f0	2042	* @param pPlainData: Pointer to the plaintext buffer
mbed_official	133:d4dda5c437f0	2043	* @param Size: Length of the plaintext buffer, must be a multiple of 16
mbed_official	133:d4dda5c437f0	2044	* @param pCypherData: Pointer to the cyphertext buffer
mbed_official	133:d4dda5c437f0	2045	* @retval HAL status
mbed_official	133:d4dda5c437f0	2046	*/
mbed_official	133:d4dda5c437f0	2047	HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef hcryp, uint8_t pPlainData, uint16_t Size, uint8_t *pCypherData)
mbed_official	133:d4dda5c437f0	2048	{
mbed_official	133:d4dda5c437f0	2049	uint32_t timeout = 0;
mbed_official	133:d4dda5c437f0	2050	uint32_t inputaddr;
mbed_official	133:d4dda5c437f0	2051	uint32_t outputaddr;
mbed_official	133:d4dda5c437f0	2052	uint32_t headersize;
mbed_official	133:d4dda5c437f0	2053	uint32_t headeraddr;
mbed_official	133:d4dda5c437f0	2054	uint32_t loopcounter = 0;
mbed_official	133:d4dda5c437f0	2055	uint32_t bufferidx = 0;
mbed_official	133:d4dda5c437f0	2056	uint8_t blockb0[16] = {0};/* Block B0 */
mbed_official	133:d4dda5c437f0	2057	uint8_t ctr[16] = {0}; /* Counter */
mbed_official	133:d4dda5c437f0	2058	uint32_t b0addr = (uint32_t)blockb0;
mbed_official	133:d4dda5c437f0	2059
mbed_official	133:d4dda5c437f0	2060	if((hcryp->State == HAL_CRYP_STATE_READY) \|\| (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
mbed_official	133:d4dda5c437f0	2061	{
mbed_official	133:d4dda5c437f0	2062	/* Process Locked */
mbed_official	133:d4dda5c437f0	2063	__HAL_LOCK(hcryp);
mbed_official	133:d4dda5c437f0	2064
mbed_official	133:d4dda5c437f0	2065	inputaddr = (uint32_t)pPlainData;
mbed_official	133:d4dda5c437f0	2066	outputaddr = (uint32_t)pCypherData;
mbed_official	133:d4dda5c437f0	2067
mbed_official	133:d4dda5c437f0	2068	headersize = hcryp->Init.HeaderSize;
mbed_official	133:d4dda5c437f0	2069	headeraddr = (uint32_t)hcryp->Init.Header;
mbed_official	133:d4dda5c437f0	2070
mbed_official	133:d4dda5c437f0	2071	hcryp->CrypInCount = Size;
mbed_official	133:d4dda5c437f0	2072	hcryp->pCrypInBuffPtr = pPlainData;
mbed_official	133:d4dda5c437f0	2073	hcryp->pCrypOutBuffPtr = pCypherData;
mbed_official	133:d4dda5c437f0	2074	hcryp->CrypOutCount = Size;
mbed_official	133:d4dda5c437f0	2075
mbed_official	133:d4dda5c437f0	2076	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	2077	hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official	133:d4dda5c437f0	2078
mbed_official	133:d4dda5c437f0	2079	/* Check if initialization phase has already been performed */
mbed_official	133:d4dda5c437f0	2080	if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official	133:d4dda5c437f0	2081	{
mbed_official	133:d4dda5c437f0	2082	/********************** Formatting the header block *****************/
mbed_official	133:d4dda5c437f0	2083	if(headersize != 0)
mbed_official	133:d4dda5c437f0	2084	{
mbed_official	133:d4dda5c437f0	2085	/* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
mbed_official	133:d4dda5c437f0	2086	if(headersize < 65280)
mbed_official	133:d4dda5c437f0	2087	{
mbed_official	133:d4dda5c437f0	2088	hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
mbed_official	133:d4dda5c437f0	2089	hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
mbed_official	133:d4dda5c437f0	2090	headersize += 2;
mbed_official	133:d4dda5c437f0	2091	}
mbed_official	133:d4dda5c437f0	2092	else
mbed_official	133:d4dda5c437f0	2093	{
mbed_official	133:d4dda5c437f0	2094	/* Header is encoded as 0xff \|\| 0xfe \|\| [headersize]32, i.e., six octets */
mbed_official	133:d4dda5c437f0	2095	hcryp->Init.pScratch[bufferidx++] = 0xFF;
mbed_official	133:d4dda5c437f0	2096	hcryp->Init.pScratch[bufferidx++] = 0xFE;
mbed_official	133:d4dda5c437f0	2097	hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
mbed_official	133:d4dda5c437f0	2098	hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
mbed_official	133:d4dda5c437f0	2099	hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
mbed_official	133:d4dda5c437f0	2100	hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
mbed_official	133:d4dda5c437f0	2101	headersize += 6;
mbed_official	133:d4dda5c437f0	2102	}
mbed_official	133:d4dda5c437f0	2103	/* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
mbed_official	133:d4dda5c437f0	2104	for(loopcounter = 0; loopcounter < headersize; loopcounter++)
mbed_official	133:d4dda5c437f0	2105	{
mbed_official	133:d4dda5c437f0	2106	hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
mbed_official	133:d4dda5c437f0	2107	}
mbed_official	133:d4dda5c437f0	2108	/* Check if the header size is modulo 16 */
mbed_official	133:d4dda5c437f0	2109	if ((headersize % 16) != 0)
mbed_official	133:d4dda5c437f0	2110	{
mbed_official	133:d4dda5c437f0	2111	/* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
mbed_official	133:d4dda5c437f0	2112	for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
mbed_official	133:d4dda5c437f0	2113	{
mbed_official	133:d4dda5c437f0	2114	hcryp->Init.pScratch[loopcounter] = 0;
mbed_official	133:d4dda5c437f0	2115	}
mbed_official	133:d4dda5c437f0	2116	/* Set the header size to modulo 16 */
mbed_official	133:d4dda5c437f0	2117	headersize = ((headersize/16) + 1) * 16;
mbed_official	133:d4dda5c437f0	2118	}
mbed_official	133:d4dda5c437f0	2119	/* Set the pointer headeraddr to hcryp->Init.pScratch */
mbed_official	133:d4dda5c437f0	2120	headeraddr = (uint32_t)hcryp->Init.pScratch;
mbed_official	133:d4dda5c437f0	2121	}
mbed_official	133:d4dda5c437f0	2122	/********************* Formatting the block B0 **********************/
mbed_official	133:d4dda5c437f0	2123	if(headersize != 0)
mbed_official	133:d4dda5c437f0	2124	{
mbed_official	133:d4dda5c437f0	2125	blockb0[0] = 0x40;
mbed_official	133:d4dda5c437f0	2126	}
mbed_official	133:d4dda5c437f0	2127	/* Flags byte */
mbed_official	133:d4dda5c437f0	2128	/* blockb0[0] \|= 0u \| (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) \| ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
mbed_official	133:d4dda5c437f0	2129	blockb0[0] \|= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
mbed_official	133:d4dda5c437f0	2130	blockb0[0] \|= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
mbed_official	133:d4dda5c437f0	2131
mbed_official	133:d4dda5c437f0	2132	for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
mbed_official	133:d4dda5c437f0	2133	{
mbed_official	133:d4dda5c437f0	2134	blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
mbed_official	133:d4dda5c437f0	2135	}
mbed_official	133:d4dda5c437f0	2136	for ( ; loopcounter < 13; loopcounter++)
mbed_official	133:d4dda5c437f0	2137	{
mbed_official	133:d4dda5c437f0	2138	blockb0[loopcounter+1] = 0;
mbed_official	133:d4dda5c437f0	2139	}
mbed_official	133:d4dda5c437f0	2140
mbed_official	133:d4dda5c437f0	2141	blockb0[14] = (Size >> 8);
mbed_official	133:d4dda5c437f0	2142	blockb0[15] = (Size & 0xFF);
mbed_official	133:d4dda5c437f0	2143
mbed_official	133:d4dda5c437f0	2144	/*********************** Formatting the initial counter *************/
mbed_official	133:d4dda5c437f0	2145	/* Byte 0:
mbed_official	133:d4dda5c437f0	2146	Bits 7 and 6 are reserved and shall be set to 0
mbed_official	133:d4dda5c437f0	2147	Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
mbed_official	133:d4dda5c437f0	2148	blocks are distinct from B0
mbed_official	133:d4dda5c437f0	2149	Bits 0, 1, and 2 contain the same encoding of q as in B0
mbed_official	133:d4dda5c437f0	2150	*/
mbed_official	133:d4dda5c437f0	2151	ctr[0] = blockb0[0] & 0x07;
mbed_official	133:d4dda5c437f0	2152	/* byte 1 to NonceSize is the IV (Nonce) */
mbed_official	133:d4dda5c437f0	2153	for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
mbed_official	133:d4dda5c437f0	2154	{
mbed_official	133:d4dda5c437f0	2155	ctr[loopcounter] = blockb0[loopcounter];
mbed_official	133:d4dda5c437f0	2156	}
mbed_official	133:d4dda5c437f0	2157	/* Set the LSB to 1 */
mbed_official	133:d4dda5c437f0	2158	ctr[15] \|= 0x01;
mbed_official	133:d4dda5c437f0	2159
mbed_official	133:d4dda5c437f0	2160	/* Set the key */
mbed_official	133:d4dda5c437f0	2161	CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official	133:d4dda5c437f0	2162
mbed_official	133:d4dda5c437f0	2163	/* Set the CRYP peripheral in AES CCM mode */
mbed_official	133:d4dda5c437f0	2164	__HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
mbed_official	133:d4dda5c437f0	2165
mbed_official	133:d4dda5c437f0	2166	/* Set the Initialization Vector */
mbed_official	133:d4dda5c437f0	2167	CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, CRYP_KEYSIZE_128B);
mbed_official	133:d4dda5c437f0	2168
mbed_official	133:d4dda5c437f0	2169	/* Select init phase */
mbed_official	133:d4dda5c437f0	2170	__HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
mbed_official	133:d4dda5c437f0	2171
mbed_official	133:d4dda5c437f0	2172	b0addr = (uint32_t)blockb0;
mbed_official	133:d4dda5c437f0	2173	/* Write the blockb0 block in the IN FIFO */
mbed_official	133:d4dda5c437f0	2174	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	2175	b0addr+=4;
mbed_official	133:d4dda5c437f0	2176	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	2177	b0addr+=4;
mbed_official	133:d4dda5c437f0	2178	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	2179	b0addr+=4;
mbed_official	133:d4dda5c437f0	2180	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	2181
mbed_official	133:d4dda5c437f0	2182	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	2183	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	2184
mbed_official	133:d4dda5c437f0	2185	/* Get timeout */
mbed_official	133:d4dda5c437f0	2186	timeout = HAL_GetTick() + 1;
mbed_official	133:d4dda5c437f0	2187
mbed_official	133:d4dda5c437f0	2188	while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official	133:d4dda5c437f0	2189	{
mbed_official	133:d4dda5c437f0	2190	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	2191	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	2192	{
mbed_official	133:d4dda5c437f0	2193	/* Change state */
mbed_official	133:d4dda5c437f0	2194	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	2195
mbed_official	133:d4dda5c437f0	2196	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	2197	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	2198
mbed_official	133:d4dda5c437f0	2199	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	2200	}
mbed_official	133:d4dda5c437f0	2201	}
mbed_official	133:d4dda5c437f0	2202	/*************************** Header phase ***************************/
mbed_official	133:d4dda5c437f0	2203	if(headersize != 0)
mbed_official	133:d4dda5c437f0	2204	{
mbed_official	133:d4dda5c437f0	2205	/* Select header phase */
mbed_official	133:d4dda5c437f0	2206	__HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
mbed_official	133:d4dda5c437f0	2207
mbed_official	133:d4dda5c437f0	2208	/* Enable Crypto processor */
mbed_official	133:d4dda5c437f0	2209	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	2210
mbed_official	133:d4dda5c437f0	2211	for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
mbed_official	133:d4dda5c437f0	2212	{
mbed_official	133:d4dda5c437f0	2213	/* Get timeout */
mbed_official	133:d4dda5c437f0	2214	timeout = HAL_GetTick() + 1;
mbed_official	133:d4dda5c437f0	2215
mbed_official	133:d4dda5c437f0	2216	while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
mbed_official	133:d4dda5c437f0	2217	{
mbed_official	133:d4dda5c437f0	2218	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	2219	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	2220	{
mbed_official	133:d4dda5c437f0	2221	/* Change state */
mbed_official	133:d4dda5c437f0	2222	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	2223
mbed_official	133:d4dda5c437f0	2224	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	2225	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	2226
mbed_official	133:d4dda5c437f0	2227	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	2228	}
mbed_official	133:d4dda5c437f0	2229	}
mbed_official	133:d4dda5c437f0	2230	/* Write the header block in the IN FIFO */
mbed_official	133:d4dda5c437f0	2231	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	2232	headeraddr+=4;
mbed_official	133:d4dda5c437f0	2233	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	2234	headeraddr+=4;
mbed_official	133:d4dda5c437f0	2235	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	2236	headeraddr+=4;
mbed_official	133:d4dda5c437f0	2237	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	2238	headeraddr+=4;
mbed_official	133:d4dda5c437f0	2239	}
mbed_official	133:d4dda5c437f0	2240
mbed_official	133:d4dda5c437f0	2241	/* Get timeout */
mbed_official	133:d4dda5c437f0	2242	timeout = HAL_GetTick() + 1;
mbed_official	133:d4dda5c437f0	2243
mbed_official	133:d4dda5c437f0	2244	while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
mbed_official	133:d4dda5c437f0	2245	{
mbed_official	133:d4dda5c437f0	2246	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	2247	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	2248	{
mbed_official	133:d4dda5c437f0	2249	/* Change state */
mbed_official	133:d4dda5c437f0	2250	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	2251
mbed_official	133:d4dda5c437f0	2252	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	2253	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	2254
mbed_official	133:d4dda5c437f0	2255	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	2256	}
mbed_official	133:d4dda5c437f0	2257	}
mbed_official	133:d4dda5c437f0	2258	}
mbed_official	133:d4dda5c437f0	2259	/* Save formatted counter into the scratch buffer pScratch */
mbed_official	133:d4dda5c437f0	2260	for(loopcounter = 0; (loopcounter < 16); loopcounter++)
mbed_official	133:d4dda5c437f0	2261	{
mbed_official	133:d4dda5c437f0	2262	hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
mbed_official	133:d4dda5c437f0	2263	}
mbed_official	133:d4dda5c437f0	2264	/* Reset bit 0 */
mbed_official	133:d4dda5c437f0	2265	hcryp->Init.pScratch[15] &= 0xfe;
mbed_official	133:d4dda5c437f0	2266
mbed_official	133:d4dda5c437f0	2267	/* Select payload phase once the header phase is performed */
mbed_official	133:d4dda5c437f0	2268	__HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official	133:d4dda5c437f0	2269
mbed_official	133:d4dda5c437f0	2270	/* Flush FIFO */
mbed_official	133:d4dda5c437f0	2271	__HAL_CRYP_FIFO_FLUSH();
mbed_official	133:d4dda5c437f0	2272
mbed_official	133:d4dda5c437f0	2273	/* Set the phase */
mbed_official	133:d4dda5c437f0	2274	hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official	133:d4dda5c437f0	2275	}
mbed_official	133:d4dda5c437f0	2276
mbed_official	133:d4dda5c437f0	2277	/* Set the input and output addresses and start DMA transfer */
mbed_official	133:d4dda5c437f0	2278	CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
mbed_official	133:d4dda5c437f0	2279
mbed_official	133:d4dda5c437f0	2280	/* Unlock process */
mbed_official	133:d4dda5c437f0	2281	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	2282
mbed_official	133:d4dda5c437f0	2283	/* Return function status */
mbed_official	133:d4dda5c437f0	2284	return HAL_OK;
mbed_official	133:d4dda5c437f0	2285	}
mbed_official	133:d4dda5c437f0	2286	else
mbed_official	133:d4dda5c437f0	2287	{
mbed_official	133:d4dda5c437f0	2288	return HAL_ERROR;
mbed_official	133:d4dda5c437f0	2289	}
mbed_official	133:d4dda5c437f0	2290	}
mbed_official	133:d4dda5c437f0	2291
mbed_official	133:d4dda5c437f0	2292	/**
mbed_official	133:d4dda5c437f0	2293	* @brief Initializes the CRYP peripheral in AES GCM decryption mode using DMA.
mbed_official	242:7074e42da0b2	2294	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
mbed_official	242:7074e42da0b2	2295	* the configuration information for CRYP module
mbed_official	133:d4dda5c437f0	2296	* @param pCypherData: Pointer to the cyphertext buffer.
mbed_official	133:d4dda5c437f0	2297	* @param Size: Length of the cyphertext buffer, must be a multiple of 16
mbed_official	133:d4dda5c437f0	2298	* @param pPlainData: Pointer to the plaintext buffer
mbed_official	133:d4dda5c437f0	2299	* @retval HAL status
mbed_official	133:d4dda5c437f0	2300	*/
mbed_official	133:d4dda5c437f0	2301	HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef hcryp, uint8_t pCypherData, uint16_t Size, uint8_t *pPlainData)
mbed_official	133:d4dda5c437f0	2302	{
mbed_official	133:d4dda5c437f0	2303	uint32_t timeout = 0;
mbed_official	133:d4dda5c437f0	2304	uint32_t inputaddr;
mbed_official	133:d4dda5c437f0	2305	uint32_t outputaddr;
mbed_official	133:d4dda5c437f0	2306
mbed_official	133:d4dda5c437f0	2307	if((hcryp->State == HAL_CRYP_STATE_READY) \|\| (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
mbed_official	133:d4dda5c437f0	2308	{
mbed_official	133:d4dda5c437f0	2309	/* Process Locked */
mbed_official	133:d4dda5c437f0	2310	__HAL_LOCK(hcryp);
mbed_official	133:d4dda5c437f0	2311
mbed_official	133:d4dda5c437f0	2312	inputaddr = (uint32_t)pCypherData;
mbed_official	133:d4dda5c437f0	2313	outputaddr = (uint32_t)pPlainData;
mbed_official	133:d4dda5c437f0	2314
mbed_official	133:d4dda5c437f0	2315	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	2316	hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official	133:d4dda5c437f0	2317
mbed_official	133:d4dda5c437f0	2318	/* Check if initialization phase has already been performed */
mbed_official	133:d4dda5c437f0	2319	if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official	133:d4dda5c437f0	2320	{
mbed_official	133:d4dda5c437f0	2321	/* Set the key */
mbed_official	133:d4dda5c437f0	2322	CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official	133:d4dda5c437f0	2323
mbed_official	133:d4dda5c437f0	2324	/* Set the CRYP peripheral in AES GCM decryption mode */
mbed_official	133:d4dda5c437f0	2325	__HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
mbed_official	133:d4dda5c437f0	2326
mbed_official	133:d4dda5c437f0	2327	/* Set the Initialization Vector */
mbed_official	133:d4dda5c437f0	2328	CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
mbed_official	133:d4dda5c437f0	2329
mbed_official	133:d4dda5c437f0	2330	/* Enable CRYP to start the init phase */
mbed_official	133:d4dda5c437f0	2331	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	2332
mbed_official	133:d4dda5c437f0	2333	/* Get timeout */
mbed_official	133:d4dda5c437f0	2334	timeout = HAL_GetTick() + 1;
mbed_official	133:d4dda5c437f0	2335
mbed_official	133:d4dda5c437f0	2336	while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official	133:d4dda5c437f0	2337	{
mbed_official	133:d4dda5c437f0	2338	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	2339	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	2340	{
mbed_official	133:d4dda5c437f0	2341	/* Change state */
mbed_official	133:d4dda5c437f0	2342	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	2343
mbed_official	133:d4dda5c437f0	2344	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	2345	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	2346
mbed_official	133:d4dda5c437f0	2347	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	2348	}
mbed_official	133:d4dda5c437f0	2349	}
mbed_official	133:d4dda5c437f0	2350
mbed_official	133:d4dda5c437f0	2351	/* Set the header phase */
mbed_official	133:d4dda5c437f0	2352	if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
mbed_official	133:d4dda5c437f0	2353	{
mbed_official	133:d4dda5c437f0	2354	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	2355	}
mbed_official	133:d4dda5c437f0	2356	/* Disable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	2357	__HAL_CRYP_DISABLE();
mbed_official	133:d4dda5c437f0	2358
mbed_official	133:d4dda5c437f0	2359	/* Select payload phase once the header phase is performed */
mbed_official	133:d4dda5c437f0	2360	__HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official	133:d4dda5c437f0	2361
mbed_official	133:d4dda5c437f0	2362	/* Set the phase */
mbed_official	133:d4dda5c437f0	2363	hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official	133:d4dda5c437f0	2364	}
mbed_official	133:d4dda5c437f0	2365
mbed_official	133:d4dda5c437f0	2366	/* Set the input and output addresses and start DMA transfer */
mbed_official	133:d4dda5c437f0	2367	CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
mbed_official	133:d4dda5c437f0	2368
mbed_official	133:d4dda5c437f0	2369	/* Unlock process */
mbed_official	133:d4dda5c437f0	2370	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	2371
mbed_official	133:d4dda5c437f0	2372	/* Return function status */
mbed_official	133:d4dda5c437f0	2373	return HAL_OK;
mbed_official	133:d4dda5c437f0	2374	}
mbed_official	133:d4dda5c437f0	2375	else
mbed_official	133:d4dda5c437f0	2376	{
mbed_official	133:d4dda5c437f0	2377	return HAL_ERROR;
mbed_official	133:d4dda5c437f0	2378	}
mbed_official	133:d4dda5c437f0	2379	}
mbed_official	133:d4dda5c437f0	2380
mbed_official	133:d4dda5c437f0	2381	/**
mbed_official	133:d4dda5c437f0	2382	* @brief Initializes the CRYP peripheral in AES CCM decryption mode using DMA
mbed_official	133:d4dda5c437f0	2383	* then decrypted pCypherData. The cypher data are available in pPlainData.
mbed_official	242:7074e42da0b2	2384	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
mbed_official	242:7074e42da0b2	2385	* the configuration information for CRYP module
mbed_official	133:d4dda5c437f0	2386	* @param pCypherData: Pointer to the cyphertext buffer
mbed_official	133:d4dda5c437f0	2387	* @param Size: Length of the plaintext buffer, must be a multiple of 16
mbed_official	133:d4dda5c437f0	2388	* @param pPlainData: Pointer to the plaintext buffer
mbed_official	133:d4dda5c437f0	2389	* @retval HAL status
mbed_official	133:d4dda5c437f0	2390	*/
mbed_official	133:d4dda5c437f0	2391	HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef hcryp, uint8_t pCypherData, uint16_t Size, uint8_t *pPlainData)
mbed_official	133:d4dda5c437f0	2392	{
mbed_official	133:d4dda5c437f0	2393	uint32_t timeout = 0;
mbed_official	133:d4dda5c437f0	2394	uint32_t inputaddr;
mbed_official	133:d4dda5c437f0	2395	uint32_t outputaddr;
mbed_official	133:d4dda5c437f0	2396	uint32_t headersize;
mbed_official	133:d4dda5c437f0	2397	uint32_t headeraddr;
mbed_official	133:d4dda5c437f0	2398	uint32_t loopcounter = 0;
mbed_official	133:d4dda5c437f0	2399	uint32_t bufferidx = 0;
mbed_official	133:d4dda5c437f0	2400	uint8_t blockb0[16] = {0};/* Block B0 */
mbed_official	133:d4dda5c437f0	2401	uint8_t ctr[16] = {0}; /* Counter */
mbed_official	133:d4dda5c437f0	2402	uint32_t b0addr = (uint32_t)blockb0;
mbed_official	133:d4dda5c437f0	2403
mbed_official	133:d4dda5c437f0	2404	if((hcryp->State == HAL_CRYP_STATE_READY) \|\| (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
mbed_official	133:d4dda5c437f0	2405	{
mbed_official	133:d4dda5c437f0	2406	/* Process Locked */
mbed_official	133:d4dda5c437f0	2407	__HAL_LOCK(hcryp);
mbed_official	133:d4dda5c437f0	2408
mbed_official	133:d4dda5c437f0	2409	inputaddr = (uint32_t)pCypherData;
mbed_official	133:d4dda5c437f0	2410	outputaddr = (uint32_t)pPlainData;
mbed_official	133:d4dda5c437f0	2411
mbed_official	133:d4dda5c437f0	2412	headersize = hcryp->Init.HeaderSize;
mbed_official	133:d4dda5c437f0	2413	headeraddr = (uint32_t)hcryp->Init.Header;
mbed_official	133:d4dda5c437f0	2414
mbed_official	133:d4dda5c437f0	2415	hcryp->CrypInCount = Size;
mbed_official	133:d4dda5c437f0	2416	hcryp->pCrypInBuffPtr = pCypherData;
mbed_official	133:d4dda5c437f0	2417	hcryp->pCrypOutBuffPtr = pPlainData;
mbed_official	133:d4dda5c437f0	2418	hcryp->CrypOutCount = Size;
mbed_official	133:d4dda5c437f0	2419
mbed_official	133:d4dda5c437f0	2420	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	2421	hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official	133:d4dda5c437f0	2422
mbed_official	133:d4dda5c437f0	2423	/* Check if initialization phase has already been performed */
mbed_official	133:d4dda5c437f0	2424	if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official	133:d4dda5c437f0	2425	{
mbed_official	133:d4dda5c437f0	2426	/********************** Formatting the header block *****************/
mbed_official	133:d4dda5c437f0	2427	if(headersize != 0)
mbed_official	133:d4dda5c437f0	2428	{
mbed_official	133:d4dda5c437f0	2429	/* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
mbed_official	133:d4dda5c437f0	2430	if(headersize < 65280)
mbed_official	133:d4dda5c437f0	2431	{
mbed_official	133:d4dda5c437f0	2432	hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
mbed_official	133:d4dda5c437f0	2433	hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
mbed_official	133:d4dda5c437f0	2434	headersize += 2;
mbed_official	133:d4dda5c437f0	2435	}
mbed_official	133:d4dda5c437f0	2436	else
mbed_official	133:d4dda5c437f0	2437	{
mbed_official	133:d4dda5c437f0	2438	/* Header is encoded as 0xff \|\| 0xfe \|\| [headersize]32, i.e., six octets */
mbed_official	133:d4dda5c437f0	2439	hcryp->Init.pScratch[bufferidx++] = 0xFF;
mbed_official	133:d4dda5c437f0	2440	hcryp->Init.pScratch[bufferidx++] = 0xFE;
mbed_official	133:d4dda5c437f0	2441	hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
mbed_official	133:d4dda5c437f0	2442	hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
mbed_official	133:d4dda5c437f0	2443	hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
mbed_official	133:d4dda5c437f0	2444	hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
mbed_official	133:d4dda5c437f0	2445	headersize += 6;
mbed_official	133:d4dda5c437f0	2446	}
mbed_official	133:d4dda5c437f0	2447	/* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
mbed_official	133:d4dda5c437f0	2448	for(loopcounter = 0; loopcounter < headersize; loopcounter++)
mbed_official	133:d4dda5c437f0	2449	{
mbed_official	133:d4dda5c437f0	2450	hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
mbed_official	133:d4dda5c437f0	2451	}
mbed_official	133:d4dda5c437f0	2452	/* Check if the header size is modulo 16 */
mbed_official	133:d4dda5c437f0	2453	if ((headersize % 16) != 0)
mbed_official	133:d4dda5c437f0	2454	{
mbed_official	133:d4dda5c437f0	2455	/* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
mbed_official	133:d4dda5c437f0	2456	for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
mbed_official	133:d4dda5c437f0	2457	{
mbed_official	133:d4dda5c437f0	2458	hcryp->Init.pScratch[loopcounter] = 0;
mbed_official	133:d4dda5c437f0	2459	}
mbed_official	133:d4dda5c437f0	2460	/* Set the header size to modulo 16 */
mbed_official	133:d4dda5c437f0	2461	headersize = ((headersize/16) + 1) * 16;
mbed_official	133:d4dda5c437f0	2462	}
mbed_official	133:d4dda5c437f0	2463	/* Set the pointer headeraddr to hcryp->Init.pScratch */
mbed_official	133:d4dda5c437f0	2464	headeraddr = (uint32_t)hcryp->Init.pScratch;
mbed_official	133:d4dda5c437f0	2465	}
mbed_official	133:d4dda5c437f0	2466	/********************* Formatting the block B0 **********************/
mbed_official	133:d4dda5c437f0	2467	if(headersize != 0)
mbed_official	133:d4dda5c437f0	2468	{
mbed_official	133:d4dda5c437f0	2469	blockb0[0] = 0x40;
mbed_official	133:d4dda5c437f0	2470	}
mbed_official	133:d4dda5c437f0	2471	/* Flags byte */
mbed_official	133:d4dda5c437f0	2472	/* blockb0[0] \|= 0u \| (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) \| ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
mbed_official	133:d4dda5c437f0	2473	blockb0[0] \|= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
mbed_official	133:d4dda5c437f0	2474	blockb0[0] \|= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
mbed_official	133:d4dda5c437f0	2475
mbed_official	133:d4dda5c437f0	2476	for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
mbed_official	133:d4dda5c437f0	2477	{
mbed_official	133:d4dda5c437f0	2478	blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
mbed_official	133:d4dda5c437f0	2479	}
mbed_official	133:d4dda5c437f0	2480	for ( ; loopcounter < 13; loopcounter++)
mbed_official	133:d4dda5c437f0	2481	{
mbed_official	133:d4dda5c437f0	2482	blockb0[loopcounter+1] = 0;
mbed_official	133:d4dda5c437f0	2483	}
mbed_official	133:d4dda5c437f0	2484
mbed_official	133:d4dda5c437f0	2485	blockb0[14] = (Size >> 8);
mbed_official	133:d4dda5c437f0	2486	blockb0[15] = (Size & 0xFF);
mbed_official	133:d4dda5c437f0	2487
mbed_official	133:d4dda5c437f0	2488	/*********************** Formatting the initial counter *************/
mbed_official	133:d4dda5c437f0	2489	/* Byte 0:
mbed_official	133:d4dda5c437f0	2490	Bits 7 and 6 are reserved and shall be set to 0
mbed_official	133:d4dda5c437f0	2491	Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
mbed_official	133:d4dda5c437f0	2492	blocks are distinct from B0
mbed_official	133:d4dda5c437f0	2493	Bits 0, 1, and 2 contain the same encoding of q as in B0
mbed_official	133:d4dda5c437f0	2494	*/
mbed_official	133:d4dda5c437f0	2495	ctr[0] = blockb0[0] & 0x07;
mbed_official	133:d4dda5c437f0	2496	/* byte 1 to NonceSize is the IV (Nonce) */
mbed_official	133:d4dda5c437f0	2497	for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
mbed_official	133:d4dda5c437f0	2498	{
mbed_official	133:d4dda5c437f0	2499	ctr[loopcounter] = blockb0[loopcounter];
mbed_official	133:d4dda5c437f0	2500	}
mbed_official	133:d4dda5c437f0	2501	/* Set the LSB to 1 */
mbed_official	133:d4dda5c437f0	2502	ctr[15] \|= 0x01;
mbed_official	133:d4dda5c437f0	2503
mbed_official	133:d4dda5c437f0	2504	/* Set the key */
mbed_official	133:d4dda5c437f0	2505	CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official	133:d4dda5c437f0	2506
mbed_official	133:d4dda5c437f0	2507	/* Set the CRYP peripheral in AES CCM mode */
mbed_official	133:d4dda5c437f0	2508	__HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
mbed_official	133:d4dda5c437f0	2509
mbed_official	133:d4dda5c437f0	2510	/* Set the Initialization Vector */
mbed_official	133:d4dda5c437f0	2511	CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, CRYP_KEYSIZE_128B);
mbed_official	133:d4dda5c437f0	2512
mbed_official	133:d4dda5c437f0	2513	/* Select init phase */
mbed_official	133:d4dda5c437f0	2514	__HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
mbed_official	133:d4dda5c437f0	2515
mbed_official	133:d4dda5c437f0	2516	b0addr = (uint32_t)blockb0;
mbed_official	133:d4dda5c437f0	2517	/* Write the blockb0 block in the IN FIFO */
mbed_official	133:d4dda5c437f0	2518	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	2519	b0addr+=4;
mbed_official	133:d4dda5c437f0	2520	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	2521	b0addr+=4;
mbed_official	133:d4dda5c437f0	2522	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	2523	b0addr+=4;
mbed_official	133:d4dda5c437f0	2524	CRYP->DR = (uint32_t)(b0addr);
mbed_official	133:d4dda5c437f0	2525
mbed_official	133:d4dda5c437f0	2526	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	2527	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	2528
mbed_official	133:d4dda5c437f0	2529	/* Get timeout */
mbed_official	133:d4dda5c437f0	2530	timeout = HAL_GetTick() + 1;
mbed_official	133:d4dda5c437f0	2531
mbed_official	133:d4dda5c437f0	2532	while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official	133:d4dda5c437f0	2533	{
mbed_official	133:d4dda5c437f0	2534	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	2535
mbed_official	133:d4dda5c437f0	2536	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	2537	{
mbed_official	133:d4dda5c437f0	2538	/* Change state */
mbed_official	133:d4dda5c437f0	2539	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	2540
mbed_official	133:d4dda5c437f0	2541	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	2542	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	2543
mbed_official	133:d4dda5c437f0	2544	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	2545
mbed_official	133:d4dda5c437f0	2546	}
mbed_official	133:d4dda5c437f0	2547	}
mbed_official	133:d4dda5c437f0	2548	/*************************** Header phase ***************************/
mbed_official	133:d4dda5c437f0	2549	if(headersize != 0)
mbed_official	133:d4dda5c437f0	2550	{
mbed_official	133:d4dda5c437f0	2551	/* Select header phase */
mbed_official	133:d4dda5c437f0	2552	__HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
mbed_official	133:d4dda5c437f0	2553
mbed_official	133:d4dda5c437f0	2554	/* Enable Crypto processor */
mbed_official	133:d4dda5c437f0	2555	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	2556
mbed_official	133:d4dda5c437f0	2557	for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
mbed_official	133:d4dda5c437f0	2558	{
mbed_official	133:d4dda5c437f0	2559	/* Get timeout */
mbed_official	133:d4dda5c437f0	2560	timeout = HAL_GetTick() + 1;
mbed_official	133:d4dda5c437f0	2561
mbed_official	133:d4dda5c437f0	2562	while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
mbed_official	133:d4dda5c437f0	2563	{
mbed_official	133:d4dda5c437f0	2564	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	2565	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	2566	{
mbed_official	133:d4dda5c437f0	2567	/* Change state */
mbed_official	133:d4dda5c437f0	2568	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	2569
mbed_official	133:d4dda5c437f0	2570	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	2571	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	2572
mbed_official	133:d4dda5c437f0	2573	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	2574	}
mbed_official	133:d4dda5c437f0	2575	}
mbed_official	133:d4dda5c437f0	2576	/* Write the header block in the IN FIFO */
mbed_official	133:d4dda5c437f0	2577	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	2578	headeraddr+=4;
mbed_official	133:d4dda5c437f0	2579	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	2580	headeraddr+=4;
mbed_official	133:d4dda5c437f0	2581	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	2582	headeraddr+=4;
mbed_official	133:d4dda5c437f0	2583	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	2584	headeraddr+=4;
mbed_official	133:d4dda5c437f0	2585	}
mbed_official	133:d4dda5c437f0	2586
mbed_official	133:d4dda5c437f0	2587	/* Get timeout */
mbed_official	133:d4dda5c437f0	2588	timeout = HAL_GetTick() + 1;
mbed_official	133:d4dda5c437f0	2589
mbed_official	133:d4dda5c437f0	2590	while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
mbed_official	133:d4dda5c437f0	2591	{
mbed_official	133:d4dda5c437f0	2592	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	2593	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	2594	{
mbed_official	133:d4dda5c437f0	2595	/* Change state */
mbed_official	133:d4dda5c437f0	2596	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	2597
mbed_official	133:d4dda5c437f0	2598	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	2599	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	2600
mbed_official	133:d4dda5c437f0	2601	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	2602	}
mbed_official	133:d4dda5c437f0	2603	}
mbed_official	133:d4dda5c437f0	2604	}
mbed_official	133:d4dda5c437f0	2605	/* Save formatted counter into the scratch buffer pScratch */
mbed_official	133:d4dda5c437f0	2606	for(loopcounter = 0; (loopcounter < 16); loopcounter++)
mbed_official	133:d4dda5c437f0	2607	{
mbed_official	133:d4dda5c437f0	2608	hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
mbed_official	133:d4dda5c437f0	2609	}
mbed_official	133:d4dda5c437f0	2610	/* Reset bit 0 */
mbed_official	133:d4dda5c437f0	2611	hcryp->Init.pScratch[15] &= 0xfe;
mbed_official	133:d4dda5c437f0	2612	/* Select payload phase once the header phase is performed */
mbed_official	133:d4dda5c437f0	2613	__HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official	133:d4dda5c437f0	2614
mbed_official	133:d4dda5c437f0	2615	/* Flush FIFO */
mbed_official	133:d4dda5c437f0	2616	__HAL_CRYP_FIFO_FLUSH();
mbed_official	133:d4dda5c437f0	2617
mbed_official	133:d4dda5c437f0	2618	/* Set the phase */
mbed_official	133:d4dda5c437f0	2619	hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official	133:d4dda5c437f0	2620	}
mbed_official	133:d4dda5c437f0	2621	/* Set the input and output addresses and start DMA transfer */
mbed_official	133:d4dda5c437f0	2622	CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
mbed_official	133:d4dda5c437f0	2623
mbed_official	133:d4dda5c437f0	2624	/* Unlock process */
mbed_official	133:d4dda5c437f0	2625	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	2626
mbed_official	133:d4dda5c437f0	2627	/* Return function status */
mbed_official	133:d4dda5c437f0	2628	return HAL_OK;
mbed_official	133:d4dda5c437f0	2629	}
mbed_official	133:d4dda5c437f0	2630	else
mbed_official	133:d4dda5c437f0	2631	{
mbed_official	133:d4dda5c437f0	2632	return HAL_ERROR;
mbed_official	133:d4dda5c437f0	2633	}
mbed_official	133:d4dda5c437f0	2634	}
mbed_official	133:d4dda5c437f0	2635
mbed_official	133:d4dda5c437f0	2636	/**
mbed_official	133:d4dda5c437f0	2637	* @brief This function handles CRYP interrupt request.
mbed_official	242:7074e42da0b2	2638	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
mbed_official	242:7074e42da0b2	2639	* the configuration information for CRYP module
mbed_official	133:d4dda5c437f0	2640	* @retval None
mbed_official	133:d4dda5c437f0	2641	*/
mbed_official	133:d4dda5c437f0	2642	void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp)
mbed_official	133:d4dda5c437f0	2643	{
mbed_official	133:d4dda5c437f0	2644	switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)
mbed_official	133:d4dda5c437f0	2645	{
mbed_official	133:d4dda5c437f0	2646	case CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT:
mbed_official	133:d4dda5c437f0	2647	HAL_CRYPEx_AESGCM_Encrypt_IT(hcryp, NULL, 0, NULL);
mbed_official	133:d4dda5c437f0	2648	break;
mbed_official	133:d4dda5c437f0	2649
mbed_official	133:d4dda5c437f0	2650	case CRYP_CR_ALGOMODE_AES_GCM_DECRYPT:
mbed_official	133:d4dda5c437f0	2651	HAL_CRYPEx_AESGCM_Decrypt_IT(hcryp, NULL, 0, NULL);
mbed_official	133:d4dda5c437f0	2652	break;
mbed_official	133:d4dda5c437f0	2653
mbed_official	133:d4dda5c437f0	2654	case CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT:
mbed_official	133:d4dda5c437f0	2655	HAL_CRYPEx_AESCCM_Encrypt_IT(hcryp, NULL, 0, NULL);
mbed_official	133:d4dda5c437f0	2656	break;
mbed_official	133:d4dda5c437f0	2657
mbed_official	133:d4dda5c437f0	2658	case CRYP_CR_ALGOMODE_AES_CCM_DECRYPT:
mbed_official	133:d4dda5c437f0	2659	HAL_CRYPEx_AESCCM_Decrypt_IT(hcryp, NULL, 0, NULL);
mbed_official	133:d4dda5c437f0	2660	break;
mbed_official	133:d4dda5c437f0	2661
mbed_official	133:d4dda5c437f0	2662	default:
mbed_official	133:d4dda5c437f0	2663	break;
mbed_official	133:d4dda5c437f0	2664	}
mbed_official	133:d4dda5c437f0	2665	}
mbed_official	133:d4dda5c437f0	2666
mbed_official	133:d4dda5c437f0	2667	/**
mbed_official	133:d4dda5c437f0	2668	* @}
mbed_official	133:d4dda5c437f0	2669	*/
mbed_official	133:d4dda5c437f0	2670
mbed_official	133:d4dda5c437f0	2671	/**
mbed_official	133:d4dda5c437f0	2672	* @brief DMA CRYP Input Data process complete callback.
mbed_official	133:d4dda5c437f0	2673	* @param hdma: DMA handle
mbed_official	133:d4dda5c437f0	2674	* @retval None
mbed_official	133:d4dda5c437f0	2675	*/
mbed_official	133:d4dda5c437f0	2676	static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma)
mbed_official	133:d4dda5c437f0	2677	{
mbed_official	133:d4dda5c437f0	2678	CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	133:d4dda5c437f0	2679
mbed_official	133:d4dda5c437f0	2680	/* Disable the DMA transfer for input Fifo request by resetting the DIEN bit
mbed_official	133:d4dda5c437f0	2681	in the DMACR register */
mbed_official	133:d4dda5c437f0	2682	CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
mbed_official	133:d4dda5c437f0	2683
mbed_official	133:d4dda5c437f0	2684	/* Call input data transfer complete callback */
mbed_official	133:d4dda5c437f0	2685	HAL_CRYP_InCpltCallback(hcryp);
mbed_official	133:d4dda5c437f0	2686	}
mbed_official	133:d4dda5c437f0	2687
mbed_official	133:d4dda5c437f0	2688	/**
mbed_official	133:d4dda5c437f0	2689	* @brief DMA CRYP Output Data process complete callback.
mbed_official	133:d4dda5c437f0	2690	* @param hdma: DMA handle
mbed_official	133:d4dda5c437f0	2691	* @retval None
mbed_official	133:d4dda5c437f0	2692	*/
mbed_official	133:d4dda5c437f0	2693	static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma)
mbed_official	133:d4dda5c437f0	2694	{
mbed_official	133:d4dda5c437f0	2695	CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	133:d4dda5c437f0	2696
mbed_official	133:d4dda5c437f0	2697	/* Disable the DMA transfer for output Fifo request by resetting the DOEN bit
mbed_official	133:d4dda5c437f0	2698	in the DMACR register */
mbed_official	133:d4dda5c437f0	2699	CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
mbed_official	133:d4dda5c437f0	2700
mbed_official	133:d4dda5c437f0	2701	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	2702	__HAL_CRYP_DISABLE();
mbed_official	133:d4dda5c437f0	2703
mbed_official	133:d4dda5c437f0	2704	/* Change the CRYP peripheral state */
mbed_official	133:d4dda5c437f0	2705	hcryp->State = HAL_CRYP_STATE_READY;
mbed_official	133:d4dda5c437f0	2706
mbed_official	133:d4dda5c437f0	2707	/* Call output data transfer complete callback */
mbed_official	133:d4dda5c437f0	2708	HAL_CRYP_OutCpltCallback(hcryp);
mbed_official	133:d4dda5c437f0	2709	}
mbed_official	133:d4dda5c437f0	2710
mbed_official	133:d4dda5c437f0	2711	/**
mbed_official	133:d4dda5c437f0	2712	* @brief DMA CRYP communication error callback.
mbed_official	133:d4dda5c437f0	2713	* @param hdma: DMA handle
mbed_official	133:d4dda5c437f0	2714	* @retval None
mbed_official	133:d4dda5c437f0	2715	*/
mbed_official	133:d4dda5c437f0	2716	static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma)
mbed_official	133:d4dda5c437f0	2717	{
mbed_official	133:d4dda5c437f0	2718	CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	133:d4dda5c437f0	2719	hcryp->State= HAL_CRYP_STATE_READY;
mbed_official	133:d4dda5c437f0	2720	HAL_CRYP_ErrorCallback(hcryp);
mbed_official	133:d4dda5c437f0	2721	}
mbed_official	133:d4dda5c437f0	2722
mbed_official	133:d4dda5c437f0	2723	/**
mbed_official	133:d4dda5c437f0	2724	* @brief Writes the Key in Key registers.
mbed_official	242:7074e42da0b2	2725	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
mbed_official	242:7074e42da0b2	2726	* the configuration information for CRYP module
mbed_official	133:d4dda5c437f0	2727	* @param Key: Pointer to Key buffer
mbed_official	133:d4dda5c437f0	2728	* @param KeySize: Size of Key
mbed_official	133:d4dda5c437f0	2729	* @retval None
mbed_official	133:d4dda5c437f0	2730	*/
mbed_official	133:d4dda5c437f0	2731	static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef hcryp, uint8_t Key, uint32_t KeySize)
mbed_official	133:d4dda5c437f0	2732	{
mbed_official	133:d4dda5c437f0	2733	uint32_t keyaddr = (uint32_t)Key;
mbed_official	133:d4dda5c437f0	2734
mbed_official	133:d4dda5c437f0	2735	switch(KeySize)
mbed_official	133:d4dda5c437f0	2736	{
mbed_official	133:d4dda5c437f0	2737	case CRYP_KEYSIZE_256B:
mbed_official	133:d4dda5c437f0	2738	/* Key Initialisation */
mbed_official	133:d4dda5c437f0	2739	CRYP->K0LR = __REV((uint32_t)(keyaddr));
mbed_official	133:d4dda5c437f0	2740	keyaddr+=4;
mbed_official	133:d4dda5c437f0	2741	CRYP->K0RR = __REV((uint32_t)(keyaddr));
mbed_official	133:d4dda5c437f0	2742	keyaddr+=4;
mbed_official	133:d4dda5c437f0	2743	CRYP->K1LR = __REV((uint32_t)(keyaddr));
mbed_official	133:d4dda5c437f0	2744	keyaddr+=4;
mbed_official	133:d4dda5c437f0	2745	CRYP->K1RR = __REV((uint32_t)(keyaddr));
mbed_official	133:d4dda5c437f0	2746	keyaddr+=4;
mbed_official	133:d4dda5c437f0	2747	CRYP->K2LR = __REV((uint32_t)(keyaddr));
mbed_official	133:d4dda5c437f0	2748	keyaddr+=4;
mbed_official	133:d4dda5c437f0	2749	CRYP->K2RR = __REV((uint32_t)(keyaddr));
mbed_official	133:d4dda5c437f0	2750	keyaddr+=4;
mbed_official	133:d4dda5c437f0	2751	CRYP->K3LR = __REV((uint32_t)(keyaddr));
mbed_official	133:d4dda5c437f0	2752	keyaddr+=4;
mbed_official	133:d4dda5c437f0	2753	CRYP->K3RR = __REV((uint32_t)(keyaddr));
mbed_official	133:d4dda5c437f0	2754	break;
mbed_official	133:d4dda5c437f0	2755	case CRYP_KEYSIZE_192B:
mbed_official	133:d4dda5c437f0	2756	CRYP->K1LR = __REV((uint32_t)(keyaddr));
mbed_official	133:d4dda5c437f0	2757	keyaddr+=4;
mbed_official	133:d4dda5c437f0	2758	CRYP->K1RR = __REV((uint32_t)(keyaddr));
mbed_official	133:d4dda5c437f0	2759	keyaddr+=4;
mbed_official	133:d4dda5c437f0	2760	CRYP->K2LR = __REV((uint32_t)(keyaddr));
mbed_official	133:d4dda5c437f0	2761	keyaddr+=4;
mbed_official	133:d4dda5c437f0	2762	CRYP->K2RR = __REV((uint32_t)(keyaddr));
mbed_official	133:d4dda5c437f0	2763	keyaddr+=4;
mbed_official	133:d4dda5c437f0	2764	CRYP->K3LR = __REV((uint32_t)(keyaddr));
mbed_official	133:d4dda5c437f0	2765	keyaddr+=4;
mbed_official	133:d4dda5c437f0	2766	CRYP->K3RR = __REV((uint32_t)(keyaddr));
mbed_official	133:d4dda5c437f0	2767	break;
mbed_official	133:d4dda5c437f0	2768	case CRYP_KEYSIZE_128B:
mbed_official	133:d4dda5c437f0	2769	CRYP->K2LR = __REV((uint32_t)(keyaddr));
mbed_official	133:d4dda5c437f0	2770	keyaddr+=4;
mbed_official	133:d4dda5c437f0	2771	CRYP->K2RR = __REV((uint32_t)(keyaddr));
mbed_official	133:d4dda5c437f0	2772	keyaddr+=4;
mbed_official	133:d4dda5c437f0	2773	CRYP->K3LR = __REV((uint32_t)(keyaddr));
mbed_official	133:d4dda5c437f0	2774	keyaddr+=4;
mbed_official	133:d4dda5c437f0	2775	CRYP->K3RR = __REV((uint32_t)(keyaddr));
mbed_official	133:d4dda5c437f0	2776	break;
mbed_official	133:d4dda5c437f0	2777	default:
mbed_official	133:d4dda5c437f0	2778	break;
mbed_official	133:d4dda5c437f0	2779	}
mbed_official	133:d4dda5c437f0	2780	}
mbed_official	133:d4dda5c437f0	2781
mbed_official	133:d4dda5c437f0	2782	/**
mbed_official	133:d4dda5c437f0	2783	* @brief Writes the InitVector/InitCounter in IV registers.
mbed_official	242:7074e42da0b2	2784	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
mbed_official	242:7074e42da0b2	2785	* the configuration information for CRYP module
mbed_official	133:d4dda5c437f0	2786	* @param InitVector: Pointer to InitVector/InitCounter buffer
mbed_official	133:d4dda5c437f0	2787	* @param IVSize: Size of the InitVector/InitCounter
mbed_official	133:d4dda5c437f0	2788	* @retval None
mbed_official	133:d4dda5c437f0	2789	*/
mbed_official	133:d4dda5c437f0	2790	static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef hcryp, uint8_t InitVector, uint32_t IVSize)
mbed_official	133:d4dda5c437f0	2791	{
mbed_official	133:d4dda5c437f0	2792	uint32_t ivaddr = (uint32_t)InitVector;
mbed_official	133:d4dda5c437f0	2793
mbed_official	133:d4dda5c437f0	2794	switch(IVSize)
mbed_official	133:d4dda5c437f0	2795	{
mbed_official	133:d4dda5c437f0	2796	case CRYP_KEYSIZE_128B:
mbed_official	133:d4dda5c437f0	2797	CRYP->IV0LR = __REV((uint32_t)(ivaddr));
mbed_official	133:d4dda5c437f0	2798	ivaddr+=4;
mbed_official	133:d4dda5c437f0	2799	CRYP->IV0RR = __REV((uint32_t)(ivaddr));
mbed_official	133:d4dda5c437f0	2800	ivaddr+=4;
mbed_official	133:d4dda5c437f0	2801	CRYP->IV1LR = __REV((uint32_t)(ivaddr));
mbed_official	133:d4dda5c437f0	2802	ivaddr+=4;
mbed_official	133:d4dda5c437f0	2803	CRYP->IV1RR = __REV((uint32_t)(ivaddr));
mbed_official	133:d4dda5c437f0	2804	break;
mbed_official	133:d4dda5c437f0	2805	/* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */
mbed_official	133:d4dda5c437f0	2806	case CRYP_KEYSIZE_192B:
mbed_official	133:d4dda5c437f0	2807	CRYP->IV0LR = __REV((uint32_t)(ivaddr));
mbed_official	133:d4dda5c437f0	2808	ivaddr+=4;
mbed_official	133:d4dda5c437f0	2809	CRYP->IV0RR = __REV((uint32_t)(ivaddr));
mbed_official	133:d4dda5c437f0	2810	break;
mbed_official	133:d4dda5c437f0	2811	case CRYP_KEYSIZE_256B:
mbed_official	133:d4dda5c437f0	2812	CRYP->IV0LR = __REV((uint32_t)(ivaddr));
mbed_official	133:d4dda5c437f0	2813	ivaddr+=4;
mbed_official	133:d4dda5c437f0	2814	CRYP->IV0RR = __REV((uint32_t)(ivaddr));
mbed_official	133:d4dda5c437f0	2815	break;
mbed_official	133:d4dda5c437f0	2816	default:
mbed_official	133:d4dda5c437f0	2817	break;
mbed_official	133:d4dda5c437f0	2818	}
mbed_official	133:d4dda5c437f0	2819	}
mbed_official	133:d4dda5c437f0	2820
mbed_official	133:d4dda5c437f0	2821	/**
mbed_official	133:d4dda5c437f0	2822	* @brief Process Data: Writes Input data in polling mode and read the Output data.
mbed_official	242:7074e42da0b2	2823	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
mbed_official	242:7074e42da0b2	2824	* the configuration information for CRYP module
mbed_official	133:d4dda5c437f0	2825	* @param Input: Pointer to the Input buffer.
mbed_official	133:d4dda5c437f0	2826	* @param Ilength: Length of the Input buffer, must be a multiple of 16
mbed_official	133:d4dda5c437f0	2827	* @param Output: Pointer to the returned buffer
mbed_official	133:d4dda5c437f0	2828	* @param Timeout: Timeout value
mbed_official	133:d4dda5c437f0	2829	* @retval None
mbed_official	133:d4dda5c437f0	2830	*/
mbed_official	133:d4dda5c437f0	2831	static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef hcryp, uint8_t Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout)
mbed_official	133:d4dda5c437f0	2832	{
mbed_official	133:d4dda5c437f0	2833	uint32_t timeout = 0;
mbed_official	133:d4dda5c437f0	2834	uint32_t i = 0;
mbed_official	133:d4dda5c437f0	2835	uint32_t inputaddr = (uint32_t)Input;
mbed_official	133:d4dda5c437f0	2836	uint32_t outputaddr = (uint32_t)Output;
mbed_official	133:d4dda5c437f0	2837
mbed_official	133:d4dda5c437f0	2838	for(i=0; (i < Ilength); i+=16)
mbed_official	133:d4dda5c437f0	2839	{
mbed_official	133:d4dda5c437f0	2840	/* Write the Input block in the IN FIFO */
mbed_official	133:d4dda5c437f0	2841	CRYP->DR = (uint32_t)(inputaddr);
mbed_official	133:d4dda5c437f0	2842	inputaddr+=4;
mbed_official	133:d4dda5c437f0	2843	CRYP->DR = (uint32_t)(inputaddr);
mbed_official	133:d4dda5c437f0	2844	inputaddr+=4;
mbed_official	133:d4dda5c437f0	2845	CRYP->DR = (uint32_t)(inputaddr);
mbed_official	133:d4dda5c437f0	2846	inputaddr+=4;
mbed_official	133:d4dda5c437f0	2847	CRYP->DR = (uint32_t)(inputaddr);
mbed_official	133:d4dda5c437f0	2848	inputaddr+=4;
mbed_official	133:d4dda5c437f0	2849
mbed_official	133:d4dda5c437f0	2850	/* Get timeout */
mbed_official	133:d4dda5c437f0	2851	timeout = HAL_GetTick() + Timeout;
mbed_official	133:d4dda5c437f0	2852
mbed_official	133:d4dda5c437f0	2853	while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
mbed_official	133:d4dda5c437f0	2854	{
mbed_official	133:d4dda5c437f0	2855	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	2856	if(Timeout != HAL_MAX_DELAY)
mbed_official	133:d4dda5c437f0	2857	{
mbed_official	133:d4dda5c437f0	2858	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	2859	{
mbed_official	133:d4dda5c437f0	2860	/* Change state */
mbed_official	133:d4dda5c437f0	2861	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	2862
mbed_official	133:d4dda5c437f0	2863	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	2864	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	2865
mbed_official	133:d4dda5c437f0	2866	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	2867	}
mbed_official	133:d4dda5c437f0	2868	}
mbed_official	133:d4dda5c437f0	2869	}
mbed_official	133:d4dda5c437f0	2870	/* Read the Output block from the OUT FIFO */
mbed_official	133:d4dda5c437f0	2871	(uint32_t)(outputaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	2872	outputaddr+=4;
mbed_official	133:d4dda5c437f0	2873	(uint32_t)(outputaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	2874	outputaddr+=4;
mbed_official	133:d4dda5c437f0	2875	(uint32_t)(outputaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	2876	outputaddr+=4;
mbed_official	133:d4dda5c437f0	2877	(uint32_t)(outputaddr) = CRYP->DOUT;
mbed_official	133:d4dda5c437f0	2878	outputaddr+=4;
mbed_official	133:d4dda5c437f0	2879	}
mbed_official	133:d4dda5c437f0	2880	/* Return function status */
mbed_official	133:d4dda5c437f0	2881	return HAL_OK;
mbed_official	133:d4dda5c437f0	2882	}
mbed_official	133:d4dda5c437f0	2883
mbed_official	133:d4dda5c437f0	2884	/**
mbed_official	133:d4dda5c437f0	2885	* @brief Sets the header phase
mbed_official	242:7074e42da0b2	2886	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
mbed_official	242:7074e42da0b2	2887	* the configuration information for CRYP module
mbed_official	133:d4dda5c437f0	2888	* @param Input: Pointer to the Input buffer.
mbed_official	133:d4dda5c437f0	2889	* @param Ilength: Length of the Input buffer, must be a multiple of 16
mbed_official	133:d4dda5c437f0	2890	* @param Timeout: Timeout value
mbed_official	133:d4dda5c437f0	2891	* @retval None
mbed_official	133:d4dda5c437f0	2892	*/
mbed_official	133:d4dda5c437f0	2893	static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef hcryp, uint8_t Input, uint16_t Ilength, uint32_t Timeout)
mbed_official	133:d4dda5c437f0	2894	{
mbed_official	133:d4dda5c437f0	2895	uint32_t timeout = 0;
mbed_official	133:d4dda5c437f0	2896	uint32_t loopcounter = 0;
mbed_official	133:d4dda5c437f0	2897	uint32_t headeraddr = (uint32_t)Input;
mbed_official	133:d4dda5c437f0	2898
mbed_official	133:d4dda5c437f0	2899	/*************************** Header phase *******************************/
mbed_official	133:d4dda5c437f0	2900	if(hcryp->Init.HeaderSize != 0)
mbed_official	133:d4dda5c437f0	2901	{
mbed_official	133:d4dda5c437f0	2902	/* Select header phase */
mbed_official	133:d4dda5c437f0	2903	__HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
mbed_official	133:d4dda5c437f0	2904	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	2905	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	2906
mbed_official	133:d4dda5c437f0	2907	for(loopcounter = 0; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=16)
mbed_official	133:d4dda5c437f0	2908	{
mbed_official	133:d4dda5c437f0	2909	/* Get timeout */
mbed_official	133:d4dda5c437f0	2910	timeout = HAL_GetTick() + Timeout;
mbed_official	133:d4dda5c437f0	2911
mbed_official	133:d4dda5c437f0	2912	while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
mbed_official	133:d4dda5c437f0	2913	{
mbed_official	133:d4dda5c437f0	2914	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	2915	if(Timeout != HAL_MAX_DELAY)
mbed_official	133:d4dda5c437f0	2916	{
mbed_official	133:d4dda5c437f0	2917	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	2918	{
mbed_official	133:d4dda5c437f0	2919	/* Change state */
mbed_official	133:d4dda5c437f0	2920	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	2921
mbed_official	133:d4dda5c437f0	2922	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	2923	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	2924
mbed_official	133:d4dda5c437f0	2925	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	2926	}
mbed_official	133:d4dda5c437f0	2927	}
mbed_official	133:d4dda5c437f0	2928	}
mbed_official	133:d4dda5c437f0	2929	/* Write the Input block in the IN FIFO */
mbed_official	133:d4dda5c437f0	2930	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	2931	headeraddr+=4;
mbed_official	133:d4dda5c437f0	2932	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	2933	headeraddr+=4;
mbed_official	133:d4dda5c437f0	2934	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	2935	headeraddr+=4;
mbed_official	133:d4dda5c437f0	2936	CRYP->DR = (uint32_t)(headeraddr);
mbed_official	133:d4dda5c437f0	2937	headeraddr+=4;
mbed_official	133:d4dda5c437f0	2938	}
mbed_official	133:d4dda5c437f0	2939
mbed_official	133:d4dda5c437f0	2940	/* Wait until the complete message has been processed */
mbed_official	133:d4dda5c437f0	2941
mbed_official	133:d4dda5c437f0	2942	/* Get timeout */
mbed_official	133:d4dda5c437f0	2943	timeout = HAL_GetTick() + Timeout;
mbed_official	133:d4dda5c437f0	2944
mbed_official	133:d4dda5c437f0	2945	while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
mbed_official	133:d4dda5c437f0	2946	{
mbed_official	133:d4dda5c437f0	2947	/* Check for the Timeout */
mbed_official	133:d4dda5c437f0	2948	if(Timeout != HAL_MAX_DELAY)
mbed_official	133:d4dda5c437f0	2949	{
mbed_official	133:d4dda5c437f0	2950	if(HAL_GetTick() >= timeout)
mbed_official	133:d4dda5c437f0	2951	{
mbed_official	133:d4dda5c437f0	2952	/* Change state */
mbed_official	133:d4dda5c437f0	2953	hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official	133:d4dda5c437f0	2954
mbed_official	133:d4dda5c437f0	2955	/* Process Unlocked */
mbed_official	133:d4dda5c437f0	2956	__HAL_UNLOCK(hcryp);
mbed_official	133:d4dda5c437f0	2957
mbed_official	133:d4dda5c437f0	2958	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	2959	}
mbed_official	133:d4dda5c437f0	2960	}
mbed_official	133:d4dda5c437f0	2961	}
mbed_official	133:d4dda5c437f0	2962	}
mbed_official	133:d4dda5c437f0	2963	/* Return function status */
mbed_official	133:d4dda5c437f0	2964	return HAL_OK;
mbed_official	133:d4dda5c437f0	2965	}
mbed_official	133:d4dda5c437f0	2966
mbed_official	133:d4dda5c437f0	2967	/**
mbed_official	133:d4dda5c437f0	2968	* @brief Sets the DMA configuration and start the DMA transfert.
mbed_official	242:7074e42da0b2	2969	* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
mbed_official	242:7074e42da0b2	2970	* the configuration information for CRYP module
mbed_official	133:d4dda5c437f0	2971	* @param inputaddr: Address of the Input buffer
mbed_official	133:d4dda5c437f0	2972	* @param Size: Size of the Input buffer, must be a multiple of 16
mbed_official	133:d4dda5c437f0	2973	* @param outputaddr: Address of the Output buffer
mbed_official	133:d4dda5c437f0	2974	* @retval None
mbed_official	133:d4dda5c437f0	2975	*/
mbed_official	133:d4dda5c437f0	2976	static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
mbed_official	133:d4dda5c437f0	2977	{
mbed_official	133:d4dda5c437f0	2978	/* Set the CRYP DMA transfer complete callback */
mbed_official	133:d4dda5c437f0	2979	hcryp->hdmain->XferCpltCallback = CRYPEx_GCMCCM_DMAInCplt;
mbed_official	133:d4dda5c437f0	2980	/* Set the DMA error callback */
mbed_official	133:d4dda5c437f0	2981	hcryp->hdmain->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
mbed_official	133:d4dda5c437f0	2982
mbed_official	133:d4dda5c437f0	2983	/* Set the CRYP DMA transfer complete callback */
mbed_official	133:d4dda5c437f0	2984	hcryp->hdmaout->XferCpltCallback = CRYPEx_GCMCCM_DMAOutCplt;
mbed_official	133:d4dda5c437f0	2985	/* Set the DMA error callback */
mbed_official	133:d4dda5c437f0	2986	hcryp->hdmaout->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
mbed_official	133:d4dda5c437f0	2987
mbed_official	133:d4dda5c437f0	2988	/* Enable the CRYP peripheral */
mbed_official	133:d4dda5c437f0	2989	__HAL_CRYP_ENABLE();
mbed_official	133:d4dda5c437f0	2990
mbed_official	133:d4dda5c437f0	2991	/* Enable the DMA In DMA Stream */
mbed_official	133:d4dda5c437f0	2992	HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&CRYP->DR, Size/4);
mbed_official	133:d4dda5c437f0	2993
mbed_official	133:d4dda5c437f0	2994	/* Enable In DMA request */
mbed_official	133:d4dda5c437f0	2995	CRYP->DMACR = CRYP_DMACR_DIEN;
mbed_official	133:d4dda5c437f0	2996
mbed_official	133:d4dda5c437f0	2997	/* Enable the DMA Out DMA Stream */
mbed_official	133:d4dda5c437f0	2998	HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&CRYP->DOUT, outputaddr, Size/4);
mbed_official	133:d4dda5c437f0	2999
mbed_official	133:d4dda5c437f0	3000	/* Enable Out DMA request */
mbed_official	133:d4dda5c437f0	3001	CRYP->DMACR \|= CRYP_DMACR_DOEN;
mbed_official	133:d4dda5c437f0	3002	}
mbed_official	133:d4dda5c437f0	3003
mbed_official	133:d4dda5c437f0	3004	/**
mbed_official	133:d4dda5c437f0	3005	* @}
mbed_official	133:d4dda5c437f0	3006	*/
mbed_official	133:d4dda5c437f0	3007	#endif /* STM32F437xx \|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	3008
mbed_official	133:d4dda5c437f0	3009	#endif /* HAL_CRYP_MODULE_ENABLED */
mbed_official	133:d4dda5c437f0	3010	/**
mbed_official	133:d4dda5c437f0	3011	* @}
mbed_official	133:d4dda5c437f0	3012	*/
mbed_official	133:d4dda5c437f0	3013
mbed_official	133:d4dda5c437f0	3014	/**
mbed_official	133:d4dda5c437f0	3015	* @}
mbed_official	133:d4dda5c437f0	3016	*/
mbed_official	133:d4dda5c437f0	3017
mbed_official	133:d4dda5c437f0	3018	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	13 Sep 2014
Imports:	4
Forks:	0
Commits:	324
Dependents:	1
Dependencies:	0
Followers:	2

targets/cmsis/TARGET_STM/TARGET_STM32F407VG/stm32f4xx_hal_cryp_ex.c@296:ec1b66a3d094, 2014-08-21 (annotated)

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