shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

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targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_cryp_ex.c@133:d4dda5c437f0, 2014-03-24 (annotated)

Committer:
mbed_official
Date:
Mon Mar 24 17:45:07 2014 +0000
Revision:
133:d4dda5c437f0
Child:
242:7074e42da0b2
Synchronized with git revision 47b961246bed973fe4cb8932781ffc8025b78a61



Full URL: https://github.com/mbedmicro/mbed/commit/47b961246bed973fe4cb8932781ffc8025b78a61/



[STM32F4-Discovery (STM32F407VG)] initial port

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 133:d4dda5c437f0 1 /**
mbed_official 133:d4dda5c437f0 2 ******************************************************************************
mbed_official 133:d4dda5c437f0 3 * @file stm32f4xx_hal_cryp_ex.c
mbed_official 133:d4dda5c437f0 4 * @author MCD Application Team
mbed_official 133:d4dda5c437f0 5 * @version V1.0.0
mbed_official 133:d4dda5c437f0 6 * @date 18-February-2014
mbed_official 133:d4dda5c437f0 7 * @brief Extended CRYP HAL module driver
mbed_official 133:d4dda5c437f0 8 * This file provides firmware functions to manage the following
mbed_official 133:d4dda5c437f0 9 * functionalities of CRYP extension peripheral:
mbed_official 133:d4dda5c437f0 10 * + Extended AES processing functions
mbed_official 133:d4dda5c437f0 11 *
mbed_official 133:d4dda5c437f0 12 @verbatim
mbed_official 133:d4dda5c437f0 13 ==============================================================================
mbed_official 133:d4dda5c437f0 14 ##### How to use this driver #####
mbed_official 133:d4dda5c437f0 15 ==============================================================================
mbed_official 133:d4dda5c437f0 16 [..]
mbed_official 133:d4dda5c437f0 17 The CRYP Extension HAL driver can be used as follows:
mbed_official 133:d4dda5c437f0 18 (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
mbed_official 133:d4dda5c437f0 19 (##) Enable the CRYP interface clock using __CRYP_CLK_ENABLE()
mbed_official 133:d4dda5c437f0 20 (##) In case of using interrupts (e.g. HAL_CRYPEx_AESGCM_Encrypt_IT())
mbed_official 133:d4dda5c437f0 21 (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
mbed_official 133:d4dda5c437f0 22 (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
mbed_official 133:d4dda5c437f0 23 (+) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
mbed_official 133:d4dda5c437f0 24 (##) In case of using DMA to control data transfer (e.g. HAL_AES_ECB_Encrypt_DMA())
mbed_official 133:d4dda5c437f0 25 (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
mbed_official 133:d4dda5c437f0 26 (+++) Configure and enable two DMA streams one for managing data transfer from
mbed_official 133:d4dda5c437f0 27 memory to peripheral (input stream) and another stream for managing data
mbed_official 133:d4dda5c437f0 28 transfer from peripheral to memory (output stream)
mbed_official 133:d4dda5c437f0 29 (+++) Associate the initilalized DMA handle to the CRYP DMA handle
mbed_official 133:d4dda5c437f0 30 using __HAL_LINKDMA()
mbed_official 133:d4dda5c437f0 31 (+++) Configure the priority and enable the NVIC for the transfer complete
mbed_official 133:d4dda5c437f0 32 interrupt on the two DMA Streams. The output stream should have higher
mbed_official 133:d4dda5c437f0 33 priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
mbed_official 133:d4dda5c437f0 34 (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
mbed_official 133:d4dda5c437f0 35 (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
mbed_official 133:d4dda5c437f0 36 (##) The key size: 128, 192 and 256. This parameter is relevant only for AES
mbed_official 133:d4dda5c437f0 37 (##) The encryption/decryption key. Its size depends on the algorithm
mbed_official 133:d4dda5c437f0 38 used for encryption/decryption
mbed_official 133:d4dda5c437f0 39 (##) The initialization vector (counter). It is not used ECB mode.
mbed_official 133:d4dda5c437f0 40 (#)Three processing (encryption/decryption) functions are available:
mbed_official 133:d4dda5c437f0 41 (##) Polling mode: encryption and decryption APIs are blocking functions
mbed_official 133:d4dda5c437f0 42 i.e. they process the data and wait till the processing is finished
mbed_official 133:d4dda5c437f0 43 e.g. HAL_CRYPEx_AESGCM_Encrypt()
mbed_official 133:d4dda5c437f0 44 (##) Interrupt mode: encryption and decryption APIs are not blocking functions
mbed_official 133:d4dda5c437f0 45 i.e. they process the data under interrupt
mbed_official 133:d4dda5c437f0 46 e.g. HAL_CRYPEx_AESGCM_Encrypt_IT()
mbed_official 133:d4dda5c437f0 47 (##) DMA mode: encryption and decryption APIs are not blocking functions
mbed_official 133:d4dda5c437f0 48 i.e. the data transfer is ensured by DMA
mbed_official 133:d4dda5c437f0 49 e.g. HAL_CRYPEx_AESGCM_Encrypt_DMA()
mbed_official 133:d4dda5c437f0 50 (#)When the processing function is called at first time after HAL_CRYP_Init()
mbed_official 133:d4dda5c437f0 51 the CRYP peripheral is initialized and processes the buffer in input.
mbed_official 133:d4dda5c437f0 52 At second call, the processing function performs an append of the already
mbed_official 133:d4dda5c437f0 53 processed buffer.
mbed_official 133:d4dda5c437f0 54 When a new data block is to be processed, call HAL_CRYP_Init() then the
mbed_official 133:d4dda5c437f0 55 processing function.
mbed_official 133:d4dda5c437f0 56 (#)In AES-GCM and AES-CCM modes are an authenticated encryption algorithms
mbed_official 133:d4dda5c437f0 57 which provide authentication messages.
mbed_official 133:d4dda5c437f0 58 HAL_AES_GCM_Finish() and HAL_AES_CCM_Finish() are used to provide those
mbed_official 133:d4dda5c437f0 59 authentication messages.
mbed_official 133:d4dda5c437f0 60 Call those functions after the processing ones (polling, interrupt or DMA).
mbed_official 133:d4dda5c437f0 61 e.g. in AES-CCM mode call HAL_CRYPEx_AESCCM_Encrypt() to encrypt the plain data
mbed_official 133:d4dda5c437f0 62 then call HAL_CRYPEx_AESCCM_Finish() to get the authentication message
mbed_official 133:d4dda5c437f0 63 (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
mbed_official 133:d4dda5c437f0 64
mbed_official 133:d4dda5c437f0 65 @endverbatim
mbed_official 133:d4dda5c437f0 66 ******************************************************************************
mbed_official 133:d4dda5c437f0 67 * @attention
mbed_official 133:d4dda5c437f0 68 *
mbed_official 133:d4dda5c437f0 69 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 133:d4dda5c437f0 70 *
mbed_official 133:d4dda5c437f0 71 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 133:d4dda5c437f0 72 * are permitted provided that the following conditions are met:
mbed_official 133:d4dda5c437f0 73 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 133:d4dda5c437f0 74 * this list of conditions and the following disclaimer.
mbed_official 133:d4dda5c437f0 75 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 133:d4dda5c437f0 76 * this list of conditions and the following disclaimer in the documentation
mbed_official 133:d4dda5c437f0 77 * and/or other materials provided with the distribution.
mbed_official 133:d4dda5c437f0 78 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 133:d4dda5c437f0 79 * may be used to endorse or promote products derived from this software
mbed_official 133:d4dda5c437f0 80 * without specific prior written permission.
mbed_official 133:d4dda5c437f0 81 *
mbed_official 133:d4dda5c437f0 82 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 133:d4dda5c437f0 83 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 133:d4dda5c437f0 84 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 133:d4dda5c437f0 85 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 133:d4dda5c437f0 86 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 133:d4dda5c437f0 87 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 133:d4dda5c437f0 88 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 133:d4dda5c437f0 89 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 133:d4dda5c437f0 90 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 133:d4dda5c437f0 91 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 133:d4dda5c437f0 92 *
mbed_official 133:d4dda5c437f0 93 ******************************************************************************
mbed_official 133:d4dda5c437f0 94 */
mbed_official 133:d4dda5c437f0 95
mbed_official 133:d4dda5c437f0 96 /* Includes ------------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 97 #include "stm32f4xx_hal.h"
mbed_official 133:d4dda5c437f0 98
mbed_official 133:d4dda5c437f0 99 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 133:d4dda5c437f0 100 * @{
mbed_official 133:d4dda5c437f0 101 */
mbed_official 133:d4dda5c437f0 102
mbed_official 133:d4dda5c437f0 103 /** @defgroup CRYPEx
mbed_official 133:d4dda5c437f0 104 * @brief CRYP Extension HAL module driver.
mbed_official 133:d4dda5c437f0 105 * @{
mbed_official 133:d4dda5c437f0 106 */
mbed_official 133:d4dda5c437f0 107
mbed_official 133:d4dda5c437f0 108 #ifdef HAL_CRYP_MODULE_ENABLED
mbed_official 133:d4dda5c437f0 109
mbed_official 133:d4dda5c437f0 110 #if defined(STM32F437xx) || defined(STM32F439xx)
mbed_official 133:d4dda5c437f0 111
mbed_official 133:d4dda5c437f0 112 /* Private typedef -----------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 113 /* Private define ------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 114 /* Private macro -------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 115 /* Private variables ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 116 /* Private function prototypes -----------------------------------------------*/
mbed_official 133:d4dda5c437f0 117 static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize);
mbed_official 133:d4dda5c437f0 118 static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);
mbed_official 133:d4dda5c437f0 119 static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout);
mbed_official 133:d4dda5c437f0 120 static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout);
mbed_official 133:d4dda5c437f0 121 static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma);
mbed_official 133:d4dda5c437f0 122 static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma);
mbed_official 133:d4dda5c437f0 123 static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma);
mbed_official 133:d4dda5c437f0 124 static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
mbed_official 133:d4dda5c437f0 125
mbed_official 133:d4dda5c437f0 126 /* Private functions ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 127
mbed_official 133:d4dda5c437f0 128 /** @defgroup CRYPEx_Private_Functions
mbed_official 133:d4dda5c437f0 129 * @{
mbed_official 133:d4dda5c437f0 130 */
mbed_official 133:d4dda5c437f0 131
mbed_official 133:d4dda5c437f0 132 /** @defgroup CRYPEx_Group1 Extended AES processing functions
mbed_official 133:d4dda5c437f0 133 * @brief Extended processing functions.
mbed_official 133:d4dda5c437f0 134 *
mbed_official 133:d4dda5c437f0 135 @verbatim
mbed_official 133:d4dda5c437f0 136 ==============================================================================
mbed_official 133:d4dda5c437f0 137 ##### Extended AES processing functions #####
mbed_official 133:d4dda5c437f0 138 ==============================================================================
mbed_official 133:d4dda5c437f0 139 [..] This section provides functions allowing to:
mbed_official 133:d4dda5c437f0 140 (+) Encrypt plaintext using AES-128/192/256 using GCM and CCM chaining modes
mbed_official 133:d4dda5c437f0 141 (+) Decrypt cyphertext using AES-128/192/256 using GCM and CCM chaining modes
mbed_official 133:d4dda5c437f0 142 (+) Finish the processing. This function is available only for GCM and CCM
mbed_official 133:d4dda5c437f0 143 [..] Three processing methods are available:
mbed_official 133:d4dda5c437f0 144 (+) Polling mode
mbed_official 133:d4dda5c437f0 145 (+) Interrupt mode
mbed_official 133:d4dda5c437f0 146 (+) DMA mode
mbed_official 133:d4dda5c437f0 147
mbed_official 133:d4dda5c437f0 148 @endverbatim
mbed_official 133:d4dda5c437f0 149 * @{
mbed_official 133:d4dda5c437f0 150 */
mbed_official 133:d4dda5c437f0 151
mbed_official 133:d4dda5c437f0 152
mbed_official 133:d4dda5c437f0 153 /**
mbed_official 133:d4dda5c437f0 154 * @brief Initializes the CRYP peripheral in AES CCM encryption mode then
mbed_official 133:d4dda5c437f0 155 * encrypt pPlainData. The cypher data are available in pCypherData.
mbed_official 133:d4dda5c437f0 156 * @param hcryp: CRYP handle
mbed_official 133:d4dda5c437f0 157 * @param pPlainData: Pointer to the plaintext buffer
mbed_official 133:d4dda5c437f0 158 * @param Size: Length of the plaintext buffer, must be a multiple of 16
mbed_official 133:d4dda5c437f0 159 * @param pCypherData: Pointer to the cyphertext buffer
mbed_official 133:d4dda5c437f0 160 * @param Timeout: Timeout duration
mbed_official 133:d4dda5c437f0 161 * @retval HAL status
mbed_official 133:d4dda5c437f0 162 */
mbed_official 133:d4dda5c437f0 163 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
mbed_official 133:d4dda5c437f0 164 {
mbed_official 133:d4dda5c437f0 165 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 166 uint32_t headersize = hcryp->Init.HeaderSize;
mbed_official 133:d4dda5c437f0 167 uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
mbed_official 133:d4dda5c437f0 168 uint32_t loopcounter = 0;
mbed_official 133:d4dda5c437f0 169 uint32_t bufferidx = 0;
mbed_official 133:d4dda5c437f0 170 uint8_t blockb0[16] = {0};/* Block B0 */
mbed_official 133:d4dda5c437f0 171 uint8_t ctr[16] = {0}; /* Counter */
mbed_official 133:d4dda5c437f0 172 uint32_t b0addr = (uint32_t)blockb0;
mbed_official 133:d4dda5c437f0 173
mbed_official 133:d4dda5c437f0 174 /* Process Locked */
mbed_official 133:d4dda5c437f0 175 __HAL_LOCK(hcryp);
mbed_official 133:d4dda5c437f0 176
mbed_official 133:d4dda5c437f0 177 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 178 hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official 133:d4dda5c437f0 179
mbed_official 133:d4dda5c437f0 180 /* Check if initialization phase has already been performed */
mbed_official 133:d4dda5c437f0 181 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official 133:d4dda5c437f0 182 {
mbed_official 133:d4dda5c437f0 183 /************************ Formatting the header block *********************/
mbed_official 133:d4dda5c437f0 184 if(headersize != 0)
mbed_official 133:d4dda5c437f0 185 {
mbed_official 133:d4dda5c437f0 186 /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
mbed_official 133:d4dda5c437f0 187 if(headersize < 65280)
mbed_official 133:d4dda5c437f0 188 {
mbed_official 133:d4dda5c437f0 189 hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
mbed_official 133:d4dda5c437f0 190 hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
mbed_official 133:d4dda5c437f0 191 headersize += 2;
mbed_official 133:d4dda5c437f0 192 }
mbed_official 133:d4dda5c437f0 193 else
mbed_official 133:d4dda5c437f0 194 {
mbed_official 133:d4dda5c437f0 195 /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
mbed_official 133:d4dda5c437f0 196 hcryp->Init.pScratch[bufferidx++] = 0xFF;
mbed_official 133:d4dda5c437f0 197 hcryp->Init.pScratch[bufferidx++] = 0xFE;
mbed_official 133:d4dda5c437f0 198 hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
mbed_official 133:d4dda5c437f0 199 hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
mbed_official 133:d4dda5c437f0 200 hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
mbed_official 133:d4dda5c437f0 201 hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
mbed_official 133:d4dda5c437f0 202 headersize += 6;
mbed_official 133:d4dda5c437f0 203 }
mbed_official 133:d4dda5c437f0 204 /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
mbed_official 133:d4dda5c437f0 205 for(loopcounter = 0; loopcounter < headersize; loopcounter++)
mbed_official 133:d4dda5c437f0 206 {
mbed_official 133:d4dda5c437f0 207 hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
mbed_official 133:d4dda5c437f0 208 }
mbed_official 133:d4dda5c437f0 209 /* Check if the header size is modulo 16 */
mbed_official 133:d4dda5c437f0 210 if ((headersize % 16) != 0)
mbed_official 133:d4dda5c437f0 211 {
mbed_official 133:d4dda5c437f0 212 /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
mbed_official 133:d4dda5c437f0 213 for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
mbed_official 133:d4dda5c437f0 214 {
mbed_official 133:d4dda5c437f0 215 hcryp->Init.pScratch[loopcounter] = 0;
mbed_official 133:d4dda5c437f0 216 }
mbed_official 133:d4dda5c437f0 217 /* Set the header size to modulo 16 */
mbed_official 133:d4dda5c437f0 218 headersize = ((headersize/16) + 1) * 16;
mbed_official 133:d4dda5c437f0 219 }
mbed_official 133:d4dda5c437f0 220 /* Set the pointer headeraddr to hcryp->Init.pScratch */
mbed_official 133:d4dda5c437f0 221 headeraddr = (uint32_t)hcryp->Init.pScratch;
mbed_official 133:d4dda5c437f0 222 }
mbed_official 133:d4dda5c437f0 223 /*********************** Formatting the block B0 **************************/
mbed_official 133:d4dda5c437f0 224 if(headersize != 0)
mbed_official 133:d4dda5c437f0 225 {
mbed_official 133:d4dda5c437f0 226 blockb0[0] = 0x40;
mbed_official 133:d4dda5c437f0 227 }
mbed_official 133:d4dda5c437f0 228 /* Flags byte */
mbed_official 133:d4dda5c437f0 229 /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
mbed_official 133:d4dda5c437f0 230 blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
mbed_official 133:d4dda5c437f0 231 blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
mbed_official 133:d4dda5c437f0 232
mbed_official 133:d4dda5c437f0 233 for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
mbed_official 133:d4dda5c437f0 234 {
mbed_official 133:d4dda5c437f0 235 blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
mbed_official 133:d4dda5c437f0 236 }
mbed_official 133:d4dda5c437f0 237 for ( ; loopcounter < 13; loopcounter++)
mbed_official 133:d4dda5c437f0 238 {
mbed_official 133:d4dda5c437f0 239 blockb0[loopcounter+1] = 0;
mbed_official 133:d4dda5c437f0 240 }
mbed_official 133:d4dda5c437f0 241
mbed_official 133:d4dda5c437f0 242 blockb0[14] = (Size >> 8);
mbed_official 133:d4dda5c437f0 243 blockb0[15] = (Size & 0xFF);
mbed_official 133:d4dda5c437f0 244
mbed_official 133:d4dda5c437f0 245 /************************* Formatting the initial counter *****************/
mbed_official 133:d4dda5c437f0 246 /* Byte 0:
mbed_official 133:d4dda5c437f0 247 Bits 7 and 6 are reserved and shall be set to 0
mbed_official 133:d4dda5c437f0 248 Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter blocks
mbed_official 133:d4dda5c437f0 249 are distinct from B0
mbed_official 133:d4dda5c437f0 250 Bits 0, 1, and 2 contain the same encoding of q as in B0
mbed_official 133:d4dda5c437f0 251 */
mbed_official 133:d4dda5c437f0 252 ctr[0] = blockb0[0] & 0x07;
mbed_official 133:d4dda5c437f0 253 /* byte 1 to NonceSize is the IV (Nonce) */
mbed_official 133:d4dda5c437f0 254 for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
mbed_official 133:d4dda5c437f0 255 {
mbed_official 133:d4dda5c437f0 256 ctr[loopcounter] = blockb0[loopcounter];
mbed_official 133:d4dda5c437f0 257 }
mbed_official 133:d4dda5c437f0 258 /* Set the LSB to 1 */
mbed_official 133:d4dda5c437f0 259 ctr[15] |= 0x01;
mbed_official 133:d4dda5c437f0 260
mbed_official 133:d4dda5c437f0 261 /* Set the key */
mbed_official 133:d4dda5c437f0 262 CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official 133:d4dda5c437f0 263
mbed_official 133:d4dda5c437f0 264 /* Set the CRYP peripheral in AES CCM mode */
mbed_official 133:d4dda5c437f0 265 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
mbed_official 133:d4dda5c437f0 266
mbed_official 133:d4dda5c437f0 267 /* Set the Initialization Vector */
mbed_official 133:d4dda5c437f0 268 CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, CRYP_KEYSIZE_128B);
mbed_official 133:d4dda5c437f0 269
mbed_official 133:d4dda5c437f0 270 /* Select init phase */
mbed_official 133:d4dda5c437f0 271 __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
mbed_official 133:d4dda5c437f0 272
mbed_official 133:d4dda5c437f0 273 b0addr = (uint32_t)blockb0;
mbed_official 133:d4dda5c437f0 274 /* Write the blockb0 block in the IN FIFO */
mbed_official 133:d4dda5c437f0 275 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 276 b0addr+=4;
mbed_official 133:d4dda5c437f0 277 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 278 b0addr+=4;
mbed_official 133:d4dda5c437f0 279 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 280 b0addr+=4;
mbed_official 133:d4dda5c437f0 281 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 282
mbed_official 133:d4dda5c437f0 283 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 284 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 285
mbed_official 133:d4dda5c437f0 286 /* Get timeout */
mbed_official 133:d4dda5c437f0 287 timeout = HAL_GetTick() + Timeout;
mbed_official 133:d4dda5c437f0 288
mbed_official 133:d4dda5c437f0 289 while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official 133:d4dda5c437f0 290 {
mbed_official 133:d4dda5c437f0 291 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 292 if(Timeout != HAL_MAX_DELAY)
mbed_official 133:d4dda5c437f0 293 {
mbed_official 133:d4dda5c437f0 294 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 295 {
mbed_official 133:d4dda5c437f0 296 /* Change state */
mbed_official 133:d4dda5c437f0 297 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 298
mbed_official 133:d4dda5c437f0 299 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 300 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 301
mbed_official 133:d4dda5c437f0 302 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 303 }
mbed_official 133:d4dda5c437f0 304 }
mbed_official 133:d4dda5c437f0 305 }
mbed_official 133:d4dda5c437f0 306 /***************************** Header phase *******************************/
mbed_official 133:d4dda5c437f0 307 if(headersize != 0)
mbed_official 133:d4dda5c437f0 308 {
mbed_official 133:d4dda5c437f0 309 /* Select header phase */
mbed_official 133:d4dda5c437f0 310 __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
mbed_official 133:d4dda5c437f0 311
mbed_official 133:d4dda5c437f0 312 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 313 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 314
mbed_official 133:d4dda5c437f0 315 for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
mbed_official 133:d4dda5c437f0 316 {
mbed_official 133:d4dda5c437f0 317 /* Get timeout */
mbed_official 133:d4dda5c437f0 318 timeout = HAL_GetTick() + Timeout;
mbed_official 133:d4dda5c437f0 319 while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
mbed_official 133:d4dda5c437f0 320 {
mbed_official 133:d4dda5c437f0 321 {
mbed_official 133:d4dda5c437f0 322 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 323 if(Timeout != HAL_MAX_DELAY)
mbed_official 133:d4dda5c437f0 324 {
mbed_official 133:d4dda5c437f0 325 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 326 {
mbed_official 133:d4dda5c437f0 327 /* Change state */
mbed_official 133:d4dda5c437f0 328 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 329
mbed_official 133:d4dda5c437f0 330 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 331 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 332
mbed_official 133:d4dda5c437f0 333 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 334 }
mbed_official 133:d4dda5c437f0 335 }
mbed_official 133:d4dda5c437f0 336 }
mbed_official 133:d4dda5c437f0 337 }
mbed_official 133:d4dda5c437f0 338 /* Write the header block in the IN FIFO */
mbed_official 133:d4dda5c437f0 339 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 340 headeraddr+=4;
mbed_official 133:d4dda5c437f0 341 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 342 headeraddr+=4;
mbed_official 133:d4dda5c437f0 343 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 344 headeraddr+=4;
mbed_official 133:d4dda5c437f0 345 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 346 headeraddr+=4;
mbed_official 133:d4dda5c437f0 347 }
mbed_official 133:d4dda5c437f0 348
mbed_official 133:d4dda5c437f0 349 /* Get timeout */
mbed_official 133:d4dda5c437f0 350 timeout = HAL_GetTick() + Timeout;
mbed_official 133:d4dda5c437f0 351
mbed_official 133:d4dda5c437f0 352 while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
mbed_official 133:d4dda5c437f0 353 {
mbed_official 133:d4dda5c437f0 354 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 355 if(Timeout != HAL_MAX_DELAY)
mbed_official 133:d4dda5c437f0 356 {
mbed_official 133:d4dda5c437f0 357 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 358 {
mbed_official 133:d4dda5c437f0 359 /* Change state */
mbed_official 133:d4dda5c437f0 360 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 361
mbed_official 133:d4dda5c437f0 362 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 363 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 364
mbed_official 133:d4dda5c437f0 365 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 366 }
mbed_official 133:d4dda5c437f0 367 }
mbed_official 133:d4dda5c437f0 368 }
mbed_official 133:d4dda5c437f0 369 }
mbed_official 133:d4dda5c437f0 370 /* Save formatted counter into the scratch buffer pScratch */
mbed_official 133:d4dda5c437f0 371 for(loopcounter = 0; (loopcounter < 16); loopcounter++)
mbed_official 133:d4dda5c437f0 372 {
mbed_official 133:d4dda5c437f0 373 hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
mbed_official 133:d4dda5c437f0 374 }
mbed_official 133:d4dda5c437f0 375 /* Reset bit 0 */
mbed_official 133:d4dda5c437f0 376 hcryp->Init.pScratch[15] &= 0xfe;
mbed_official 133:d4dda5c437f0 377
mbed_official 133:d4dda5c437f0 378 /* Select payload phase once the header phase is performed */
mbed_official 133:d4dda5c437f0 379 __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official 133:d4dda5c437f0 380
mbed_official 133:d4dda5c437f0 381 /* Flush FIFO */
mbed_official 133:d4dda5c437f0 382 __HAL_CRYP_FIFO_FLUSH();
mbed_official 133:d4dda5c437f0 383
mbed_official 133:d4dda5c437f0 384 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 385 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 386
mbed_official 133:d4dda5c437f0 387 /* Set the phase */
mbed_official 133:d4dda5c437f0 388 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official 133:d4dda5c437f0 389 }
mbed_official 133:d4dda5c437f0 390
mbed_official 133:d4dda5c437f0 391 /* Write Plain Data and Get Cypher Data */
mbed_official 133:d4dda5c437f0 392 if(CRYPEx_GCMCCM_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 393 {
mbed_official 133:d4dda5c437f0 394 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 395 }
mbed_official 133:d4dda5c437f0 396
mbed_official 133:d4dda5c437f0 397 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 398 hcryp->State = HAL_CRYP_STATE_READY;
mbed_official 133:d4dda5c437f0 399
mbed_official 133:d4dda5c437f0 400 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 401 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 402
mbed_official 133:d4dda5c437f0 403 /* Return function status */
mbed_official 133:d4dda5c437f0 404 return HAL_OK;
mbed_official 133:d4dda5c437f0 405 }
mbed_official 133:d4dda5c437f0 406
mbed_official 133:d4dda5c437f0 407 /**
mbed_official 133:d4dda5c437f0 408 * @brief Initializes the CRYP peripheral in AES GCM encryption mode then
mbed_official 133:d4dda5c437f0 409 * encrypt pPlainData. The cypher data are available in pCypherData.
mbed_official 133:d4dda5c437f0 410 * @param hcryp: CRYP handle
mbed_official 133:d4dda5c437f0 411 * @param pPlainData: Pointer to the plaintext buffer
mbed_official 133:d4dda5c437f0 412 * @param Size: Length of the plaintext buffer, must be a multiple of 16
mbed_official 133:d4dda5c437f0 413 * @param pCypherData: Pointer to the cyphertext buffer
mbed_official 133:d4dda5c437f0 414 * @param Timeout: Timeout duration
mbed_official 133:d4dda5c437f0 415 * @retval HAL status
mbed_official 133:d4dda5c437f0 416 */
mbed_official 133:d4dda5c437f0 417 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
mbed_official 133:d4dda5c437f0 418 {
mbed_official 133:d4dda5c437f0 419 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 420
mbed_official 133:d4dda5c437f0 421 /* Process Locked */
mbed_official 133:d4dda5c437f0 422 __HAL_LOCK(hcryp);
mbed_official 133:d4dda5c437f0 423
mbed_official 133:d4dda5c437f0 424 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 425 hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official 133:d4dda5c437f0 426
mbed_official 133:d4dda5c437f0 427 /* Check if initialization phase has already been performed */
mbed_official 133:d4dda5c437f0 428 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official 133:d4dda5c437f0 429 {
mbed_official 133:d4dda5c437f0 430 /* Set the key */
mbed_official 133:d4dda5c437f0 431 CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official 133:d4dda5c437f0 432
mbed_official 133:d4dda5c437f0 433 /* Set the CRYP peripheral in AES GCM mode */
mbed_official 133:d4dda5c437f0 434 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
mbed_official 133:d4dda5c437f0 435
mbed_official 133:d4dda5c437f0 436 /* Set the Initialization Vector */
mbed_official 133:d4dda5c437f0 437 CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
mbed_official 133:d4dda5c437f0 438
mbed_official 133:d4dda5c437f0 439 /* Flush FIFO */
mbed_official 133:d4dda5c437f0 440 __HAL_CRYP_FIFO_FLUSH();
mbed_official 133:d4dda5c437f0 441
mbed_official 133:d4dda5c437f0 442 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 443 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 444
mbed_official 133:d4dda5c437f0 445 /* Get timeout */
mbed_official 133:d4dda5c437f0 446 timeout = HAL_GetTick() + Timeout;
mbed_official 133:d4dda5c437f0 447
mbed_official 133:d4dda5c437f0 448 while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official 133:d4dda5c437f0 449 {
mbed_official 133:d4dda5c437f0 450 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 451 if(Timeout != HAL_MAX_DELAY)
mbed_official 133:d4dda5c437f0 452 {
mbed_official 133:d4dda5c437f0 453 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 454 {
mbed_official 133:d4dda5c437f0 455 /* Change state */
mbed_official 133:d4dda5c437f0 456 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 457
mbed_official 133:d4dda5c437f0 458 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 459 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 460
mbed_official 133:d4dda5c437f0 461 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 462 }
mbed_official 133:d4dda5c437f0 463 }
mbed_official 133:d4dda5c437f0 464 }
mbed_official 133:d4dda5c437f0 465
mbed_official 133:d4dda5c437f0 466 /* Set the header phase */
mbed_official 133:d4dda5c437f0 467 if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 468 {
mbed_official 133:d4dda5c437f0 469 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 470 }
mbed_official 133:d4dda5c437f0 471
mbed_official 133:d4dda5c437f0 472 /* Disable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 473 __HAL_CRYP_DISABLE();
mbed_official 133:d4dda5c437f0 474
mbed_official 133:d4dda5c437f0 475 /* Select payload phase once the header phase is performed */
mbed_official 133:d4dda5c437f0 476 __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official 133:d4dda5c437f0 477
mbed_official 133:d4dda5c437f0 478 /* Flush FIFO */
mbed_official 133:d4dda5c437f0 479 __HAL_CRYP_FIFO_FLUSH();
mbed_official 133:d4dda5c437f0 480
mbed_official 133:d4dda5c437f0 481 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 482 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 483
mbed_official 133:d4dda5c437f0 484 /* Set the phase */
mbed_official 133:d4dda5c437f0 485 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official 133:d4dda5c437f0 486 }
mbed_official 133:d4dda5c437f0 487
mbed_official 133:d4dda5c437f0 488 /* Write Plain Data and Get Cypher Data */
mbed_official 133:d4dda5c437f0 489 if(CRYPEx_GCMCCM_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 490 {
mbed_official 133:d4dda5c437f0 491 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 492 }
mbed_official 133:d4dda5c437f0 493
mbed_official 133:d4dda5c437f0 494 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 495 hcryp->State = HAL_CRYP_STATE_READY;
mbed_official 133:d4dda5c437f0 496
mbed_official 133:d4dda5c437f0 497 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 498 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 499
mbed_official 133:d4dda5c437f0 500 /* Return function status */
mbed_official 133:d4dda5c437f0 501 return HAL_OK;
mbed_official 133:d4dda5c437f0 502 }
mbed_official 133:d4dda5c437f0 503
mbed_official 133:d4dda5c437f0 504 /**
mbed_official 133:d4dda5c437f0 505 * @brief Initializes the CRYP peripheral in AES GCM decryption mode then
mbed_official 133:d4dda5c437f0 506 * decrypted pCypherData. The cypher data are available in pPlainData.
mbed_official 133:d4dda5c437f0 507 * @param hcryp: CRYP handle
mbed_official 133:d4dda5c437f0 508 * @param pCypherData: Pointer to the cyphertext buffer
mbed_official 133:d4dda5c437f0 509 * @param Size: Length of the cyphertext buffer, must be a multiple of 16
mbed_official 133:d4dda5c437f0 510 * @param pPlainData: Pointer to the plaintext buffer
mbed_official 133:d4dda5c437f0 511 * @param Timeout: Timeout duration
mbed_official 133:d4dda5c437f0 512 * @retval HAL status
mbed_official 133:d4dda5c437f0 513 */
mbed_official 133:d4dda5c437f0 514 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
mbed_official 133:d4dda5c437f0 515 {
mbed_official 133:d4dda5c437f0 516 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 517
mbed_official 133:d4dda5c437f0 518 /* Process Locked */
mbed_official 133:d4dda5c437f0 519 __HAL_LOCK(hcryp);
mbed_official 133:d4dda5c437f0 520
mbed_official 133:d4dda5c437f0 521 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 522 hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official 133:d4dda5c437f0 523
mbed_official 133:d4dda5c437f0 524 /* Check if initialization phase has already been performed */
mbed_official 133:d4dda5c437f0 525 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official 133:d4dda5c437f0 526 {
mbed_official 133:d4dda5c437f0 527 /* Set the key */
mbed_official 133:d4dda5c437f0 528 CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official 133:d4dda5c437f0 529
mbed_official 133:d4dda5c437f0 530 /* Set the CRYP peripheral in AES GCM decryption mode */
mbed_official 133:d4dda5c437f0 531 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
mbed_official 133:d4dda5c437f0 532
mbed_official 133:d4dda5c437f0 533 /* Set the Initialization Vector */
mbed_official 133:d4dda5c437f0 534 CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
mbed_official 133:d4dda5c437f0 535
mbed_official 133:d4dda5c437f0 536 /* Flush FIFO */
mbed_official 133:d4dda5c437f0 537 __HAL_CRYP_FIFO_FLUSH();
mbed_official 133:d4dda5c437f0 538
mbed_official 133:d4dda5c437f0 539 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 540 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 541
mbed_official 133:d4dda5c437f0 542 /* Get the timeout */
mbed_official 133:d4dda5c437f0 543 timeout = HAL_GetTick() + Timeout;
mbed_official 133:d4dda5c437f0 544
mbed_official 133:d4dda5c437f0 545 while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official 133:d4dda5c437f0 546 {
mbed_official 133:d4dda5c437f0 547 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 548 if(Timeout != HAL_MAX_DELAY)
mbed_official 133:d4dda5c437f0 549 {
mbed_official 133:d4dda5c437f0 550 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 551 {
mbed_official 133:d4dda5c437f0 552 /* Change state */
mbed_official 133:d4dda5c437f0 553 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 554
mbed_official 133:d4dda5c437f0 555 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 556 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 557
mbed_official 133:d4dda5c437f0 558 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 559 }
mbed_official 133:d4dda5c437f0 560 }
mbed_official 133:d4dda5c437f0 561 }
mbed_official 133:d4dda5c437f0 562
mbed_official 133:d4dda5c437f0 563 /* Set the header phase */
mbed_official 133:d4dda5c437f0 564 if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 565 {
mbed_official 133:d4dda5c437f0 566 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 567 }
mbed_official 133:d4dda5c437f0 568 /* Disable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 569 __HAL_CRYP_DISABLE();
mbed_official 133:d4dda5c437f0 570
mbed_official 133:d4dda5c437f0 571 /* Select payload phase once the header phase is performed */
mbed_official 133:d4dda5c437f0 572 __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official 133:d4dda5c437f0 573
mbed_official 133:d4dda5c437f0 574 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 575 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 576
mbed_official 133:d4dda5c437f0 577 /* Set the phase */
mbed_official 133:d4dda5c437f0 578 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official 133:d4dda5c437f0 579 }
mbed_official 133:d4dda5c437f0 580
mbed_official 133:d4dda5c437f0 581 /* Write Plain Data and Get Cypher Data */
mbed_official 133:d4dda5c437f0 582 if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 583 {
mbed_official 133:d4dda5c437f0 584 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 585 }
mbed_official 133:d4dda5c437f0 586
mbed_official 133:d4dda5c437f0 587 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 588 hcryp->State = HAL_CRYP_STATE_READY;
mbed_official 133:d4dda5c437f0 589
mbed_official 133:d4dda5c437f0 590 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 591 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 592
mbed_official 133:d4dda5c437f0 593 /* Return function status */
mbed_official 133:d4dda5c437f0 594 return HAL_OK;
mbed_official 133:d4dda5c437f0 595 }
mbed_official 133:d4dda5c437f0 596
mbed_official 133:d4dda5c437f0 597 /**
mbed_official 133:d4dda5c437f0 598 * @brief Computes the authentication TAG.
mbed_official 133:d4dda5c437f0 599 * @param hcryp: CRYP handle
mbed_official 133:d4dda5c437f0 600 * @param Size: Total length of the plain/cyphertext buffer
mbed_official 133:d4dda5c437f0 601 * @param AuthTag: Pointer to the authentication buffer
mbed_official 133:d4dda5c437f0 602 * @param Timeout: Timeout duration
mbed_official 133:d4dda5c437f0 603 * @retval HAL status
mbed_official 133:d4dda5c437f0 604 */
mbed_official 133:d4dda5c437f0 605 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint16_t Size, uint8_t *AuthTag, uint32_t Timeout)
mbed_official 133:d4dda5c437f0 606 {
mbed_official 133:d4dda5c437f0 607 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 608 uint32_t headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */
mbed_official 133:d4dda5c437f0 609 uint32_t inputlength = Size * 8; /* input length in bits */
mbed_official 133:d4dda5c437f0 610 uint32_t tagaddr = (uint32_t)AuthTag;
mbed_official 133:d4dda5c437f0 611
mbed_official 133:d4dda5c437f0 612 /* Process Locked */
mbed_official 133:d4dda5c437f0 613 __HAL_LOCK(hcryp);
mbed_official 133:d4dda5c437f0 614
mbed_official 133:d4dda5c437f0 615 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 616 hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official 133:d4dda5c437f0 617
mbed_official 133:d4dda5c437f0 618 /* Check if initialization phase has already been performed */
mbed_official 133:d4dda5c437f0 619 if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)
mbed_official 133:d4dda5c437f0 620 {
mbed_official 133:d4dda5c437f0 621 /* Change the CRYP phase */
mbed_official 133:d4dda5c437f0 622 hcryp->Phase = HAL_CRYP_PHASE_FINAL;
mbed_official 133:d4dda5c437f0 623
mbed_official 133:d4dda5c437f0 624 /* Disable CRYP to start the final phase */
mbed_official 133:d4dda5c437f0 625 __HAL_CRYP_DISABLE();
mbed_official 133:d4dda5c437f0 626
mbed_official 133:d4dda5c437f0 627 /* Select final phase */
mbed_official 133:d4dda5c437f0 628 __HAL_CRYP_SET_PHASE(CRYP_PHASE_FINAL);
mbed_official 133:d4dda5c437f0 629
mbed_official 133:d4dda5c437f0 630 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 631 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 632
mbed_official 133:d4dda5c437f0 633 /* Write the number of bits in header (64 bits) followed by the number of bits
mbed_official 133:d4dda5c437f0 634 in the payload */
mbed_official 133:d4dda5c437f0 635 if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
mbed_official 133:d4dda5c437f0 636 {
mbed_official 133:d4dda5c437f0 637 CRYP->DR = 0;
mbed_official 133:d4dda5c437f0 638 CRYP->DR = __RBIT(headerlength);
mbed_official 133:d4dda5c437f0 639 CRYP->DR = 0;
mbed_official 133:d4dda5c437f0 640 CRYP->DR = __RBIT(inputlength);
mbed_official 133:d4dda5c437f0 641 }
mbed_official 133:d4dda5c437f0 642 else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
mbed_official 133:d4dda5c437f0 643 {
mbed_official 133:d4dda5c437f0 644 CRYP->DR = 0;
mbed_official 133:d4dda5c437f0 645 CRYP->DR = __REV(headerlength);
mbed_official 133:d4dda5c437f0 646 CRYP->DR = 0;
mbed_official 133:d4dda5c437f0 647 CRYP->DR = __REV(inputlength);
mbed_official 133:d4dda5c437f0 648 }
mbed_official 133:d4dda5c437f0 649 else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
mbed_official 133:d4dda5c437f0 650 {
mbed_official 133:d4dda5c437f0 651 CRYP->DR = 0;
mbed_official 133:d4dda5c437f0 652 CRYP->DR = __REV16(headerlength);
mbed_official 133:d4dda5c437f0 653 CRYP->DR = 0;
mbed_official 133:d4dda5c437f0 654 CRYP->DR = __REV16(inputlength);
mbed_official 133:d4dda5c437f0 655 }
mbed_official 133:d4dda5c437f0 656 else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
mbed_official 133:d4dda5c437f0 657 {
mbed_official 133:d4dda5c437f0 658 CRYP->DR = 0;
mbed_official 133:d4dda5c437f0 659 CRYP->DR = (uint32_t)(headerlength);
mbed_official 133:d4dda5c437f0 660 CRYP->DR = 0;
mbed_official 133:d4dda5c437f0 661 CRYP->DR = (uint32_t)(inputlength);
mbed_official 133:d4dda5c437f0 662 }
mbed_official 133:d4dda5c437f0 663 /* Get timeout */
mbed_official 133:d4dda5c437f0 664 timeout = HAL_GetTick() + Timeout;
mbed_official 133:d4dda5c437f0 665
mbed_official 133:d4dda5c437f0 666 while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
mbed_official 133:d4dda5c437f0 667 {
mbed_official 133:d4dda5c437f0 668 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 669 if(Timeout != HAL_MAX_DELAY)
mbed_official 133:d4dda5c437f0 670 {
mbed_official 133:d4dda5c437f0 671 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 672 {
mbed_official 133:d4dda5c437f0 673 /* Change state */
mbed_official 133:d4dda5c437f0 674 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 675
mbed_official 133:d4dda5c437f0 676 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 677 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 678
mbed_official 133:d4dda5c437f0 679 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 680 }
mbed_official 133:d4dda5c437f0 681 }
mbed_official 133:d4dda5c437f0 682 }
mbed_official 133:d4dda5c437f0 683
mbed_official 133:d4dda5c437f0 684 /* Read the Auth TAG in the IN FIFO */
mbed_official 133:d4dda5c437f0 685 *(uint32_t*)(tagaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 686 tagaddr+=4;
mbed_official 133:d4dda5c437f0 687 *(uint32_t*)(tagaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 688 tagaddr+=4;
mbed_official 133:d4dda5c437f0 689 *(uint32_t*)(tagaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 690 tagaddr+=4;
mbed_official 133:d4dda5c437f0 691 *(uint32_t*)(tagaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 692 }
mbed_official 133:d4dda5c437f0 693
mbed_official 133:d4dda5c437f0 694 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 695 hcryp->State = HAL_CRYP_STATE_READY;
mbed_official 133:d4dda5c437f0 696
mbed_official 133:d4dda5c437f0 697 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 698 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 699
mbed_official 133:d4dda5c437f0 700 /* Return function status */
mbed_official 133:d4dda5c437f0 701 return HAL_OK;
mbed_official 133:d4dda5c437f0 702 }
mbed_official 133:d4dda5c437f0 703
mbed_official 133:d4dda5c437f0 704 /**
mbed_official 133:d4dda5c437f0 705 * @brief Computes the authentication TAG for AES CCM mode.
mbed_official 133:d4dda5c437f0 706 * @note This API is called after HAL_AES_CCM_Encrypt()/HAL_AES_CCM_Decrypt()
mbed_official 133:d4dda5c437f0 707 * @param hcryp: CRYP handle
mbed_official 133:d4dda5c437f0 708 * @param AuthTag: Pointer to the authentication buffer
mbed_official 133:d4dda5c437f0 709 * @param Timeout: Timeout duration
mbed_official 133:d4dda5c437f0 710 * @retval HAL status
mbed_official 133:d4dda5c437f0 711 */
mbed_official 133:d4dda5c437f0 712 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout)
mbed_official 133:d4dda5c437f0 713 {
mbed_official 133:d4dda5c437f0 714 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 715 uint32_t tagaddr = (uint32_t)AuthTag;
mbed_official 133:d4dda5c437f0 716 uint32_t ctraddr = (uint32_t)hcryp->Init.pScratch;
mbed_official 133:d4dda5c437f0 717 uint32_t temptag[4] = {0}; /* Temporary TAG (MAC) */
mbed_official 133:d4dda5c437f0 718 uint32_t loopcounter;
mbed_official 133:d4dda5c437f0 719
mbed_official 133:d4dda5c437f0 720 /* Process Locked */
mbed_official 133:d4dda5c437f0 721 __HAL_LOCK(hcryp);
mbed_official 133:d4dda5c437f0 722
mbed_official 133:d4dda5c437f0 723 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 724 hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official 133:d4dda5c437f0 725
mbed_official 133:d4dda5c437f0 726 /* Check if initialization phase has already been performed */
mbed_official 133:d4dda5c437f0 727 if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)
mbed_official 133:d4dda5c437f0 728 {
mbed_official 133:d4dda5c437f0 729 /* Change the CRYP phase */
mbed_official 133:d4dda5c437f0 730 hcryp->Phase = HAL_CRYP_PHASE_FINAL;
mbed_official 133:d4dda5c437f0 731
mbed_official 133:d4dda5c437f0 732 /* Disable CRYP to start the final phase */
mbed_official 133:d4dda5c437f0 733 __HAL_CRYP_DISABLE();
mbed_official 133:d4dda5c437f0 734
mbed_official 133:d4dda5c437f0 735 /* Select final phase */
mbed_official 133:d4dda5c437f0 736 __HAL_CRYP_SET_PHASE(CRYP_PHASE_FINAL);
mbed_official 133:d4dda5c437f0 737
mbed_official 133:d4dda5c437f0 738 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 739 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 740
mbed_official 133:d4dda5c437f0 741 /* Write the counter block in the IN FIFO */
mbed_official 133:d4dda5c437f0 742 CRYP->DR = *(uint32_t*)ctraddr;
mbed_official 133:d4dda5c437f0 743 ctraddr+=4;
mbed_official 133:d4dda5c437f0 744 CRYP->DR = *(uint32_t*)ctraddr;
mbed_official 133:d4dda5c437f0 745 ctraddr+=4;
mbed_official 133:d4dda5c437f0 746 CRYP->DR = *(uint32_t*)ctraddr;
mbed_official 133:d4dda5c437f0 747 ctraddr+=4;
mbed_official 133:d4dda5c437f0 748 CRYP->DR = *(uint32_t*)ctraddr;
mbed_official 133:d4dda5c437f0 749
mbed_official 133:d4dda5c437f0 750 /* Get timeout */
mbed_official 133:d4dda5c437f0 751 timeout = HAL_GetTick() + Timeout;
mbed_official 133:d4dda5c437f0 752
mbed_official 133:d4dda5c437f0 753 while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
mbed_official 133:d4dda5c437f0 754 {
mbed_official 133:d4dda5c437f0 755 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 756 if(Timeout != HAL_MAX_DELAY)
mbed_official 133:d4dda5c437f0 757 {
mbed_official 133:d4dda5c437f0 758 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 759 {
mbed_official 133:d4dda5c437f0 760 /* Change state */
mbed_official 133:d4dda5c437f0 761 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 762
mbed_official 133:d4dda5c437f0 763 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 764 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 765
mbed_official 133:d4dda5c437f0 766 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 767 }
mbed_official 133:d4dda5c437f0 768 }
mbed_official 133:d4dda5c437f0 769 }
mbed_official 133:d4dda5c437f0 770
mbed_official 133:d4dda5c437f0 771 /* Read the Auth TAG in the IN FIFO */
mbed_official 133:d4dda5c437f0 772 temptag[0] = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 773 temptag[1] = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 774 temptag[2] = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 775 temptag[3] = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 776 }
mbed_official 133:d4dda5c437f0 777
mbed_official 133:d4dda5c437f0 778 /* Copy temporary authentication TAG in user TAG buffer */
mbed_official 133:d4dda5c437f0 779 for(loopcounter = 0; loopcounter < hcryp->Init.TagSize ; loopcounter++)
mbed_official 133:d4dda5c437f0 780 {
mbed_official 133:d4dda5c437f0 781 /* Set the authentication TAG buffer */
mbed_official 133:d4dda5c437f0 782 *((uint8_t*)tagaddr+loopcounter) = *((uint8_t*)temptag+loopcounter);
mbed_official 133:d4dda5c437f0 783 }
mbed_official 133:d4dda5c437f0 784
mbed_official 133:d4dda5c437f0 785 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 786 hcryp->State = HAL_CRYP_STATE_READY;
mbed_official 133:d4dda5c437f0 787
mbed_official 133:d4dda5c437f0 788 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 789 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 790
mbed_official 133:d4dda5c437f0 791 /* Return function status */
mbed_official 133:d4dda5c437f0 792 return HAL_OK;
mbed_official 133:d4dda5c437f0 793 }
mbed_official 133:d4dda5c437f0 794
mbed_official 133:d4dda5c437f0 795 /**
mbed_official 133:d4dda5c437f0 796 * @brief Initializes the CRYP peripheral in AES CCM decryption mode then
mbed_official 133:d4dda5c437f0 797 * decrypted pCypherData. The cypher data are available in pPlainData.
mbed_official 133:d4dda5c437f0 798 * @param hcryp: CRYP handle
mbed_official 133:d4dda5c437f0 799 * @param pPlainData: Pointer to the plaintext buffer
mbed_official 133:d4dda5c437f0 800 * @param Size: Length of the plaintext buffer, must be a multiple of 16
mbed_official 133:d4dda5c437f0 801 * @param pCypherData: Pointer to the cyphertext buffer
mbed_official 133:d4dda5c437f0 802 * @param Timeout: Timeout duration
mbed_official 133:d4dda5c437f0 803 * @retval HAL status
mbed_official 133:d4dda5c437f0 804 */
mbed_official 133:d4dda5c437f0 805 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
mbed_official 133:d4dda5c437f0 806 {
mbed_official 133:d4dda5c437f0 807 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 808 uint32_t headersize = hcryp->Init.HeaderSize;
mbed_official 133:d4dda5c437f0 809 uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
mbed_official 133:d4dda5c437f0 810 uint32_t loopcounter = 0;
mbed_official 133:d4dda5c437f0 811 uint32_t bufferidx = 0;
mbed_official 133:d4dda5c437f0 812 uint8_t blockb0[16] = {0};/* Block B0 */
mbed_official 133:d4dda5c437f0 813 uint8_t ctr[16] = {0}; /* Counter */
mbed_official 133:d4dda5c437f0 814 uint32_t b0addr = (uint32_t)blockb0;
mbed_official 133:d4dda5c437f0 815
mbed_official 133:d4dda5c437f0 816 /* Process Locked */
mbed_official 133:d4dda5c437f0 817 __HAL_LOCK(hcryp);
mbed_official 133:d4dda5c437f0 818
mbed_official 133:d4dda5c437f0 819 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 820 hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official 133:d4dda5c437f0 821
mbed_official 133:d4dda5c437f0 822 /* Check if initialization phase has already been performed */
mbed_official 133:d4dda5c437f0 823 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official 133:d4dda5c437f0 824 {
mbed_official 133:d4dda5c437f0 825 /************************ Formatting the header block *********************/
mbed_official 133:d4dda5c437f0 826 if(headersize != 0)
mbed_official 133:d4dda5c437f0 827 {
mbed_official 133:d4dda5c437f0 828 /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
mbed_official 133:d4dda5c437f0 829 if(headersize < 65280)
mbed_official 133:d4dda5c437f0 830 {
mbed_official 133:d4dda5c437f0 831 hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
mbed_official 133:d4dda5c437f0 832 hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
mbed_official 133:d4dda5c437f0 833 headersize += 2;
mbed_official 133:d4dda5c437f0 834 }
mbed_official 133:d4dda5c437f0 835 else
mbed_official 133:d4dda5c437f0 836 {
mbed_official 133:d4dda5c437f0 837 /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
mbed_official 133:d4dda5c437f0 838 hcryp->Init.pScratch[bufferidx++] = 0xFF;
mbed_official 133:d4dda5c437f0 839 hcryp->Init.pScratch[bufferidx++] = 0xFE;
mbed_official 133:d4dda5c437f0 840 hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
mbed_official 133:d4dda5c437f0 841 hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
mbed_official 133:d4dda5c437f0 842 hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
mbed_official 133:d4dda5c437f0 843 hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
mbed_official 133:d4dda5c437f0 844 headersize += 6;
mbed_official 133:d4dda5c437f0 845 }
mbed_official 133:d4dda5c437f0 846 /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
mbed_official 133:d4dda5c437f0 847 for(loopcounter = 0; loopcounter < headersize; loopcounter++)
mbed_official 133:d4dda5c437f0 848 {
mbed_official 133:d4dda5c437f0 849 hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
mbed_official 133:d4dda5c437f0 850 }
mbed_official 133:d4dda5c437f0 851 /* Check if the header size is modulo 16 */
mbed_official 133:d4dda5c437f0 852 if ((headersize % 16) != 0)
mbed_official 133:d4dda5c437f0 853 {
mbed_official 133:d4dda5c437f0 854 /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
mbed_official 133:d4dda5c437f0 855 for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
mbed_official 133:d4dda5c437f0 856 {
mbed_official 133:d4dda5c437f0 857 hcryp->Init.pScratch[loopcounter] = 0;
mbed_official 133:d4dda5c437f0 858 }
mbed_official 133:d4dda5c437f0 859 /* Set the header size to modulo 16 */
mbed_official 133:d4dda5c437f0 860 headersize = ((headersize/16) + 1) * 16;
mbed_official 133:d4dda5c437f0 861 }
mbed_official 133:d4dda5c437f0 862 /* Set the pointer headeraddr to hcryp->Init.pScratch */
mbed_official 133:d4dda5c437f0 863 headeraddr = (uint32_t)hcryp->Init.pScratch;
mbed_official 133:d4dda5c437f0 864 }
mbed_official 133:d4dda5c437f0 865 /*********************** Formatting the block B0 **************************/
mbed_official 133:d4dda5c437f0 866 if(headersize != 0)
mbed_official 133:d4dda5c437f0 867 {
mbed_official 133:d4dda5c437f0 868 blockb0[0] = 0x40;
mbed_official 133:d4dda5c437f0 869 }
mbed_official 133:d4dda5c437f0 870 /* Flags byte */
mbed_official 133:d4dda5c437f0 871 /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
mbed_official 133:d4dda5c437f0 872 blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
mbed_official 133:d4dda5c437f0 873 blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
mbed_official 133:d4dda5c437f0 874
mbed_official 133:d4dda5c437f0 875 for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
mbed_official 133:d4dda5c437f0 876 {
mbed_official 133:d4dda5c437f0 877 blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
mbed_official 133:d4dda5c437f0 878 }
mbed_official 133:d4dda5c437f0 879 for ( ; loopcounter < 13; loopcounter++)
mbed_official 133:d4dda5c437f0 880 {
mbed_official 133:d4dda5c437f0 881 blockb0[loopcounter+1] = 0;
mbed_official 133:d4dda5c437f0 882 }
mbed_official 133:d4dda5c437f0 883
mbed_official 133:d4dda5c437f0 884 blockb0[14] = (Size >> 8);
mbed_official 133:d4dda5c437f0 885 blockb0[15] = (Size & 0xFF);
mbed_official 133:d4dda5c437f0 886
mbed_official 133:d4dda5c437f0 887 /************************* Formatting the initial counter *****************/
mbed_official 133:d4dda5c437f0 888 /* Byte 0:
mbed_official 133:d4dda5c437f0 889 Bits 7 and 6 are reserved and shall be set to 0
mbed_official 133:d4dda5c437f0 890 Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
mbed_official 133:d4dda5c437f0 891 blocks are distinct from B0
mbed_official 133:d4dda5c437f0 892 Bits 0, 1, and 2 contain the same encoding of q as in B0
mbed_official 133:d4dda5c437f0 893 */
mbed_official 133:d4dda5c437f0 894 ctr[0] = blockb0[0] & 0x07;
mbed_official 133:d4dda5c437f0 895 /* byte 1 to NonceSize is the IV (Nonce) */
mbed_official 133:d4dda5c437f0 896 for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
mbed_official 133:d4dda5c437f0 897 {
mbed_official 133:d4dda5c437f0 898 ctr[loopcounter] = blockb0[loopcounter];
mbed_official 133:d4dda5c437f0 899 }
mbed_official 133:d4dda5c437f0 900 /* Set the LSB to 1 */
mbed_official 133:d4dda5c437f0 901 ctr[15] |= 0x01;
mbed_official 133:d4dda5c437f0 902
mbed_official 133:d4dda5c437f0 903 /* Set the key */
mbed_official 133:d4dda5c437f0 904 CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official 133:d4dda5c437f0 905
mbed_official 133:d4dda5c437f0 906 /* Set the CRYP peripheral in AES CCM mode */
mbed_official 133:d4dda5c437f0 907 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
mbed_official 133:d4dda5c437f0 908
mbed_official 133:d4dda5c437f0 909 /* Set the Initialization Vector */
mbed_official 133:d4dda5c437f0 910 CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, CRYP_KEYSIZE_128B);
mbed_official 133:d4dda5c437f0 911
mbed_official 133:d4dda5c437f0 912 /* Select init phase */
mbed_official 133:d4dda5c437f0 913 __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
mbed_official 133:d4dda5c437f0 914
mbed_official 133:d4dda5c437f0 915 b0addr = (uint32_t)blockb0;
mbed_official 133:d4dda5c437f0 916 /* Write the blockb0 block in the IN FIFO */
mbed_official 133:d4dda5c437f0 917 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 918 b0addr+=4;
mbed_official 133:d4dda5c437f0 919 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 920 b0addr+=4;
mbed_official 133:d4dda5c437f0 921 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 922 b0addr+=4;
mbed_official 133:d4dda5c437f0 923 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 924
mbed_official 133:d4dda5c437f0 925 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 926 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 927
mbed_official 133:d4dda5c437f0 928 /* Get timeout */
mbed_official 133:d4dda5c437f0 929 timeout = HAL_GetTick() + Timeout;
mbed_official 133:d4dda5c437f0 930
mbed_official 133:d4dda5c437f0 931 while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official 133:d4dda5c437f0 932 {
mbed_official 133:d4dda5c437f0 933 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 934 if(Timeout != HAL_MAX_DELAY)
mbed_official 133:d4dda5c437f0 935 {
mbed_official 133:d4dda5c437f0 936 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 937 {
mbed_official 133:d4dda5c437f0 938 /* Change state */
mbed_official 133:d4dda5c437f0 939 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 940
mbed_official 133:d4dda5c437f0 941 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 942 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 943
mbed_official 133:d4dda5c437f0 944 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 945 }
mbed_official 133:d4dda5c437f0 946 }
mbed_official 133:d4dda5c437f0 947 }
mbed_official 133:d4dda5c437f0 948 /***************************** Header phase *******************************/
mbed_official 133:d4dda5c437f0 949 if(headersize != 0)
mbed_official 133:d4dda5c437f0 950 {
mbed_official 133:d4dda5c437f0 951 /* Select header phase */
mbed_official 133:d4dda5c437f0 952 __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
mbed_official 133:d4dda5c437f0 953
mbed_official 133:d4dda5c437f0 954 /* Enable Crypto processor */
mbed_official 133:d4dda5c437f0 955 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 956
mbed_official 133:d4dda5c437f0 957 for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
mbed_official 133:d4dda5c437f0 958 {
mbed_official 133:d4dda5c437f0 959 /* Get timeout */
mbed_official 133:d4dda5c437f0 960 timeout = HAL_GetTick() + Timeout;
mbed_official 133:d4dda5c437f0 961
mbed_official 133:d4dda5c437f0 962 while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
mbed_official 133:d4dda5c437f0 963 {
mbed_official 133:d4dda5c437f0 964 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 965 if(Timeout != HAL_MAX_DELAY)
mbed_official 133:d4dda5c437f0 966 {
mbed_official 133:d4dda5c437f0 967 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 968 {
mbed_official 133:d4dda5c437f0 969 /* Change state */
mbed_official 133:d4dda5c437f0 970 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 971
mbed_official 133:d4dda5c437f0 972 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 973 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 974
mbed_official 133:d4dda5c437f0 975 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 976 }
mbed_official 133:d4dda5c437f0 977 }
mbed_official 133:d4dda5c437f0 978 }
mbed_official 133:d4dda5c437f0 979 /* Write the header block in the IN FIFO */
mbed_official 133:d4dda5c437f0 980 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 981 headeraddr+=4;
mbed_official 133:d4dda5c437f0 982 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 983 headeraddr+=4;
mbed_official 133:d4dda5c437f0 984 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 985 headeraddr+=4;
mbed_official 133:d4dda5c437f0 986 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 987 headeraddr+=4;
mbed_official 133:d4dda5c437f0 988 }
mbed_official 133:d4dda5c437f0 989
mbed_official 133:d4dda5c437f0 990 /* Get timeout */
mbed_official 133:d4dda5c437f0 991 timeout = HAL_GetTick() + Timeout;
mbed_official 133:d4dda5c437f0 992
mbed_official 133:d4dda5c437f0 993 while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
mbed_official 133:d4dda5c437f0 994 {
mbed_official 133:d4dda5c437f0 995 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 996 if(Timeout != HAL_MAX_DELAY)
mbed_official 133:d4dda5c437f0 997 {
mbed_official 133:d4dda5c437f0 998 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 999 {
mbed_official 133:d4dda5c437f0 1000 /* Change state */
mbed_official 133:d4dda5c437f0 1001 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 1002
mbed_official 133:d4dda5c437f0 1003 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1004 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 1005
mbed_official 133:d4dda5c437f0 1006 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 1007 }
mbed_official 133:d4dda5c437f0 1008 }
mbed_official 133:d4dda5c437f0 1009 }
mbed_official 133:d4dda5c437f0 1010 }
mbed_official 133:d4dda5c437f0 1011 /* Save formatted counter into the scratch buffer pScratch */
mbed_official 133:d4dda5c437f0 1012 for(loopcounter = 0; (loopcounter < 16); loopcounter++)
mbed_official 133:d4dda5c437f0 1013 {
mbed_official 133:d4dda5c437f0 1014 hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
mbed_official 133:d4dda5c437f0 1015 }
mbed_official 133:d4dda5c437f0 1016 /* Reset bit 0 */
mbed_official 133:d4dda5c437f0 1017 hcryp->Init.pScratch[15] &= 0xfe;
mbed_official 133:d4dda5c437f0 1018 /* Select payload phase once the header phase is performed */
mbed_official 133:d4dda5c437f0 1019 __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official 133:d4dda5c437f0 1020
mbed_official 133:d4dda5c437f0 1021 /* Flush FIFO */
mbed_official 133:d4dda5c437f0 1022 __HAL_CRYP_FIFO_FLUSH();
mbed_official 133:d4dda5c437f0 1023
mbed_official 133:d4dda5c437f0 1024 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 1025 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 1026
mbed_official 133:d4dda5c437f0 1027 /* Set the phase */
mbed_official 133:d4dda5c437f0 1028 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official 133:d4dda5c437f0 1029 }
mbed_official 133:d4dda5c437f0 1030
mbed_official 133:d4dda5c437f0 1031 /* Write Plain Data and Get Cypher Data */
mbed_official 133:d4dda5c437f0 1032 if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 1033 {
mbed_official 133:d4dda5c437f0 1034 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 1035 }
mbed_official 133:d4dda5c437f0 1036
mbed_official 133:d4dda5c437f0 1037 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 1038 hcryp->State = HAL_CRYP_STATE_READY;
mbed_official 133:d4dda5c437f0 1039
mbed_official 133:d4dda5c437f0 1040 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1041 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 1042
mbed_official 133:d4dda5c437f0 1043 /* Return function status */
mbed_official 133:d4dda5c437f0 1044 return HAL_OK;
mbed_official 133:d4dda5c437f0 1045 }
mbed_official 133:d4dda5c437f0 1046
mbed_official 133:d4dda5c437f0 1047 /**
mbed_official 133:d4dda5c437f0 1048 * @brief Initializes the CRYP peripheral in AES GCM encryption mode using IT.
mbed_official 133:d4dda5c437f0 1049 * @param hcryp: CRYP handle
mbed_official 133:d4dda5c437f0 1050 * @param pPlainData: Pointer to the plaintext buffer
mbed_official 133:d4dda5c437f0 1051 * @param Size: Length of the plaintext buffer, must be a multiple of 16
mbed_official 133:d4dda5c437f0 1052 * @param pCypherData: Pointer to the cyphertext buffer
mbed_official 133:d4dda5c437f0 1053 * @retval HAL status
mbed_official 133:d4dda5c437f0 1054 */
mbed_official 133:d4dda5c437f0 1055 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
mbed_official 133:d4dda5c437f0 1056 {
mbed_official 133:d4dda5c437f0 1057 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 1058 uint32_t inputaddr;
mbed_official 133:d4dda5c437f0 1059 uint32_t outputaddr;
mbed_official 133:d4dda5c437f0 1060
mbed_official 133:d4dda5c437f0 1061 if(hcryp->State == HAL_CRYP_STATE_READY)
mbed_official 133:d4dda5c437f0 1062 {
mbed_official 133:d4dda5c437f0 1063 /* Process Locked */
mbed_official 133:d4dda5c437f0 1064 __HAL_LOCK(hcryp);
mbed_official 133:d4dda5c437f0 1065
mbed_official 133:d4dda5c437f0 1066 /* Get the buffer addresses and sizes */
mbed_official 133:d4dda5c437f0 1067 hcryp->CrypInCount = Size;
mbed_official 133:d4dda5c437f0 1068 hcryp->pCrypInBuffPtr = pPlainData;
mbed_official 133:d4dda5c437f0 1069 hcryp->pCrypOutBuffPtr = pCypherData;
mbed_official 133:d4dda5c437f0 1070 hcryp->CrypOutCount = Size;
mbed_official 133:d4dda5c437f0 1071
mbed_official 133:d4dda5c437f0 1072 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 1073 hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official 133:d4dda5c437f0 1074
mbed_official 133:d4dda5c437f0 1075 /* Check if initialization phase has already been performed */
mbed_official 133:d4dda5c437f0 1076 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official 133:d4dda5c437f0 1077 {
mbed_official 133:d4dda5c437f0 1078 /* Set the key */
mbed_official 133:d4dda5c437f0 1079 CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official 133:d4dda5c437f0 1080
mbed_official 133:d4dda5c437f0 1081 /* Set the CRYP peripheral in AES GCM mode */
mbed_official 133:d4dda5c437f0 1082 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
mbed_official 133:d4dda5c437f0 1083
mbed_official 133:d4dda5c437f0 1084 /* Set the Initialization Vector */
mbed_official 133:d4dda5c437f0 1085 CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
mbed_official 133:d4dda5c437f0 1086
mbed_official 133:d4dda5c437f0 1087 /* Flush FIFO */
mbed_official 133:d4dda5c437f0 1088 __HAL_CRYP_FIFO_FLUSH();
mbed_official 133:d4dda5c437f0 1089
mbed_official 133:d4dda5c437f0 1090 /* Enable CRYP to start the init phase */
mbed_official 133:d4dda5c437f0 1091 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 1092
mbed_official 133:d4dda5c437f0 1093 /* Get timeout */
mbed_official 133:d4dda5c437f0 1094 timeout = HAL_GetTick() + 1;
mbed_official 133:d4dda5c437f0 1095
mbed_official 133:d4dda5c437f0 1096 while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official 133:d4dda5c437f0 1097 {
mbed_official 133:d4dda5c437f0 1098 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 1099
mbed_official 133:d4dda5c437f0 1100 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 1101 {
mbed_official 133:d4dda5c437f0 1102 /* Change state */
mbed_official 133:d4dda5c437f0 1103 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 1104
mbed_official 133:d4dda5c437f0 1105 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1106 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 1107
mbed_official 133:d4dda5c437f0 1108 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 1109
mbed_official 133:d4dda5c437f0 1110 }
mbed_official 133:d4dda5c437f0 1111 }
mbed_official 133:d4dda5c437f0 1112
mbed_official 133:d4dda5c437f0 1113 /* Set the header phase */
mbed_official 133:d4dda5c437f0 1114 if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
mbed_official 133:d4dda5c437f0 1115 {
mbed_official 133:d4dda5c437f0 1116 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 1117 }
mbed_official 133:d4dda5c437f0 1118 /* Disable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 1119 __HAL_CRYP_DISABLE();
mbed_official 133:d4dda5c437f0 1120
mbed_official 133:d4dda5c437f0 1121 /* Select payload phase once the header phase is performed */
mbed_official 133:d4dda5c437f0 1122 __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official 133:d4dda5c437f0 1123
mbed_official 133:d4dda5c437f0 1124 /* Flush FIFO */
mbed_official 133:d4dda5c437f0 1125 __HAL_CRYP_FIFO_FLUSH();
mbed_official 133:d4dda5c437f0 1126
mbed_official 133:d4dda5c437f0 1127 /* Set the phase */
mbed_official 133:d4dda5c437f0 1128 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official 133:d4dda5c437f0 1129 }
mbed_official 133:d4dda5c437f0 1130
mbed_official 133:d4dda5c437f0 1131 if(Size != 0)
mbed_official 133:d4dda5c437f0 1132 {
mbed_official 133:d4dda5c437f0 1133 /* Enable Interrupts */
mbed_official 133:d4dda5c437f0 1134 __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
mbed_official 133:d4dda5c437f0 1135 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 1136 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 1137 }
mbed_official 133:d4dda5c437f0 1138 else
mbed_official 133:d4dda5c437f0 1139 {
mbed_official 133:d4dda5c437f0 1140 /* Process Locked */
mbed_official 133:d4dda5c437f0 1141 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 1142 /* Change the CRYP state and phase */
mbed_official 133:d4dda5c437f0 1143 hcryp->State = HAL_CRYP_STATE_READY;
mbed_official 133:d4dda5c437f0 1144 }
mbed_official 133:d4dda5c437f0 1145 /* Return function status */
mbed_official 133:d4dda5c437f0 1146 return HAL_OK;
mbed_official 133:d4dda5c437f0 1147 }
mbed_official 133:d4dda5c437f0 1148 else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
mbed_official 133:d4dda5c437f0 1149 {
mbed_official 133:d4dda5c437f0 1150 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
mbed_official 133:d4dda5c437f0 1151 /* Write the Input block in the IN FIFO */
mbed_official 133:d4dda5c437f0 1152 CRYP->DR = *(uint32_t*)(inputaddr);
mbed_official 133:d4dda5c437f0 1153 inputaddr+=4;
mbed_official 133:d4dda5c437f0 1154 CRYP->DR = *(uint32_t*)(inputaddr);
mbed_official 133:d4dda5c437f0 1155 inputaddr+=4;
mbed_official 133:d4dda5c437f0 1156 CRYP->DR = *(uint32_t*)(inputaddr);
mbed_official 133:d4dda5c437f0 1157 inputaddr+=4;
mbed_official 133:d4dda5c437f0 1158 CRYP->DR = *(uint32_t*)(inputaddr);
mbed_official 133:d4dda5c437f0 1159 hcryp->pCrypInBuffPtr += 16;
mbed_official 133:d4dda5c437f0 1160 hcryp->CrypInCount -= 16;
mbed_official 133:d4dda5c437f0 1161 if(hcryp->CrypInCount == 0)
mbed_official 133:d4dda5c437f0 1162 {
mbed_official 133:d4dda5c437f0 1163 __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
mbed_official 133:d4dda5c437f0 1164 /* Call the Input data transfer complete callback */
mbed_official 133:d4dda5c437f0 1165 HAL_CRYP_InCpltCallback(hcryp);
mbed_official 133:d4dda5c437f0 1166 }
mbed_official 133:d4dda5c437f0 1167 }
mbed_official 133:d4dda5c437f0 1168 else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
mbed_official 133:d4dda5c437f0 1169 {
mbed_official 133:d4dda5c437f0 1170 outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
mbed_official 133:d4dda5c437f0 1171 /* Read the Output block from the Output FIFO */
mbed_official 133:d4dda5c437f0 1172 *(uint32_t*)(outputaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 1173 outputaddr+=4;
mbed_official 133:d4dda5c437f0 1174 *(uint32_t*)(outputaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 1175 outputaddr+=4;
mbed_official 133:d4dda5c437f0 1176 *(uint32_t*)(outputaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 1177 outputaddr+=4;
mbed_official 133:d4dda5c437f0 1178 *(uint32_t*)(outputaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 1179 hcryp->pCrypOutBuffPtr += 16;
mbed_official 133:d4dda5c437f0 1180 hcryp->CrypOutCount -= 16;
mbed_official 133:d4dda5c437f0 1181 if(hcryp->CrypOutCount == 0)
mbed_official 133:d4dda5c437f0 1182 {
mbed_official 133:d4dda5c437f0 1183 __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
mbed_official 133:d4dda5c437f0 1184 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1185 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 1186 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 1187 hcryp->State = HAL_CRYP_STATE_READY;
mbed_official 133:d4dda5c437f0 1188 /* Call Input transfer complete callback */
mbed_official 133:d4dda5c437f0 1189 HAL_CRYP_OutCpltCallback(hcryp);
mbed_official 133:d4dda5c437f0 1190 }
mbed_official 133:d4dda5c437f0 1191 }
mbed_official 133:d4dda5c437f0 1192
mbed_official 133:d4dda5c437f0 1193 /* Return function status */
mbed_official 133:d4dda5c437f0 1194 return HAL_OK;
mbed_official 133:d4dda5c437f0 1195 }
mbed_official 133:d4dda5c437f0 1196
mbed_official 133:d4dda5c437f0 1197 /**
mbed_official 133:d4dda5c437f0 1198 * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.
mbed_official 133:d4dda5c437f0 1199 * @param hcryp: CRYP handle
mbed_official 133:d4dda5c437f0 1200 * @param pPlainData: Pointer to the plaintext buffer
mbed_official 133:d4dda5c437f0 1201 * @param Size: Length of the plaintext buffer, must be a multiple of 16
mbed_official 133:d4dda5c437f0 1202 * @param pCypherData: Pointer to the cyphertext buffer
mbed_official 133:d4dda5c437f0 1203 * @retval HAL status
mbed_official 133:d4dda5c437f0 1204 */
mbed_official 133:d4dda5c437f0 1205 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
mbed_official 133:d4dda5c437f0 1206 {
mbed_official 133:d4dda5c437f0 1207 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 1208 uint32_t inputaddr;
mbed_official 133:d4dda5c437f0 1209 uint32_t outputaddr;
mbed_official 133:d4dda5c437f0 1210
mbed_official 133:d4dda5c437f0 1211 uint32_t headersize = hcryp->Init.HeaderSize;
mbed_official 133:d4dda5c437f0 1212 uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
mbed_official 133:d4dda5c437f0 1213 uint32_t loopcounter = 0;
mbed_official 133:d4dda5c437f0 1214 uint32_t bufferidx = 0;
mbed_official 133:d4dda5c437f0 1215 uint8_t blockb0[16] = {0};/* Block B0 */
mbed_official 133:d4dda5c437f0 1216 uint8_t ctr[16] = {0}; /* Counter */
mbed_official 133:d4dda5c437f0 1217 uint32_t b0addr = (uint32_t)blockb0;
mbed_official 133:d4dda5c437f0 1218
mbed_official 133:d4dda5c437f0 1219 if(hcryp->State == HAL_CRYP_STATE_READY)
mbed_official 133:d4dda5c437f0 1220 {
mbed_official 133:d4dda5c437f0 1221 /* Process Locked */
mbed_official 133:d4dda5c437f0 1222 __HAL_LOCK(hcryp);
mbed_official 133:d4dda5c437f0 1223
mbed_official 133:d4dda5c437f0 1224 hcryp->CrypInCount = Size;
mbed_official 133:d4dda5c437f0 1225 hcryp->pCrypInBuffPtr = pPlainData;
mbed_official 133:d4dda5c437f0 1226 hcryp->pCrypOutBuffPtr = pCypherData;
mbed_official 133:d4dda5c437f0 1227 hcryp->CrypOutCount = Size;
mbed_official 133:d4dda5c437f0 1228
mbed_official 133:d4dda5c437f0 1229 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 1230 hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official 133:d4dda5c437f0 1231
mbed_official 133:d4dda5c437f0 1232 /* Check if initialization phase has already been performed */
mbed_official 133:d4dda5c437f0 1233 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official 133:d4dda5c437f0 1234 {
mbed_official 133:d4dda5c437f0 1235 /************************ Formatting the header block *******************/
mbed_official 133:d4dda5c437f0 1236 if(headersize != 0)
mbed_official 133:d4dda5c437f0 1237 {
mbed_official 133:d4dda5c437f0 1238 /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
mbed_official 133:d4dda5c437f0 1239 if(headersize < 65280)
mbed_official 133:d4dda5c437f0 1240 {
mbed_official 133:d4dda5c437f0 1241 hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
mbed_official 133:d4dda5c437f0 1242 hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
mbed_official 133:d4dda5c437f0 1243 headersize += 2;
mbed_official 133:d4dda5c437f0 1244 }
mbed_official 133:d4dda5c437f0 1245 else
mbed_official 133:d4dda5c437f0 1246 {
mbed_official 133:d4dda5c437f0 1247 /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
mbed_official 133:d4dda5c437f0 1248 hcryp->Init.pScratch[bufferidx++] = 0xFF;
mbed_official 133:d4dda5c437f0 1249 hcryp->Init.pScratch[bufferidx++] = 0xFE;
mbed_official 133:d4dda5c437f0 1250 hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
mbed_official 133:d4dda5c437f0 1251 hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
mbed_official 133:d4dda5c437f0 1252 hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
mbed_official 133:d4dda5c437f0 1253 hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
mbed_official 133:d4dda5c437f0 1254 headersize += 6;
mbed_official 133:d4dda5c437f0 1255 }
mbed_official 133:d4dda5c437f0 1256 /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
mbed_official 133:d4dda5c437f0 1257 for(loopcounter = 0; loopcounter < headersize; loopcounter++)
mbed_official 133:d4dda5c437f0 1258 {
mbed_official 133:d4dda5c437f0 1259 hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
mbed_official 133:d4dda5c437f0 1260 }
mbed_official 133:d4dda5c437f0 1261 /* Check if the header size is modulo 16 */
mbed_official 133:d4dda5c437f0 1262 if ((headersize % 16) != 0)
mbed_official 133:d4dda5c437f0 1263 {
mbed_official 133:d4dda5c437f0 1264 /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
mbed_official 133:d4dda5c437f0 1265 for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
mbed_official 133:d4dda5c437f0 1266 {
mbed_official 133:d4dda5c437f0 1267 hcryp->Init.pScratch[loopcounter] = 0;
mbed_official 133:d4dda5c437f0 1268 }
mbed_official 133:d4dda5c437f0 1269 /* Set the header size to modulo 16 */
mbed_official 133:d4dda5c437f0 1270 headersize = ((headersize/16) + 1) * 16;
mbed_official 133:d4dda5c437f0 1271 }
mbed_official 133:d4dda5c437f0 1272 /* Set the pointer headeraddr to hcryp->Init.pScratch */
mbed_official 133:d4dda5c437f0 1273 headeraddr = (uint32_t)hcryp->Init.pScratch;
mbed_official 133:d4dda5c437f0 1274 }
mbed_official 133:d4dda5c437f0 1275 /*********************** Formatting the block B0 ************************/
mbed_official 133:d4dda5c437f0 1276 if(headersize != 0)
mbed_official 133:d4dda5c437f0 1277 {
mbed_official 133:d4dda5c437f0 1278 blockb0[0] = 0x40;
mbed_official 133:d4dda5c437f0 1279 }
mbed_official 133:d4dda5c437f0 1280 /* Flags byte */
mbed_official 133:d4dda5c437f0 1281 /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
mbed_official 133:d4dda5c437f0 1282 blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
mbed_official 133:d4dda5c437f0 1283 blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
mbed_official 133:d4dda5c437f0 1284
mbed_official 133:d4dda5c437f0 1285 for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
mbed_official 133:d4dda5c437f0 1286 {
mbed_official 133:d4dda5c437f0 1287 blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
mbed_official 133:d4dda5c437f0 1288 }
mbed_official 133:d4dda5c437f0 1289 for ( ; loopcounter < 13; loopcounter++)
mbed_official 133:d4dda5c437f0 1290 {
mbed_official 133:d4dda5c437f0 1291 blockb0[loopcounter+1] = 0;
mbed_official 133:d4dda5c437f0 1292 }
mbed_official 133:d4dda5c437f0 1293
mbed_official 133:d4dda5c437f0 1294 blockb0[14] = (Size >> 8);
mbed_official 133:d4dda5c437f0 1295 blockb0[15] = (Size & 0xFF);
mbed_official 133:d4dda5c437f0 1296
mbed_official 133:d4dda5c437f0 1297 /************************* Formatting the initial counter ***************/
mbed_official 133:d4dda5c437f0 1298 /* Byte 0:
mbed_official 133:d4dda5c437f0 1299 Bits 7 and 6 are reserved and shall be set to 0
mbed_official 133:d4dda5c437f0 1300 Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
mbed_official 133:d4dda5c437f0 1301 blocks are distinct from B0
mbed_official 133:d4dda5c437f0 1302 Bits 0, 1, and 2 contain the same encoding of q as in B0
mbed_official 133:d4dda5c437f0 1303 */
mbed_official 133:d4dda5c437f0 1304 ctr[0] = blockb0[0] & 0x07;
mbed_official 133:d4dda5c437f0 1305 /* byte 1 to NonceSize is the IV (Nonce) */
mbed_official 133:d4dda5c437f0 1306 for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
mbed_official 133:d4dda5c437f0 1307 {
mbed_official 133:d4dda5c437f0 1308 ctr[loopcounter] = blockb0[loopcounter];
mbed_official 133:d4dda5c437f0 1309 }
mbed_official 133:d4dda5c437f0 1310 /* Set the LSB to 1 */
mbed_official 133:d4dda5c437f0 1311 ctr[15] |= 0x01;
mbed_official 133:d4dda5c437f0 1312
mbed_official 133:d4dda5c437f0 1313 /* Set the key */
mbed_official 133:d4dda5c437f0 1314 CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official 133:d4dda5c437f0 1315
mbed_official 133:d4dda5c437f0 1316 /* Set the CRYP peripheral in AES CCM mode */
mbed_official 133:d4dda5c437f0 1317 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
mbed_official 133:d4dda5c437f0 1318
mbed_official 133:d4dda5c437f0 1319 /* Set the Initialization Vector */
mbed_official 133:d4dda5c437f0 1320 CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, hcryp->Init.KeySize);
mbed_official 133:d4dda5c437f0 1321
mbed_official 133:d4dda5c437f0 1322 /* Select init phase */
mbed_official 133:d4dda5c437f0 1323 __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
mbed_official 133:d4dda5c437f0 1324
mbed_official 133:d4dda5c437f0 1325 b0addr = (uint32_t)blockb0;
mbed_official 133:d4dda5c437f0 1326 /* Write the blockb0 block in the IN FIFO */
mbed_official 133:d4dda5c437f0 1327 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 1328 b0addr+=4;
mbed_official 133:d4dda5c437f0 1329 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 1330 b0addr+=4;
mbed_official 133:d4dda5c437f0 1331 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 1332 b0addr+=4;
mbed_official 133:d4dda5c437f0 1333 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 1334
mbed_official 133:d4dda5c437f0 1335 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 1336 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 1337
mbed_official 133:d4dda5c437f0 1338 /* Get timeout */
mbed_official 133:d4dda5c437f0 1339 timeout = HAL_GetTick() + 1;
mbed_official 133:d4dda5c437f0 1340
mbed_official 133:d4dda5c437f0 1341 while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official 133:d4dda5c437f0 1342 {
mbed_official 133:d4dda5c437f0 1343 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 1344 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 1345 {
mbed_official 133:d4dda5c437f0 1346 /* Change state */
mbed_official 133:d4dda5c437f0 1347 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 1348
mbed_official 133:d4dda5c437f0 1349 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1350 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 1351
mbed_official 133:d4dda5c437f0 1352 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 1353 }
mbed_official 133:d4dda5c437f0 1354 }
mbed_official 133:d4dda5c437f0 1355 /***************************** Header phase *****************************/
mbed_official 133:d4dda5c437f0 1356 if(headersize != 0)
mbed_official 133:d4dda5c437f0 1357 {
mbed_official 133:d4dda5c437f0 1358 /* Select header phase */
mbed_official 133:d4dda5c437f0 1359 __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
mbed_official 133:d4dda5c437f0 1360
mbed_official 133:d4dda5c437f0 1361 /* Enable Crypto processor */
mbed_official 133:d4dda5c437f0 1362 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 1363
mbed_official 133:d4dda5c437f0 1364 for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
mbed_official 133:d4dda5c437f0 1365 {
mbed_official 133:d4dda5c437f0 1366 /* Get timeout */
mbed_official 133:d4dda5c437f0 1367 timeout = HAL_GetTick() + 1;
mbed_official 133:d4dda5c437f0 1368
mbed_official 133:d4dda5c437f0 1369 while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
mbed_official 133:d4dda5c437f0 1370 {
mbed_official 133:d4dda5c437f0 1371 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 1372 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 1373 {
mbed_official 133:d4dda5c437f0 1374 /* Change state */
mbed_official 133:d4dda5c437f0 1375 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 1376
mbed_official 133:d4dda5c437f0 1377 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1378 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 1379
mbed_official 133:d4dda5c437f0 1380 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 1381 }
mbed_official 133:d4dda5c437f0 1382 }
mbed_official 133:d4dda5c437f0 1383 /* Write the header block in the IN FIFO */
mbed_official 133:d4dda5c437f0 1384 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 1385 headeraddr+=4;
mbed_official 133:d4dda5c437f0 1386 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 1387 headeraddr+=4;
mbed_official 133:d4dda5c437f0 1388 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 1389 headeraddr+=4;
mbed_official 133:d4dda5c437f0 1390 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 1391 headeraddr+=4;
mbed_official 133:d4dda5c437f0 1392 }
mbed_official 133:d4dda5c437f0 1393
mbed_official 133:d4dda5c437f0 1394 /* Get timeout */
mbed_official 133:d4dda5c437f0 1395 timeout = HAL_GetTick() + 1;
mbed_official 133:d4dda5c437f0 1396
mbed_official 133:d4dda5c437f0 1397 while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
mbed_official 133:d4dda5c437f0 1398 {
mbed_official 133:d4dda5c437f0 1399 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 1400 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 1401 {
mbed_official 133:d4dda5c437f0 1402 /* Change state */
mbed_official 133:d4dda5c437f0 1403 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 1404
mbed_official 133:d4dda5c437f0 1405 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1406 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 1407
mbed_official 133:d4dda5c437f0 1408 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 1409 }
mbed_official 133:d4dda5c437f0 1410 }
mbed_official 133:d4dda5c437f0 1411 }
mbed_official 133:d4dda5c437f0 1412 /* Save formatted counter into the scratch buffer pScratch */
mbed_official 133:d4dda5c437f0 1413 for(loopcounter = 0; (loopcounter < 16); loopcounter++)
mbed_official 133:d4dda5c437f0 1414 {
mbed_official 133:d4dda5c437f0 1415 hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
mbed_official 133:d4dda5c437f0 1416 }
mbed_official 133:d4dda5c437f0 1417 /* Reset bit 0 */
mbed_official 133:d4dda5c437f0 1418 hcryp->Init.pScratch[15] &= 0xfe;
mbed_official 133:d4dda5c437f0 1419
mbed_official 133:d4dda5c437f0 1420 /* Select payload phase once the header phase is performed */
mbed_official 133:d4dda5c437f0 1421 __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official 133:d4dda5c437f0 1422
mbed_official 133:d4dda5c437f0 1423 /* Flush FIFO */
mbed_official 133:d4dda5c437f0 1424 __HAL_CRYP_FIFO_FLUSH();
mbed_official 133:d4dda5c437f0 1425
mbed_official 133:d4dda5c437f0 1426 /* Set the phase */
mbed_official 133:d4dda5c437f0 1427 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official 133:d4dda5c437f0 1428 }
mbed_official 133:d4dda5c437f0 1429
mbed_official 133:d4dda5c437f0 1430 if(Size != 0)
mbed_official 133:d4dda5c437f0 1431 {
mbed_official 133:d4dda5c437f0 1432 /* Enable Interrupts */
mbed_official 133:d4dda5c437f0 1433 __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
mbed_official 133:d4dda5c437f0 1434 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 1435 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 1436 }
mbed_official 133:d4dda5c437f0 1437 else
mbed_official 133:d4dda5c437f0 1438 {
mbed_official 133:d4dda5c437f0 1439 /* Change the CRYP state and phase */
mbed_official 133:d4dda5c437f0 1440 hcryp->State = HAL_CRYP_STATE_READY;
mbed_official 133:d4dda5c437f0 1441 }
mbed_official 133:d4dda5c437f0 1442
mbed_official 133:d4dda5c437f0 1443 /* Return function status */
mbed_official 133:d4dda5c437f0 1444 return HAL_OK;
mbed_official 133:d4dda5c437f0 1445 }
mbed_official 133:d4dda5c437f0 1446 else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
mbed_official 133:d4dda5c437f0 1447 {
mbed_official 133:d4dda5c437f0 1448 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
mbed_official 133:d4dda5c437f0 1449 /* Write the Input block in the IN FIFO */
mbed_official 133:d4dda5c437f0 1450 CRYP->DR = *(uint32_t*)(inputaddr);
mbed_official 133:d4dda5c437f0 1451 inputaddr+=4;
mbed_official 133:d4dda5c437f0 1452 CRYP->DR = *(uint32_t*)(inputaddr);
mbed_official 133:d4dda5c437f0 1453 inputaddr+=4;
mbed_official 133:d4dda5c437f0 1454 CRYP->DR = *(uint32_t*)(inputaddr);
mbed_official 133:d4dda5c437f0 1455 inputaddr+=4;
mbed_official 133:d4dda5c437f0 1456 CRYP->DR = *(uint32_t*)(inputaddr);
mbed_official 133:d4dda5c437f0 1457 hcryp->pCrypInBuffPtr += 16;
mbed_official 133:d4dda5c437f0 1458 hcryp->CrypInCount -= 16;
mbed_official 133:d4dda5c437f0 1459 if(hcryp->CrypInCount == 0)
mbed_official 133:d4dda5c437f0 1460 {
mbed_official 133:d4dda5c437f0 1461 __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
mbed_official 133:d4dda5c437f0 1462 /* Call Input transfer complete callback */
mbed_official 133:d4dda5c437f0 1463 HAL_CRYP_InCpltCallback(hcryp);
mbed_official 133:d4dda5c437f0 1464 }
mbed_official 133:d4dda5c437f0 1465 }
mbed_official 133:d4dda5c437f0 1466 else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
mbed_official 133:d4dda5c437f0 1467 {
mbed_official 133:d4dda5c437f0 1468 outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
mbed_official 133:d4dda5c437f0 1469 /* Read the Output block from the Output FIFO */
mbed_official 133:d4dda5c437f0 1470 *(uint32_t*)(outputaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 1471 outputaddr+=4;
mbed_official 133:d4dda5c437f0 1472 *(uint32_t*)(outputaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 1473 outputaddr+=4;
mbed_official 133:d4dda5c437f0 1474 *(uint32_t*)(outputaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 1475 outputaddr+=4;
mbed_official 133:d4dda5c437f0 1476 *(uint32_t*)(outputaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 1477 hcryp->pCrypOutBuffPtr += 16;
mbed_official 133:d4dda5c437f0 1478 hcryp->CrypOutCount -= 16;
mbed_official 133:d4dda5c437f0 1479 if(hcryp->CrypOutCount == 0)
mbed_official 133:d4dda5c437f0 1480 {
mbed_official 133:d4dda5c437f0 1481 __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
mbed_official 133:d4dda5c437f0 1482 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1483 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 1484 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 1485 hcryp->State = HAL_CRYP_STATE_READY;
mbed_official 133:d4dda5c437f0 1486 /* Call Input transfer complete callback */
mbed_official 133:d4dda5c437f0 1487 HAL_CRYP_OutCpltCallback(hcryp);
mbed_official 133:d4dda5c437f0 1488 }
mbed_official 133:d4dda5c437f0 1489 }
mbed_official 133:d4dda5c437f0 1490
mbed_official 133:d4dda5c437f0 1491 /* Return function status */
mbed_official 133:d4dda5c437f0 1492 return HAL_OK;
mbed_official 133:d4dda5c437f0 1493 }
mbed_official 133:d4dda5c437f0 1494
mbed_official 133:d4dda5c437f0 1495 /**
mbed_official 133:d4dda5c437f0 1496 * @brief Initializes the CRYP peripheral in AES GCM decryption mode using IT.
mbed_official 133:d4dda5c437f0 1497 * @param hcryp: CRYP handle
mbed_official 133:d4dda5c437f0 1498 * @param pCypherData: Pointer to the cyphertext buffer
mbed_official 133:d4dda5c437f0 1499 * @param Size: Length of the cyphertext buffer, must be a multiple of 16
mbed_official 133:d4dda5c437f0 1500 * @param pPlainData: Pointer to the plaintext buffer
mbed_official 133:d4dda5c437f0 1501 * @retval HAL status
mbed_official 133:d4dda5c437f0 1502 */
mbed_official 133:d4dda5c437f0 1503 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
mbed_official 133:d4dda5c437f0 1504 {
mbed_official 133:d4dda5c437f0 1505 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 1506 uint32_t inputaddr;
mbed_official 133:d4dda5c437f0 1507 uint32_t outputaddr;
mbed_official 133:d4dda5c437f0 1508
mbed_official 133:d4dda5c437f0 1509 if(hcryp->State == HAL_CRYP_STATE_READY)
mbed_official 133:d4dda5c437f0 1510 {
mbed_official 133:d4dda5c437f0 1511 /* Process Locked */
mbed_official 133:d4dda5c437f0 1512 __HAL_LOCK(hcryp);
mbed_official 133:d4dda5c437f0 1513
mbed_official 133:d4dda5c437f0 1514 /* Get the buffer addresses and sizes */
mbed_official 133:d4dda5c437f0 1515 hcryp->CrypInCount = Size;
mbed_official 133:d4dda5c437f0 1516 hcryp->pCrypInBuffPtr = pCypherData;
mbed_official 133:d4dda5c437f0 1517 hcryp->pCrypOutBuffPtr = pPlainData;
mbed_official 133:d4dda5c437f0 1518 hcryp->CrypOutCount = Size;
mbed_official 133:d4dda5c437f0 1519
mbed_official 133:d4dda5c437f0 1520 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 1521 hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official 133:d4dda5c437f0 1522
mbed_official 133:d4dda5c437f0 1523 /* Check if initialization phase has already been performed */
mbed_official 133:d4dda5c437f0 1524 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official 133:d4dda5c437f0 1525 {
mbed_official 133:d4dda5c437f0 1526 /* Set the key */
mbed_official 133:d4dda5c437f0 1527 CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official 133:d4dda5c437f0 1528
mbed_official 133:d4dda5c437f0 1529 /* Set the CRYP peripheral in AES GCM decryption mode */
mbed_official 133:d4dda5c437f0 1530 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
mbed_official 133:d4dda5c437f0 1531
mbed_official 133:d4dda5c437f0 1532 /* Set the Initialization Vector */
mbed_official 133:d4dda5c437f0 1533 CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
mbed_official 133:d4dda5c437f0 1534
mbed_official 133:d4dda5c437f0 1535 /* Flush FIFO */
mbed_official 133:d4dda5c437f0 1536 __HAL_CRYP_FIFO_FLUSH();
mbed_official 133:d4dda5c437f0 1537
mbed_official 133:d4dda5c437f0 1538 /* Enable CRYP to start the init phase */
mbed_official 133:d4dda5c437f0 1539 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 1540
mbed_official 133:d4dda5c437f0 1541 /* Get timeout */
mbed_official 133:d4dda5c437f0 1542 timeout = HAL_GetTick() + 1;
mbed_official 133:d4dda5c437f0 1543
mbed_official 133:d4dda5c437f0 1544 while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official 133:d4dda5c437f0 1545 {
mbed_official 133:d4dda5c437f0 1546 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 1547 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 1548 {
mbed_official 133:d4dda5c437f0 1549 /* Change state */
mbed_official 133:d4dda5c437f0 1550 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 1551
mbed_official 133:d4dda5c437f0 1552 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1553 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 1554
mbed_official 133:d4dda5c437f0 1555 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 1556 }
mbed_official 133:d4dda5c437f0 1557 }
mbed_official 133:d4dda5c437f0 1558
mbed_official 133:d4dda5c437f0 1559 /* Set the header phase */
mbed_official 133:d4dda5c437f0 1560 if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
mbed_official 133:d4dda5c437f0 1561 {
mbed_official 133:d4dda5c437f0 1562 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 1563 }
mbed_official 133:d4dda5c437f0 1564 /* Disable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 1565 __HAL_CRYP_DISABLE();
mbed_official 133:d4dda5c437f0 1566
mbed_official 133:d4dda5c437f0 1567 /* Select payload phase once the header phase is performed */
mbed_official 133:d4dda5c437f0 1568 __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official 133:d4dda5c437f0 1569
mbed_official 133:d4dda5c437f0 1570 /* Set the phase */
mbed_official 133:d4dda5c437f0 1571 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official 133:d4dda5c437f0 1572 }
mbed_official 133:d4dda5c437f0 1573
mbed_official 133:d4dda5c437f0 1574 if(Size != 0)
mbed_official 133:d4dda5c437f0 1575 {
mbed_official 133:d4dda5c437f0 1576 /* Enable Interrupts */
mbed_official 133:d4dda5c437f0 1577 __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
mbed_official 133:d4dda5c437f0 1578 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 1579 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 1580 }
mbed_official 133:d4dda5c437f0 1581 else
mbed_official 133:d4dda5c437f0 1582 {
mbed_official 133:d4dda5c437f0 1583 /* Process Locked */
mbed_official 133:d4dda5c437f0 1584 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 1585 /* Change the CRYP state and phase */
mbed_official 133:d4dda5c437f0 1586 hcryp->State = HAL_CRYP_STATE_READY;
mbed_official 133:d4dda5c437f0 1587 }
mbed_official 133:d4dda5c437f0 1588
mbed_official 133:d4dda5c437f0 1589 /* Return function status */
mbed_official 133:d4dda5c437f0 1590 return HAL_OK;
mbed_official 133:d4dda5c437f0 1591 }
mbed_official 133:d4dda5c437f0 1592 else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
mbed_official 133:d4dda5c437f0 1593 {
mbed_official 133:d4dda5c437f0 1594 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
mbed_official 133:d4dda5c437f0 1595 /* Write the Input block in the IN FIFO */
mbed_official 133:d4dda5c437f0 1596 CRYP->DR = *(uint32_t*)(inputaddr);
mbed_official 133:d4dda5c437f0 1597 inputaddr+=4;
mbed_official 133:d4dda5c437f0 1598 CRYP->DR = *(uint32_t*)(inputaddr);
mbed_official 133:d4dda5c437f0 1599 inputaddr+=4;
mbed_official 133:d4dda5c437f0 1600 CRYP->DR = *(uint32_t*)(inputaddr);
mbed_official 133:d4dda5c437f0 1601 inputaddr+=4;
mbed_official 133:d4dda5c437f0 1602 CRYP->DR = *(uint32_t*)(inputaddr);
mbed_official 133:d4dda5c437f0 1603 hcryp->pCrypInBuffPtr += 16;
mbed_official 133:d4dda5c437f0 1604 hcryp->CrypInCount -= 16;
mbed_official 133:d4dda5c437f0 1605 if(hcryp->CrypInCount == 0)
mbed_official 133:d4dda5c437f0 1606 {
mbed_official 133:d4dda5c437f0 1607 __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
mbed_official 133:d4dda5c437f0 1608 /* Call the Input data transfer complete callback */
mbed_official 133:d4dda5c437f0 1609 HAL_CRYP_InCpltCallback(hcryp);
mbed_official 133:d4dda5c437f0 1610 }
mbed_official 133:d4dda5c437f0 1611 }
mbed_official 133:d4dda5c437f0 1612 else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
mbed_official 133:d4dda5c437f0 1613 {
mbed_official 133:d4dda5c437f0 1614 outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
mbed_official 133:d4dda5c437f0 1615 /* Read the Output block from the Output FIFO */
mbed_official 133:d4dda5c437f0 1616 *(uint32_t*)(outputaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 1617 outputaddr+=4;
mbed_official 133:d4dda5c437f0 1618 *(uint32_t*)(outputaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 1619 outputaddr+=4;
mbed_official 133:d4dda5c437f0 1620 *(uint32_t*)(outputaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 1621 outputaddr+=4;
mbed_official 133:d4dda5c437f0 1622 *(uint32_t*)(outputaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 1623 hcryp->pCrypOutBuffPtr += 16;
mbed_official 133:d4dda5c437f0 1624 hcryp->CrypOutCount -= 16;
mbed_official 133:d4dda5c437f0 1625 if(hcryp->CrypOutCount == 0)
mbed_official 133:d4dda5c437f0 1626 {
mbed_official 133:d4dda5c437f0 1627 __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
mbed_official 133:d4dda5c437f0 1628 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1629 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 1630 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 1631 hcryp->State = HAL_CRYP_STATE_READY;
mbed_official 133:d4dda5c437f0 1632 /* Call Input transfer complete callback */
mbed_official 133:d4dda5c437f0 1633 HAL_CRYP_OutCpltCallback(hcryp);
mbed_official 133:d4dda5c437f0 1634 }
mbed_official 133:d4dda5c437f0 1635 }
mbed_official 133:d4dda5c437f0 1636
mbed_official 133:d4dda5c437f0 1637 /* Return function status */
mbed_official 133:d4dda5c437f0 1638 return HAL_OK;
mbed_official 133:d4dda5c437f0 1639 }
mbed_official 133:d4dda5c437f0 1640
mbed_official 133:d4dda5c437f0 1641 /**
mbed_official 133:d4dda5c437f0 1642 * @brief Initializes the CRYP peripheral in AES CCM decryption mode using interrupt
mbed_official 133:d4dda5c437f0 1643 * then decrypted pCypherData. The cypher data are available in pPlainData.
mbed_official 133:d4dda5c437f0 1644 * @param hcryp: CRYP handle
mbed_official 133:d4dda5c437f0 1645 * @param pCypherData: Pointer to the cyphertext buffer
mbed_official 133:d4dda5c437f0 1646 * @param Size: Length of the plaintext buffer, must be a multiple of 16
mbed_official 133:d4dda5c437f0 1647 * @param pPlainData: Pointer to the plaintext buffer
mbed_official 133:d4dda5c437f0 1648 * @retval HAL status
mbed_official 133:d4dda5c437f0 1649 */
mbed_official 133:d4dda5c437f0 1650 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
mbed_official 133:d4dda5c437f0 1651 {
mbed_official 133:d4dda5c437f0 1652 uint32_t inputaddr;
mbed_official 133:d4dda5c437f0 1653 uint32_t outputaddr;
mbed_official 133:d4dda5c437f0 1654 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 1655 uint32_t headersize = hcryp->Init.HeaderSize;
mbed_official 133:d4dda5c437f0 1656 uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
mbed_official 133:d4dda5c437f0 1657 uint32_t loopcounter = 0;
mbed_official 133:d4dda5c437f0 1658 uint32_t bufferidx = 0;
mbed_official 133:d4dda5c437f0 1659 uint8_t blockb0[16] = {0};/* Block B0 */
mbed_official 133:d4dda5c437f0 1660 uint8_t ctr[16] = {0}; /* Counter */
mbed_official 133:d4dda5c437f0 1661 uint32_t b0addr = (uint32_t)blockb0;
mbed_official 133:d4dda5c437f0 1662
mbed_official 133:d4dda5c437f0 1663 if(hcryp->State == HAL_CRYP_STATE_READY)
mbed_official 133:d4dda5c437f0 1664 {
mbed_official 133:d4dda5c437f0 1665 /* Process Locked */
mbed_official 133:d4dda5c437f0 1666 __HAL_LOCK(hcryp);
mbed_official 133:d4dda5c437f0 1667
mbed_official 133:d4dda5c437f0 1668 hcryp->CrypInCount = Size;
mbed_official 133:d4dda5c437f0 1669 hcryp->pCrypInBuffPtr = pCypherData;
mbed_official 133:d4dda5c437f0 1670 hcryp->pCrypOutBuffPtr = pPlainData;
mbed_official 133:d4dda5c437f0 1671 hcryp->CrypOutCount = Size;
mbed_official 133:d4dda5c437f0 1672
mbed_official 133:d4dda5c437f0 1673 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 1674 hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official 133:d4dda5c437f0 1675
mbed_official 133:d4dda5c437f0 1676 /* Check if initialization phase has already been performed */
mbed_official 133:d4dda5c437f0 1677 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official 133:d4dda5c437f0 1678 {
mbed_official 133:d4dda5c437f0 1679 /************************ Formatting the header block *******************/
mbed_official 133:d4dda5c437f0 1680 if(headersize != 0)
mbed_official 133:d4dda5c437f0 1681 {
mbed_official 133:d4dda5c437f0 1682 /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
mbed_official 133:d4dda5c437f0 1683 if(headersize < 65280)
mbed_official 133:d4dda5c437f0 1684 {
mbed_official 133:d4dda5c437f0 1685 hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
mbed_official 133:d4dda5c437f0 1686 hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
mbed_official 133:d4dda5c437f0 1687 headersize += 2;
mbed_official 133:d4dda5c437f0 1688 }
mbed_official 133:d4dda5c437f0 1689 else
mbed_official 133:d4dda5c437f0 1690 {
mbed_official 133:d4dda5c437f0 1691 /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
mbed_official 133:d4dda5c437f0 1692 hcryp->Init.pScratch[bufferidx++] = 0xFF;
mbed_official 133:d4dda5c437f0 1693 hcryp->Init.pScratch[bufferidx++] = 0xFE;
mbed_official 133:d4dda5c437f0 1694 hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
mbed_official 133:d4dda5c437f0 1695 hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
mbed_official 133:d4dda5c437f0 1696 hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
mbed_official 133:d4dda5c437f0 1697 hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
mbed_official 133:d4dda5c437f0 1698 headersize += 6;
mbed_official 133:d4dda5c437f0 1699 }
mbed_official 133:d4dda5c437f0 1700 /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
mbed_official 133:d4dda5c437f0 1701 for(loopcounter = 0; loopcounter < headersize; loopcounter++)
mbed_official 133:d4dda5c437f0 1702 {
mbed_official 133:d4dda5c437f0 1703 hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
mbed_official 133:d4dda5c437f0 1704 }
mbed_official 133:d4dda5c437f0 1705 /* Check if the header size is modulo 16 */
mbed_official 133:d4dda5c437f0 1706 if ((headersize % 16) != 0)
mbed_official 133:d4dda5c437f0 1707 {
mbed_official 133:d4dda5c437f0 1708 /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
mbed_official 133:d4dda5c437f0 1709 for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
mbed_official 133:d4dda5c437f0 1710 {
mbed_official 133:d4dda5c437f0 1711 hcryp->Init.pScratch[loopcounter] = 0;
mbed_official 133:d4dda5c437f0 1712 }
mbed_official 133:d4dda5c437f0 1713 /* Set the header size to modulo 16 */
mbed_official 133:d4dda5c437f0 1714 headersize = ((headersize/16) + 1) * 16;
mbed_official 133:d4dda5c437f0 1715 }
mbed_official 133:d4dda5c437f0 1716 /* Set the pointer headeraddr to hcryp->Init.pScratch */
mbed_official 133:d4dda5c437f0 1717 headeraddr = (uint32_t)hcryp->Init.pScratch;
mbed_official 133:d4dda5c437f0 1718 }
mbed_official 133:d4dda5c437f0 1719 /*********************** Formatting the block B0 ************************/
mbed_official 133:d4dda5c437f0 1720 if(headersize != 0)
mbed_official 133:d4dda5c437f0 1721 {
mbed_official 133:d4dda5c437f0 1722 blockb0[0] = 0x40;
mbed_official 133:d4dda5c437f0 1723 }
mbed_official 133:d4dda5c437f0 1724 /* Flags byte */
mbed_official 133:d4dda5c437f0 1725 /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
mbed_official 133:d4dda5c437f0 1726 blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
mbed_official 133:d4dda5c437f0 1727 blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
mbed_official 133:d4dda5c437f0 1728
mbed_official 133:d4dda5c437f0 1729 for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
mbed_official 133:d4dda5c437f0 1730 {
mbed_official 133:d4dda5c437f0 1731 blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
mbed_official 133:d4dda5c437f0 1732 }
mbed_official 133:d4dda5c437f0 1733 for ( ; loopcounter < 13; loopcounter++)
mbed_official 133:d4dda5c437f0 1734 {
mbed_official 133:d4dda5c437f0 1735 blockb0[loopcounter+1] = 0;
mbed_official 133:d4dda5c437f0 1736 }
mbed_official 133:d4dda5c437f0 1737
mbed_official 133:d4dda5c437f0 1738 blockb0[14] = (Size >> 8);
mbed_official 133:d4dda5c437f0 1739 blockb0[15] = (Size & 0xFF);
mbed_official 133:d4dda5c437f0 1740
mbed_official 133:d4dda5c437f0 1741 /************************* Formatting the initial counter ***************/
mbed_official 133:d4dda5c437f0 1742 /* Byte 0:
mbed_official 133:d4dda5c437f0 1743 Bits 7 and 6 are reserved and shall be set to 0
mbed_official 133:d4dda5c437f0 1744 Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
mbed_official 133:d4dda5c437f0 1745 blocks are distinct from B0
mbed_official 133:d4dda5c437f0 1746 Bits 0, 1, and 2 contain the same encoding of q as in B0
mbed_official 133:d4dda5c437f0 1747 */
mbed_official 133:d4dda5c437f0 1748 ctr[0] = blockb0[0] & 0x07;
mbed_official 133:d4dda5c437f0 1749 /* byte 1 to NonceSize is the IV (Nonce) */
mbed_official 133:d4dda5c437f0 1750 for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
mbed_official 133:d4dda5c437f0 1751 {
mbed_official 133:d4dda5c437f0 1752 ctr[loopcounter] = blockb0[loopcounter];
mbed_official 133:d4dda5c437f0 1753 }
mbed_official 133:d4dda5c437f0 1754 /* Set the LSB to 1 */
mbed_official 133:d4dda5c437f0 1755 ctr[15] |= 0x01;
mbed_official 133:d4dda5c437f0 1756
mbed_official 133:d4dda5c437f0 1757 /* Set the key */
mbed_official 133:d4dda5c437f0 1758 CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official 133:d4dda5c437f0 1759
mbed_official 133:d4dda5c437f0 1760 /* Set the CRYP peripheral in AES CCM mode */
mbed_official 133:d4dda5c437f0 1761 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
mbed_official 133:d4dda5c437f0 1762
mbed_official 133:d4dda5c437f0 1763 /* Set the Initialization Vector */
mbed_official 133:d4dda5c437f0 1764 CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, hcryp->Init.KeySize);
mbed_official 133:d4dda5c437f0 1765
mbed_official 133:d4dda5c437f0 1766 /* Select init phase */
mbed_official 133:d4dda5c437f0 1767 __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
mbed_official 133:d4dda5c437f0 1768
mbed_official 133:d4dda5c437f0 1769 b0addr = (uint32_t)blockb0;
mbed_official 133:d4dda5c437f0 1770 /* Write the blockb0 block in the IN FIFO */
mbed_official 133:d4dda5c437f0 1771 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 1772 b0addr+=4;
mbed_official 133:d4dda5c437f0 1773 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 1774 b0addr+=4;
mbed_official 133:d4dda5c437f0 1775 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 1776 b0addr+=4;
mbed_official 133:d4dda5c437f0 1777 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 1778
mbed_official 133:d4dda5c437f0 1779 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 1780 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 1781
mbed_official 133:d4dda5c437f0 1782 /* Get timeout */
mbed_official 133:d4dda5c437f0 1783 timeout = HAL_GetTick() + 1;
mbed_official 133:d4dda5c437f0 1784
mbed_official 133:d4dda5c437f0 1785 while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official 133:d4dda5c437f0 1786 {
mbed_official 133:d4dda5c437f0 1787 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 1788 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 1789 {
mbed_official 133:d4dda5c437f0 1790 /* Change state */
mbed_official 133:d4dda5c437f0 1791 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 1792
mbed_official 133:d4dda5c437f0 1793 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1794 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 1795
mbed_official 133:d4dda5c437f0 1796 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 1797 }
mbed_official 133:d4dda5c437f0 1798 }
mbed_official 133:d4dda5c437f0 1799 /***************************** Header phase *****************************/
mbed_official 133:d4dda5c437f0 1800 if(headersize != 0)
mbed_official 133:d4dda5c437f0 1801 {
mbed_official 133:d4dda5c437f0 1802 /* Select header phase */
mbed_official 133:d4dda5c437f0 1803 __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
mbed_official 133:d4dda5c437f0 1804
mbed_official 133:d4dda5c437f0 1805 /* Enable Crypto processor */
mbed_official 133:d4dda5c437f0 1806 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 1807
mbed_official 133:d4dda5c437f0 1808 for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
mbed_official 133:d4dda5c437f0 1809 {
mbed_official 133:d4dda5c437f0 1810 /* Get timeout */
mbed_official 133:d4dda5c437f0 1811 timeout = HAL_GetTick() + 1;
mbed_official 133:d4dda5c437f0 1812
mbed_official 133:d4dda5c437f0 1813 while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
mbed_official 133:d4dda5c437f0 1814 {
mbed_official 133:d4dda5c437f0 1815 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 1816 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 1817 {
mbed_official 133:d4dda5c437f0 1818 /* Change state */
mbed_official 133:d4dda5c437f0 1819 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 1820
mbed_official 133:d4dda5c437f0 1821 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1822 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 1823
mbed_official 133:d4dda5c437f0 1824 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 1825 }
mbed_official 133:d4dda5c437f0 1826 }
mbed_official 133:d4dda5c437f0 1827 /* Write the header block in the IN FIFO */
mbed_official 133:d4dda5c437f0 1828 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 1829 headeraddr+=4;
mbed_official 133:d4dda5c437f0 1830 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 1831 headeraddr+=4;
mbed_official 133:d4dda5c437f0 1832 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 1833 headeraddr+=4;
mbed_official 133:d4dda5c437f0 1834 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 1835 headeraddr+=4;
mbed_official 133:d4dda5c437f0 1836 }
mbed_official 133:d4dda5c437f0 1837
mbed_official 133:d4dda5c437f0 1838 /* Get timeout */
mbed_official 133:d4dda5c437f0 1839 timeout = HAL_GetTick() + 1;
mbed_official 133:d4dda5c437f0 1840
mbed_official 133:d4dda5c437f0 1841 while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
mbed_official 133:d4dda5c437f0 1842 {
mbed_official 133:d4dda5c437f0 1843 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 1844 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 1845 {
mbed_official 133:d4dda5c437f0 1846 /* Change state */
mbed_official 133:d4dda5c437f0 1847 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 1848
mbed_official 133:d4dda5c437f0 1849 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1850 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 1851
mbed_official 133:d4dda5c437f0 1852 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 1853 }
mbed_official 133:d4dda5c437f0 1854 }
mbed_official 133:d4dda5c437f0 1855 }
mbed_official 133:d4dda5c437f0 1856 /* Save formatted counter into the scratch buffer pScratch */
mbed_official 133:d4dda5c437f0 1857 for(loopcounter = 0; (loopcounter < 16); loopcounter++)
mbed_official 133:d4dda5c437f0 1858 {
mbed_official 133:d4dda5c437f0 1859 hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
mbed_official 133:d4dda5c437f0 1860 }
mbed_official 133:d4dda5c437f0 1861 /* Reset bit 0 */
mbed_official 133:d4dda5c437f0 1862 hcryp->Init.pScratch[15] &= 0xfe;
mbed_official 133:d4dda5c437f0 1863 /* Select payload phase once the header phase is performed */
mbed_official 133:d4dda5c437f0 1864 __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official 133:d4dda5c437f0 1865
mbed_official 133:d4dda5c437f0 1866 /* Flush FIFO */
mbed_official 133:d4dda5c437f0 1867 __HAL_CRYP_FIFO_FLUSH();
mbed_official 133:d4dda5c437f0 1868
mbed_official 133:d4dda5c437f0 1869 /* Set the phase */
mbed_official 133:d4dda5c437f0 1870 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official 133:d4dda5c437f0 1871 }
mbed_official 133:d4dda5c437f0 1872
mbed_official 133:d4dda5c437f0 1873 /* Enable Interrupts */
mbed_official 133:d4dda5c437f0 1874 __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
mbed_official 133:d4dda5c437f0 1875
mbed_official 133:d4dda5c437f0 1876 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 1877 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 1878
mbed_official 133:d4dda5c437f0 1879 /* Return function status */
mbed_official 133:d4dda5c437f0 1880 return HAL_OK;
mbed_official 133:d4dda5c437f0 1881 }
mbed_official 133:d4dda5c437f0 1882 else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
mbed_official 133:d4dda5c437f0 1883 {
mbed_official 133:d4dda5c437f0 1884 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
mbed_official 133:d4dda5c437f0 1885 /* Write the Input block in the IN FIFO */
mbed_official 133:d4dda5c437f0 1886 CRYP->DR = *(uint32_t*)(inputaddr);
mbed_official 133:d4dda5c437f0 1887 inputaddr+=4;
mbed_official 133:d4dda5c437f0 1888 CRYP->DR = *(uint32_t*)(inputaddr);
mbed_official 133:d4dda5c437f0 1889 inputaddr+=4;
mbed_official 133:d4dda5c437f0 1890 CRYP->DR = *(uint32_t*)(inputaddr);
mbed_official 133:d4dda5c437f0 1891 inputaddr+=4;
mbed_official 133:d4dda5c437f0 1892 CRYP->DR = *(uint32_t*)(inputaddr);
mbed_official 133:d4dda5c437f0 1893 hcryp->pCrypInBuffPtr += 16;
mbed_official 133:d4dda5c437f0 1894 hcryp->CrypInCount -= 16;
mbed_official 133:d4dda5c437f0 1895 if(hcryp->CrypInCount == 0)
mbed_official 133:d4dda5c437f0 1896 {
mbed_official 133:d4dda5c437f0 1897 __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
mbed_official 133:d4dda5c437f0 1898 /* Call the Input data transfer complete callback */
mbed_official 133:d4dda5c437f0 1899 HAL_CRYP_InCpltCallback(hcryp);
mbed_official 133:d4dda5c437f0 1900 }
mbed_official 133:d4dda5c437f0 1901 }
mbed_official 133:d4dda5c437f0 1902 else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
mbed_official 133:d4dda5c437f0 1903 {
mbed_official 133:d4dda5c437f0 1904 outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
mbed_official 133:d4dda5c437f0 1905 /* Read the Output block from the Output FIFO */
mbed_official 133:d4dda5c437f0 1906 *(uint32_t*)(outputaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 1907 outputaddr+=4;
mbed_official 133:d4dda5c437f0 1908 *(uint32_t*)(outputaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 1909 outputaddr+=4;
mbed_official 133:d4dda5c437f0 1910 *(uint32_t*)(outputaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 1911 outputaddr+=4;
mbed_official 133:d4dda5c437f0 1912 *(uint32_t*)(outputaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 1913 hcryp->pCrypOutBuffPtr += 16;
mbed_official 133:d4dda5c437f0 1914 hcryp->CrypOutCount -= 16;
mbed_official 133:d4dda5c437f0 1915 if(hcryp->CrypOutCount == 0)
mbed_official 133:d4dda5c437f0 1916 {
mbed_official 133:d4dda5c437f0 1917 __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
mbed_official 133:d4dda5c437f0 1918 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1919 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 1920 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 1921 hcryp->State = HAL_CRYP_STATE_READY;
mbed_official 133:d4dda5c437f0 1922 /* Call Input transfer complete callback */
mbed_official 133:d4dda5c437f0 1923 HAL_CRYP_OutCpltCallback(hcryp);
mbed_official 133:d4dda5c437f0 1924 }
mbed_official 133:d4dda5c437f0 1925 }
mbed_official 133:d4dda5c437f0 1926
mbed_official 133:d4dda5c437f0 1927 /* Return function status */
mbed_official 133:d4dda5c437f0 1928 return HAL_OK;
mbed_official 133:d4dda5c437f0 1929 }
mbed_official 133:d4dda5c437f0 1930
mbed_official 133:d4dda5c437f0 1931 /**
mbed_official 133:d4dda5c437f0 1932 * @brief Initializes the CRYP peripheral in AES GCM encryption mode using DMA.
mbed_official 133:d4dda5c437f0 1933 * @param hcryp: CRYP handle
mbed_official 133:d4dda5c437f0 1934 * @param pPlainData: Pointer to the plaintext buffer
mbed_official 133:d4dda5c437f0 1935 * @param Size: Length of the plaintext buffer, must be a multiple of 16
mbed_official 133:d4dda5c437f0 1936 * @param pCypherData: Pointer to the cyphertext buffer
mbed_official 133:d4dda5c437f0 1937 * @retval HAL status
mbed_official 133:d4dda5c437f0 1938 */
mbed_official 133:d4dda5c437f0 1939 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
mbed_official 133:d4dda5c437f0 1940 {
mbed_official 133:d4dda5c437f0 1941 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 1942 uint32_t inputaddr;
mbed_official 133:d4dda5c437f0 1943 uint32_t outputaddr;
mbed_official 133:d4dda5c437f0 1944
mbed_official 133:d4dda5c437f0 1945 if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
mbed_official 133:d4dda5c437f0 1946 {
mbed_official 133:d4dda5c437f0 1947 /* Process Locked */
mbed_official 133:d4dda5c437f0 1948 __HAL_LOCK(hcryp);
mbed_official 133:d4dda5c437f0 1949
mbed_official 133:d4dda5c437f0 1950 inputaddr = (uint32_t)pPlainData;
mbed_official 133:d4dda5c437f0 1951 outputaddr = (uint32_t)pCypherData;
mbed_official 133:d4dda5c437f0 1952
mbed_official 133:d4dda5c437f0 1953 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 1954 hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official 133:d4dda5c437f0 1955
mbed_official 133:d4dda5c437f0 1956 /* Check if initialization phase has already been performed */
mbed_official 133:d4dda5c437f0 1957 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official 133:d4dda5c437f0 1958 {
mbed_official 133:d4dda5c437f0 1959 /* Set the key */
mbed_official 133:d4dda5c437f0 1960 CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official 133:d4dda5c437f0 1961
mbed_official 133:d4dda5c437f0 1962 /* Set the CRYP peripheral in AES GCM mode */
mbed_official 133:d4dda5c437f0 1963 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
mbed_official 133:d4dda5c437f0 1964
mbed_official 133:d4dda5c437f0 1965 /* Set the Initialization Vector */
mbed_official 133:d4dda5c437f0 1966 CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
mbed_official 133:d4dda5c437f0 1967
mbed_official 133:d4dda5c437f0 1968 /* Flush FIFO */
mbed_official 133:d4dda5c437f0 1969 __HAL_CRYP_FIFO_FLUSH();
mbed_official 133:d4dda5c437f0 1970
mbed_official 133:d4dda5c437f0 1971 /* Enable CRYP to start the init phase */
mbed_official 133:d4dda5c437f0 1972 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 1973
mbed_official 133:d4dda5c437f0 1974 /* Get timeout */
mbed_official 133:d4dda5c437f0 1975 timeout = HAL_GetTick() + 1;
mbed_official 133:d4dda5c437f0 1976
mbed_official 133:d4dda5c437f0 1977 while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official 133:d4dda5c437f0 1978 {
mbed_official 133:d4dda5c437f0 1979 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 1980 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 1981 {
mbed_official 133:d4dda5c437f0 1982 /* Change state */
mbed_official 133:d4dda5c437f0 1983 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 1984
mbed_official 133:d4dda5c437f0 1985 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1986 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 1987
mbed_official 133:d4dda5c437f0 1988 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 1989 }
mbed_official 133:d4dda5c437f0 1990 }
mbed_official 133:d4dda5c437f0 1991 /* Flush FIFO */
mbed_official 133:d4dda5c437f0 1992 __HAL_CRYP_FIFO_FLUSH();
mbed_official 133:d4dda5c437f0 1993
mbed_official 133:d4dda5c437f0 1994 /* Set the header phase */
mbed_official 133:d4dda5c437f0 1995 if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
mbed_official 133:d4dda5c437f0 1996 {
mbed_official 133:d4dda5c437f0 1997 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 1998 }
mbed_official 133:d4dda5c437f0 1999 /* Disable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 2000 __HAL_CRYP_DISABLE();
mbed_official 133:d4dda5c437f0 2001
mbed_official 133:d4dda5c437f0 2002 /* Select payload phase once the header phase is performed */
mbed_official 133:d4dda5c437f0 2003 __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official 133:d4dda5c437f0 2004
mbed_official 133:d4dda5c437f0 2005 /* Flush FIFO */
mbed_official 133:d4dda5c437f0 2006 __HAL_CRYP_FIFO_FLUSH();
mbed_official 133:d4dda5c437f0 2007
mbed_official 133:d4dda5c437f0 2008 /* Set the phase */
mbed_official 133:d4dda5c437f0 2009 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official 133:d4dda5c437f0 2010 }
mbed_official 133:d4dda5c437f0 2011
mbed_official 133:d4dda5c437f0 2012 /* Set the input and output addresses and start DMA transfer */
mbed_official 133:d4dda5c437f0 2013 CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
mbed_official 133:d4dda5c437f0 2014
mbed_official 133:d4dda5c437f0 2015 /* Unlock process */
mbed_official 133:d4dda5c437f0 2016 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 2017
mbed_official 133:d4dda5c437f0 2018 /* Return function status */
mbed_official 133:d4dda5c437f0 2019 return HAL_OK;
mbed_official 133:d4dda5c437f0 2020 }
mbed_official 133:d4dda5c437f0 2021 else
mbed_official 133:d4dda5c437f0 2022 {
mbed_official 133:d4dda5c437f0 2023 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 2024 }
mbed_official 133:d4dda5c437f0 2025 }
mbed_official 133:d4dda5c437f0 2026
mbed_official 133:d4dda5c437f0 2027 /**
mbed_official 133:d4dda5c437f0 2028 * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.
mbed_official 133:d4dda5c437f0 2029 * @param hcryp: CRYP handle
mbed_official 133:d4dda5c437f0 2030 * @param pPlainData: Pointer to the plaintext buffer
mbed_official 133:d4dda5c437f0 2031 * @param Size: Length of the plaintext buffer, must be a multiple of 16
mbed_official 133:d4dda5c437f0 2032 * @param pCypherData: Pointer to the cyphertext buffer
mbed_official 133:d4dda5c437f0 2033 * @retval HAL status
mbed_official 133:d4dda5c437f0 2034 */
mbed_official 133:d4dda5c437f0 2035 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
mbed_official 133:d4dda5c437f0 2036 {
mbed_official 133:d4dda5c437f0 2037 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 2038 uint32_t inputaddr;
mbed_official 133:d4dda5c437f0 2039 uint32_t outputaddr;
mbed_official 133:d4dda5c437f0 2040 uint32_t headersize;
mbed_official 133:d4dda5c437f0 2041 uint32_t headeraddr;
mbed_official 133:d4dda5c437f0 2042 uint32_t loopcounter = 0;
mbed_official 133:d4dda5c437f0 2043 uint32_t bufferidx = 0;
mbed_official 133:d4dda5c437f0 2044 uint8_t blockb0[16] = {0};/* Block B0 */
mbed_official 133:d4dda5c437f0 2045 uint8_t ctr[16] = {0}; /* Counter */
mbed_official 133:d4dda5c437f0 2046 uint32_t b0addr = (uint32_t)blockb0;
mbed_official 133:d4dda5c437f0 2047
mbed_official 133:d4dda5c437f0 2048 if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
mbed_official 133:d4dda5c437f0 2049 {
mbed_official 133:d4dda5c437f0 2050 /* Process Locked */
mbed_official 133:d4dda5c437f0 2051 __HAL_LOCK(hcryp);
mbed_official 133:d4dda5c437f0 2052
mbed_official 133:d4dda5c437f0 2053 inputaddr = (uint32_t)pPlainData;
mbed_official 133:d4dda5c437f0 2054 outputaddr = (uint32_t)pCypherData;
mbed_official 133:d4dda5c437f0 2055
mbed_official 133:d4dda5c437f0 2056 headersize = hcryp->Init.HeaderSize;
mbed_official 133:d4dda5c437f0 2057 headeraddr = (uint32_t)hcryp->Init.Header;
mbed_official 133:d4dda5c437f0 2058
mbed_official 133:d4dda5c437f0 2059 hcryp->CrypInCount = Size;
mbed_official 133:d4dda5c437f0 2060 hcryp->pCrypInBuffPtr = pPlainData;
mbed_official 133:d4dda5c437f0 2061 hcryp->pCrypOutBuffPtr = pCypherData;
mbed_official 133:d4dda5c437f0 2062 hcryp->CrypOutCount = Size;
mbed_official 133:d4dda5c437f0 2063
mbed_official 133:d4dda5c437f0 2064 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 2065 hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official 133:d4dda5c437f0 2066
mbed_official 133:d4dda5c437f0 2067 /* Check if initialization phase has already been performed */
mbed_official 133:d4dda5c437f0 2068 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official 133:d4dda5c437f0 2069 {
mbed_official 133:d4dda5c437f0 2070 /************************ Formatting the header block *******************/
mbed_official 133:d4dda5c437f0 2071 if(headersize != 0)
mbed_official 133:d4dda5c437f0 2072 {
mbed_official 133:d4dda5c437f0 2073 /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
mbed_official 133:d4dda5c437f0 2074 if(headersize < 65280)
mbed_official 133:d4dda5c437f0 2075 {
mbed_official 133:d4dda5c437f0 2076 hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
mbed_official 133:d4dda5c437f0 2077 hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
mbed_official 133:d4dda5c437f0 2078 headersize += 2;
mbed_official 133:d4dda5c437f0 2079 }
mbed_official 133:d4dda5c437f0 2080 else
mbed_official 133:d4dda5c437f0 2081 {
mbed_official 133:d4dda5c437f0 2082 /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
mbed_official 133:d4dda5c437f0 2083 hcryp->Init.pScratch[bufferidx++] = 0xFF;
mbed_official 133:d4dda5c437f0 2084 hcryp->Init.pScratch[bufferidx++] = 0xFE;
mbed_official 133:d4dda5c437f0 2085 hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
mbed_official 133:d4dda5c437f0 2086 hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
mbed_official 133:d4dda5c437f0 2087 hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
mbed_official 133:d4dda5c437f0 2088 hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
mbed_official 133:d4dda5c437f0 2089 headersize += 6;
mbed_official 133:d4dda5c437f0 2090 }
mbed_official 133:d4dda5c437f0 2091 /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
mbed_official 133:d4dda5c437f0 2092 for(loopcounter = 0; loopcounter < headersize; loopcounter++)
mbed_official 133:d4dda5c437f0 2093 {
mbed_official 133:d4dda5c437f0 2094 hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
mbed_official 133:d4dda5c437f0 2095 }
mbed_official 133:d4dda5c437f0 2096 /* Check if the header size is modulo 16 */
mbed_official 133:d4dda5c437f0 2097 if ((headersize % 16) != 0)
mbed_official 133:d4dda5c437f0 2098 {
mbed_official 133:d4dda5c437f0 2099 /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
mbed_official 133:d4dda5c437f0 2100 for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
mbed_official 133:d4dda5c437f0 2101 {
mbed_official 133:d4dda5c437f0 2102 hcryp->Init.pScratch[loopcounter] = 0;
mbed_official 133:d4dda5c437f0 2103 }
mbed_official 133:d4dda5c437f0 2104 /* Set the header size to modulo 16 */
mbed_official 133:d4dda5c437f0 2105 headersize = ((headersize/16) + 1) * 16;
mbed_official 133:d4dda5c437f0 2106 }
mbed_official 133:d4dda5c437f0 2107 /* Set the pointer headeraddr to hcryp->Init.pScratch */
mbed_official 133:d4dda5c437f0 2108 headeraddr = (uint32_t)hcryp->Init.pScratch;
mbed_official 133:d4dda5c437f0 2109 }
mbed_official 133:d4dda5c437f0 2110 /*********************** Formatting the block B0 ************************/
mbed_official 133:d4dda5c437f0 2111 if(headersize != 0)
mbed_official 133:d4dda5c437f0 2112 {
mbed_official 133:d4dda5c437f0 2113 blockb0[0] = 0x40;
mbed_official 133:d4dda5c437f0 2114 }
mbed_official 133:d4dda5c437f0 2115 /* Flags byte */
mbed_official 133:d4dda5c437f0 2116 /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
mbed_official 133:d4dda5c437f0 2117 blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
mbed_official 133:d4dda5c437f0 2118 blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
mbed_official 133:d4dda5c437f0 2119
mbed_official 133:d4dda5c437f0 2120 for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
mbed_official 133:d4dda5c437f0 2121 {
mbed_official 133:d4dda5c437f0 2122 blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
mbed_official 133:d4dda5c437f0 2123 }
mbed_official 133:d4dda5c437f0 2124 for ( ; loopcounter < 13; loopcounter++)
mbed_official 133:d4dda5c437f0 2125 {
mbed_official 133:d4dda5c437f0 2126 blockb0[loopcounter+1] = 0;
mbed_official 133:d4dda5c437f0 2127 }
mbed_official 133:d4dda5c437f0 2128
mbed_official 133:d4dda5c437f0 2129 blockb0[14] = (Size >> 8);
mbed_official 133:d4dda5c437f0 2130 blockb0[15] = (Size & 0xFF);
mbed_official 133:d4dda5c437f0 2131
mbed_official 133:d4dda5c437f0 2132 /************************* Formatting the initial counter ***************/
mbed_official 133:d4dda5c437f0 2133 /* Byte 0:
mbed_official 133:d4dda5c437f0 2134 Bits 7 and 6 are reserved and shall be set to 0
mbed_official 133:d4dda5c437f0 2135 Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
mbed_official 133:d4dda5c437f0 2136 blocks are distinct from B0
mbed_official 133:d4dda5c437f0 2137 Bits 0, 1, and 2 contain the same encoding of q as in B0
mbed_official 133:d4dda5c437f0 2138 */
mbed_official 133:d4dda5c437f0 2139 ctr[0] = blockb0[0] & 0x07;
mbed_official 133:d4dda5c437f0 2140 /* byte 1 to NonceSize is the IV (Nonce) */
mbed_official 133:d4dda5c437f0 2141 for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
mbed_official 133:d4dda5c437f0 2142 {
mbed_official 133:d4dda5c437f0 2143 ctr[loopcounter] = blockb0[loopcounter];
mbed_official 133:d4dda5c437f0 2144 }
mbed_official 133:d4dda5c437f0 2145 /* Set the LSB to 1 */
mbed_official 133:d4dda5c437f0 2146 ctr[15] |= 0x01;
mbed_official 133:d4dda5c437f0 2147
mbed_official 133:d4dda5c437f0 2148 /* Set the key */
mbed_official 133:d4dda5c437f0 2149 CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official 133:d4dda5c437f0 2150
mbed_official 133:d4dda5c437f0 2151 /* Set the CRYP peripheral in AES CCM mode */
mbed_official 133:d4dda5c437f0 2152 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
mbed_official 133:d4dda5c437f0 2153
mbed_official 133:d4dda5c437f0 2154 /* Set the Initialization Vector */
mbed_official 133:d4dda5c437f0 2155 CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, CRYP_KEYSIZE_128B);
mbed_official 133:d4dda5c437f0 2156
mbed_official 133:d4dda5c437f0 2157 /* Select init phase */
mbed_official 133:d4dda5c437f0 2158 __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
mbed_official 133:d4dda5c437f0 2159
mbed_official 133:d4dda5c437f0 2160 b0addr = (uint32_t)blockb0;
mbed_official 133:d4dda5c437f0 2161 /* Write the blockb0 block in the IN FIFO */
mbed_official 133:d4dda5c437f0 2162 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 2163 b0addr+=4;
mbed_official 133:d4dda5c437f0 2164 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 2165 b0addr+=4;
mbed_official 133:d4dda5c437f0 2166 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 2167 b0addr+=4;
mbed_official 133:d4dda5c437f0 2168 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 2169
mbed_official 133:d4dda5c437f0 2170 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 2171 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 2172
mbed_official 133:d4dda5c437f0 2173 /* Get timeout */
mbed_official 133:d4dda5c437f0 2174 timeout = HAL_GetTick() + 1;
mbed_official 133:d4dda5c437f0 2175
mbed_official 133:d4dda5c437f0 2176 while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official 133:d4dda5c437f0 2177 {
mbed_official 133:d4dda5c437f0 2178 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 2179 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 2180 {
mbed_official 133:d4dda5c437f0 2181 /* Change state */
mbed_official 133:d4dda5c437f0 2182 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 2183
mbed_official 133:d4dda5c437f0 2184 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 2185 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 2186
mbed_official 133:d4dda5c437f0 2187 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 2188 }
mbed_official 133:d4dda5c437f0 2189 }
mbed_official 133:d4dda5c437f0 2190 /***************************** Header phase *****************************/
mbed_official 133:d4dda5c437f0 2191 if(headersize != 0)
mbed_official 133:d4dda5c437f0 2192 {
mbed_official 133:d4dda5c437f0 2193 /* Select header phase */
mbed_official 133:d4dda5c437f0 2194 __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
mbed_official 133:d4dda5c437f0 2195
mbed_official 133:d4dda5c437f0 2196 /* Enable Crypto processor */
mbed_official 133:d4dda5c437f0 2197 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 2198
mbed_official 133:d4dda5c437f0 2199 for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
mbed_official 133:d4dda5c437f0 2200 {
mbed_official 133:d4dda5c437f0 2201 /* Get timeout */
mbed_official 133:d4dda5c437f0 2202 timeout = HAL_GetTick() + 1;
mbed_official 133:d4dda5c437f0 2203
mbed_official 133:d4dda5c437f0 2204 while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
mbed_official 133:d4dda5c437f0 2205 {
mbed_official 133:d4dda5c437f0 2206 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 2207 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 2208 {
mbed_official 133:d4dda5c437f0 2209 /* Change state */
mbed_official 133:d4dda5c437f0 2210 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 2211
mbed_official 133:d4dda5c437f0 2212 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 2213 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 2214
mbed_official 133:d4dda5c437f0 2215 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 2216 }
mbed_official 133:d4dda5c437f0 2217 }
mbed_official 133:d4dda5c437f0 2218 /* Write the header block in the IN FIFO */
mbed_official 133:d4dda5c437f0 2219 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 2220 headeraddr+=4;
mbed_official 133:d4dda5c437f0 2221 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 2222 headeraddr+=4;
mbed_official 133:d4dda5c437f0 2223 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 2224 headeraddr+=4;
mbed_official 133:d4dda5c437f0 2225 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 2226 headeraddr+=4;
mbed_official 133:d4dda5c437f0 2227 }
mbed_official 133:d4dda5c437f0 2228
mbed_official 133:d4dda5c437f0 2229 /* Get timeout */
mbed_official 133:d4dda5c437f0 2230 timeout = HAL_GetTick() + 1;
mbed_official 133:d4dda5c437f0 2231
mbed_official 133:d4dda5c437f0 2232 while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
mbed_official 133:d4dda5c437f0 2233 {
mbed_official 133:d4dda5c437f0 2234 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 2235 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 2236 {
mbed_official 133:d4dda5c437f0 2237 /* Change state */
mbed_official 133:d4dda5c437f0 2238 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 2239
mbed_official 133:d4dda5c437f0 2240 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 2241 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 2242
mbed_official 133:d4dda5c437f0 2243 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 2244 }
mbed_official 133:d4dda5c437f0 2245 }
mbed_official 133:d4dda5c437f0 2246 }
mbed_official 133:d4dda5c437f0 2247 /* Save formatted counter into the scratch buffer pScratch */
mbed_official 133:d4dda5c437f0 2248 for(loopcounter = 0; (loopcounter < 16); loopcounter++)
mbed_official 133:d4dda5c437f0 2249 {
mbed_official 133:d4dda5c437f0 2250 hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
mbed_official 133:d4dda5c437f0 2251 }
mbed_official 133:d4dda5c437f0 2252 /* Reset bit 0 */
mbed_official 133:d4dda5c437f0 2253 hcryp->Init.pScratch[15] &= 0xfe;
mbed_official 133:d4dda5c437f0 2254
mbed_official 133:d4dda5c437f0 2255 /* Select payload phase once the header phase is performed */
mbed_official 133:d4dda5c437f0 2256 __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official 133:d4dda5c437f0 2257
mbed_official 133:d4dda5c437f0 2258 /* Flush FIFO */
mbed_official 133:d4dda5c437f0 2259 __HAL_CRYP_FIFO_FLUSH();
mbed_official 133:d4dda5c437f0 2260
mbed_official 133:d4dda5c437f0 2261 /* Set the phase */
mbed_official 133:d4dda5c437f0 2262 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official 133:d4dda5c437f0 2263 }
mbed_official 133:d4dda5c437f0 2264
mbed_official 133:d4dda5c437f0 2265 /* Set the input and output addresses and start DMA transfer */
mbed_official 133:d4dda5c437f0 2266 CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
mbed_official 133:d4dda5c437f0 2267
mbed_official 133:d4dda5c437f0 2268 /* Unlock process */
mbed_official 133:d4dda5c437f0 2269 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 2270
mbed_official 133:d4dda5c437f0 2271 /* Return function status */
mbed_official 133:d4dda5c437f0 2272 return HAL_OK;
mbed_official 133:d4dda5c437f0 2273 }
mbed_official 133:d4dda5c437f0 2274 else
mbed_official 133:d4dda5c437f0 2275 {
mbed_official 133:d4dda5c437f0 2276 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 2277 }
mbed_official 133:d4dda5c437f0 2278 }
mbed_official 133:d4dda5c437f0 2279
mbed_official 133:d4dda5c437f0 2280 /**
mbed_official 133:d4dda5c437f0 2281 * @brief Initializes the CRYP peripheral in AES GCM decryption mode using DMA.
mbed_official 133:d4dda5c437f0 2282 * @param hcryp: CRYP handle
mbed_official 133:d4dda5c437f0 2283 * @param pCypherData: Pointer to the cyphertext buffer.
mbed_official 133:d4dda5c437f0 2284 * @param Size: Length of the cyphertext buffer, must be a multiple of 16
mbed_official 133:d4dda5c437f0 2285 * @param pPlainData: Pointer to the plaintext buffer
mbed_official 133:d4dda5c437f0 2286 * @retval HAL status
mbed_official 133:d4dda5c437f0 2287 */
mbed_official 133:d4dda5c437f0 2288 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
mbed_official 133:d4dda5c437f0 2289 {
mbed_official 133:d4dda5c437f0 2290 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 2291 uint32_t inputaddr;
mbed_official 133:d4dda5c437f0 2292 uint32_t outputaddr;
mbed_official 133:d4dda5c437f0 2293
mbed_official 133:d4dda5c437f0 2294 if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
mbed_official 133:d4dda5c437f0 2295 {
mbed_official 133:d4dda5c437f0 2296 /* Process Locked */
mbed_official 133:d4dda5c437f0 2297 __HAL_LOCK(hcryp);
mbed_official 133:d4dda5c437f0 2298
mbed_official 133:d4dda5c437f0 2299 inputaddr = (uint32_t)pCypherData;
mbed_official 133:d4dda5c437f0 2300 outputaddr = (uint32_t)pPlainData;
mbed_official 133:d4dda5c437f0 2301
mbed_official 133:d4dda5c437f0 2302 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 2303 hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official 133:d4dda5c437f0 2304
mbed_official 133:d4dda5c437f0 2305 /* Check if initialization phase has already been performed */
mbed_official 133:d4dda5c437f0 2306 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official 133:d4dda5c437f0 2307 {
mbed_official 133:d4dda5c437f0 2308 /* Set the key */
mbed_official 133:d4dda5c437f0 2309 CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official 133:d4dda5c437f0 2310
mbed_official 133:d4dda5c437f0 2311 /* Set the CRYP peripheral in AES GCM decryption mode */
mbed_official 133:d4dda5c437f0 2312 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
mbed_official 133:d4dda5c437f0 2313
mbed_official 133:d4dda5c437f0 2314 /* Set the Initialization Vector */
mbed_official 133:d4dda5c437f0 2315 CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
mbed_official 133:d4dda5c437f0 2316
mbed_official 133:d4dda5c437f0 2317 /* Enable CRYP to start the init phase */
mbed_official 133:d4dda5c437f0 2318 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 2319
mbed_official 133:d4dda5c437f0 2320 /* Get timeout */
mbed_official 133:d4dda5c437f0 2321 timeout = HAL_GetTick() + 1;
mbed_official 133:d4dda5c437f0 2322
mbed_official 133:d4dda5c437f0 2323 while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official 133:d4dda5c437f0 2324 {
mbed_official 133:d4dda5c437f0 2325 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 2326 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 2327 {
mbed_official 133:d4dda5c437f0 2328 /* Change state */
mbed_official 133:d4dda5c437f0 2329 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 2330
mbed_official 133:d4dda5c437f0 2331 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 2332 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 2333
mbed_official 133:d4dda5c437f0 2334 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 2335 }
mbed_official 133:d4dda5c437f0 2336 }
mbed_official 133:d4dda5c437f0 2337
mbed_official 133:d4dda5c437f0 2338 /* Set the header phase */
mbed_official 133:d4dda5c437f0 2339 if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
mbed_official 133:d4dda5c437f0 2340 {
mbed_official 133:d4dda5c437f0 2341 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 2342 }
mbed_official 133:d4dda5c437f0 2343 /* Disable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 2344 __HAL_CRYP_DISABLE();
mbed_official 133:d4dda5c437f0 2345
mbed_official 133:d4dda5c437f0 2346 /* Select payload phase once the header phase is performed */
mbed_official 133:d4dda5c437f0 2347 __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official 133:d4dda5c437f0 2348
mbed_official 133:d4dda5c437f0 2349 /* Set the phase */
mbed_official 133:d4dda5c437f0 2350 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official 133:d4dda5c437f0 2351 }
mbed_official 133:d4dda5c437f0 2352
mbed_official 133:d4dda5c437f0 2353 /* Set the input and output addresses and start DMA transfer */
mbed_official 133:d4dda5c437f0 2354 CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
mbed_official 133:d4dda5c437f0 2355
mbed_official 133:d4dda5c437f0 2356 /* Unlock process */
mbed_official 133:d4dda5c437f0 2357 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 2358
mbed_official 133:d4dda5c437f0 2359 /* Return function status */
mbed_official 133:d4dda5c437f0 2360 return HAL_OK;
mbed_official 133:d4dda5c437f0 2361 }
mbed_official 133:d4dda5c437f0 2362 else
mbed_official 133:d4dda5c437f0 2363 {
mbed_official 133:d4dda5c437f0 2364 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 2365 }
mbed_official 133:d4dda5c437f0 2366 }
mbed_official 133:d4dda5c437f0 2367
mbed_official 133:d4dda5c437f0 2368 /**
mbed_official 133:d4dda5c437f0 2369 * @brief Initializes the CRYP peripheral in AES CCM decryption mode using DMA
mbed_official 133:d4dda5c437f0 2370 * then decrypted pCypherData. The cypher data are available in pPlainData.
mbed_official 133:d4dda5c437f0 2371 * @param hcryp: CRYP handle
mbed_official 133:d4dda5c437f0 2372 * @param pCypherData: Pointer to the cyphertext buffer
mbed_official 133:d4dda5c437f0 2373 * @param Size: Length of the plaintext buffer, must be a multiple of 16
mbed_official 133:d4dda5c437f0 2374 * @param pPlainData: Pointer to the plaintext buffer
mbed_official 133:d4dda5c437f0 2375 * @retval HAL status
mbed_official 133:d4dda5c437f0 2376 */
mbed_official 133:d4dda5c437f0 2377 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
mbed_official 133:d4dda5c437f0 2378 {
mbed_official 133:d4dda5c437f0 2379 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 2380 uint32_t inputaddr;
mbed_official 133:d4dda5c437f0 2381 uint32_t outputaddr;
mbed_official 133:d4dda5c437f0 2382 uint32_t headersize;
mbed_official 133:d4dda5c437f0 2383 uint32_t headeraddr;
mbed_official 133:d4dda5c437f0 2384 uint32_t loopcounter = 0;
mbed_official 133:d4dda5c437f0 2385 uint32_t bufferidx = 0;
mbed_official 133:d4dda5c437f0 2386 uint8_t blockb0[16] = {0};/* Block B0 */
mbed_official 133:d4dda5c437f0 2387 uint8_t ctr[16] = {0}; /* Counter */
mbed_official 133:d4dda5c437f0 2388 uint32_t b0addr = (uint32_t)blockb0;
mbed_official 133:d4dda5c437f0 2389
mbed_official 133:d4dda5c437f0 2390 if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
mbed_official 133:d4dda5c437f0 2391 {
mbed_official 133:d4dda5c437f0 2392 /* Process Locked */
mbed_official 133:d4dda5c437f0 2393 __HAL_LOCK(hcryp);
mbed_official 133:d4dda5c437f0 2394
mbed_official 133:d4dda5c437f0 2395 inputaddr = (uint32_t)pCypherData;
mbed_official 133:d4dda5c437f0 2396 outputaddr = (uint32_t)pPlainData;
mbed_official 133:d4dda5c437f0 2397
mbed_official 133:d4dda5c437f0 2398 headersize = hcryp->Init.HeaderSize;
mbed_official 133:d4dda5c437f0 2399 headeraddr = (uint32_t)hcryp->Init.Header;
mbed_official 133:d4dda5c437f0 2400
mbed_official 133:d4dda5c437f0 2401 hcryp->CrypInCount = Size;
mbed_official 133:d4dda5c437f0 2402 hcryp->pCrypInBuffPtr = pCypherData;
mbed_official 133:d4dda5c437f0 2403 hcryp->pCrypOutBuffPtr = pPlainData;
mbed_official 133:d4dda5c437f0 2404 hcryp->CrypOutCount = Size;
mbed_official 133:d4dda5c437f0 2405
mbed_official 133:d4dda5c437f0 2406 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 2407 hcryp->State = HAL_CRYP_STATE_BUSY;
mbed_official 133:d4dda5c437f0 2408
mbed_official 133:d4dda5c437f0 2409 /* Check if initialization phase has already been performed */
mbed_official 133:d4dda5c437f0 2410 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
mbed_official 133:d4dda5c437f0 2411 {
mbed_official 133:d4dda5c437f0 2412 /************************ Formatting the header block *******************/
mbed_official 133:d4dda5c437f0 2413 if(headersize != 0)
mbed_official 133:d4dda5c437f0 2414 {
mbed_official 133:d4dda5c437f0 2415 /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
mbed_official 133:d4dda5c437f0 2416 if(headersize < 65280)
mbed_official 133:d4dda5c437f0 2417 {
mbed_official 133:d4dda5c437f0 2418 hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
mbed_official 133:d4dda5c437f0 2419 hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
mbed_official 133:d4dda5c437f0 2420 headersize += 2;
mbed_official 133:d4dda5c437f0 2421 }
mbed_official 133:d4dda5c437f0 2422 else
mbed_official 133:d4dda5c437f0 2423 {
mbed_official 133:d4dda5c437f0 2424 /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
mbed_official 133:d4dda5c437f0 2425 hcryp->Init.pScratch[bufferidx++] = 0xFF;
mbed_official 133:d4dda5c437f0 2426 hcryp->Init.pScratch[bufferidx++] = 0xFE;
mbed_official 133:d4dda5c437f0 2427 hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
mbed_official 133:d4dda5c437f0 2428 hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
mbed_official 133:d4dda5c437f0 2429 hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
mbed_official 133:d4dda5c437f0 2430 hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
mbed_official 133:d4dda5c437f0 2431 headersize += 6;
mbed_official 133:d4dda5c437f0 2432 }
mbed_official 133:d4dda5c437f0 2433 /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
mbed_official 133:d4dda5c437f0 2434 for(loopcounter = 0; loopcounter < headersize; loopcounter++)
mbed_official 133:d4dda5c437f0 2435 {
mbed_official 133:d4dda5c437f0 2436 hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
mbed_official 133:d4dda5c437f0 2437 }
mbed_official 133:d4dda5c437f0 2438 /* Check if the header size is modulo 16 */
mbed_official 133:d4dda5c437f0 2439 if ((headersize % 16) != 0)
mbed_official 133:d4dda5c437f0 2440 {
mbed_official 133:d4dda5c437f0 2441 /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
mbed_official 133:d4dda5c437f0 2442 for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
mbed_official 133:d4dda5c437f0 2443 {
mbed_official 133:d4dda5c437f0 2444 hcryp->Init.pScratch[loopcounter] = 0;
mbed_official 133:d4dda5c437f0 2445 }
mbed_official 133:d4dda5c437f0 2446 /* Set the header size to modulo 16 */
mbed_official 133:d4dda5c437f0 2447 headersize = ((headersize/16) + 1) * 16;
mbed_official 133:d4dda5c437f0 2448 }
mbed_official 133:d4dda5c437f0 2449 /* Set the pointer headeraddr to hcryp->Init.pScratch */
mbed_official 133:d4dda5c437f0 2450 headeraddr = (uint32_t)hcryp->Init.pScratch;
mbed_official 133:d4dda5c437f0 2451 }
mbed_official 133:d4dda5c437f0 2452 /*********************** Formatting the block B0 ************************/
mbed_official 133:d4dda5c437f0 2453 if(headersize != 0)
mbed_official 133:d4dda5c437f0 2454 {
mbed_official 133:d4dda5c437f0 2455 blockb0[0] = 0x40;
mbed_official 133:d4dda5c437f0 2456 }
mbed_official 133:d4dda5c437f0 2457 /* Flags byte */
mbed_official 133:d4dda5c437f0 2458 /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
mbed_official 133:d4dda5c437f0 2459 blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
mbed_official 133:d4dda5c437f0 2460 blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
mbed_official 133:d4dda5c437f0 2461
mbed_official 133:d4dda5c437f0 2462 for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
mbed_official 133:d4dda5c437f0 2463 {
mbed_official 133:d4dda5c437f0 2464 blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
mbed_official 133:d4dda5c437f0 2465 }
mbed_official 133:d4dda5c437f0 2466 for ( ; loopcounter < 13; loopcounter++)
mbed_official 133:d4dda5c437f0 2467 {
mbed_official 133:d4dda5c437f0 2468 blockb0[loopcounter+1] = 0;
mbed_official 133:d4dda5c437f0 2469 }
mbed_official 133:d4dda5c437f0 2470
mbed_official 133:d4dda5c437f0 2471 blockb0[14] = (Size >> 8);
mbed_official 133:d4dda5c437f0 2472 blockb0[15] = (Size & 0xFF);
mbed_official 133:d4dda5c437f0 2473
mbed_official 133:d4dda5c437f0 2474 /************************* Formatting the initial counter ***************/
mbed_official 133:d4dda5c437f0 2475 /* Byte 0:
mbed_official 133:d4dda5c437f0 2476 Bits 7 and 6 are reserved and shall be set to 0
mbed_official 133:d4dda5c437f0 2477 Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
mbed_official 133:d4dda5c437f0 2478 blocks are distinct from B0
mbed_official 133:d4dda5c437f0 2479 Bits 0, 1, and 2 contain the same encoding of q as in B0
mbed_official 133:d4dda5c437f0 2480 */
mbed_official 133:d4dda5c437f0 2481 ctr[0] = blockb0[0] & 0x07;
mbed_official 133:d4dda5c437f0 2482 /* byte 1 to NonceSize is the IV (Nonce) */
mbed_official 133:d4dda5c437f0 2483 for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
mbed_official 133:d4dda5c437f0 2484 {
mbed_official 133:d4dda5c437f0 2485 ctr[loopcounter] = blockb0[loopcounter];
mbed_official 133:d4dda5c437f0 2486 }
mbed_official 133:d4dda5c437f0 2487 /* Set the LSB to 1 */
mbed_official 133:d4dda5c437f0 2488 ctr[15] |= 0x01;
mbed_official 133:d4dda5c437f0 2489
mbed_official 133:d4dda5c437f0 2490 /* Set the key */
mbed_official 133:d4dda5c437f0 2491 CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
mbed_official 133:d4dda5c437f0 2492
mbed_official 133:d4dda5c437f0 2493 /* Set the CRYP peripheral in AES CCM mode */
mbed_official 133:d4dda5c437f0 2494 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
mbed_official 133:d4dda5c437f0 2495
mbed_official 133:d4dda5c437f0 2496 /* Set the Initialization Vector */
mbed_official 133:d4dda5c437f0 2497 CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, CRYP_KEYSIZE_128B);
mbed_official 133:d4dda5c437f0 2498
mbed_official 133:d4dda5c437f0 2499 /* Select init phase */
mbed_official 133:d4dda5c437f0 2500 __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
mbed_official 133:d4dda5c437f0 2501
mbed_official 133:d4dda5c437f0 2502 b0addr = (uint32_t)blockb0;
mbed_official 133:d4dda5c437f0 2503 /* Write the blockb0 block in the IN FIFO */
mbed_official 133:d4dda5c437f0 2504 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 2505 b0addr+=4;
mbed_official 133:d4dda5c437f0 2506 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 2507 b0addr+=4;
mbed_official 133:d4dda5c437f0 2508 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 2509 b0addr+=4;
mbed_official 133:d4dda5c437f0 2510 CRYP->DR = *(uint32_t*)(b0addr);
mbed_official 133:d4dda5c437f0 2511
mbed_official 133:d4dda5c437f0 2512 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 2513 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 2514
mbed_official 133:d4dda5c437f0 2515 /* Get timeout */
mbed_official 133:d4dda5c437f0 2516 timeout = HAL_GetTick() + 1;
mbed_official 133:d4dda5c437f0 2517
mbed_official 133:d4dda5c437f0 2518 while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
mbed_official 133:d4dda5c437f0 2519 {
mbed_official 133:d4dda5c437f0 2520 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 2521
mbed_official 133:d4dda5c437f0 2522 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 2523 {
mbed_official 133:d4dda5c437f0 2524 /* Change state */
mbed_official 133:d4dda5c437f0 2525 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 2526
mbed_official 133:d4dda5c437f0 2527 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 2528 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 2529
mbed_official 133:d4dda5c437f0 2530 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 2531
mbed_official 133:d4dda5c437f0 2532 }
mbed_official 133:d4dda5c437f0 2533 }
mbed_official 133:d4dda5c437f0 2534 /***************************** Header phase *****************************/
mbed_official 133:d4dda5c437f0 2535 if(headersize != 0)
mbed_official 133:d4dda5c437f0 2536 {
mbed_official 133:d4dda5c437f0 2537 /* Select header phase */
mbed_official 133:d4dda5c437f0 2538 __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
mbed_official 133:d4dda5c437f0 2539
mbed_official 133:d4dda5c437f0 2540 /* Enable Crypto processor */
mbed_official 133:d4dda5c437f0 2541 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 2542
mbed_official 133:d4dda5c437f0 2543 for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
mbed_official 133:d4dda5c437f0 2544 {
mbed_official 133:d4dda5c437f0 2545 /* Get timeout */
mbed_official 133:d4dda5c437f0 2546 timeout = HAL_GetTick() + 1;
mbed_official 133:d4dda5c437f0 2547
mbed_official 133:d4dda5c437f0 2548 while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
mbed_official 133:d4dda5c437f0 2549 {
mbed_official 133:d4dda5c437f0 2550 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 2551 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 2552 {
mbed_official 133:d4dda5c437f0 2553 /* Change state */
mbed_official 133:d4dda5c437f0 2554 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 2555
mbed_official 133:d4dda5c437f0 2556 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 2557 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 2558
mbed_official 133:d4dda5c437f0 2559 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 2560 }
mbed_official 133:d4dda5c437f0 2561 }
mbed_official 133:d4dda5c437f0 2562 /* Write the header block in the IN FIFO */
mbed_official 133:d4dda5c437f0 2563 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 2564 headeraddr+=4;
mbed_official 133:d4dda5c437f0 2565 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 2566 headeraddr+=4;
mbed_official 133:d4dda5c437f0 2567 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 2568 headeraddr+=4;
mbed_official 133:d4dda5c437f0 2569 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 2570 headeraddr+=4;
mbed_official 133:d4dda5c437f0 2571 }
mbed_official 133:d4dda5c437f0 2572
mbed_official 133:d4dda5c437f0 2573 /* Get timeout */
mbed_official 133:d4dda5c437f0 2574 timeout = HAL_GetTick() + 1;
mbed_official 133:d4dda5c437f0 2575
mbed_official 133:d4dda5c437f0 2576 while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
mbed_official 133:d4dda5c437f0 2577 {
mbed_official 133:d4dda5c437f0 2578 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 2579 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 2580 {
mbed_official 133:d4dda5c437f0 2581 /* Change state */
mbed_official 133:d4dda5c437f0 2582 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 2583
mbed_official 133:d4dda5c437f0 2584 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 2585 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 2586
mbed_official 133:d4dda5c437f0 2587 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 2588 }
mbed_official 133:d4dda5c437f0 2589 }
mbed_official 133:d4dda5c437f0 2590 }
mbed_official 133:d4dda5c437f0 2591 /* Save formatted counter into the scratch buffer pScratch */
mbed_official 133:d4dda5c437f0 2592 for(loopcounter = 0; (loopcounter < 16); loopcounter++)
mbed_official 133:d4dda5c437f0 2593 {
mbed_official 133:d4dda5c437f0 2594 hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
mbed_official 133:d4dda5c437f0 2595 }
mbed_official 133:d4dda5c437f0 2596 /* Reset bit 0 */
mbed_official 133:d4dda5c437f0 2597 hcryp->Init.pScratch[15] &= 0xfe;
mbed_official 133:d4dda5c437f0 2598 /* Select payload phase once the header phase is performed */
mbed_official 133:d4dda5c437f0 2599 __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
mbed_official 133:d4dda5c437f0 2600
mbed_official 133:d4dda5c437f0 2601 /* Flush FIFO */
mbed_official 133:d4dda5c437f0 2602 __HAL_CRYP_FIFO_FLUSH();
mbed_official 133:d4dda5c437f0 2603
mbed_official 133:d4dda5c437f0 2604 /* Set the phase */
mbed_official 133:d4dda5c437f0 2605 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
mbed_official 133:d4dda5c437f0 2606 }
mbed_official 133:d4dda5c437f0 2607 /* Set the input and output addresses and start DMA transfer */
mbed_official 133:d4dda5c437f0 2608 CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
mbed_official 133:d4dda5c437f0 2609
mbed_official 133:d4dda5c437f0 2610 /* Unlock process */
mbed_official 133:d4dda5c437f0 2611 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 2612
mbed_official 133:d4dda5c437f0 2613 /* Return function status */
mbed_official 133:d4dda5c437f0 2614 return HAL_OK;
mbed_official 133:d4dda5c437f0 2615 }
mbed_official 133:d4dda5c437f0 2616 else
mbed_official 133:d4dda5c437f0 2617 {
mbed_official 133:d4dda5c437f0 2618 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 2619 }
mbed_official 133:d4dda5c437f0 2620 }
mbed_official 133:d4dda5c437f0 2621
mbed_official 133:d4dda5c437f0 2622 /**
mbed_official 133:d4dda5c437f0 2623 * @brief This function handles CRYP interrupt request.
mbed_official 133:d4dda5c437f0 2624 * @param hcryp: CRYP handle
mbed_official 133:d4dda5c437f0 2625 * @retval None
mbed_official 133:d4dda5c437f0 2626 */
mbed_official 133:d4dda5c437f0 2627 void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp)
mbed_official 133:d4dda5c437f0 2628 {
mbed_official 133:d4dda5c437f0 2629 switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)
mbed_official 133:d4dda5c437f0 2630 {
mbed_official 133:d4dda5c437f0 2631 case CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT:
mbed_official 133:d4dda5c437f0 2632 HAL_CRYPEx_AESGCM_Encrypt_IT(hcryp, NULL, 0, NULL);
mbed_official 133:d4dda5c437f0 2633 break;
mbed_official 133:d4dda5c437f0 2634
mbed_official 133:d4dda5c437f0 2635 case CRYP_CR_ALGOMODE_AES_GCM_DECRYPT:
mbed_official 133:d4dda5c437f0 2636 HAL_CRYPEx_AESGCM_Decrypt_IT(hcryp, NULL, 0, NULL);
mbed_official 133:d4dda5c437f0 2637 break;
mbed_official 133:d4dda5c437f0 2638
mbed_official 133:d4dda5c437f0 2639 case CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT:
mbed_official 133:d4dda5c437f0 2640 HAL_CRYPEx_AESCCM_Encrypt_IT(hcryp, NULL, 0, NULL);
mbed_official 133:d4dda5c437f0 2641 break;
mbed_official 133:d4dda5c437f0 2642
mbed_official 133:d4dda5c437f0 2643 case CRYP_CR_ALGOMODE_AES_CCM_DECRYPT:
mbed_official 133:d4dda5c437f0 2644 HAL_CRYPEx_AESCCM_Decrypt_IT(hcryp, NULL, 0, NULL);
mbed_official 133:d4dda5c437f0 2645 break;
mbed_official 133:d4dda5c437f0 2646
mbed_official 133:d4dda5c437f0 2647 default:
mbed_official 133:d4dda5c437f0 2648 break;
mbed_official 133:d4dda5c437f0 2649 }
mbed_official 133:d4dda5c437f0 2650 }
mbed_official 133:d4dda5c437f0 2651
mbed_official 133:d4dda5c437f0 2652 /**
mbed_official 133:d4dda5c437f0 2653 * @}
mbed_official 133:d4dda5c437f0 2654 */
mbed_official 133:d4dda5c437f0 2655
mbed_official 133:d4dda5c437f0 2656 /**
mbed_official 133:d4dda5c437f0 2657 * @brief DMA CRYP Input Data process complete callback.
mbed_official 133:d4dda5c437f0 2658 * @param hdma: DMA handle
mbed_official 133:d4dda5c437f0 2659 * @retval None
mbed_official 133:d4dda5c437f0 2660 */
mbed_official 133:d4dda5c437f0 2661 static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 2662 {
mbed_official 133:d4dda5c437f0 2663 CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 133:d4dda5c437f0 2664
mbed_official 133:d4dda5c437f0 2665 /* Disable the DMA transfer for input Fifo request by resetting the DIEN bit
mbed_official 133:d4dda5c437f0 2666 in the DMACR register */
mbed_official 133:d4dda5c437f0 2667 CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
mbed_official 133:d4dda5c437f0 2668
mbed_official 133:d4dda5c437f0 2669 /* Call input data transfer complete callback */
mbed_official 133:d4dda5c437f0 2670 HAL_CRYP_InCpltCallback(hcryp);
mbed_official 133:d4dda5c437f0 2671 }
mbed_official 133:d4dda5c437f0 2672
mbed_official 133:d4dda5c437f0 2673 /**
mbed_official 133:d4dda5c437f0 2674 * @brief DMA CRYP Output Data process complete callback.
mbed_official 133:d4dda5c437f0 2675 * @param hdma: DMA handle
mbed_official 133:d4dda5c437f0 2676 * @retval None
mbed_official 133:d4dda5c437f0 2677 */
mbed_official 133:d4dda5c437f0 2678 static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 2679 {
mbed_official 133:d4dda5c437f0 2680 CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 133:d4dda5c437f0 2681
mbed_official 133:d4dda5c437f0 2682 /* Disable the DMA transfer for output Fifo request by resetting the DOEN bit
mbed_official 133:d4dda5c437f0 2683 in the DMACR register */
mbed_official 133:d4dda5c437f0 2684 CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
mbed_official 133:d4dda5c437f0 2685
mbed_official 133:d4dda5c437f0 2686 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 2687 __HAL_CRYP_DISABLE();
mbed_official 133:d4dda5c437f0 2688
mbed_official 133:d4dda5c437f0 2689 /* Change the CRYP peripheral state */
mbed_official 133:d4dda5c437f0 2690 hcryp->State = HAL_CRYP_STATE_READY;
mbed_official 133:d4dda5c437f0 2691
mbed_official 133:d4dda5c437f0 2692 /* Call output data transfer complete callback */
mbed_official 133:d4dda5c437f0 2693 HAL_CRYP_OutCpltCallback(hcryp);
mbed_official 133:d4dda5c437f0 2694 }
mbed_official 133:d4dda5c437f0 2695
mbed_official 133:d4dda5c437f0 2696 /**
mbed_official 133:d4dda5c437f0 2697 * @brief DMA CRYP communication error callback.
mbed_official 133:d4dda5c437f0 2698 * @param hdma: DMA handle
mbed_official 133:d4dda5c437f0 2699 * @retval None
mbed_official 133:d4dda5c437f0 2700 */
mbed_official 133:d4dda5c437f0 2701 static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 2702 {
mbed_official 133:d4dda5c437f0 2703 CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 133:d4dda5c437f0 2704 hcryp->State= HAL_CRYP_STATE_READY;
mbed_official 133:d4dda5c437f0 2705 HAL_CRYP_ErrorCallback(hcryp);
mbed_official 133:d4dda5c437f0 2706 }
mbed_official 133:d4dda5c437f0 2707
mbed_official 133:d4dda5c437f0 2708 /**
mbed_official 133:d4dda5c437f0 2709 * @brief Writes the Key in Key registers.
mbed_official 133:d4dda5c437f0 2710 * @param hcryp: CRYP handle
mbed_official 133:d4dda5c437f0 2711 * @param Key: Pointer to Key buffer
mbed_official 133:d4dda5c437f0 2712 * @param KeySize: Size of Key
mbed_official 133:d4dda5c437f0 2713 * @retval None
mbed_official 133:d4dda5c437f0 2714 */
mbed_official 133:d4dda5c437f0 2715 static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)
mbed_official 133:d4dda5c437f0 2716 {
mbed_official 133:d4dda5c437f0 2717 uint32_t keyaddr = (uint32_t)Key;
mbed_official 133:d4dda5c437f0 2718
mbed_official 133:d4dda5c437f0 2719 switch(KeySize)
mbed_official 133:d4dda5c437f0 2720 {
mbed_official 133:d4dda5c437f0 2721 case CRYP_KEYSIZE_256B:
mbed_official 133:d4dda5c437f0 2722 /* Key Initialisation */
mbed_official 133:d4dda5c437f0 2723 CRYP->K0LR = __REV(*(uint32_t*)(keyaddr));
mbed_official 133:d4dda5c437f0 2724 keyaddr+=4;
mbed_official 133:d4dda5c437f0 2725 CRYP->K0RR = __REV(*(uint32_t*)(keyaddr));
mbed_official 133:d4dda5c437f0 2726 keyaddr+=4;
mbed_official 133:d4dda5c437f0 2727 CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));
mbed_official 133:d4dda5c437f0 2728 keyaddr+=4;
mbed_official 133:d4dda5c437f0 2729 CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));
mbed_official 133:d4dda5c437f0 2730 keyaddr+=4;
mbed_official 133:d4dda5c437f0 2731 CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
mbed_official 133:d4dda5c437f0 2732 keyaddr+=4;
mbed_official 133:d4dda5c437f0 2733 CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
mbed_official 133:d4dda5c437f0 2734 keyaddr+=4;
mbed_official 133:d4dda5c437f0 2735 CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
mbed_official 133:d4dda5c437f0 2736 keyaddr+=4;
mbed_official 133:d4dda5c437f0 2737 CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
mbed_official 133:d4dda5c437f0 2738 break;
mbed_official 133:d4dda5c437f0 2739 case CRYP_KEYSIZE_192B:
mbed_official 133:d4dda5c437f0 2740 CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));
mbed_official 133:d4dda5c437f0 2741 keyaddr+=4;
mbed_official 133:d4dda5c437f0 2742 CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));
mbed_official 133:d4dda5c437f0 2743 keyaddr+=4;
mbed_official 133:d4dda5c437f0 2744 CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
mbed_official 133:d4dda5c437f0 2745 keyaddr+=4;
mbed_official 133:d4dda5c437f0 2746 CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
mbed_official 133:d4dda5c437f0 2747 keyaddr+=4;
mbed_official 133:d4dda5c437f0 2748 CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
mbed_official 133:d4dda5c437f0 2749 keyaddr+=4;
mbed_official 133:d4dda5c437f0 2750 CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
mbed_official 133:d4dda5c437f0 2751 break;
mbed_official 133:d4dda5c437f0 2752 case CRYP_KEYSIZE_128B:
mbed_official 133:d4dda5c437f0 2753 CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
mbed_official 133:d4dda5c437f0 2754 keyaddr+=4;
mbed_official 133:d4dda5c437f0 2755 CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
mbed_official 133:d4dda5c437f0 2756 keyaddr+=4;
mbed_official 133:d4dda5c437f0 2757 CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
mbed_official 133:d4dda5c437f0 2758 keyaddr+=4;
mbed_official 133:d4dda5c437f0 2759 CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
mbed_official 133:d4dda5c437f0 2760 break;
mbed_official 133:d4dda5c437f0 2761 default:
mbed_official 133:d4dda5c437f0 2762 break;
mbed_official 133:d4dda5c437f0 2763 }
mbed_official 133:d4dda5c437f0 2764 }
mbed_official 133:d4dda5c437f0 2765
mbed_official 133:d4dda5c437f0 2766 /**
mbed_official 133:d4dda5c437f0 2767 * @brief Writes the InitVector/InitCounter in IV registers.
mbed_official 133:d4dda5c437f0 2768 * @param hcryp: CRYP handle
mbed_official 133:d4dda5c437f0 2769 * @param InitVector: Pointer to InitVector/InitCounter buffer
mbed_official 133:d4dda5c437f0 2770 * @param IVSize: Size of the InitVector/InitCounter
mbed_official 133:d4dda5c437f0 2771 * @retval None
mbed_official 133:d4dda5c437f0 2772 */
mbed_official 133:d4dda5c437f0 2773 static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize)
mbed_official 133:d4dda5c437f0 2774 {
mbed_official 133:d4dda5c437f0 2775 uint32_t ivaddr = (uint32_t)InitVector;
mbed_official 133:d4dda5c437f0 2776
mbed_official 133:d4dda5c437f0 2777 switch(IVSize)
mbed_official 133:d4dda5c437f0 2778 {
mbed_official 133:d4dda5c437f0 2779 case CRYP_KEYSIZE_128B:
mbed_official 133:d4dda5c437f0 2780 CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
mbed_official 133:d4dda5c437f0 2781 ivaddr+=4;
mbed_official 133:d4dda5c437f0 2782 CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
mbed_official 133:d4dda5c437f0 2783 ivaddr+=4;
mbed_official 133:d4dda5c437f0 2784 CRYP->IV1LR = __REV(*(uint32_t*)(ivaddr));
mbed_official 133:d4dda5c437f0 2785 ivaddr+=4;
mbed_official 133:d4dda5c437f0 2786 CRYP->IV1RR = __REV(*(uint32_t*)(ivaddr));
mbed_official 133:d4dda5c437f0 2787 break;
mbed_official 133:d4dda5c437f0 2788 /* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */
mbed_official 133:d4dda5c437f0 2789 case CRYP_KEYSIZE_192B:
mbed_official 133:d4dda5c437f0 2790 CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
mbed_official 133:d4dda5c437f0 2791 ivaddr+=4;
mbed_official 133:d4dda5c437f0 2792 CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
mbed_official 133:d4dda5c437f0 2793 break;
mbed_official 133:d4dda5c437f0 2794 case CRYP_KEYSIZE_256B:
mbed_official 133:d4dda5c437f0 2795 CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
mbed_official 133:d4dda5c437f0 2796 ivaddr+=4;
mbed_official 133:d4dda5c437f0 2797 CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
mbed_official 133:d4dda5c437f0 2798 break;
mbed_official 133:d4dda5c437f0 2799 default:
mbed_official 133:d4dda5c437f0 2800 break;
mbed_official 133:d4dda5c437f0 2801 }
mbed_official 133:d4dda5c437f0 2802 }
mbed_official 133:d4dda5c437f0 2803
mbed_official 133:d4dda5c437f0 2804 /**
mbed_official 133:d4dda5c437f0 2805 * @brief Process Data: Writes Input data in polling mode and read the Output data.
mbed_official 133:d4dda5c437f0 2806 * @param hcryp: CRYP handle
mbed_official 133:d4dda5c437f0 2807 * @param Input: Pointer to the Input buffer.
mbed_official 133:d4dda5c437f0 2808 * @param Ilength: Length of the Input buffer, must be a multiple of 16
mbed_official 133:d4dda5c437f0 2809 * @param Output: Pointer to the returned buffer
mbed_official 133:d4dda5c437f0 2810 * @param Timeout: Timeout value
mbed_official 133:d4dda5c437f0 2811 * @retval None
mbed_official 133:d4dda5c437f0 2812 */
mbed_official 133:d4dda5c437f0 2813 static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout)
mbed_official 133:d4dda5c437f0 2814 {
mbed_official 133:d4dda5c437f0 2815 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 2816 uint32_t i = 0;
mbed_official 133:d4dda5c437f0 2817 uint32_t inputaddr = (uint32_t)Input;
mbed_official 133:d4dda5c437f0 2818 uint32_t outputaddr = (uint32_t)Output;
mbed_official 133:d4dda5c437f0 2819
mbed_official 133:d4dda5c437f0 2820 for(i=0; (i < Ilength); i+=16)
mbed_official 133:d4dda5c437f0 2821 {
mbed_official 133:d4dda5c437f0 2822 /* Write the Input block in the IN FIFO */
mbed_official 133:d4dda5c437f0 2823 CRYP->DR = *(uint32_t*)(inputaddr);
mbed_official 133:d4dda5c437f0 2824 inputaddr+=4;
mbed_official 133:d4dda5c437f0 2825 CRYP->DR = *(uint32_t*)(inputaddr);
mbed_official 133:d4dda5c437f0 2826 inputaddr+=4;
mbed_official 133:d4dda5c437f0 2827 CRYP->DR = *(uint32_t*)(inputaddr);
mbed_official 133:d4dda5c437f0 2828 inputaddr+=4;
mbed_official 133:d4dda5c437f0 2829 CRYP->DR = *(uint32_t*)(inputaddr);
mbed_official 133:d4dda5c437f0 2830 inputaddr+=4;
mbed_official 133:d4dda5c437f0 2831
mbed_official 133:d4dda5c437f0 2832 /* Get timeout */
mbed_official 133:d4dda5c437f0 2833 timeout = HAL_GetTick() + Timeout;
mbed_official 133:d4dda5c437f0 2834
mbed_official 133:d4dda5c437f0 2835 while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
mbed_official 133:d4dda5c437f0 2836 {
mbed_official 133:d4dda5c437f0 2837 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 2838 if(Timeout != HAL_MAX_DELAY)
mbed_official 133:d4dda5c437f0 2839 {
mbed_official 133:d4dda5c437f0 2840 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 2841 {
mbed_official 133:d4dda5c437f0 2842 /* Change state */
mbed_official 133:d4dda5c437f0 2843 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 2844
mbed_official 133:d4dda5c437f0 2845 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 2846 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 2847
mbed_official 133:d4dda5c437f0 2848 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 2849 }
mbed_official 133:d4dda5c437f0 2850 }
mbed_official 133:d4dda5c437f0 2851 }
mbed_official 133:d4dda5c437f0 2852 /* Read the Output block from the OUT FIFO */
mbed_official 133:d4dda5c437f0 2853 *(uint32_t*)(outputaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 2854 outputaddr+=4;
mbed_official 133:d4dda5c437f0 2855 *(uint32_t*)(outputaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 2856 outputaddr+=4;
mbed_official 133:d4dda5c437f0 2857 *(uint32_t*)(outputaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 2858 outputaddr+=4;
mbed_official 133:d4dda5c437f0 2859 *(uint32_t*)(outputaddr) = CRYP->DOUT;
mbed_official 133:d4dda5c437f0 2860 outputaddr+=4;
mbed_official 133:d4dda5c437f0 2861 }
mbed_official 133:d4dda5c437f0 2862 /* Return function status */
mbed_official 133:d4dda5c437f0 2863 return HAL_OK;
mbed_official 133:d4dda5c437f0 2864 }
mbed_official 133:d4dda5c437f0 2865
mbed_official 133:d4dda5c437f0 2866 /**
mbed_official 133:d4dda5c437f0 2867 * @brief Sets the header phase
mbed_official 133:d4dda5c437f0 2868 * @param hcryp: CRYP handle
mbed_official 133:d4dda5c437f0 2869 * @param Input: Pointer to the Input buffer.
mbed_official 133:d4dda5c437f0 2870 * @param Ilength: Length of the Input buffer, must be a multiple of 16
mbed_official 133:d4dda5c437f0 2871 * @param Timeout: Timeout value
mbed_official 133:d4dda5c437f0 2872 * @retval None
mbed_official 133:d4dda5c437f0 2873 */
mbed_official 133:d4dda5c437f0 2874 static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout)
mbed_official 133:d4dda5c437f0 2875 {
mbed_official 133:d4dda5c437f0 2876 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 2877 uint32_t loopcounter = 0;
mbed_official 133:d4dda5c437f0 2878 uint32_t headeraddr = (uint32_t)Input;
mbed_official 133:d4dda5c437f0 2879
mbed_official 133:d4dda5c437f0 2880 /***************************** Header phase *********************************/
mbed_official 133:d4dda5c437f0 2881 if(hcryp->Init.HeaderSize != 0)
mbed_official 133:d4dda5c437f0 2882 {
mbed_official 133:d4dda5c437f0 2883 /* Select header phase */
mbed_official 133:d4dda5c437f0 2884 __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
mbed_official 133:d4dda5c437f0 2885 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 2886 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 2887
mbed_official 133:d4dda5c437f0 2888 for(loopcounter = 0; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=16)
mbed_official 133:d4dda5c437f0 2889 {
mbed_official 133:d4dda5c437f0 2890 /* Get timeout */
mbed_official 133:d4dda5c437f0 2891 timeout = HAL_GetTick() + Timeout;
mbed_official 133:d4dda5c437f0 2892
mbed_official 133:d4dda5c437f0 2893 while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
mbed_official 133:d4dda5c437f0 2894 {
mbed_official 133:d4dda5c437f0 2895 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 2896 if(Timeout != HAL_MAX_DELAY)
mbed_official 133:d4dda5c437f0 2897 {
mbed_official 133:d4dda5c437f0 2898 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 2899 {
mbed_official 133:d4dda5c437f0 2900 /* Change state */
mbed_official 133:d4dda5c437f0 2901 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 2902
mbed_official 133:d4dda5c437f0 2903 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 2904 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 2905
mbed_official 133:d4dda5c437f0 2906 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 2907 }
mbed_official 133:d4dda5c437f0 2908 }
mbed_official 133:d4dda5c437f0 2909 }
mbed_official 133:d4dda5c437f0 2910 /* Write the Input block in the IN FIFO */
mbed_official 133:d4dda5c437f0 2911 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 2912 headeraddr+=4;
mbed_official 133:d4dda5c437f0 2913 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 2914 headeraddr+=4;
mbed_official 133:d4dda5c437f0 2915 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 2916 headeraddr+=4;
mbed_official 133:d4dda5c437f0 2917 CRYP->DR = *(uint32_t*)(headeraddr);
mbed_official 133:d4dda5c437f0 2918 headeraddr+=4;
mbed_official 133:d4dda5c437f0 2919 }
mbed_official 133:d4dda5c437f0 2920
mbed_official 133:d4dda5c437f0 2921 /* Wait until the complete message has been processed */
mbed_official 133:d4dda5c437f0 2922
mbed_official 133:d4dda5c437f0 2923 /* Get timeout */
mbed_official 133:d4dda5c437f0 2924 timeout = HAL_GetTick() + Timeout;
mbed_official 133:d4dda5c437f0 2925
mbed_official 133:d4dda5c437f0 2926 while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
mbed_official 133:d4dda5c437f0 2927 {
mbed_official 133:d4dda5c437f0 2928 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 2929 if(Timeout != HAL_MAX_DELAY)
mbed_official 133:d4dda5c437f0 2930 {
mbed_official 133:d4dda5c437f0 2931 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 2932 {
mbed_official 133:d4dda5c437f0 2933 /* Change state */
mbed_official 133:d4dda5c437f0 2934 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 2935
mbed_official 133:d4dda5c437f0 2936 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 2937 __HAL_UNLOCK(hcryp);
mbed_official 133:d4dda5c437f0 2938
mbed_official 133:d4dda5c437f0 2939 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 2940 }
mbed_official 133:d4dda5c437f0 2941 }
mbed_official 133:d4dda5c437f0 2942 }
mbed_official 133:d4dda5c437f0 2943 }
mbed_official 133:d4dda5c437f0 2944 /* Return function status */
mbed_official 133:d4dda5c437f0 2945 return HAL_OK;
mbed_official 133:d4dda5c437f0 2946 }
mbed_official 133:d4dda5c437f0 2947
mbed_official 133:d4dda5c437f0 2948 /**
mbed_official 133:d4dda5c437f0 2949 * @brief Sets the DMA configuration and start the DMA transfert.
mbed_official 133:d4dda5c437f0 2950 * @param hcryp: CRYP handle
mbed_official 133:d4dda5c437f0 2951 * @param inputaddr: Address of the Input buffer
mbed_official 133:d4dda5c437f0 2952 * @param Size: Size of the Input buffer, must be a multiple of 16
mbed_official 133:d4dda5c437f0 2953 * @param outputaddr: Address of the Output buffer
mbed_official 133:d4dda5c437f0 2954 * @retval None
mbed_official 133:d4dda5c437f0 2955 */
mbed_official 133:d4dda5c437f0 2956 static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
mbed_official 133:d4dda5c437f0 2957 {
mbed_official 133:d4dda5c437f0 2958 /* Set the CRYP DMA transfer complete callback */
mbed_official 133:d4dda5c437f0 2959 hcryp->hdmain->XferCpltCallback = CRYPEx_GCMCCM_DMAInCplt;
mbed_official 133:d4dda5c437f0 2960 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 2961 hcryp->hdmain->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
mbed_official 133:d4dda5c437f0 2962
mbed_official 133:d4dda5c437f0 2963 /* Set the CRYP DMA transfer complete callback */
mbed_official 133:d4dda5c437f0 2964 hcryp->hdmaout->XferCpltCallback = CRYPEx_GCMCCM_DMAOutCplt;
mbed_official 133:d4dda5c437f0 2965 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 2966 hcryp->hdmaout->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
mbed_official 133:d4dda5c437f0 2967
mbed_official 133:d4dda5c437f0 2968 /* Enable the CRYP peripheral */
mbed_official 133:d4dda5c437f0 2969 __HAL_CRYP_ENABLE();
mbed_official 133:d4dda5c437f0 2970
mbed_official 133:d4dda5c437f0 2971 /* Enable the DMA In DMA Stream */
mbed_official 133:d4dda5c437f0 2972 HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&CRYP->DR, Size/4);
mbed_official 133:d4dda5c437f0 2973
mbed_official 133:d4dda5c437f0 2974 /* Enable In DMA request */
mbed_official 133:d4dda5c437f0 2975 CRYP->DMACR = CRYP_DMACR_DIEN;
mbed_official 133:d4dda5c437f0 2976
mbed_official 133:d4dda5c437f0 2977 /* Enable the DMA Out DMA Stream */
mbed_official 133:d4dda5c437f0 2978 HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&CRYP->DOUT, outputaddr, Size/4);
mbed_official 133:d4dda5c437f0 2979
mbed_official 133:d4dda5c437f0 2980 /* Enable Out DMA request */
mbed_official 133:d4dda5c437f0 2981 CRYP->DMACR |= CRYP_DMACR_DOEN;
mbed_official 133:d4dda5c437f0 2982 }
mbed_official 133:d4dda5c437f0 2983
mbed_official 133:d4dda5c437f0 2984 /**
mbed_official 133:d4dda5c437f0 2985 * @}
mbed_official 133:d4dda5c437f0 2986 */
mbed_official 133:d4dda5c437f0 2987 #endif /* STM32F437xx || STM32F439xx */
mbed_official 133:d4dda5c437f0 2988
mbed_official 133:d4dda5c437f0 2989 #endif /* HAL_CRYP_MODULE_ENABLED */
mbed_official 133:d4dda5c437f0 2990 /**
mbed_official 133:d4dda5c437f0 2991 * @}
mbed_official 133:d4dda5c437f0 2992 */
mbed_official 133:d4dda5c437f0 2993
mbed_official 133:d4dda5c437f0 2994 /**
mbed_official 133:d4dda5c437f0 2995 * @}
mbed_official 133:d4dda5c437f0 2996 */
mbed_official 133:d4dda5c437f0 2997
mbed_official 133:d4dda5c437f0 2998 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/