mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_sdhc.h@323:9e901b0a5aa1, 2014-09-13 (annotated)
- Committer:
- shaoziyang
- Date:
- Sat Sep 13 14:25:46 2014 +0000
- Revision:
- 323:9e901b0a5aa1
- Parent:
- 320:be04b2b1e3f2
test with CLOCK_SETUP = 0
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 146:f64d43ff0c18 | 1 | /* |
mbed_official | 146:f64d43ff0c18 | 2 | * Copyright (c) 2014, Freescale Semiconductor, Inc. |
mbed_official | 146:f64d43ff0c18 | 3 | * All rights reserved. |
mbed_official | 146:f64d43ff0c18 | 4 | * |
mbed_official | 146:f64d43ff0c18 | 5 | * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED |
mbed_official | 146:f64d43ff0c18 | 6 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
mbed_official | 146:f64d43ff0c18 | 7 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT |
mbed_official | 146:f64d43ff0c18 | 8 | * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
mbed_official | 146:f64d43ff0c18 | 9 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
mbed_official | 146:f64d43ff0c18 | 10 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
mbed_official | 146:f64d43ff0c18 | 11 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
mbed_official | 146:f64d43ff0c18 | 12 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
mbed_official | 146:f64d43ff0c18 | 13 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
mbed_official | 146:f64d43ff0c18 | 14 | * OF SUCH DAMAGE. |
mbed_official | 146:f64d43ff0c18 | 15 | */ |
mbed_official | 146:f64d43ff0c18 | 16 | /* |
mbed_official | 146:f64d43ff0c18 | 17 | * WARNING! DO NOT EDIT THIS FILE DIRECTLY! |
mbed_official | 146:f64d43ff0c18 | 18 | * |
mbed_official | 146:f64d43ff0c18 | 19 | * This file was generated automatically and any changes may be lost. |
mbed_official | 146:f64d43ff0c18 | 20 | */ |
mbed_official | 146:f64d43ff0c18 | 21 | #ifndef __HW_SDHC_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 22 | #define __HW_SDHC_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 23 | |
mbed_official | 146:f64d43ff0c18 | 24 | #include "regs.h" |
mbed_official | 146:f64d43ff0c18 | 25 | |
mbed_official | 146:f64d43ff0c18 | 26 | /* |
mbed_official | 146:f64d43ff0c18 | 27 | * MK64F12 SDHC |
mbed_official | 146:f64d43ff0c18 | 28 | * |
mbed_official | 146:f64d43ff0c18 | 29 | * Secured Digital Host Controller |
mbed_official | 146:f64d43ff0c18 | 30 | * |
mbed_official | 146:f64d43ff0c18 | 31 | * Registers defined in this header file: |
mbed_official | 146:f64d43ff0c18 | 32 | * - HW_SDHC_DSADDR - DMA System Address register |
mbed_official | 146:f64d43ff0c18 | 33 | * - HW_SDHC_BLKATTR - Block Attributes register |
mbed_official | 146:f64d43ff0c18 | 34 | * - HW_SDHC_CMDARG - Command Argument register |
mbed_official | 146:f64d43ff0c18 | 35 | * - HW_SDHC_XFERTYP - Transfer Type register |
mbed_official | 146:f64d43ff0c18 | 36 | * - HW_SDHC_CMDRSP0 - Command Response 0 |
mbed_official | 146:f64d43ff0c18 | 37 | * - HW_SDHC_CMDRSP1 - Command Response 1 |
mbed_official | 146:f64d43ff0c18 | 38 | * - HW_SDHC_CMDRSP2 - Command Response 2 |
mbed_official | 146:f64d43ff0c18 | 39 | * - HW_SDHC_CMDRSP3 - Command Response 3 |
mbed_official | 146:f64d43ff0c18 | 40 | * - HW_SDHC_DATPORT - Buffer Data Port register |
mbed_official | 146:f64d43ff0c18 | 41 | * - HW_SDHC_PRSSTAT - Present State register |
mbed_official | 146:f64d43ff0c18 | 42 | * - HW_SDHC_PROCTL - Protocol Control register |
mbed_official | 146:f64d43ff0c18 | 43 | * - HW_SDHC_SYSCTL - System Control register |
mbed_official | 146:f64d43ff0c18 | 44 | * - HW_SDHC_IRQSTAT - Interrupt Status register |
mbed_official | 146:f64d43ff0c18 | 45 | * - HW_SDHC_IRQSTATEN - Interrupt Status Enable register |
mbed_official | 146:f64d43ff0c18 | 46 | * - HW_SDHC_IRQSIGEN - Interrupt Signal Enable register |
mbed_official | 146:f64d43ff0c18 | 47 | * - HW_SDHC_AC12ERR - Auto CMD12 Error Status Register |
mbed_official | 146:f64d43ff0c18 | 48 | * - HW_SDHC_HTCAPBLT - Host Controller Capabilities |
mbed_official | 146:f64d43ff0c18 | 49 | * - HW_SDHC_WML - Watermark Level Register |
mbed_official | 146:f64d43ff0c18 | 50 | * - HW_SDHC_FEVT - Force Event register |
mbed_official | 146:f64d43ff0c18 | 51 | * - HW_SDHC_ADMAES - ADMA Error Status register |
mbed_official | 146:f64d43ff0c18 | 52 | * - HW_SDHC_ADSADDR - ADMA System Addressregister |
mbed_official | 146:f64d43ff0c18 | 53 | * - HW_SDHC_VENDOR - Vendor Specific register |
mbed_official | 146:f64d43ff0c18 | 54 | * - HW_SDHC_MMCBOOT - MMC Boot register |
mbed_official | 146:f64d43ff0c18 | 55 | * - HW_SDHC_HOSTVER - Host Controller Version |
mbed_official | 146:f64d43ff0c18 | 56 | * |
mbed_official | 146:f64d43ff0c18 | 57 | * - hw_sdhc_t - Struct containing all module registers. |
mbed_official | 146:f64d43ff0c18 | 58 | */ |
mbed_official | 146:f64d43ff0c18 | 59 | |
mbed_official | 146:f64d43ff0c18 | 60 | //! @name Module base addresses |
mbed_official | 146:f64d43ff0c18 | 61 | //@{ |
mbed_official | 146:f64d43ff0c18 | 62 | #ifndef REGS_SDHC_BASE |
mbed_official | 146:f64d43ff0c18 | 63 | #define HW_SDHC_INSTANCE_COUNT (1U) //!< Number of instances of the SDHC module. |
mbed_official | 146:f64d43ff0c18 | 64 | #define REGS_SDHC_BASE (0x400B1000U) //!< Base address for SDHC. |
mbed_official | 146:f64d43ff0c18 | 65 | #endif |
mbed_official | 146:f64d43ff0c18 | 66 | //@} |
mbed_official | 146:f64d43ff0c18 | 67 | |
mbed_official | 146:f64d43ff0c18 | 68 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 69 | // HW_SDHC_DSADDR - DMA System Address register |
mbed_official | 146:f64d43ff0c18 | 70 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 71 | |
mbed_official | 146:f64d43ff0c18 | 72 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 73 | /*! |
mbed_official | 146:f64d43ff0c18 | 74 | * @brief HW_SDHC_DSADDR - DMA System Address register (RW) |
mbed_official | 146:f64d43ff0c18 | 75 | * |
mbed_official | 146:f64d43ff0c18 | 76 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 77 | * |
mbed_official | 146:f64d43ff0c18 | 78 | * This register contains the physical system memory address used for DMA |
mbed_official | 146:f64d43ff0c18 | 79 | * transfers. |
mbed_official | 146:f64d43ff0c18 | 80 | */ |
mbed_official | 146:f64d43ff0c18 | 81 | typedef union _hw_sdhc_dsaddr |
mbed_official | 146:f64d43ff0c18 | 82 | { |
mbed_official | 146:f64d43ff0c18 | 83 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 84 | struct _hw_sdhc_dsaddr_bitfields |
mbed_official | 146:f64d43ff0c18 | 85 | { |
mbed_official | 146:f64d43ff0c18 | 86 | uint32_t RESERVED0 : 2; //!< [1:0] |
mbed_official | 146:f64d43ff0c18 | 87 | uint32_t DSADDR : 30; //!< [31:2] DMA System Address |
mbed_official | 146:f64d43ff0c18 | 88 | } B; |
mbed_official | 146:f64d43ff0c18 | 89 | } hw_sdhc_dsaddr_t; |
mbed_official | 146:f64d43ff0c18 | 90 | #endif |
mbed_official | 146:f64d43ff0c18 | 91 | |
mbed_official | 146:f64d43ff0c18 | 92 | /*! |
mbed_official | 146:f64d43ff0c18 | 93 | * @name Constants and macros for entire SDHC_DSADDR register |
mbed_official | 146:f64d43ff0c18 | 94 | */ |
mbed_official | 146:f64d43ff0c18 | 95 | //@{ |
mbed_official | 146:f64d43ff0c18 | 96 | #define HW_SDHC_DSADDR_ADDR (REGS_SDHC_BASE + 0x0U) |
mbed_official | 146:f64d43ff0c18 | 97 | |
mbed_official | 146:f64d43ff0c18 | 98 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 99 | #define HW_SDHC_DSADDR (*(__IO hw_sdhc_dsaddr_t *) HW_SDHC_DSADDR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 100 | #define HW_SDHC_DSADDR_RD() (HW_SDHC_DSADDR.U) |
mbed_official | 146:f64d43ff0c18 | 101 | #define HW_SDHC_DSADDR_WR(v) (HW_SDHC_DSADDR.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 102 | #define HW_SDHC_DSADDR_SET(v) (HW_SDHC_DSADDR_WR(HW_SDHC_DSADDR_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 103 | #define HW_SDHC_DSADDR_CLR(v) (HW_SDHC_DSADDR_WR(HW_SDHC_DSADDR_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 104 | #define HW_SDHC_DSADDR_TOG(v) (HW_SDHC_DSADDR_WR(HW_SDHC_DSADDR_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 105 | #endif |
mbed_official | 146:f64d43ff0c18 | 106 | //@} |
mbed_official | 146:f64d43ff0c18 | 107 | |
mbed_official | 146:f64d43ff0c18 | 108 | /* |
mbed_official | 146:f64d43ff0c18 | 109 | * Constants & macros for individual SDHC_DSADDR bitfields |
mbed_official | 146:f64d43ff0c18 | 110 | */ |
mbed_official | 146:f64d43ff0c18 | 111 | |
mbed_official | 146:f64d43ff0c18 | 112 | /*! |
mbed_official | 146:f64d43ff0c18 | 113 | * @name Register SDHC_DSADDR, field DSADDR[31:2] (RW) |
mbed_official | 146:f64d43ff0c18 | 114 | * |
mbed_official | 146:f64d43ff0c18 | 115 | * Contains the 32-bit system memory address for a DMA transfer. Because the |
mbed_official | 146:f64d43ff0c18 | 116 | * address must be word (4 bytes) align, the least 2 bits are reserved, always 0. |
mbed_official | 146:f64d43ff0c18 | 117 | * When the SDHC stops a DMA transfer, this register points to the system address |
mbed_official | 146:f64d43ff0c18 | 118 | * of the next contiguous data position. It can be accessed only when no |
mbed_official | 146:f64d43ff0c18 | 119 | * transaction is executing, that is, after a transaction has stopped. Read operation |
mbed_official | 146:f64d43ff0c18 | 120 | * during transfers may return an invalid value. The host driver shall initialize |
mbed_official | 146:f64d43ff0c18 | 121 | * this register before starting a DMA transaction. After DMA has stopped, the |
mbed_official | 146:f64d43ff0c18 | 122 | * system address of the next contiguous data position can be read from this register. |
mbed_official | 146:f64d43ff0c18 | 123 | * This register is protected during a data transfer. When data lines are |
mbed_official | 146:f64d43ff0c18 | 124 | * active, write to this register is ignored. The host driver shall wait, until |
mbed_official | 146:f64d43ff0c18 | 125 | * PRSSTAT[DLA] is cleared, before writing to this register. The SDHC internal DMA does |
mbed_official | 146:f64d43ff0c18 | 126 | * not support a virtual memory system. It supports only continuous physical |
mbed_official | 146:f64d43ff0c18 | 127 | * memory access. And due to AHB burst limitations, if the burst must cross the 1 KB |
mbed_official | 146:f64d43ff0c18 | 128 | * boundary, SDHC will automatically change SEQ burst type to NSEQ. Because this |
mbed_official | 146:f64d43ff0c18 | 129 | * register supports dynamic address reflecting, when IRQSTAT[TC] bit is set, it |
mbed_official | 146:f64d43ff0c18 | 130 | * automatically alters the value of internal address counter, so SW cannot |
mbed_official | 146:f64d43ff0c18 | 131 | * change this register when IRQSTAT[TC] is set. |
mbed_official | 146:f64d43ff0c18 | 132 | */ |
mbed_official | 146:f64d43ff0c18 | 133 | //@{ |
mbed_official | 146:f64d43ff0c18 | 134 | #define BP_SDHC_DSADDR_DSADDR (2U) //!< Bit position for SDHC_DSADDR_DSADDR. |
mbed_official | 146:f64d43ff0c18 | 135 | #define BM_SDHC_DSADDR_DSADDR (0xFFFFFFFCU) //!< Bit mask for SDHC_DSADDR_DSADDR. |
mbed_official | 146:f64d43ff0c18 | 136 | #define BS_SDHC_DSADDR_DSADDR (30U) //!< Bit field size in bits for SDHC_DSADDR_DSADDR. |
mbed_official | 146:f64d43ff0c18 | 137 | |
mbed_official | 146:f64d43ff0c18 | 138 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 139 | //! @brief Read current value of the SDHC_DSADDR_DSADDR field. |
mbed_official | 146:f64d43ff0c18 | 140 | #define BR_SDHC_DSADDR_DSADDR (HW_SDHC_DSADDR.B.DSADDR) |
mbed_official | 146:f64d43ff0c18 | 141 | #endif |
mbed_official | 146:f64d43ff0c18 | 142 | |
mbed_official | 146:f64d43ff0c18 | 143 | //! @brief Format value for bitfield SDHC_DSADDR_DSADDR. |
mbed_official | 146:f64d43ff0c18 | 144 | #define BF_SDHC_DSADDR_DSADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_DSADDR_DSADDR), uint32_t) & BM_SDHC_DSADDR_DSADDR) |
mbed_official | 146:f64d43ff0c18 | 145 | |
mbed_official | 146:f64d43ff0c18 | 146 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 147 | //! @brief Set the DSADDR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 148 | #define BW_SDHC_DSADDR_DSADDR(v) (HW_SDHC_DSADDR_WR((HW_SDHC_DSADDR_RD() & ~BM_SDHC_DSADDR_DSADDR) | BF_SDHC_DSADDR_DSADDR(v))) |
mbed_official | 146:f64d43ff0c18 | 149 | #endif |
mbed_official | 146:f64d43ff0c18 | 150 | //@} |
mbed_official | 146:f64d43ff0c18 | 151 | |
mbed_official | 146:f64d43ff0c18 | 152 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 153 | // HW_SDHC_BLKATTR - Block Attributes register |
mbed_official | 146:f64d43ff0c18 | 154 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 155 | |
mbed_official | 146:f64d43ff0c18 | 156 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 157 | /*! |
mbed_official | 146:f64d43ff0c18 | 158 | * @brief HW_SDHC_BLKATTR - Block Attributes register (RW) |
mbed_official | 146:f64d43ff0c18 | 159 | * |
mbed_official | 146:f64d43ff0c18 | 160 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 161 | * |
mbed_official | 146:f64d43ff0c18 | 162 | * This register is used to configure the number of data blocks and the number |
mbed_official | 146:f64d43ff0c18 | 163 | * of bytes in each block. |
mbed_official | 146:f64d43ff0c18 | 164 | */ |
mbed_official | 146:f64d43ff0c18 | 165 | typedef union _hw_sdhc_blkattr |
mbed_official | 146:f64d43ff0c18 | 166 | { |
mbed_official | 146:f64d43ff0c18 | 167 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 168 | struct _hw_sdhc_blkattr_bitfields |
mbed_official | 146:f64d43ff0c18 | 169 | { |
mbed_official | 146:f64d43ff0c18 | 170 | uint32_t BLKSIZE : 13; //!< [12:0] Transfer Block Size |
mbed_official | 146:f64d43ff0c18 | 171 | uint32_t RESERVED0 : 3; //!< [15:13] |
mbed_official | 146:f64d43ff0c18 | 172 | uint32_t BLKCNT : 16; //!< [31:16] Blocks Count For Current Transfer |
mbed_official | 146:f64d43ff0c18 | 173 | } B; |
mbed_official | 146:f64d43ff0c18 | 174 | } hw_sdhc_blkattr_t; |
mbed_official | 146:f64d43ff0c18 | 175 | #endif |
mbed_official | 146:f64d43ff0c18 | 176 | |
mbed_official | 146:f64d43ff0c18 | 177 | /*! |
mbed_official | 146:f64d43ff0c18 | 178 | * @name Constants and macros for entire SDHC_BLKATTR register |
mbed_official | 146:f64d43ff0c18 | 179 | */ |
mbed_official | 146:f64d43ff0c18 | 180 | //@{ |
mbed_official | 146:f64d43ff0c18 | 181 | #define HW_SDHC_BLKATTR_ADDR (REGS_SDHC_BASE + 0x4U) |
mbed_official | 146:f64d43ff0c18 | 182 | |
mbed_official | 146:f64d43ff0c18 | 183 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 184 | #define HW_SDHC_BLKATTR (*(__IO hw_sdhc_blkattr_t *) HW_SDHC_BLKATTR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 185 | #define HW_SDHC_BLKATTR_RD() (HW_SDHC_BLKATTR.U) |
mbed_official | 146:f64d43ff0c18 | 186 | #define HW_SDHC_BLKATTR_WR(v) (HW_SDHC_BLKATTR.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 187 | #define HW_SDHC_BLKATTR_SET(v) (HW_SDHC_BLKATTR_WR(HW_SDHC_BLKATTR_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 188 | #define HW_SDHC_BLKATTR_CLR(v) (HW_SDHC_BLKATTR_WR(HW_SDHC_BLKATTR_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 189 | #define HW_SDHC_BLKATTR_TOG(v) (HW_SDHC_BLKATTR_WR(HW_SDHC_BLKATTR_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 190 | #endif |
mbed_official | 146:f64d43ff0c18 | 191 | //@} |
mbed_official | 146:f64d43ff0c18 | 192 | |
mbed_official | 146:f64d43ff0c18 | 193 | /* |
mbed_official | 146:f64d43ff0c18 | 194 | * Constants & macros for individual SDHC_BLKATTR bitfields |
mbed_official | 146:f64d43ff0c18 | 195 | */ |
mbed_official | 146:f64d43ff0c18 | 196 | |
mbed_official | 146:f64d43ff0c18 | 197 | /*! |
mbed_official | 146:f64d43ff0c18 | 198 | * @name Register SDHC_BLKATTR, field BLKSIZE[12:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 199 | * |
mbed_official | 146:f64d43ff0c18 | 200 | * Specifies the block size for block data transfers. Values ranging from 1 byte |
mbed_official | 146:f64d43ff0c18 | 201 | * up to the maximum buffer size can be set. It can be accessed only when no |
mbed_official | 146:f64d43ff0c18 | 202 | * transaction is executing, that is, after a transaction has stopped. Read |
mbed_official | 146:f64d43ff0c18 | 203 | * operations during transfers may return an invalid value, and write operations will be |
mbed_official | 146:f64d43ff0c18 | 204 | * ignored. |
mbed_official | 146:f64d43ff0c18 | 205 | * |
mbed_official | 146:f64d43ff0c18 | 206 | * Values: |
mbed_official | 146:f64d43ff0c18 | 207 | * - 0 - No data transfer. |
mbed_official | 146:f64d43ff0c18 | 208 | * - 1 - 1 Byte |
mbed_official | 146:f64d43ff0c18 | 209 | * - 10 - 2 Bytes |
mbed_official | 146:f64d43ff0c18 | 210 | * - 11 - 3 Bytes |
mbed_official | 146:f64d43ff0c18 | 211 | * - 100 - 4 Bytes |
mbed_official | 146:f64d43ff0c18 | 212 | * - 111111111 - 511 Bytes |
mbed_official | 146:f64d43ff0c18 | 213 | * - 1000000000 - 512 Bytes |
mbed_official | 146:f64d43ff0c18 | 214 | * - 100000000000 - 2048 Bytes |
mbed_official | 146:f64d43ff0c18 | 215 | * - 1000000000000 - 4096 Bytes |
mbed_official | 146:f64d43ff0c18 | 216 | */ |
mbed_official | 146:f64d43ff0c18 | 217 | //@{ |
mbed_official | 146:f64d43ff0c18 | 218 | #define BP_SDHC_BLKATTR_BLKSIZE (0U) //!< Bit position for SDHC_BLKATTR_BLKSIZE. |
mbed_official | 146:f64d43ff0c18 | 219 | #define BM_SDHC_BLKATTR_BLKSIZE (0x00001FFFU) //!< Bit mask for SDHC_BLKATTR_BLKSIZE. |
mbed_official | 146:f64d43ff0c18 | 220 | #define BS_SDHC_BLKATTR_BLKSIZE (13U) //!< Bit field size in bits for SDHC_BLKATTR_BLKSIZE. |
mbed_official | 146:f64d43ff0c18 | 221 | |
mbed_official | 146:f64d43ff0c18 | 222 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 223 | //! @brief Read current value of the SDHC_BLKATTR_BLKSIZE field. |
mbed_official | 146:f64d43ff0c18 | 224 | #define BR_SDHC_BLKATTR_BLKSIZE (HW_SDHC_BLKATTR.B.BLKSIZE) |
mbed_official | 146:f64d43ff0c18 | 225 | #endif |
mbed_official | 146:f64d43ff0c18 | 226 | |
mbed_official | 146:f64d43ff0c18 | 227 | //! @brief Format value for bitfield SDHC_BLKATTR_BLKSIZE. |
mbed_official | 146:f64d43ff0c18 | 228 | #define BF_SDHC_BLKATTR_BLKSIZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_BLKATTR_BLKSIZE), uint32_t) & BM_SDHC_BLKATTR_BLKSIZE) |
mbed_official | 146:f64d43ff0c18 | 229 | |
mbed_official | 146:f64d43ff0c18 | 230 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 231 | //! @brief Set the BLKSIZE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 232 | #define BW_SDHC_BLKATTR_BLKSIZE(v) (HW_SDHC_BLKATTR_WR((HW_SDHC_BLKATTR_RD() & ~BM_SDHC_BLKATTR_BLKSIZE) | BF_SDHC_BLKATTR_BLKSIZE(v))) |
mbed_official | 146:f64d43ff0c18 | 233 | #endif |
mbed_official | 146:f64d43ff0c18 | 234 | //@} |
mbed_official | 146:f64d43ff0c18 | 235 | |
mbed_official | 146:f64d43ff0c18 | 236 | /*! |
mbed_official | 146:f64d43ff0c18 | 237 | * @name Register SDHC_BLKATTR, field BLKCNT[31:16] (RW) |
mbed_official | 146:f64d43ff0c18 | 238 | * |
mbed_official | 146:f64d43ff0c18 | 239 | * This register is enabled when XFERTYP[BCEN] is set to 1 and is valid only for |
mbed_official | 146:f64d43ff0c18 | 240 | * multiple block transfers. For single block transfer, this register will |
mbed_official | 146:f64d43ff0c18 | 241 | * always read as 1. The host driver shall set this register to a value between 1 and |
mbed_official | 146:f64d43ff0c18 | 242 | * the maximum block count. The SDHC decrements the block count after each block |
mbed_official | 146:f64d43ff0c18 | 243 | * transfer and stops when the count reaches zero. Setting the block count to 0 |
mbed_official | 146:f64d43ff0c18 | 244 | * results in no data blocks being transferred. This register must be accessed |
mbed_official | 146:f64d43ff0c18 | 245 | * only when no transaction is executing, that is, after transactions are stopped. |
mbed_official | 146:f64d43ff0c18 | 246 | * During data transfer, read operations on this register may return an invalid |
mbed_official | 146:f64d43ff0c18 | 247 | * value and write operations are ignored. When saving transfer content as a result |
mbed_official | 146:f64d43ff0c18 | 248 | * of a suspend command, the number of blocks yet to be transferred can be |
mbed_official | 146:f64d43ff0c18 | 249 | * determined by reading this register. The reading of this register must be applied |
mbed_official | 146:f64d43ff0c18 | 250 | * after transfer is paused by stop at block gap operation and before sending the |
mbed_official | 146:f64d43ff0c18 | 251 | * command marked as suspend. This is because when suspend command is sent out, |
mbed_official | 146:f64d43ff0c18 | 252 | * SDHC will regard the current transfer as aborted and change BLKCNT back to its |
mbed_official | 146:f64d43ff0c18 | 253 | * original value instead of keeping the dynamical indicator of remained block |
mbed_official | 146:f64d43ff0c18 | 254 | * count. When restoring transfer content prior to issuing a resume command, the |
mbed_official | 146:f64d43ff0c18 | 255 | * host driver shall restore the previously saved block count. Although the BLKCNT |
mbed_official | 146:f64d43ff0c18 | 256 | * field is 0 after reset, the read of reset value is 0x1. This is because when |
mbed_official | 146:f64d43ff0c18 | 257 | * XFERTYP[MSBSEL] is 0, indicating a single block transfer, the read value of |
mbed_official | 146:f64d43ff0c18 | 258 | * BLKCNT is always 1. |
mbed_official | 146:f64d43ff0c18 | 259 | * |
mbed_official | 146:f64d43ff0c18 | 260 | * Values: |
mbed_official | 146:f64d43ff0c18 | 261 | * - 0 - Stop count. |
mbed_official | 146:f64d43ff0c18 | 262 | * - 1 - 1 block |
mbed_official | 146:f64d43ff0c18 | 263 | * - 10 - 2 blocks |
mbed_official | 146:f64d43ff0c18 | 264 | * - 1111111111111111 - 65535 blocks |
mbed_official | 146:f64d43ff0c18 | 265 | */ |
mbed_official | 146:f64d43ff0c18 | 266 | //@{ |
mbed_official | 146:f64d43ff0c18 | 267 | #define BP_SDHC_BLKATTR_BLKCNT (16U) //!< Bit position for SDHC_BLKATTR_BLKCNT. |
mbed_official | 146:f64d43ff0c18 | 268 | #define BM_SDHC_BLKATTR_BLKCNT (0xFFFF0000U) //!< Bit mask for SDHC_BLKATTR_BLKCNT. |
mbed_official | 146:f64d43ff0c18 | 269 | #define BS_SDHC_BLKATTR_BLKCNT (16U) //!< Bit field size in bits for SDHC_BLKATTR_BLKCNT. |
mbed_official | 146:f64d43ff0c18 | 270 | |
mbed_official | 146:f64d43ff0c18 | 271 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 272 | //! @brief Read current value of the SDHC_BLKATTR_BLKCNT field. |
mbed_official | 146:f64d43ff0c18 | 273 | #define BR_SDHC_BLKATTR_BLKCNT (HW_SDHC_BLKATTR.B.BLKCNT) |
mbed_official | 146:f64d43ff0c18 | 274 | #endif |
mbed_official | 146:f64d43ff0c18 | 275 | |
mbed_official | 146:f64d43ff0c18 | 276 | //! @brief Format value for bitfield SDHC_BLKATTR_BLKCNT. |
mbed_official | 146:f64d43ff0c18 | 277 | #define BF_SDHC_BLKATTR_BLKCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_BLKATTR_BLKCNT), uint32_t) & BM_SDHC_BLKATTR_BLKCNT) |
mbed_official | 146:f64d43ff0c18 | 278 | |
mbed_official | 146:f64d43ff0c18 | 279 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 280 | //! @brief Set the BLKCNT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 281 | #define BW_SDHC_BLKATTR_BLKCNT(v) (HW_SDHC_BLKATTR_WR((HW_SDHC_BLKATTR_RD() & ~BM_SDHC_BLKATTR_BLKCNT) | BF_SDHC_BLKATTR_BLKCNT(v))) |
mbed_official | 146:f64d43ff0c18 | 282 | #endif |
mbed_official | 146:f64d43ff0c18 | 283 | //@} |
mbed_official | 146:f64d43ff0c18 | 284 | |
mbed_official | 146:f64d43ff0c18 | 285 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 286 | // HW_SDHC_CMDARG - Command Argument register |
mbed_official | 146:f64d43ff0c18 | 287 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 288 | |
mbed_official | 146:f64d43ff0c18 | 289 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 290 | /*! |
mbed_official | 146:f64d43ff0c18 | 291 | * @brief HW_SDHC_CMDARG - Command Argument register (RW) |
mbed_official | 146:f64d43ff0c18 | 292 | * |
mbed_official | 146:f64d43ff0c18 | 293 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 294 | * |
mbed_official | 146:f64d43ff0c18 | 295 | * This register contains the SD/MMC command argument. |
mbed_official | 146:f64d43ff0c18 | 296 | */ |
mbed_official | 146:f64d43ff0c18 | 297 | typedef union _hw_sdhc_cmdarg |
mbed_official | 146:f64d43ff0c18 | 298 | { |
mbed_official | 146:f64d43ff0c18 | 299 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 300 | struct _hw_sdhc_cmdarg_bitfields |
mbed_official | 146:f64d43ff0c18 | 301 | { |
mbed_official | 146:f64d43ff0c18 | 302 | uint32_t CMDARG : 32; //!< [31:0] Command Argument |
mbed_official | 146:f64d43ff0c18 | 303 | } B; |
mbed_official | 146:f64d43ff0c18 | 304 | } hw_sdhc_cmdarg_t; |
mbed_official | 146:f64d43ff0c18 | 305 | #endif |
mbed_official | 146:f64d43ff0c18 | 306 | |
mbed_official | 146:f64d43ff0c18 | 307 | /*! |
mbed_official | 146:f64d43ff0c18 | 308 | * @name Constants and macros for entire SDHC_CMDARG register |
mbed_official | 146:f64d43ff0c18 | 309 | */ |
mbed_official | 146:f64d43ff0c18 | 310 | //@{ |
mbed_official | 146:f64d43ff0c18 | 311 | #define HW_SDHC_CMDARG_ADDR (REGS_SDHC_BASE + 0x8U) |
mbed_official | 146:f64d43ff0c18 | 312 | |
mbed_official | 146:f64d43ff0c18 | 313 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 314 | #define HW_SDHC_CMDARG (*(__IO hw_sdhc_cmdarg_t *) HW_SDHC_CMDARG_ADDR) |
mbed_official | 146:f64d43ff0c18 | 315 | #define HW_SDHC_CMDARG_RD() (HW_SDHC_CMDARG.U) |
mbed_official | 146:f64d43ff0c18 | 316 | #define HW_SDHC_CMDARG_WR(v) (HW_SDHC_CMDARG.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 317 | #define HW_SDHC_CMDARG_SET(v) (HW_SDHC_CMDARG_WR(HW_SDHC_CMDARG_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 318 | #define HW_SDHC_CMDARG_CLR(v) (HW_SDHC_CMDARG_WR(HW_SDHC_CMDARG_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 319 | #define HW_SDHC_CMDARG_TOG(v) (HW_SDHC_CMDARG_WR(HW_SDHC_CMDARG_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 320 | #endif |
mbed_official | 146:f64d43ff0c18 | 321 | //@} |
mbed_official | 146:f64d43ff0c18 | 322 | |
mbed_official | 146:f64d43ff0c18 | 323 | /* |
mbed_official | 146:f64d43ff0c18 | 324 | * Constants & macros for individual SDHC_CMDARG bitfields |
mbed_official | 146:f64d43ff0c18 | 325 | */ |
mbed_official | 146:f64d43ff0c18 | 326 | |
mbed_official | 146:f64d43ff0c18 | 327 | /*! |
mbed_official | 146:f64d43ff0c18 | 328 | * @name Register SDHC_CMDARG, field CMDARG[31:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 329 | * |
mbed_official | 146:f64d43ff0c18 | 330 | * The SD/MMC command argument is specified as bits 39-8 of the command format |
mbed_official | 146:f64d43ff0c18 | 331 | * in the SD or MMC specification. This register is write protected when |
mbed_official | 146:f64d43ff0c18 | 332 | * PRSSTAT[CDIHB0] is set. |
mbed_official | 146:f64d43ff0c18 | 333 | */ |
mbed_official | 146:f64d43ff0c18 | 334 | //@{ |
mbed_official | 146:f64d43ff0c18 | 335 | #define BP_SDHC_CMDARG_CMDARG (0U) //!< Bit position for SDHC_CMDARG_CMDARG. |
mbed_official | 146:f64d43ff0c18 | 336 | #define BM_SDHC_CMDARG_CMDARG (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDARG_CMDARG. |
mbed_official | 146:f64d43ff0c18 | 337 | #define BS_SDHC_CMDARG_CMDARG (32U) //!< Bit field size in bits for SDHC_CMDARG_CMDARG. |
mbed_official | 146:f64d43ff0c18 | 338 | |
mbed_official | 146:f64d43ff0c18 | 339 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 340 | //! @brief Read current value of the SDHC_CMDARG_CMDARG field. |
mbed_official | 146:f64d43ff0c18 | 341 | #define BR_SDHC_CMDARG_CMDARG (HW_SDHC_CMDARG.U) |
mbed_official | 146:f64d43ff0c18 | 342 | #endif |
mbed_official | 146:f64d43ff0c18 | 343 | |
mbed_official | 146:f64d43ff0c18 | 344 | //! @brief Format value for bitfield SDHC_CMDARG_CMDARG. |
mbed_official | 146:f64d43ff0c18 | 345 | #define BF_SDHC_CMDARG_CMDARG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_CMDARG_CMDARG), uint32_t) & BM_SDHC_CMDARG_CMDARG) |
mbed_official | 146:f64d43ff0c18 | 346 | |
mbed_official | 146:f64d43ff0c18 | 347 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 348 | //! @brief Set the CMDARG field to a new value. |
mbed_official | 146:f64d43ff0c18 | 349 | #define BW_SDHC_CMDARG_CMDARG(v) (HW_SDHC_CMDARG_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 350 | #endif |
mbed_official | 146:f64d43ff0c18 | 351 | //@} |
mbed_official | 146:f64d43ff0c18 | 352 | |
mbed_official | 146:f64d43ff0c18 | 353 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 354 | // HW_SDHC_XFERTYP - Transfer Type register |
mbed_official | 146:f64d43ff0c18 | 355 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 356 | |
mbed_official | 146:f64d43ff0c18 | 357 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 358 | /*! |
mbed_official | 146:f64d43ff0c18 | 359 | * @brief HW_SDHC_XFERTYP - Transfer Type register (RW) |
mbed_official | 146:f64d43ff0c18 | 360 | * |
mbed_official | 146:f64d43ff0c18 | 361 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 362 | * |
mbed_official | 146:f64d43ff0c18 | 363 | * This register is used to control the operation of data transfers. The host |
mbed_official | 146:f64d43ff0c18 | 364 | * driver shall set this register before issuing a command followed by a data |
mbed_official | 146:f64d43ff0c18 | 365 | * transfer, or before issuing a resume command. To prevent data loss, the SDHC |
mbed_official | 146:f64d43ff0c18 | 366 | * prevents writing to the bits that are involved in the data transfer of this |
mbed_official | 146:f64d43ff0c18 | 367 | * register, when data transfer is active. These bits are DPSEL, MBSEL, DTDSEL, AC12EN, |
mbed_official | 146:f64d43ff0c18 | 368 | * BCEN, and DMAEN. The host driver shall check PRSSTAT[CDIHB] and PRSSTAT[CIHB] |
mbed_official | 146:f64d43ff0c18 | 369 | * before writing to this register. When PRSSTAT[CDIHB] is set, any attempt to |
mbed_official | 146:f64d43ff0c18 | 370 | * send a command with data by writing to this register is ignored; when |
mbed_official | 146:f64d43ff0c18 | 371 | * PRSSTAT[CIHB] bit is set, any write to this register is ignored. On sending commands with |
mbed_official | 146:f64d43ff0c18 | 372 | * data transfer involved, it is mandatory that the block size is nonzero. |
mbed_official | 146:f64d43ff0c18 | 373 | * Besides, block count must also be nonzero, or indicated as single block transfer |
mbed_official | 146:f64d43ff0c18 | 374 | * (bit 5 of this register is 0 when written), or block count is disabled (bit 1 of |
mbed_official | 146:f64d43ff0c18 | 375 | * this register is 0 when written), otherwise SDHC will ignore the sending of |
mbed_official | 146:f64d43ff0c18 | 376 | * this command and do nothing. For write command, with all above restrictions, it |
mbed_official | 146:f64d43ff0c18 | 377 | * is also mandatory that the write protect switch is not active (WPSPL bit of |
mbed_official | 146:f64d43ff0c18 | 378 | * Present State Register is 1), otherwise SDHC will also ignore the command. If |
mbed_official | 146:f64d43ff0c18 | 379 | * the commands with data transfer does not receive the response in 64 clock |
mbed_official | 146:f64d43ff0c18 | 380 | * cycles, that is, response time-out, SDHC will regard the external device does not |
mbed_official | 146:f64d43ff0c18 | 381 | * accept the command and abort the data transfer. In this scenario, the driver |
mbed_official | 146:f64d43ff0c18 | 382 | * must issue the command again to retry the transfer. It is also possible that, |
mbed_official | 146:f64d43ff0c18 | 383 | * for some reason, the card responds to the command but SDHC does not receive the |
mbed_official | 146:f64d43ff0c18 | 384 | * response, and if it is internal DMA (either simple DMA or ADMA) read |
mbed_official | 146:f64d43ff0c18 | 385 | * operation, the external system memory is over-written by the internal DMA with data |
mbed_official | 146:f64d43ff0c18 | 386 | * sent back from the card. The following table shows the summary of how register |
mbed_official | 146:f64d43ff0c18 | 387 | * settings determine the type of data transfer. Transfer Type register setting for |
mbed_official | 146:f64d43ff0c18 | 388 | * various transfer types Multi/Single block select Block count enable Block |
mbed_official | 146:f64d43ff0c18 | 389 | * count Function 0 Don't care Don't care Single transfer 1 0 Don't care Infinite |
mbed_official | 146:f64d43ff0c18 | 390 | * transfer 1 1 Positive number Multiple transfer 1 1 Zero No data transfer The |
mbed_official | 146:f64d43ff0c18 | 391 | * following table shows the relationship between XFERTYP[CICEN] and XFERTYP[CCCEN], |
mbed_official | 146:f64d43ff0c18 | 392 | * in regards to XFERTYP[RSPTYP] as well as the name of the response type. |
mbed_official | 146:f64d43ff0c18 | 393 | * Relationship between parameters and the name of the response type Response type |
mbed_official | 146:f64d43ff0c18 | 394 | * (RSPTYP) Index check enable (CICEN) CRC check enable (CCCEN) Name of response |
mbed_official | 146:f64d43ff0c18 | 395 | * type 00 0 0 No Response 01 0 1 IR2 10 0 0 R3,R4 10 1 1 R1,R5,R6 11 1 1 R1b,R5b In |
mbed_official | 146:f64d43ff0c18 | 396 | * the SDIO specification, response type notation for R5b is not defined. R5 |
mbed_official | 146:f64d43ff0c18 | 397 | * includes R5b in the SDIO specification. But R5b is defined in this specification |
mbed_official | 146:f64d43ff0c18 | 398 | * to specify that the SDHC will check the busy status after receiving a |
mbed_official | 146:f64d43ff0c18 | 399 | * response. For example, usually CMD52 is used with R5, but the I/O abort command shall |
mbed_official | 146:f64d43ff0c18 | 400 | * be used with R5b. The CRC field for R3 and R4 is expected to be all 1 bits. |
mbed_official | 146:f64d43ff0c18 | 401 | * The CRC check shall be disabled for these response types. |
mbed_official | 146:f64d43ff0c18 | 402 | */ |
mbed_official | 146:f64d43ff0c18 | 403 | typedef union _hw_sdhc_xfertyp |
mbed_official | 146:f64d43ff0c18 | 404 | { |
mbed_official | 146:f64d43ff0c18 | 405 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 406 | struct _hw_sdhc_xfertyp_bitfields |
mbed_official | 146:f64d43ff0c18 | 407 | { |
mbed_official | 146:f64d43ff0c18 | 408 | uint32_t DMAEN : 1; //!< [0] DMA Enable |
mbed_official | 146:f64d43ff0c18 | 409 | uint32_t BCEN : 1; //!< [1] Block Count Enable |
mbed_official | 146:f64d43ff0c18 | 410 | uint32_t AC12EN : 1; //!< [2] Auto CMD12 Enable |
mbed_official | 146:f64d43ff0c18 | 411 | uint32_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 412 | uint32_t DTDSEL : 1; //!< [4] Data Transfer Direction Select |
mbed_official | 146:f64d43ff0c18 | 413 | uint32_t MSBSEL : 1; //!< [5] Multi/Single Block Select |
mbed_official | 146:f64d43ff0c18 | 414 | uint32_t RESERVED1 : 10; //!< [15:6] |
mbed_official | 146:f64d43ff0c18 | 415 | uint32_t RSPTYP : 2; //!< [17:16] Response Type Select |
mbed_official | 146:f64d43ff0c18 | 416 | uint32_t RESERVED2 : 1; //!< [18] |
mbed_official | 146:f64d43ff0c18 | 417 | uint32_t CCCEN : 1; //!< [19] Command CRC Check Enable |
mbed_official | 146:f64d43ff0c18 | 418 | uint32_t CICEN : 1; //!< [20] Command Index Check Enable |
mbed_official | 146:f64d43ff0c18 | 419 | uint32_t DPSEL : 1; //!< [21] Data Present Select |
mbed_official | 146:f64d43ff0c18 | 420 | uint32_t CMDTYP : 2; //!< [23:22] Command Type |
mbed_official | 146:f64d43ff0c18 | 421 | uint32_t CMDINX : 6; //!< [29:24] Command Index |
mbed_official | 146:f64d43ff0c18 | 422 | uint32_t RESERVED3 : 2; //!< [31:30] |
mbed_official | 146:f64d43ff0c18 | 423 | } B; |
mbed_official | 146:f64d43ff0c18 | 424 | } hw_sdhc_xfertyp_t; |
mbed_official | 146:f64d43ff0c18 | 425 | #endif |
mbed_official | 146:f64d43ff0c18 | 426 | |
mbed_official | 146:f64d43ff0c18 | 427 | /*! |
mbed_official | 146:f64d43ff0c18 | 428 | * @name Constants and macros for entire SDHC_XFERTYP register |
mbed_official | 146:f64d43ff0c18 | 429 | */ |
mbed_official | 146:f64d43ff0c18 | 430 | //@{ |
mbed_official | 146:f64d43ff0c18 | 431 | #define HW_SDHC_XFERTYP_ADDR (REGS_SDHC_BASE + 0xCU) |
mbed_official | 146:f64d43ff0c18 | 432 | |
mbed_official | 146:f64d43ff0c18 | 433 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 434 | #define HW_SDHC_XFERTYP (*(__IO hw_sdhc_xfertyp_t *) HW_SDHC_XFERTYP_ADDR) |
mbed_official | 146:f64d43ff0c18 | 435 | #define HW_SDHC_XFERTYP_RD() (HW_SDHC_XFERTYP.U) |
mbed_official | 146:f64d43ff0c18 | 436 | #define HW_SDHC_XFERTYP_WR(v) (HW_SDHC_XFERTYP.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 437 | #define HW_SDHC_XFERTYP_SET(v) (HW_SDHC_XFERTYP_WR(HW_SDHC_XFERTYP_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 438 | #define HW_SDHC_XFERTYP_CLR(v) (HW_SDHC_XFERTYP_WR(HW_SDHC_XFERTYP_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 439 | #define HW_SDHC_XFERTYP_TOG(v) (HW_SDHC_XFERTYP_WR(HW_SDHC_XFERTYP_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 440 | #endif |
mbed_official | 146:f64d43ff0c18 | 441 | //@} |
mbed_official | 146:f64d43ff0c18 | 442 | |
mbed_official | 146:f64d43ff0c18 | 443 | /* |
mbed_official | 146:f64d43ff0c18 | 444 | * Constants & macros for individual SDHC_XFERTYP bitfields |
mbed_official | 146:f64d43ff0c18 | 445 | */ |
mbed_official | 146:f64d43ff0c18 | 446 | |
mbed_official | 146:f64d43ff0c18 | 447 | /*! |
mbed_official | 146:f64d43ff0c18 | 448 | * @name Register SDHC_XFERTYP, field DMAEN[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 449 | * |
mbed_official | 146:f64d43ff0c18 | 450 | * Enables DMA functionality. If this bit is set to 1, a DMA operation shall |
mbed_official | 146:f64d43ff0c18 | 451 | * begin when the host driver sets the DPSEL bit of this register. Whether the |
mbed_official | 146:f64d43ff0c18 | 452 | * simple DMA, or the advanced DMA, is active depends on PROCTL[DMAS]. |
mbed_official | 146:f64d43ff0c18 | 453 | * |
mbed_official | 146:f64d43ff0c18 | 454 | * Values: |
mbed_official | 146:f64d43ff0c18 | 455 | * - 0 - Disable |
mbed_official | 146:f64d43ff0c18 | 456 | * - 1 - Enable |
mbed_official | 146:f64d43ff0c18 | 457 | */ |
mbed_official | 146:f64d43ff0c18 | 458 | //@{ |
mbed_official | 146:f64d43ff0c18 | 459 | #define BP_SDHC_XFERTYP_DMAEN (0U) //!< Bit position for SDHC_XFERTYP_DMAEN. |
mbed_official | 146:f64d43ff0c18 | 460 | #define BM_SDHC_XFERTYP_DMAEN (0x00000001U) //!< Bit mask for SDHC_XFERTYP_DMAEN. |
mbed_official | 146:f64d43ff0c18 | 461 | #define BS_SDHC_XFERTYP_DMAEN (1U) //!< Bit field size in bits for SDHC_XFERTYP_DMAEN. |
mbed_official | 146:f64d43ff0c18 | 462 | |
mbed_official | 146:f64d43ff0c18 | 463 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 464 | //! @brief Read current value of the SDHC_XFERTYP_DMAEN field. |
mbed_official | 146:f64d43ff0c18 | 465 | #define BR_SDHC_XFERTYP_DMAEN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DMAEN)) |
mbed_official | 146:f64d43ff0c18 | 466 | #endif |
mbed_official | 146:f64d43ff0c18 | 467 | |
mbed_official | 146:f64d43ff0c18 | 468 | //! @brief Format value for bitfield SDHC_XFERTYP_DMAEN. |
mbed_official | 146:f64d43ff0c18 | 469 | #define BF_SDHC_XFERTYP_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_DMAEN), uint32_t) & BM_SDHC_XFERTYP_DMAEN) |
mbed_official | 146:f64d43ff0c18 | 470 | |
mbed_official | 146:f64d43ff0c18 | 471 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 472 | //! @brief Set the DMAEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 473 | #define BW_SDHC_XFERTYP_DMAEN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DMAEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 474 | #endif |
mbed_official | 146:f64d43ff0c18 | 475 | //@} |
mbed_official | 146:f64d43ff0c18 | 476 | |
mbed_official | 146:f64d43ff0c18 | 477 | /*! |
mbed_official | 146:f64d43ff0c18 | 478 | * @name Register SDHC_XFERTYP, field BCEN[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 479 | * |
mbed_official | 146:f64d43ff0c18 | 480 | * Used to enable the Block Count register, which is only relevant for multiple |
mbed_official | 146:f64d43ff0c18 | 481 | * block transfers. When this bit is 0, the internal counter for block is |
mbed_official | 146:f64d43ff0c18 | 482 | * disabled, which is useful in executing an infinite transfer. |
mbed_official | 146:f64d43ff0c18 | 483 | * |
mbed_official | 146:f64d43ff0c18 | 484 | * Values: |
mbed_official | 146:f64d43ff0c18 | 485 | * - 0 - Disable |
mbed_official | 146:f64d43ff0c18 | 486 | * - 1 - Enable |
mbed_official | 146:f64d43ff0c18 | 487 | */ |
mbed_official | 146:f64d43ff0c18 | 488 | //@{ |
mbed_official | 146:f64d43ff0c18 | 489 | #define BP_SDHC_XFERTYP_BCEN (1U) //!< Bit position for SDHC_XFERTYP_BCEN. |
mbed_official | 146:f64d43ff0c18 | 490 | #define BM_SDHC_XFERTYP_BCEN (0x00000002U) //!< Bit mask for SDHC_XFERTYP_BCEN. |
mbed_official | 146:f64d43ff0c18 | 491 | #define BS_SDHC_XFERTYP_BCEN (1U) //!< Bit field size in bits for SDHC_XFERTYP_BCEN. |
mbed_official | 146:f64d43ff0c18 | 492 | |
mbed_official | 146:f64d43ff0c18 | 493 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 494 | //! @brief Read current value of the SDHC_XFERTYP_BCEN field. |
mbed_official | 146:f64d43ff0c18 | 495 | #define BR_SDHC_XFERTYP_BCEN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_BCEN)) |
mbed_official | 146:f64d43ff0c18 | 496 | #endif |
mbed_official | 146:f64d43ff0c18 | 497 | |
mbed_official | 146:f64d43ff0c18 | 498 | //! @brief Format value for bitfield SDHC_XFERTYP_BCEN. |
mbed_official | 146:f64d43ff0c18 | 499 | #define BF_SDHC_XFERTYP_BCEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_BCEN), uint32_t) & BM_SDHC_XFERTYP_BCEN) |
mbed_official | 146:f64d43ff0c18 | 500 | |
mbed_official | 146:f64d43ff0c18 | 501 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 502 | //! @brief Set the BCEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 503 | #define BW_SDHC_XFERTYP_BCEN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_BCEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 504 | #endif |
mbed_official | 146:f64d43ff0c18 | 505 | //@} |
mbed_official | 146:f64d43ff0c18 | 506 | |
mbed_official | 146:f64d43ff0c18 | 507 | /*! |
mbed_official | 146:f64d43ff0c18 | 508 | * @name Register SDHC_XFERTYP, field AC12EN[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 509 | * |
mbed_official | 146:f64d43ff0c18 | 510 | * Multiple block transfers for memory require a CMD12 to stop the transaction. |
mbed_official | 146:f64d43ff0c18 | 511 | * When this bit is set to 1, the SDHC will issue a CMD12 automatically when the |
mbed_official | 146:f64d43ff0c18 | 512 | * last block transfer has completed. The host driver shall not set this bit to |
mbed_official | 146:f64d43ff0c18 | 513 | * issue commands that do not require CMD12 to stop a multiple block data |
mbed_official | 146:f64d43ff0c18 | 514 | * transfer. In particular, secure commands defined in File Security Specification (see |
mbed_official | 146:f64d43ff0c18 | 515 | * reference list) do not require CMD12. In single block transfer, the SDHC will |
mbed_official | 146:f64d43ff0c18 | 516 | * ignore this bit whether it is set or not. |
mbed_official | 146:f64d43ff0c18 | 517 | * |
mbed_official | 146:f64d43ff0c18 | 518 | * Values: |
mbed_official | 146:f64d43ff0c18 | 519 | * - 0 - Disable |
mbed_official | 146:f64d43ff0c18 | 520 | * - 1 - Enable |
mbed_official | 146:f64d43ff0c18 | 521 | */ |
mbed_official | 146:f64d43ff0c18 | 522 | //@{ |
mbed_official | 146:f64d43ff0c18 | 523 | #define BP_SDHC_XFERTYP_AC12EN (2U) //!< Bit position for SDHC_XFERTYP_AC12EN. |
mbed_official | 146:f64d43ff0c18 | 524 | #define BM_SDHC_XFERTYP_AC12EN (0x00000004U) //!< Bit mask for SDHC_XFERTYP_AC12EN. |
mbed_official | 146:f64d43ff0c18 | 525 | #define BS_SDHC_XFERTYP_AC12EN (1U) //!< Bit field size in bits for SDHC_XFERTYP_AC12EN. |
mbed_official | 146:f64d43ff0c18 | 526 | |
mbed_official | 146:f64d43ff0c18 | 527 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 528 | //! @brief Read current value of the SDHC_XFERTYP_AC12EN field. |
mbed_official | 146:f64d43ff0c18 | 529 | #define BR_SDHC_XFERTYP_AC12EN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_AC12EN)) |
mbed_official | 146:f64d43ff0c18 | 530 | #endif |
mbed_official | 146:f64d43ff0c18 | 531 | |
mbed_official | 146:f64d43ff0c18 | 532 | //! @brief Format value for bitfield SDHC_XFERTYP_AC12EN. |
mbed_official | 146:f64d43ff0c18 | 533 | #define BF_SDHC_XFERTYP_AC12EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_AC12EN), uint32_t) & BM_SDHC_XFERTYP_AC12EN) |
mbed_official | 146:f64d43ff0c18 | 534 | |
mbed_official | 146:f64d43ff0c18 | 535 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 536 | //! @brief Set the AC12EN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 537 | #define BW_SDHC_XFERTYP_AC12EN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_AC12EN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 538 | #endif |
mbed_official | 146:f64d43ff0c18 | 539 | //@} |
mbed_official | 146:f64d43ff0c18 | 540 | |
mbed_official | 146:f64d43ff0c18 | 541 | /*! |
mbed_official | 146:f64d43ff0c18 | 542 | * @name Register SDHC_XFERTYP, field DTDSEL[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 543 | * |
mbed_official | 146:f64d43ff0c18 | 544 | * Defines the direction of DAT line data transfers. The bit is set to 1 by the |
mbed_official | 146:f64d43ff0c18 | 545 | * host driver to transfer data from the SD card to the SDHC and is set to 0 for |
mbed_official | 146:f64d43ff0c18 | 546 | * all other commands. |
mbed_official | 146:f64d43ff0c18 | 547 | * |
mbed_official | 146:f64d43ff0c18 | 548 | * Values: |
mbed_official | 146:f64d43ff0c18 | 549 | * - 0 - Write host to card. |
mbed_official | 146:f64d43ff0c18 | 550 | * - 1 - Read card to host. |
mbed_official | 146:f64d43ff0c18 | 551 | */ |
mbed_official | 146:f64d43ff0c18 | 552 | //@{ |
mbed_official | 146:f64d43ff0c18 | 553 | #define BP_SDHC_XFERTYP_DTDSEL (4U) //!< Bit position for SDHC_XFERTYP_DTDSEL. |
mbed_official | 146:f64d43ff0c18 | 554 | #define BM_SDHC_XFERTYP_DTDSEL (0x00000010U) //!< Bit mask for SDHC_XFERTYP_DTDSEL. |
mbed_official | 146:f64d43ff0c18 | 555 | #define BS_SDHC_XFERTYP_DTDSEL (1U) //!< Bit field size in bits for SDHC_XFERTYP_DTDSEL. |
mbed_official | 146:f64d43ff0c18 | 556 | |
mbed_official | 146:f64d43ff0c18 | 557 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 558 | //! @brief Read current value of the SDHC_XFERTYP_DTDSEL field. |
mbed_official | 146:f64d43ff0c18 | 559 | #define BR_SDHC_XFERTYP_DTDSEL (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DTDSEL)) |
mbed_official | 146:f64d43ff0c18 | 560 | #endif |
mbed_official | 146:f64d43ff0c18 | 561 | |
mbed_official | 146:f64d43ff0c18 | 562 | //! @brief Format value for bitfield SDHC_XFERTYP_DTDSEL. |
mbed_official | 146:f64d43ff0c18 | 563 | #define BF_SDHC_XFERTYP_DTDSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_DTDSEL), uint32_t) & BM_SDHC_XFERTYP_DTDSEL) |
mbed_official | 146:f64d43ff0c18 | 564 | |
mbed_official | 146:f64d43ff0c18 | 565 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 566 | //! @brief Set the DTDSEL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 567 | #define BW_SDHC_XFERTYP_DTDSEL(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DTDSEL) = (v)) |
mbed_official | 146:f64d43ff0c18 | 568 | #endif |
mbed_official | 146:f64d43ff0c18 | 569 | //@} |
mbed_official | 146:f64d43ff0c18 | 570 | |
mbed_official | 146:f64d43ff0c18 | 571 | /*! |
mbed_official | 146:f64d43ff0c18 | 572 | * @name Register SDHC_XFERTYP, field MSBSEL[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 573 | * |
mbed_official | 146:f64d43ff0c18 | 574 | * Enables multiple block DAT line data transfers. For any other commands, this |
mbed_official | 146:f64d43ff0c18 | 575 | * bit shall be set to 0. If this bit is 0, it is not necessary to set the block |
mbed_official | 146:f64d43ff0c18 | 576 | * count register. |
mbed_official | 146:f64d43ff0c18 | 577 | * |
mbed_official | 146:f64d43ff0c18 | 578 | * Values: |
mbed_official | 146:f64d43ff0c18 | 579 | * - 0 - Single block. |
mbed_official | 146:f64d43ff0c18 | 580 | * - 1 - Multiple blocks. |
mbed_official | 146:f64d43ff0c18 | 581 | */ |
mbed_official | 146:f64d43ff0c18 | 582 | //@{ |
mbed_official | 146:f64d43ff0c18 | 583 | #define BP_SDHC_XFERTYP_MSBSEL (5U) //!< Bit position for SDHC_XFERTYP_MSBSEL. |
mbed_official | 146:f64d43ff0c18 | 584 | #define BM_SDHC_XFERTYP_MSBSEL (0x00000020U) //!< Bit mask for SDHC_XFERTYP_MSBSEL. |
mbed_official | 146:f64d43ff0c18 | 585 | #define BS_SDHC_XFERTYP_MSBSEL (1U) //!< Bit field size in bits for SDHC_XFERTYP_MSBSEL. |
mbed_official | 146:f64d43ff0c18 | 586 | |
mbed_official | 146:f64d43ff0c18 | 587 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 588 | //! @brief Read current value of the SDHC_XFERTYP_MSBSEL field. |
mbed_official | 146:f64d43ff0c18 | 589 | #define BR_SDHC_XFERTYP_MSBSEL (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_MSBSEL)) |
mbed_official | 146:f64d43ff0c18 | 590 | #endif |
mbed_official | 146:f64d43ff0c18 | 591 | |
mbed_official | 146:f64d43ff0c18 | 592 | //! @brief Format value for bitfield SDHC_XFERTYP_MSBSEL. |
mbed_official | 146:f64d43ff0c18 | 593 | #define BF_SDHC_XFERTYP_MSBSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_MSBSEL), uint32_t) & BM_SDHC_XFERTYP_MSBSEL) |
mbed_official | 146:f64d43ff0c18 | 594 | |
mbed_official | 146:f64d43ff0c18 | 595 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 596 | //! @brief Set the MSBSEL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 597 | #define BW_SDHC_XFERTYP_MSBSEL(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_MSBSEL) = (v)) |
mbed_official | 146:f64d43ff0c18 | 598 | #endif |
mbed_official | 146:f64d43ff0c18 | 599 | //@} |
mbed_official | 146:f64d43ff0c18 | 600 | |
mbed_official | 146:f64d43ff0c18 | 601 | /*! |
mbed_official | 146:f64d43ff0c18 | 602 | * @name Register SDHC_XFERTYP, field RSPTYP[17:16] (RW) |
mbed_official | 146:f64d43ff0c18 | 603 | * |
mbed_official | 146:f64d43ff0c18 | 604 | * Values: |
mbed_official | 146:f64d43ff0c18 | 605 | * - 00 - No response. |
mbed_official | 146:f64d43ff0c18 | 606 | * - 01 - Response length 136. |
mbed_official | 146:f64d43ff0c18 | 607 | * - 10 - Response length 48. |
mbed_official | 146:f64d43ff0c18 | 608 | * - 11 - Response length 48, check busy after response. |
mbed_official | 146:f64d43ff0c18 | 609 | */ |
mbed_official | 146:f64d43ff0c18 | 610 | //@{ |
mbed_official | 146:f64d43ff0c18 | 611 | #define BP_SDHC_XFERTYP_RSPTYP (16U) //!< Bit position for SDHC_XFERTYP_RSPTYP. |
mbed_official | 146:f64d43ff0c18 | 612 | #define BM_SDHC_XFERTYP_RSPTYP (0x00030000U) //!< Bit mask for SDHC_XFERTYP_RSPTYP. |
mbed_official | 146:f64d43ff0c18 | 613 | #define BS_SDHC_XFERTYP_RSPTYP (2U) //!< Bit field size in bits for SDHC_XFERTYP_RSPTYP. |
mbed_official | 146:f64d43ff0c18 | 614 | |
mbed_official | 146:f64d43ff0c18 | 615 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 616 | //! @brief Read current value of the SDHC_XFERTYP_RSPTYP field. |
mbed_official | 146:f64d43ff0c18 | 617 | #define BR_SDHC_XFERTYP_RSPTYP (HW_SDHC_XFERTYP.B.RSPTYP) |
mbed_official | 146:f64d43ff0c18 | 618 | #endif |
mbed_official | 146:f64d43ff0c18 | 619 | |
mbed_official | 146:f64d43ff0c18 | 620 | //! @brief Format value for bitfield SDHC_XFERTYP_RSPTYP. |
mbed_official | 146:f64d43ff0c18 | 621 | #define BF_SDHC_XFERTYP_RSPTYP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_RSPTYP), uint32_t) & BM_SDHC_XFERTYP_RSPTYP) |
mbed_official | 146:f64d43ff0c18 | 622 | |
mbed_official | 146:f64d43ff0c18 | 623 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 624 | //! @brief Set the RSPTYP field to a new value. |
mbed_official | 146:f64d43ff0c18 | 625 | #define BW_SDHC_XFERTYP_RSPTYP(v) (HW_SDHC_XFERTYP_WR((HW_SDHC_XFERTYP_RD() & ~BM_SDHC_XFERTYP_RSPTYP) | BF_SDHC_XFERTYP_RSPTYP(v))) |
mbed_official | 146:f64d43ff0c18 | 626 | #endif |
mbed_official | 146:f64d43ff0c18 | 627 | //@} |
mbed_official | 146:f64d43ff0c18 | 628 | |
mbed_official | 146:f64d43ff0c18 | 629 | /*! |
mbed_official | 146:f64d43ff0c18 | 630 | * @name Register SDHC_XFERTYP, field CCCEN[19] (RW) |
mbed_official | 146:f64d43ff0c18 | 631 | * |
mbed_official | 146:f64d43ff0c18 | 632 | * If this bit is set to 1, the SDHC shall check the CRC field in the response. |
mbed_official | 146:f64d43ff0c18 | 633 | * If an error is detected, it is reported as a Command CRC Error. If this bit is |
mbed_official | 146:f64d43ff0c18 | 634 | * set to 0, the CRC field is not checked. The number of bits checked by the CRC |
mbed_official | 146:f64d43ff0c18 | 635 | * field value changes according to the length of the response. |
mbed_official | 146:f64d43ff0c18 | 636 | * |
mbed_official | 146:f64d43ff0c18 | 637 | * Values: |
mbed_official | 146:f64d43ff0c18 | 638 | * - 0 - Disable |
mbed_official | 146:f64d43ff0c18 | 639 | * - 1 - Enable |
mbed_official | 146:f64d43ff0c18 | 640 | */ |
mbed_official | 146:f64d43ff0c18 | 641 | //@{ |
mbed_official | 146:f64d43ff0c18 | 642 | #define BP_SDHC_XFERTYP_CCCEN (19U) //!< Bit position for SDHC_XFERTYP_CCCEN. |
mbed_official | 146:f64d43ff0c18 | 643 | #define BM_SDHC_XFERTYP_CCCEN (0x00080000U) //!< Bit mask for SDHC_XFERTYP_CCCEN. |
mbed_official | 146:f64d43ff0c18 | 644 | #define BS_SDHC_XFERTYP_CCCEN (1U) //!< Bit field size in bits for SDHC_XFERTYP_CCCEN. |
mbed_official | 146:f64d43ff0c18 | 645 | |
mbed_official | 146:f64d43ff0c18 | 646 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 647 | //! @brief Read current value of the SDHC_XFERTYP_CCCEN field. |
mbed_official | 146:f64d43ff0c18 | 648 | #define BR_SDHC_XFERTYP_CCCEN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_CCCEN)) |
mbed_official | 146:f64d43ff0c18 | 649 | #endif |
mbed_official | 146:f64d43ff0c18 | 650 | |
mbed_official | 146:f64d43ff0c18 | 651 | //! @brief Format value for bitfield SDHC_XFERTYP_CCCEN. |
mbed_official | 146:f64d43ff0c18 | 652 | #define BF_SDHC_XFERTYP_CCCEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_CCCEN), uint32_t) & BM_SDHC_XFERTYP_CCCEN) |
mbed_official | 146:f64d43ff0c18 | 653 | |
mbed_official | 146:f64d43ff0c18 | 654 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 655 | //! @brief Set the CCCEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 656 | #define BW_SDHC_XFERTYP_CCCEN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_CCCEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 657 | #endif |
mbed_official | 146:f64d43ff0c18 | 658 | //@} |
mbed_official | 146:f64d43ff0c18 | 659 | |
mbed_official | 146:f64d43ff0c18 | 660 | /*! |
mbed_official | 146:f64d43ff0c18 | 661 | * @name Register SDHC_XFERTYP, field CICEN[20] (RW) |
mbed_official | 146:f64d43ff0c18 | 662 | * |
mbed_official | 146:f64d43ff0c18 | 663 | * If this bit is set to 1, the SDHC will check the index field in the response |
mbed_official | 146:f64d43ff0c18 | 664 | * to see if it has the same value as the command index. If it is not, it is |
mbed_official | 146:f64d43ff0c18 | 665 | * reported as a command index error. If this bit is set to 0, the index field is not |
mbed_official | 146:f64d43ff0c18 | 666 | * checked. |
mbed_official | 146:f64d43ff0c18 | 667 | * |
mbed_official | 146:f64d43ff0c18 | 668 | * Values: |
mbed_official | 146:f64d43ff0c18 | 669 | * - 0 - Disable |
mbed_official | 146:f64d43ff0c18 | 670 | * - 1 - Enable |
mbed_official | 146:f64d43ff0c18 | 671 | */ |
mbed_official | 146:f64d43ff0c18 | 672 | //@{ |
mbed_official | 146:f64d43ff0c18 | 673 | #define BP_SDHC_XFERTYP_CICEN (20U) //!< Bit position for SDHC_XFERTYP_CICEN. |
mbed_official | 146:f64d43ff0c18 | 674 | #define BM_SDHC_XFERTYP_CICEN (0x00100000U) //!< Bit mask for SDHC_XFERTYP_CICEN. |
mbed_official | 146:f64d43ff0c18 | 675 | #define BS_SDHC_XFERTYP_CICEN (1U) //!< Bit field size in bits for SDHC_XFERTYP_CICEN. |
mbed_official | 146:f64d43ff0c18 | 676 | |
mbed_official | 146:f64d43ff0c18 | 677 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 678 | //! @brief Read current value of the SDHC_XFERTYP_CICEN field. |
mbed_official | 146:f64d43ff0c18 | 679 | #define BR_SDHC_XFERTYP_CICEN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_CICEN)) |
mbed_official | 146:f64d43ff0c18 | 680 | #endif |
mbed_official | 146:f64d43ff0c18 | 681 | |
mbed_official | 146:f64d43ff0c18 | 682 | //! @brief Format value for bitfield SDHC_XFERTYP_CICEN. |
mbed_official | 146:f64d43ff0c18 | 683 | #define BF_SDHC_XFERTYP_CICEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_CICEN), uint32_t) & BM_SDHC_XFERTYP_CICEN) |
mbed_official | 146:f64d43ff0c18 | 684 | |
mbed_official | 146:f64d43ff0c18 | 685 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 686 | //! @brief Set the CICEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 687 | #define BW_SDHC_XFERTYP_CICEN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_CICEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 688 | #endif |
mbed_official | 146:f64d43ff0c18 | 689 | //@} |
mbed_official | 146:f64d43ff0c18 | 690 | |
mbed_official | 146:f64d43ff0c18 | 691 | /*! |
mbed_official | 146:f64d43ff0c18 | 692 | * @name Register SDHC_XFERTYP, field DPSEL[21] (RW) |
mbed_official | 146:f64d43ff0c18 | 693 | * |
mbed_official | 146:f64d43ff0c18 | 694 | * This bit is set to 1 to indicate that data is present and shall be |
mbed_official | 146:f64d43ff0c18 | 695 | * transferred using the DAT line. It is set to 0 for the following: Commands using only |
mbed_official | 146:f64d43ff0c18 | 696 | * the CMD line, for example: CMD52. Commands with no data transfer, but using the |
mbed_official | 146:f64d43ff0c18 | 697 | * busy signal on DAT[0] line, R1b or R5b, for example: CMD38. In resume command, |
mbed_official | 146:f64d43ff0c18 | 698 | * this bit shall be set, and other bits in this register shall be set the same |
mbed_official | 146:f64d43ff0c18 | 699 | * as when the transfer was initially launched. When the Write Protect switch is |
mbed_official | 146:f64d43ff0c18 | 700 | * on, that is, the WPSPL bit is active as 0, any command with a write operation |
mbed_official | 146:f64d43ff0c18 | 701 | * will be ignored. That is to say, when this bit is set, while the DTDSEL bit is |
mbed_official | 146:f64d43ff0c18 | 702 | * 0, writes to the register Transfer Type are ignored. |
mbed_official | 146:f64d43ff0c18 | 703 | * |
mbed_official | 146:f64d43ff0c18 | 704 | * Values: |
mbed_official | 146:f64d43ff0c18 | 705 | * - 0 - No data present. |
mbed_official | 146:f64d43ff0c18 | 706 | * - 1 - Data present. |
mbed_official | 146:f64d43ff0c18 | 707 | */ |
mbed_official | 146:f64d43ff0c18 | 708 | //@{ |
mbed_official | 146:f64d43ff0c18 | 709 | #define BP_SDHC_XFERTYP_DPSEL (21U) //!< Bit position for SDHC_XFERTYP_DPSEL. |
mbed_official | 146:f64d43ff0c18 | 710 | #define BM_SDHC_XFERTYP_DPSEL (0x00200000U) //!< Bit mask for SDHC_XFERTYP_DPSEL. |
mbed_official | 146:f64d43ff0c18 | 711 | #define BS_SDHC_XFERTYP_DPSEL (1U) //!< Bit field size in bits for SDHC_XFERTYP_DPSEL. |
mbed_official | 146:f64d43ff0c18 | 712 | |
mbed_official | 146:f64d43ff0c18 | 713 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 714 | //! @brief Read current value of the SDHC_XFERTYP_DPSEL field. |
mbed_official | 146:f64d43ff0c18 | 715 | #define BR_SDHC_XFERTYP_DPSEL (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DPSEL)) |
mbed_official | 146:f64d43ff0c18 | 716 | #endif |
mbed_official | 146:f64d43ff0c18 | 717 | |
mbed_official | 146:f64d43ff0c18 | 718 | //! @brief Format value for bitfield SDHC_XFERTYP_DPSEL. |
mbed_official | 146:f64d43ff0c18 | 719 | #define BF_SDHC_XFERTYP_DPSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_DPSEL), uint32_t) & BM_SDHC_XFERTYP_DPSEL) |
mbed_official | 146:f64d43ff0c18 | 720 | |
mbed_official | 146:f64d43ff0c18 | 721 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 722 | //! @brief Set the DPSEL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 723 | #define BW_SDHC_XFERTYP_DPSEL(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DPSEL) = (v)) |
mbed_official | 146:f64d43ff0c18 | 724 | #endif |
mbed_official | 146:f64d43ff0c18 | 725 | //@} |
mbed_official | 146:f64d43ff0c18 | 726 | |
mbed_official | 146:f64d43ff0c18 | 727 | /*! |
mbed_official | 146:f64d43ff0c18 | 728 | * @name Register SDHC_XFERTYP, field CMDTYP[23:22] (RW) |
mbed_official | 146:f64d43ff0c18 | 729 | * |
mbed_official | 146:f64d43ff0c18 | 730 | * There are three types of special commands: suspend, resume, and abort. These |
mbed_official | 146:f64d43ff0c18 | 731 | * bits shall be set to 00b for all other commands. Suspend command: If the |
mbed_official | 146:f64d43ff0c18 | 732 | * suspend command succeeds, the SDHC shall assume that the card bus has been released |
mbed_official | 146:f64d43ff0c18 | 733 | * and that it is possible to issue the next command which uses the DAT line. |
mbed_official | 146:f64d43ff0c18 | 734 | * Because the SDHC does not monitor the content of command response, it does not |
mbed_official | 146:f64d43ff0c18 | 735 | * know if the suspend command succeeded or not. It is the host driver's |
mbed_official | 146:f64d43ff0c18 | 736 | * responsibility to check the status of the suspend command and send another command |
mbed_official | 146:f64d43ff0c18 | 737 | * marked as suspend to inform the SDHC that a suspend command was successfully |
mbed_official | 146:f64d43ff0c18 | 738 | * issued. After the end bit of command is sent, the SDHC deasserts read wait for read |
mbed_official | 146:f64d43ff0c18 | 739 | * transactions and stops checking busy for write transactions. In 4-bit mode, |
mbed_official | 146:f64d43ff0c18 | 740 | * the interrupt cycle starts. If the suspend command fails, the SDHC will |
mbed_official | 146:f64d43ff0c18 | 741 | * maintain its current state, and the host driver shall restart the transfer by setting |
mbed_official | 146:f64d43ff0c18 | 742 | * PROCTL[CREQ]. Resume command: The host driver restarts the data transfer by |
mbed_official | 146:f64d43ff0c18 | 743 | * restoring the registers saved before sending the suspend command and then sends |
mbed_official | 146:f64d43ff0c18 | 744 | * the resume command. The SDHC will check for a pending busy state before |
mbed_official | 146:f64d43ff0c18 | 745 | * starting write transfers. Abort command: If this command is set when executing a |
mbed_official | 146:f64d43ff0c18 | 746 | * read transfer, the SDHC will stop reads to the buffer. If this command is set |
mbed_official | 146:f64d43ff0c18 | 747 | * when executing a write transfer, the SDHC will stop driving the DAT line. After |
mbed_official | 146:f64d43ff0c18 | 748 | * issuing the abort command, the host driver must issue a software reset (abort |
mbed_official | 146:f64d43ff0c18 | 749 | * transaction). |
mbed_official | 146:f64d43ff0c18 | 750 | * |
mbed_official | 146:f64d43ff0c18 | 751 | * Values: |
mbed_official | 146:f64d43ff0c18 | 752 | * - 00 - Normal other commands. |
mbed_official | 146:f64d43ff0c18 | 753 | * - 01 - Suspend CMD52 for writing bus suspend in CCCR. |
mbed_official | 146:f64d43ff0c18 | 754 | * - 10 - Resume CMD52 for writing function select in CCCR. |
mbed_official | 146:f64d43ff0c18 | 755 | * - 11 - Abort CMD12, CMD52 for writing I/O abort in CCCR. |
mbed_official | 146:f64d43ff0c18 | 756 | */ |
mbed_official | 146:f64d43ff0c18 | 757 | //@{ |
mbed_official | 146:f64d43ff0c18 | 758 | #define BP_SDHC_XFERTYP_CMDTYP (22U) //!< Bit position for SDHC_XFERTYP_CMDTYP. |
mbed_official | 146:f64d43ff0c18 | 759 | #define BM_SDHC_XFERTYP_CMDTYP (0x00C00000U) //!< Bit mask for SDHC_XFERTYP_CMDTYP. |
mbed_official | 146:f64d43ff0c18 | 760 | #define BS_SDHC_XFERTYP_CMDTYP (2U) //!< Bit field size in bits for SDHC_XFERTYP_CMDTYP. |
mbed_official | 146:f64d43ff0c18 | 761 | |
mbed_official | 146:f64d43ff0c18 | 762 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 763 | //! @brief Read current value of the SDHC_XFERTYP_CMDTYP field. |
mbed_official | 146:f64d43ff0c18 | 764 | #define BR_SDHC_XFERTYP_CMDTYP (HW_SDHC_XFERTYP.B.CMDTYP) |
mbed_official | 146:f64d43ff0c18 | 765 | #endif |
mbed_official | 146:f64d43ff0c18 | 766 | |
mbed_official | 146:f64d43ff0c18 | 767 | //! @brief Format value for bitfield SDHC_XFERTYP_CMDTYP. |
mbed_official | 146:f64d43ff0c18 | 768 | #define BF_SDHC_XFERTYP_CMDTYP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_CMDTYP), uint32_t) & BM_SDHC_XFERTYP_CMDTYP) |
mbed_official | 146:f64d43ff0c18 | 769 | |
mbed_official | 146:f64d43ff0c18 | 770 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 771 | //! @brief Set the CMDTYP field to a new value. |
mbed_official | 146:f64d43ff0c18 | 772 | #define BW_SDHC_XFERTYP_CMDTYP(v) (HW_SDHC_XFERTYP_WR((HW_SDHC_XFERTYP_RD() & ~BM_SDHC_XFERTYP_CMDTYP) | BF_SDHC_XFERTYP_CMDTYP(v))) |
mbed_official | 146:f64d43ff0c18 | 773 | #endif |
mbed_official | 146:f64d43ff0c18 | 774 | //@} |
mbed_official | 146:f64d43ff0c18 | 775 | |
mbed_official | 146:f64d43ff0c18 | 776 | /*! |
mbed_official | 146:f64d43ff0c18 | 777 | * @name Register SDHC_XFERTYP, field CMDINX[29:24] (RW) |
mbed_official | 146:f64d43ff0c18 | 778 | * |
mbed_official | 146:f64d43ff0c18 | 779 | * These bits shall be set to the command number that is specified in bits 45-40 |
mbed_official | 146:f64d43ff0c18 | 780 | * of the command-format in the SD Memory Card Physical Layer Specification and |
mbed_official | 146:f64d43ff0c18 | 781 | * SDIO Card Specification. |
mbed_official | 146:f64d43ff0c18 | 782 | */ |
mbed_official | 146:f64d43ff0c18 | 783 | //@{ |
mbed_official | 146:f64d43ff0c18 | 784 | #define BP_SDHC_XFERTYP_CMDINX (24U) //!< Bit position for SDHC_XFERTYP_CMDINX. |
mbed_official | 146:f64d43ff0c18 | 785 | #define BM_SDHC_XFERTYP_CMDINX (0x3F000000U) //!< Bit mask for SDHC_XFERTYP_CMDINX. |
mbed_official | 146:f64d43ff0c18 | 786 | #define BS_SDHC_XFERTYP_CMDINX (6U) //!< Bit field size in bits for SDHC_XFERTYP_CMDINX. |
mbed_official | 146:f64d43ff0c18 | 787 | |
mbed_official | 146:f64d43ff0c18 | 788 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 789 | //! @brief Read current value of the SDHC_XFERTYP_CMDINX field. |
mbed_official | 146:f64d43ff0c18 | 790 | #define BR_SDHC_XFERTYP_CMDINX (HW_SDHC_XFERTYP.B.CMDINX) |
mbed_official | 146:f64d43ff0c18 | 791 | #endif |
mbed_official | 146:f64d43ff0c18 | 792 | |
mbed_official | 146:f64d43ff0c18 | 793 | //! @brief Format value for bitfield SDHC_XFERTYP_CMDINX. |
mbed_official | 146:f64d43ff0c18 | 794 | #define BF_SDHC_XFERTYP_CMDINX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_CMDINX), uint32_t) & BM_SDHC_XFERTYP_CMDINX) |
mbed_official | 146:f64d43ff0c18 | 795 | |
mbed_official | 146:f64d43ff0c18 | 796 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 797 | //! @brief Set the CMDINX field to a new value. |
mbed_official | 146:f64d43ff0c18 | 798 | #define BW_SDHC_XFERTYP_CMDINX(v) (HW_SDHC_XFERTYP_WR((HW_SDHC_XFERTYP_RD() & ~BM_SDHC_XFERTYP_CMDINX) | BF_SDHC_XFERTYP_CMDINX(v))) |
mbed_official | 146:f64d43ff0c18 | 799 | #endif |
mbed_official | 146:f64d43ff0c18 | 800 | //@} |
mbed_official | 146:f64d43ff0c18 | 801 | |
mbed_official | 146:f64d43ff0c18 | 802 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 803 | // HW_SDHC_CMDRSP0 - Command Response 0 |
mbed_official | 146:f64d43ff0c18 | 804 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 805 | |
mbed_official | 146:f64d43ff0c18 | 806 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 807 | /*! |
mbed_official | 146:f64d43ff0c18 | 808 | * @brief HW_SDHC_CMDRSP0 - Command Response 0 (RO) |
mbed_official | 146:f64d43ff0c18 | 809 | * |
mbed_official | 146:f64d43ff0c18 | 810 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 811 | * |
mbed_official | 146:f64d43ff0c18 | 812 | * This register is used to store part 0 of the response bits from the card. |
mbed_official | 146:f64d43ff0c18 | 813 | */ |
mbed_official | 146:f64d43ff0c18 | 814 | typedef union _hw_sdhc_cmdrsp0 |
mbed_official | 146:f64d43ff0c18 | 815 | { |
mbed_official | 146:f64d43ff0c18 | 816 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 817 | struct _hw_sdhc_cmdrsp0_bitfields |
mbed_official | 146:f64d43ff0c18 | 818 | { |
mbed_official | 146:f64d43ff0c18 | 819 | uint32_t CMDRSP0 : 32; //!< [31:0] Command Response 0 |
mbed_official | 146:f64d43ff0c18 | 820 | } B; |
mbed_official | 146:f64d43ff0c18 | 821 | } hw_sdhc_cmdrsp0_t; |
mbed_official | 146:f64d43ff0c18 | 822 | #endif |
mbed_official | 146:f64d43ff0c18 | 823 | |
mbed_official | 146:f64d43ff0c18 | 824 | /*! |
mbed_official | 146:f64d43ff0c18 | 825 | * @name Constants and macros for entire SDHC_CMDRSP0 register |
mbed_official | 146:f64d43ff0c18 | 826 | */ |
mbed_official | 146:f64d43ff0c18 | 827 | //@{ |
mbed_official | 146:f64d43ff0c18 | 828 | #define HW_SDHC_CMDRSP0_ADDR (REGS_SDHC_BASE + 0x10U) |
mbed_official | 146:f64d43ff0c18 | 829 | |
mbed_official | 146:f64d43ff0c18 | 830 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 831 | #define HW_SDHC_CMDRSP0 (*(__I hw_sdhc_cmdrsp0_t *) HW_SDHC_CMDRSP0_ADDR) |
mbed_official | 146:f64d43ff0c18 | 832 | #define HW_SDHC_CMDRSP0_RD() (HW_SDHC_CMDRSP0.U) |
mbed_official | 146:f64d43ff0c18 | 833 | #endif |
mbed_official | 146:f64d43ff0c18 | 834 | //@} |
mbed_official | 146:f64d43ff0c18 | 835 | |
mbed_official | 146:f64d43ff0c18 | 836 | /* |
mbed_official | 146:f64d43ff0c18 | 837 | * Constants & macros for individual SDHC_CMDRSP0 bitfields |
mbed_official | 146:f64d43ff0c18 | 838 | */ |
mbed_official | 146:f64d43ff0c18 | 839 | |
mbed_official | 146:f64d43ff0c18 | 840 | /*! |
mbed_official | 146:f64d43ff0c18 | 841 | * @name Register SDHC_CMDRSP0, field CMDRSP0[31:0] (RO) |
mbed_official | 146:f64d43ff0c18 | 842 | */ |
mbed_official | 146:f64d43ff0c18 | 843 | //@{ |
mbed_official | 146:f64d43ff0c18 | 844 | #define BP_SDHC_CMDRSP0_CMDRSP0 (0U) //!< Bit position for SDHC_CMDRSP0_CMDRSP0. |
mbed_official | 146:f64d43ff0c18 | 845 | #define BM_SDHC_CMDRSP0_CMDRSP0 (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDRSP0_CMDRSP0. |
mbed_official | 146:f64d43ff0c18 | 846 | #define BS_SDHC_CMDRSP0_CMDRSP0 (32U) //!< Bit field size in bits for SDHC_CMDRSP0_CMDRSP0. |
mbed_official | 146:f64d43ff0c18 | 847 | |
mbed_official | 146:f64d43ff0c18 | 848 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 849 | //! @brief Read current value of the SDHC_CMDRSP0_CMDRSP0 field. |
mbed_official | 146:f64d43ff0c18 | 850 | #define BR_SDHC_CMDRSP0_CMDRSP0 (HW_SDHC_CMDRSP0.U) |
mbed_official | 146:f64d43ff0c18 | 851 | #endif |
mbed_official | 146:f64d43ff0c18 | 852 | //@} |
mbed_official | 146:f64d43ff0c18 | 853 | |
mbed_official | 146:f64d43ff0c18 | 854 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 855 | // HW_SDHC_CMDRSP1 - Command Response 1 |
mbed_official | 146:f64d43ff0c18 | 856 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 857 | |
mbed_official | 146:f64d43ff0c18 | 858 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 859 | /*! |
mbed_official | 146:f64d43ff0c18 | 860 | * @brief HW_SDHC_CMDRSP1 - Command Response 1 (RO) |
mbed_official | 146:f64d43ff0c18 | 861 | * |
mbed_official | 146:f64d43ff0c18 | 862 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 863 | * |
mbed_official | 146:f64d43ff0c18 | 864 | * This register is used to store part 1 of the response bits from the card. |
mbed_official | 146:f64d43ff0c18 | 865 | */ |
mbed_official | 146:f64d43ff0c18 | 866 | typedef union _hw_sdhc_cmdrsp1 |
mbed_official | 146:f64d43ff0c18 | 867 | { |
mbed_official | 146:f64d43ff0c18 | 868 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 869 | struct _hw_sdhc_cmdrsp1_bitfields |
mbed_official | 146:f64d43ff0c18 | 870 | { |
mbed_official | 146:f64d43ff0c18 | 871 | uint32_t CMDRSP1 : 32; //!< [31:0] Command Response 1 |
mbed_official | 146:f64d43ff0c18 | 872 | } B; |
mbed_official | 146:f64d43ff0c18 | 873 | } hw_sdhc_cmdrsp1_t; |
mbed_official | 146:f64d43ff0c18 | 874 | #endif |
mbed_official | 146:f64d43ff0c18 | 875 | |
mbed_official | 146:f64d43ff0c18 | 876 | /*! |
mbed_official | 146:f64d43ff0c18 | 877 | * @name Constants and macros for entire SDHC_CMDRSP1 register |
mbed_official | 146:f64d43ff0c18 | 878 | */ |
mbed_official | 146:f64d43ff0c18 | 879 | //@{ |
mbed_official | 146:f64d43ff0c18 | 880 | #define HW_SDHC_CMDRSP1_ADDR (REGS_SDHC_BASE + 0x14U) |
mbed_official | 146:f64d43ff0c18 | 881 | |
mbed_official | 146:f64d43ff0c18 | 882 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 883 | #define HW_SDHC_CMDRSP1 (*(__I hw_sdhc_cmdrsp1_t *) HW_SDHC_CMDRSP1_ADDR) |
mbed_official | 146:f64d43ff0c18 | 884 | #define HW_SDHC_CMDRSP1_RD() (HW_SDHC_CMDRSP1.U) |
mbed_official | 146:f64d43ff0c18 | 885 | #endif |
mbed_official | 146:f64d43ff0c18 | 886 | //@} |
mbed_official | 146:f64d43ff0c18 | 887 | |
mbed_official | 146:f64d43ff0c18 | 888 | /* |
mbed_official | 146:f64d43ff0c18 | 889 | * Constants & macros for individual SDHC_CMDRSP1 bitfields |
mbed_official | 146:f64d43ff0c18 | 890 | */ |
mbed_official | 146:f64d43ff0c18 | 891 | |
mbed_official | 146:f64d43ff0c18 | 892 | /*! |
mbed_official | 146:f64d43ff0c18 | 893 | * @name Register SDHC_CMDRSP1, field CMDRSP1[31:0] (RO) |
mbed_official | 146:f64d43ff0c18 | 894 | */ |
mbed_official | 146:f64d43ff0c18 | 895 | //@{ |
mbed_official | 146:f64d43ff0c18 | 896 | #define BP_SDHC_CMDRSP1_CMDRSP1 (0U) //!< Bit position for SDHC_CMDRSP1_CMDRSP1. |
mbed_official | 146:f64d43ff0c18 | 897 | #define BM_SDHC_CMDRSP1_CMDRSP1 (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDRSP1_CMDRSP1. |
mbed_official | 146:f64d43ff0c18 | 898 | #define BS_SDHC_CMDRSP1_CMDRSP1 (32U) //!< Bit field size in bits for SDHC_CMDRSP1_CMDRSP1. |
mbed_official | 146:f64d43ff0c18 | 899 | |
mbed_official | 146:f64d43ff0c18 | 900 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 901 | //! @brief Read current value of the SDHC_CMDRSP1_CMDRSP1 field. |
mbed_official | 146:f64d43ff0c18 | 902 | #define BR_SDHC_CMDRSP1_CMDRSP1 (HW_SDHC_CMDRSP1.U) |
mbed_official | 146:f64d43ff0c18 | 903 | #endif |
mbed_official | 146:f64d43ff0c18 | 904 | //@} |
mbed_official | 146:f64d43ff0c18 | 905 | |
mbed_official | 146:f64d43ff0c18 | 906 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 907 | // HW_SDHC_CMDRSP2 - Command Response 2 |
mbed_official | 146:f64d43ff0c18 | 908 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 909 | |
mbed_official | 146:f64d43ff0c18 | 910 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 911 | /*! |
mbed_official | 146:f64d43ff0c18 | 912 | * @brief HW_SDHC_CMDRSP2 - Command Response 2 (RO) |
mbed_official | 146:f64d43ff0c18 | 913 | * |
mbed_official | 146:f64d43ff0c18 | 914 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 915 | * |
mbed_official | 146:f64d43ff0c18 | 916 | * This register is used to store part 2 of the response bits from the card. |
mbed_official | 146:f64d43ff0c18 | 917 | */ |
mbed_official | 146:f64d43ff0c18 | 918 | typedef union _hw_sdhc_cmdrsp2 |
mbed_official | 146:f64d43ff0c18 | 919 | { |
mbed_official | 146:f64d43ff0c18 | 920 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 921 | struct _hw_sdhc_cmdrsp2_bitfields |
mbed_official | 146:f64d43ff0c18 | 922 | { |
mbed_official | 146:f64d43ff0c18 | 923 | uint32_t CMDRSP2 : 32; //!< [31:0] Command Response 2 |
mbed_official | 146:f64d43ff0c18 | 924 | } B; |
mbed_official | 146:f64d43ff0c18 | 925 | } hw_sdhc_cmdrsp2_t; |
mbed_official | 146:f64d43ff0c18 | 926 | #endif |
mbed_official | 146:f64d43ff0c18 | 927 | |
mbed_official | 146:f64d43ff0c18 | 928 | /*! |
mbed_official | 146:f64d43ff0c18 | 929 | * @name Constants and macros for entire SDHC_CMDRSP2 register |
mbed_official | 146:f64d43ff0c18 | 930 | */ |
mbed_official | 146:f64d43ff0c18 | 931 | //@{ |
mbed_official | 146:f64d43ff0c18 | 932 | #define HW_SDHC_CMDRSP2_ADDR (REGS_SDHC_BASE + 0x18U) |
mbed_official | 146:f64d43ff0c18 | 933 | |
mbed_official | 146:f64d43ff0c18 | 934 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 935 | #define HW_SDHC_CMDRSP2 (*(__I hw_sdhc_cmdrsp2_t *) HW_SDHC_CMDRSP2_ADDR) |
mbed_official | 146:f64d43ff0c18 | 936 | #define HW_SDHC_CMDRSP2_RD() (HW_SDHC_CMDRSP2.U) |
mbed_official | 146:f64d43ff0c18 | 937 | #endif |
mbed_official | 146:f64d43ff0c18 | 938 | //@} |
mbed_official | 146:f64d43ff0c18 | 939 | |
mbed_official | 146:f64d43ff0c18 | 940 | /* |
mbed_official | 146:f64d43ff0c18 | 941 | * Constants & macros for individual SDHC_CMDRSP2 bitfields |
mbed_official | 146:f64d43ff0c18 | 942 | */ |
mbed_official | 146:f64d43ff0c18 | 943 | |
mbed_official | 146:f64d43ff0c18 | 944 | /*! |
mbed_official | 146:f64d43ff0c18 | 945 | * @name Register SDHC_CMDRSP2, field CMDRSP2[31:0] (RO) |
mbed_official | 146:f64d43ff0c18 | 946 | */ |
mbed_official | 146:f64d43ff0c18 | 947 | //@{ |
mbed_official | 146:f64d43ff0c18 | 948 | #define BP_SDHC_CMDRSP2_CMDRSP2 (0U) //!< Bit position for SDHC_CMDRSP2_CMDRSP2. |
mbed_official | 146:f64d43ff0c18 | 949 | #define BM_SDHC_CMDRSP2_CMDRSP2 (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDRSP2_CMDRSP2. |
mbed_official | 146:f64d43ff0c18 | 950 | #define BS_SDHC_CMDRSP2_CMDRSP2 (32U) //!< Bit field size in bits for SDHC_CMDRSP2_CMDRSP2. |
mbed_official | 146:f64d43ff0c18 | 951 | |
mbed_official | 146:f64d43ff0c18 | 952 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 953 | //! @brief Read current value of the SDHC_CMDRSP2_CMDRSP2 field. |
mbed_official | 146:f64d43ff0c18 | 954 | #define BR_SDHC_CMDRSP2_CMDRSP2 (HW_SDHC_CMDRSP2.U) |
mbed_official | 146:f64d43ff0c18 | 955 | #endif |
mbed_official | 146:f64d43ff0c18 | 956 | //@} |
mbed_official | 146:f64d43ff0c18 | 957 | |
mbed_official | 146:f64d43ff0c18 | 958 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 959 | // HW_SDHC_CMDRSP3 - Command Response 3 |
mbed_official | 146:f64d43ff0c18 | 960 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 961 | |
mbed_official | 146:f64d43ff0c18 | 962 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 963 | /*! |
mbed_official | 146:f64d43ff0c18 | 964 | * @brief HW_SDHC_CMDRSP3 - Command Response 3 (RO) |
mbed_official | 146:f64d43ff0c18 | 965 | * |
mbed_official | 146:f64d43ff0c18 | 966 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 967 | * |
mbed_official | 146:f64d43ff0c18 | 968 | * This register is used to store part 3 of the response bits from the card. The |
mbed_official | 146:f64d43ff0c18 | 969 | * following table describes the mapping of command responses from the SD bus to |
mbed_official | 146:f64d43ff0c18 | 970 | * command response registers for each response type. In the table, R[ ] refers |
mbed_official | 146:f64d43ff0c18 | 971 | * to a bit range within the response data as transmitted on the SD bus. Response |
mbed_official | 146:f64d43ff0c18 | 972 | * bit definition for each response type Response type Meaning of response |
mbed_official | 146:f64d43ff0c18 | 973 | * Response field Response register R1,R1b (normal response) Card status R[39:8] |
mbed_official | 146:f64d43ff0c18 | 974 | * CMDRSP0 R1b (Auto CMD12 response) Card status for auto CMD12 R[39:8] CMDRSP3 R2 |
mbed_official | 146:f64d43ff0c18 | 975 | * (CID, CSD register) CID/CSD register [127:8] R[127:8] {CMDRSP3[23:0], CMDRSP2, |
mbed_official | 146:f64d43ff0c18 | 976 | * CMDRSP1, CMDRSP0} R3 (OCR register) OCR register for memory R[39:8] CMDRSP0 R4 |
mbed_official | 146:f64d43ff0c18 | 977 | * (OCR register) OCR register for I/O etc. R[39:8] CMDRSP0 R5, R5b SDIO response |
mbed_official | 146:f64d43ff0c18 | 978 | * R[39:8] CMDRSP0 R6 (Publish RCA) New published RCA[31:16] and card |
mbed_official | 146:f64d43ff0c18 | 979 | * status[15:0] R[39:9] CMDRSP0 This table shows that most responses with a length of 48 |
mbed_official | 146:f64d43ff0c18 | 980 | * (R[47:0]) have 32-bit of the response data (R[39:8]) stored in the CMDRSP0 |
mbed_official | 146:f64d43ff0c18 | 981 | * register. Responses of type R1b (auto CMD12 responses) have response data bits |
mbed_official | 146:f64d43ff0c18 | 982 | * (R[39:8]) stored in the CMDRSP3 register. Responses with length 136 (R[135:0]) have |
mbed_official | 146:f64d43ff0c18 | 983 | * 120-bit of the response data (R[127:8]) stored in the CMDRSP0, 1, 2, and 3 |
mbed_official | 146:f64d43ff0c18 | 984 | * registers. To be able to read the response status efficiently, the SDHC stores |
mbed_official | 146:f64d43ff0c18 | 985 | * only a part of the response data in the command response registers. This |
mbed_official | 146:f64d43ff0c18 | 986 | * enables the host driver to efficiently read 32-bit of response data in one read |
mbed_official | 146:f64d43ff0c18 | 987 | * cycle on a 32-bit bus system. Parts of the response, the index field and the CRC, |
mbed_official | 146:f64d43ff0c18 | 988 | * are checked by the SDHC, as specified by XFERTYP[CICEN] and XFERTYP[CCCEN], |
mbed_official | 146:f64d43ff0c18 | 989 | * and generate an error interrupt if any error is detected. The bit range for the |
mbed_official | 146:f64d43ff0c18 | 990 | * CRC check depends on the response length. If the response length is 48, the |
mbed_official | 146:f64d43ff0c18 | 991 | * SDHC will check R[47:1], and if the response length is 136 the SDHC will check |
mbed_official | 146:f64d43ff0c18 | 992 | * R[119:1]. Because the SDHC may have a multiple block data transfer executing |
mbed_official | 146:f64d43ff0c18 | 993 | * concurrently with a CMD_wo_DAT command, the SDHC stores the auto CMD12 response |
mbed_official | 146:f64d43ff0c18 | 994 | * in the CMDRSP3 register. The CMD_wo_DAT response is stored in CMDRSP0. This |
mbed_official | 146:f64d43ff0c18 | 995 | * allows the SDHC to avoid overwriting the Auto CMD12 response with the CMD_wo_DAT |
mbed_official | 146:f64d43ff0c18 | 996 | * and vice versa. When the SDHC modifies part of the command response |
mbed_official | 146:f64d43ff0c18 | 997 | * registers, as shown in the table above, it preserves the unmodified bits. |
mbed_official | 146:f64d43ff0c18 | 998 | */ |
mbed_official | 146:f64d43ff0c18 | 999 | typedef union _hw_sdhc_cmdrsp3 |
mbed_official | 146:f64d43ff0c18 | 1000 | { |
mbed_official | 146:f64d43ff0c18 | 1001 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 1002 | struct _hw_sdhc_cmdrsp3_bitfields |
mbed_official | 146:f64d43ff0c18 | 1003 | { |
mbed_official | 146:f64d43ff0c18 | 1004 | uint32_t CMDRSP3 : 32; //!< [31:0] Command Response 3 |
mbed_official | 146:f64d43ff0c18 | 1005 | } B; |
mbed_official | 146:f64d43ff0c18 | 1006 | } hw_sdhc_cmdrsp3_t; |
mbed_official | 146:f64d43ff0c18 | 1007 | #endif |
mbed_official | 146:f64d43ff0c18 | 1008 | |
mbed_official | 146:f64d43ff0c18 | 1009 | /*! |
mbed_official | 146:f64d43ff0c18 | 1010 | * @name Constants and macros for entire SDHC_CMDRSP3 register |
mbed_official | 146:f64d43ff0c18 | 1011 | */ |
mbed_official | 146:f64d43ff0c18 | 1012 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1013 | #define HW_SDHC_CMDRSP3_ADDR (REGS_SDHC_BASE + 0x1CU) |
mbed_official | 146:f64d43ff0c18 | 1014 | |
mbed_official | 146:f64d43ff0c18 | 1015 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1016 | #define HW_SDHC_CMDRSP3 (*(__I hw_sdhc_cmdrsp3_t *) HW_SDHC_CMDRSP3_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1017 | #define HW_SDHC_CMDRSP3_RD() (HW_SDHC_CMDRSP3.U) |
mbed_official | 146:f64d43ff0c18 | 1018 | #endif |
mbed_official | 146:f64d43ff0c18 | 1019 | //@} |
mbed_official | 146:f64d43ff0c18 | 1020 | |
mbed_official | 146:f64d43ff0c18 | 1021 | /* |
mbed_official | 146:f64d43ff0c18 | 1022 | * Constants & macros for individual SDHC_CMDRSP3 bitfields |
mbed_official | 146:f64d43ff0c18 | 1023 | */ |
mbed_official | 146:f64d43ff0c18 | 1024 | |
mbed_official | 146:f64d43ff0c18 | 1025 | /*! |
mbed_official | 146:f64d43ff0c18 | 1026 | * @name Register SDHC_CMDRSP3, field CMDRSP3[31:0] (RO) |
mbed_official | 146:f64d43ff0c18 | 1027 | */ |
mbed_official | 146:f64d43ff0c18 | 1028 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1029 | #define BP_SDHC_CMDRSP3_CMDRSP3 (0U) //!< Bit position for SDHC_CMDRSP3_CMDRSP3. |
mbed_official | 146:f64d43ff0c18 | 1030 | #define BM_SDHC_CMDRSP3_CMDRSP3 (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDRSP3_CMDRSP3. |
mbed_official | 146:f64d43ff0c18 | 1031 | #define BS_SDHC_CMDRSP3_CMDRSP3 (32U) //!< Bit field size in bits for SDHC_CMDRSP3_CMDRSP3. |
mbed_official | 146:f64d43ff0c18 | 1032 | |
mbed_official | 146:f64d43ff0c18 | 1033 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1034 | //! @brief Read current value of the SDHC_CMDRSP3_CMDRSP3 field. |
mbed_official | 146:f64d43ff0c18 | 1035 | #define BR_SDHC_CMDRSP3_CMDRSP3 (HW_SDHC_CMDRSP3.U) |
mbed_official | 146:f64d43ff0c18 | 1036 | #endif |
mbed_official | 146:f64d43ff0c18 | 1037 | //@} |
mbed_official | 146:f64d43ff0c18 | 1038 | |
mbed_official | 146:f64d43ff0c18 | 1039 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1040 | // HW_SDHC_DATPORT - Buffer Data Port register |
mbed_official | 146:f64d43ff0c18 | 1041 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1042 | |
mbed_official | 146:f64d43ff0c18 | 1043 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1044 | /*! |
mbed_official | 146:f64d43ff0c18 | 1045 | * @brief HW_SDHC_DATPORT - Buffer Data Port register (RW) |
mbed_official | 146:f64d43ff0c18 | 1046 | * |
mbed_official | 146:f64d43ff0c18 | 1047 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 1048 | * |
mbed_official | 146:f64d43ff0c18 | 1049 | * This is a 32-bit data port register used to access the internal buffer and it |
mbed_official | 146:f64d43ff0c18 | 1050 | * cannot be updated in Idle mode. |
mbed_official | 146:f64d43ff0c18 | 1051 | */ |
mbed_official | 146:f64d43ff0c18 | 1052 | typedef union _hw_sdhc_datport |
mbed_official | 146:f64d43ff0c18 | 1053 | { |
mbed_official | 146:f64d43ff0c18 | 1054 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 1055 | struct _hw_sdhc_datport_bitfields |
mbed_official | 146:f64d43ff0c18 | 1056 | { |
mbed_official | 146:f64d43ff0c18 | 1057 | uint32_t DATCONT : 32; //!< [31:0] Data Content |
mbed_official | 146:f64d43ff0c18 | 1058 | } B; |
mbed_official | 146:f64d43ff0c18 | 1059 | } hw_sdhc_datport_t; |
mbed_official | 146:f64d43ff0c18 | 1060 | #endif |
mbed_official | 146:f64d43ff0c18 | 1061 | |
mbed_official | 146:f64d43ff0c18 | 1062 | /*! |
mbed_official | 146:f64d43ff0c18 | 1063 | * @name Constants and macros for entire SDHC_DATPORT register |
mbed_official | 146:f64d43ff0c18 | 1064 | */ |
mbed_official | 146:f64d43ff0c18 | 1065 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1066 | #define HW_SDHC_DATPORT_ADDR (REGS_SDHC_BASE + 0x20U) |
mbed_official | 146:f64d43ff0c18 | 1067 | |
mbed_official | 146:f64d43ff0c18 | 1068 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1069 | #define HW_SDHC_DATPORT (*(__IO hw_sdhc_datport_t *) HW_SDHC_DATPORT_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1070 | #define HW_SDHC_DATPORT_RD() (HW_SDHC_DATPORT.U) |
mbed_official | 146:f64d43ff0c18 | 1071 | #define HW_SDHC_DATPORT_WR(v) (HW_SDHC_DATPORT.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1072 | #define HW_SDHC_DATPORT_SET(v) (HW_SDHC_DATPORT_WR(HW_SDHC_DATPORT_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1073 | #define HW_SDHC_DATPORT_CLR(v) (HW_SDHC_DATPORT_WR(HW_SDHC_DATPORT_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1074 | #define HW_SDHC_DATPORT_TOG(v) (HW_SDHC_DATPORT_WR(HW_SDHC_DATPORT_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1075 | #endif |
mbed_official | 146:f64d43ff0c18 | 1076 | //@} |
mbed_official | 146:f64d43ff0c18 | 1077 | |
mbed_official | 146:f64d43ff0c18 | 1078 | /* |
mbed_official | 146:f64d43ff0c18 | 1079 | * Constants & macros for individual SDHC_DATPORT bitfields |
mbed_official | 146:f64d43ff0c18 | 1080 | */ |
mbed_official | 146:f64d43ff0c18 | 1081 | |
mbed_official | 146:f64d43ff0c18 | 1082 | /*! |
mbed_official | 146:f64d43ff0c18 | 1083 | * @name Register SDHC_DATPORT, field DATCONT[31:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1084 | * |
mbed_official | 146:f64d43ff0c18 | 1085 | * The Buffer Data Port register is for 32-bit data access by the CPU or the |
mbed_official | 146:f64d43ff0c18 | 1086 | * external DMA. When the internal DMA is enabled, any write to this register is |
mbed_official | 146:f64d43ff0c18 | 1087 | * ignored, and any read from this register will always yield 0s. |
mbed_official | 146:f64d43ff0c18 | 1088 | */ |
mbed_official | 146:f64d43ff0c18 | 1089 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1090 | #define BP_SDHC_DATPORT_DATCONT (0U) //!< Bit position for SDHC_DATPORT_DATCONT. |
mbed_official | 146:f64d43ff0c18 | 1091 | #define BM_SDHC_DATPORT_DATCONT (0xFFFFFFFFU) //!< Bit mask for SDHC_DATPORT_DATCONT. |
mbed_official | 146:f64d43ff0c18 | 1092 | #define BS_SDHC_DATPORT_DATCONT (32U) //!< Bit field size in bits for SDHC_DATPORT_DATCONT. |
mbed_official | 146:f64d43ff0c18 | 1093 | |
mbed_official | 146:f64d43ff0c18 | 1094 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1095 | //! @brief Read current value of the SDHC_DATPORT_DATCONT field. |
mbed_official | 146:f64d43ff0c18 | 1096 | #define BR_SDHC_DATPORT_DATCONT (HW_SDHC_DATPORT.U) |
mbed_official | 146:f64d43ff0c18 | 1097 | #endif |
mbed_official | 146:f64d43ff0c18 | 1098 | |
mbed_official | 146:f64d43ff0c18 | 1099 | //! @brief Format value for bitfield SDHC_DATPORT_DATCONT. |
mbed_official | 146:f64d43ff0c18 | 1100 | #define BF_SDHC_DATPORT_DATCONT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_DATPORT_DATCONT), uint32_t) & BM_SDHC_DATPORT_DATCONT) |
mbed_official | 146:f64d43ff0c18 | 1101 | |
mbed_official | 146:f64d43ff0c18 | 1102 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1103 | //! @brief Set the DATCONT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1104 | #define BW_SDHC_DATPORT_DATCONT(v) (HW_SDHC_DATPORT_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 1105 | #endif |
mbed_official | 146:f64d43ff0c18 | 1106 | //@} |
mbed_official | 146:f64d43ff0c18 | 1107 | |
mbed_official | 146:f64d43ff0c18 | 1108 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1109 | // HW_SDHC_PRSSTAT - Present State register |
mbed_official | 146:f64d43ff0c18 | 1110 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1111 | |
mbed_official | 146:f64d43ff0c18 | 1112 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1113 | /*! |
mbed_official | 146:f64d43ff0c18 | 1114 | * @brief HW_SDHC_PRSSTAT - Present State register (RO) |
mbed_official | 146:f64d43ff0c18 | 1115 | * |
mbed_official | 146:f64d43ff0c18 | 1116 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 1117 | * |
mbed_official | 146:f64d43ff0c18 | 1118 | * The host driver can get status of the SDHC from this 32-bit read-only |
mbed_official | 146:f64d43ff0c18 | 1119 | * register. The host driver can issue CMD0, CMD12, CMD13 (for memory) and CMD52 (for |
mbed_official | 146:f64d43ff0c18 | 1120 | * SDIO) when the DAT lines are busy during a data transfer. These commands can be |
mbed_official | 146:f64d43ff0c18 | 1121 | * issued when Command Inhibit (CIHB) is set to zero. Other commands shall be |
mbed_official | 146:f64d43ff0c18 | 1122 | * issued when Command Inhibit (CDIHB) is set to zero. Possible changes to the SD |
mbed_official | 146:f64d43ff0c18 | 1123 | * Physical Specification may add other commands to this list in the future. |
mbed_official | 146:f64d43ff0c18 | 1124 | */ |
mbed_official | 146:f64d43ff0c18 | 1125 | typedef union _hw_sdhc_prsstat |
mbed_official | 146:f64d43ff0c18 | 1126 | { |
mbed_official | 146:f64d43ff0c18 | 1127 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 1128 | struct _hw_sdhc_prsstat_bitfields |
mbed_official | 146:f64d43ff0c18 | 1129 | { |
mbed_official | 146:f64d43ff0c18 | 1130 | uint32_t CIHB : 1; //!< [0] Command Inhibit (CMD) |
mbed_official | 146:f64d43ff0c18 | 1131 | uint32_t CDIHB : 1; //!< [1] Command Inhibit (DAT) |
mbed_official | 146:f64d43ff0c18 | 1132 | uint32_t DLA : 1; //!< [2] Data Line Active |
mbed_official | 146:f64d43ff0c18 | 1133 | uint32_t SDSTB : 1; //!< [3] SD Clock Stable |
mbed_official | 146:f64d43ff0c18 | 1134 | uint32_t IPGOFF : 1; //!< [4] Bus Clock Gated Off Internally |
mbed_official | 146:f64d43ff0c18 | 1135 | uint32_t HCKOFF : 1; //!< [5] System Clock Gated Off Internally |
mbed_official | 146:f64d43ff0c18 | 1136 | uint32_t PEROFF : 1; //!< [6] SDHC clock Gated Off Internally |
mbed_official | 146:f64d43ff0c18 | 1137 | uint32_t SDOFF : 1; //!< [7] SD Clock Gated Off Internally |
mbed_official | 146:f64d43ff0c18 | 1138 | uint32_t WTA : 1; //!< [8] Write Transfer Active |
mbed_official | 146:f64d43ff0c18 | 1139 | uint32_t RTA : 1; //!< [9] Read Transfer Active |
mbed_official | 146:f64d43ff0c18 | 1140 | uint32_t BWEN : 1; //!< [10] Buffer Write Enable |
mbed_official | 146:f64d43ff0c18 | 1141 | uint32_t BREN : 1; //!< [11] Buffer Read Enable |
mbed_official | 146:f64d43ff0c18 | 1142 | uint32_t RESERVED0 : 4; //!< [15:12] |
mbed_official | 146:f64d43ff0c18 | 1143 | uint32_t CINS : 1; //!< [16] Card Inserted |
mbed_official | 146:f64d43ff0c18 | 1144 | uint32_t RESERVED1 : 6; //!< [22:17] |
mbed_official | 146:f64d43ff0c18 | 1145 | uint32_t CLSL : 1; //!< [23] CMD Line Signal Level |
mbed_official | 146:f64d43ff0c18 | 1146 | uint32_t DLSL : 8; //!< [31:24] DAT Line Signal Level |
mbed_official | 146:f64d43ff0c18 | 1147 | } B; |
mbed_official | 146:f64d43ff0c18 | 1148 | } hw_sdhc_prsstat_t; |
mbed_official | 146:f64d43ff0c18 | 1149 | #endif |
mbed_official | 146:f64d43ff0c18 | 1150 | |
mbed_official | 146:f64d43ff0c18 | 1151 | /*! |
mbed_official | 146:f64d43ff0c18 | 1152 | * @name Constants and macros for entire SDHC_PRSSTAT register |
mbed_official | 146:f64d43ff0c18 | 1153 | */ |
mbed_official | 146:f64d43ff0c18 | 1154 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1155 | #define HW_SDHC_PRSSTAT_ADDR (REGS_SDHC_BASE + 0x24U) |
mbed_official | 146:f64d43ff0c18 | 1156 | |
mbed_official | 146:f64d43ff0c18 | 1157 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1158 | #define HW_SDHC_PRSSTAT (*(__I hw_sdhc_prsstat_t *) HW_SDHC_PRSSTAT_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1159 | #define HW_SDHC_PRSSTAT_RD() (HW_SDHC_PRSSTAT.U) |
mbed_official | 146:f64d43ff0c18 | 1160 | #endif |
mbed_official | 146:f64d43ff0c18 | 1161 | //@} |
mbed_official | 146:f64d43ff0c18 | 1162 | |
mbed_official | 146:f64d43ff0c18 | 1163 | /* |
mbed_official | 146:f64d43ff0c18 | 1164 | * Constants & macros for individual SDHC_PRSSTAT bitfields |
mbed_official | 146:f64d43ff0c18 | 1165 | */ |
mbed_official | 146:f64d43ff0c18 | 1166 | |
mbed_official | 146:f64d43ff0c18 | 1167 | /*! |
mbed_official | 146:f64d43ff0c18 | 1168 | * @name Register SDHC_PRSSTAT, field CIHB[0] (RO) |
mbed_official | 146:f64d43ff0c18 | 1169 | * |
mbed_official | 146:f64d43ff0c18 | 1170 | * If this status bit is 0, it indicates that the CMD line is not in use and the |
mbed_official | 146:f64d43ff0c18 | 1171 | * SDHC can issue a SD/MMC Command using the CMD line. This bit is set also |
mbed_official | 146:f64d43ff0c18 | 1172 | * immediately after the Transfer Type register is written. This bit is cleared when |
mbed_official | 146:f64d43ff0c18 | 1173 | * the command response is received. Even if the CDIHB bit is set to 1, Commands |
mbed_official | 146:f64d43ff0c18 | 1174 | * using only the CMD line can be issued if this bit is 0. Changing from 1 to 0 |
mbed_official | 146:f64d43ff0c18 | 1175 | * generates a command complete interrupt in the interrupt status register. If the |
mbed_official | 146:f64d43ff0c18 | 1176 | * SDHC cannot issue the command because of a command conflict error (see |
mbed_official | 146:f64d43ff0c18 | 1177 | * command CRC error) or because of a command not issued by auto CMD12 error, this bit |
mbed_official | 146:f64d43ff0c18 | 1178 | * will remain 1 and the command complete is not set. The status of issuing an |
mbed_official | 146:f64d43ff0c18 | 1179 | * auto CMD12 does not show on this bit. |
mbed_official | 146:f64d43ff0c18 | 1180 | * |
mbed_official | 146:f64d43ff0c18 | 1181 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1182 | * - 0 - Can issue command using only CMD line. |
mbed_official | 146:f64d43ff0c18 | 1183 | * - 1 - Cannot issue command. |
mbed_official | 146:f64d43ff0c18 | 1184 | */ |
mbed_official | 146:f64d43ff0c18 | 1185 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1186 | #define BP_SDHC_PRSSTAT_CIHB (0U) //!< Bit position for SDHC_PRSSTAT_CIHB. |
mbed_official | 146:f64d43ff0c18 | 1187 | #define BM_SDHC_PRSSTAT_CIHB (0x00000001U) //!< Bit mask for SDHC_PRSSTAT_CIHB. |
mbed_official | 146:f64d43ff0c18 | 1188 | #define BS_SDHC_PRSSTAT_CIHB (1U) //!< Bit field size in bits for SDHC_PRSSTAT_CIHB. |
mbed_official | 146:f64d43ff0c18 | 1189 | |
mbed_official | 146:f64d43ff0c18 | 1190 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1191 | //! @brief Read current value of the SDHC_PRSSTAT_CIHB field. |
mbed_official | 146:f64d43ff0c18 | 1192 | #define BR_SDHC_PRSSTAT_CIHB (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_CIHB)) |
mbed_official | 146:f64d43ff0c18 | 1193 | #endif |
mbed_official | 146:f64d43ff0c18 | 1194 | //@} |
mbed_official | 146:f64d43ff0c18 | 1195 | |
mbed_official | 146:f64d43ff0c18 | 1196 | /*! |
mbed_official | 146:f64d43ff0c18 | 1197 | * @name Register SDHC_PRSSTAT, field CDIHB[1] (RO) |
mbed_official | 146:f64d43ff0c18 | 1198 | * |
mbed_official | 146:f64d43ff0c18 | 1199 | * This status bit is generated if either the DLA or the RTA is set to 1. If |
mbed_official | 146:f64d43ff0c18 | 1200 | * this bit is 0, it indicates that the SDHC can issue the next SD/MMC Command. |
mbed_official | 146:f64d43ff0c18 | 1201 | * Commands with a busy signal belong to CDIHB, for example, R1b, R5b type. Except in |
mbed_official | 146:f64d43ff0c18 | 1202 | * the case when the command busy is finished, changing from 1 to 0 generates a |
mbed_official | 146:f64d43ff0c18 | 1203 | * transfer complete interrupt in the Interrupt Status register. The SD host |
mbed_official | 146:f64d43ff0c18 | 1204 | * driver can save registers for a suspend transaction after this bit has changed |
mbed_official | 146:f64d43ff0c18 | 1205 | * from 1 to 0. |
mbed_official | 146:f64d43ff0c18 | 1206 | * |
mbed_official | 146:f64d43ff0c18 | 1207 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1208 | * - 0 - Can issue command which uses the DAT line. |
mbed_official | 146:f64d43ff0c18 | 1209 | * - 1 - Cannot issue command which uses the DAT line. |
mbed_official | 146:f64d43ff0c18 | 1210 | */ |
mbed_official | 146:f64d43ff0c18 | 1211 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1212 | #define BP_SDHC_PRSSTAT_CDIHB (1U) //!< Bit position for SDHC_PRSSTAT_CDIHB. |
mbed_official | 146:f64d43ff0c18 | 1213 | #define BM_SDHC_PRSSTAT_CDIHB (0x00000002U) //!< Bit mask for SDHC_PRSSTAT_CDIHB. |
mbed_official | 146:f64d43ff0c18 | 1214 | #define BS_SDHC_PRSSTAT_CDIHB (1U) //!< Bit field size in bits for SDHC_PRSSTAT_CDIHB. |
mbed_official | 146:f64d43ff0c18 | 1215 | |
mbed_official | 146:f64d43ff0c18 | 1216 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1217 | //! @brief Read current value of the SDHC_PRSSTAT_CDIHB field. |
mbed_official | 146:f64d43ff0c18 | 1218 | #define BR_SDHC_PRSSTAT_CDIHB (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_CDIHB)) |
mbed_official | 146:f64d43ff0c18 | 1219 | #endif |
mbed_official | 146:f64d43ff0c18 | 1220 | //@} |
mbed_official | 146:f64d43ff0c18 | 1221 | |
mbed_official | 146:f64d43ff0c18 | 1222 | /*! |
mbed_official | 146:f64d43ff0c18 | 1223 | * @name Register SDHC_PRSSTAT, field DLA[2] (RO) |
mbed_official | 146:f64d43ff0c18 | 1224 | * |
mbed_official | 146:f64d43ff0c18 | 1225 | * Indicates whether one of the DAT lines on the SD bus is in use. In the case |
mbed_official | 146:f64d43ff0c18 | 1226 | * of read transactions: This status indicates whether a read transfer is |
mbed_official | 146:f64d43ff0c18 | 1227 | * executing on the SD bus. Changes in this value from 1 to 0, between data blocks, |
mbed_official | 146:f64d43ff0c18 | 1228 | * generates a block gap event interrupt in the Interrupt Status register. This bit |
mbed_official | 146:f64d43ff0c18 | 1229 | * will be set in either of the following cases: After the end bit of the read |
mbed_official | 146:f64d43ff0c18 | 1230 | * command. When writing a 1 to PROCTL[CREQ] to restart a read transfer. This bit |
mbed_official | 146:f64d43ff0c18 | 1231 | * will be cleared in either of the following cases: When the end bit of the last |
mbed_official | 146:f64d43ff0c18 | 1232 | * data block is sent from the SD bus to the SDHC. When the read wait state is |
mbed_official | 146:f64d43ff0c18 | 1233 | * stopped by a suspend command and the DAT2 line is released. The SDHC will wait at |
mbed_official | 146:f64d43ff0c18 | 1234 | * the next block gap by driving read wait at the start of the interrupt cycle. |
mbed_official | 146:f64d43ff0c18 | 1235 | * If the read wait signal is already driven (data buffer cannot receive data), |
mbed_official | 146:f64d43ff0c18 | 1236 | * the SDHC can wait for a current block gap by continuing to drive the read wait |
mbed_official | 146:f64d43ff0c18 | 1237 | * signal. It is necessary to support read wait to use the suspend / resume |
mbed_official | 146:f64d43ff0c18 | 1238 | * function. This bit will remain 1 during read wait. In the case of write |
mbed_official | 146:f64d43ff0c18 | 1239 | * transactions: This status indicates that a write transfer is executing on the SD bus. |
mbed_official | 146:f64d43ff0c18 | 1240 | * Changes in this value from 1 to 0 generate a transfer complete interrupt in the |
mbed_official | 146:f64d43ff0c18 | 1241 | * interrupt status register. This bit will be set in either of the following |
mbed_official | 146:f64d43ff0c18 | 1242 | * cases: After the end bit of the write command. When writing to 1 to PROCTL[CREQ] to |
mbed_official | 146:f64d43ff0c18 | 1243 | * continue a write transfer. This bit will be cleared in either of the |
mbed_official | 146:f64d43ff0c18 | 1244 | * following cases: When the SD card releases write busy of the last data block, the SDHC |
mbed_official | 146:f64d43ff0c18 | 1245 | * will also detect if the output is not busy. If the SD card does not drive the |
mbed_official | 146:f64d43ff0c18 | 1246 | * busy signal after the CRC status is received, the SDHC shall assume the card |
mbed_official | 146:f64d43ff0c18 | 1247 | * drive "Not busy". When the SD card releases write busy, prior to waiting for |
mbed_official | 146:f64d43ff0c18 | 1248 | * write transfer, and as a result of a stop at block gap request. In the case of |
mbed_official | 146:f64d43ff0c18 | 1249 | * command with busy pending: This status indicates that a busy state follows the |
mbed_official | 146:f64d43ff0c18 | 1250 | * command and the data line is in use. This bit will be cleared when the DAT0 |
mbed_official | 146:f64d43ff0c18 | 1251 | * line is released. |
mbed_official | 146:f64d43ff0c18 | 1252 | * |
mbed_official | 146:f64d43ff0c18 | 1253 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1254 | * - 0 - DAT line inactive. |
mbed_official | 146:f64d43ff0c18 | 1255 | * - 1 - DAT line active. |
mbed_official | 146:f64d43ff0c18 | 1256 | */ |
mbed_official | 146:f64d43ff0c18 | 1257 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1258 | #define BP_SDHC_PRSSTAT_DLA (2U) //!< Bit position for SDHC_PRSSTAT_DLA. |
mbed_official | 146:f64d43ff0c18 | 1259 | #define BM_SDHC_PRSSTAT_DLA (0x00000004U) //!< Bit mask for SDHC_PRSSTAT_DLA. |
mbed_official | 146:f64d43ff0c18 | 1260 | #define BS_SDHC_PRSSTAT_DLA (1U) //!< Bit field size in bits for SDHC_PRSSTAT_DLA. |
mbed_official | 146:f64d43ff0c18 | 1261 | |
mbed_official | 146:f64d43ff0c18 | 1262 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1263 | //! @brief Read current value of the SDHC_PRSSTAT_DLA field. |
mbed_official | 146:f64d43ff0c18 | 1264 | #define BR_SDHC_PRSSTAT_DLA (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_DLA)) |
mbed_official | 146:f64d43ff0c18 | 1265 | #endif |
mbed_official | 146:f64d43ff0c18 | 1266 | //@} |
mbed_official | 146:f64d43ff0c18 | 1267 | |
mbed_official | 146:f64d43ff0c18 | 1268 | /*! |
mbed_official | 146:f64d43ff0c18 | 1269 | * @name Register SDHC_PRSSTAT, field SDSTB[3] (RO) |
mbed_official | 146:f64d43ff0c18 | 1270 | * |
mbed_official | 146:f64d43ff0c18 | 1271 | * Indicates that the internal card clock is stable. This bit is for the host |
mbed_official | 146:f64d43ff0c18 | 1272 | * driver to poll clock status when changing the clock frequency. It is recommended |
mbed_official | 146:f64d43ff0c18 | 1273 | * to clear SYSCTL[SDCLKEN] to remove glitch on the card clock when the |
mbed_official | 146:f64d43ff0c18 | 1274 | * frequency is changing. |
mbed_official | 146:f64d43ff0c18 | 1275 | * |
mbed_official | 146:f64d43ff0c18 | 1276 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1277 | * - 0 - Clock is changing frequency and not stable. |
mbed_official | 146:f64d43ff0c18 | 1278 | * - 1 - Clock is stable. |
mbed_official | 146:f64d43ff0c18 | 1279 | */ |
mbed_official | 146:f64d43ff0c18 | 1280 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1281 | #define BP_SDHC_PRSSTAT_SDSTB (3U) //!< Bit position for SDHC_PRSSTAT_SDSTB. |
mbed_official | 146:f64d43ff0c18 | 1282 | #define BM_SDHC_PRSSTAT_SDSTB (0x00000008U) //!< Bit mask for SDHC_PRSSTAT_SDSTB. |
mbed_official | 146:f64d43ff0c18 | 1283 | #define BS_SDHC_PRSSTAT_SDSTB (1U) //!< Bit field size in bits for SDHC_PRSSTAT_SDSTB. |
mbed_official | 146:f64d43ff0c18 | 1284 | |
mbed_official | 146:f64d43ff0c18 | 1285 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1286 | //! @brief Read current value of the SDHC_PRSSTAT_SDSTB field. |
mbed_official | 146:f64d43ff0c18 | 1287 | #define BR_SDHC_PRSSTAT_SDSTB (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_SDSTB)) |
mbed_official | 146:f64d43ff0c18 | 1288 | #endif |
mbed_official | 146:f64d43ff0c18 | 1289 | //@} |
mbed_official | 146:f64d43ff0c18 | 1290 | |
mbed_official | 146:f64d43ff0c18 | 1291 | /*! |
mbed_official | 146:f64d43ff0c18 | 1292 | * @name Register SDHC_PRSSTAT, field IPGOFF[4] (RO) |
mbed_official | 146:f64d43ff0c18 | 1293 | * |
mbed_official | 146:f64d43ff0c18 | 1294 | * Indicates that the bus clock is internally gated off. This bit is for the |
mbed_official | 146:f64d43ff0c18 | 1295 | * host driver to debug. |
mbed_official | 146:f64d43ff0c18 | 1296 | * |
mbed_official | 146:f64d43ff0c18 | 1297 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1298 | * - 0 - Bus clock is active. |
mbed_official | 146:f64d43ff0c18 | 1299 | * - 1 - Bus clock is gated off. |
mbed_official | 146:f64d43ff0c18 | 1300 | */ |
mbed_official | 146:f64d43ff0c18 | 1301 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1302 | #define BP_SDHC_PRSSTAT_IPGOFF (4U) //!< Bit position for SDHC_PRSSTAT_IPGOFF. |
mbed_official | 146:f64d43ff0c18 | 1303 | #define BM_SDHC_PRSSTAT_IPGOFF (0x00000010U) //!< Bit mask for SDHC_PRSSTAT_IPGOFF. |
mbed_official | 146:f64d43ff0c18 | 1304 | #define BS_SDHC_PRSSTAT_IPGOFF (1U) //!< Bit field size in bits for SDHC_PRSSTAT_IPGOFF. |
mbed_official | 146:f64d43ff0c18 | 1305 | |
mbed_official | 146:f64d43ff0c18 | 1306 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1307 | //! @brief Read current value of the SDHC_PRSSTAT_IPGOFF field. |
mbed_official | 146:f64d43ff0c18 | 1308 | #define BR_SDHC_PRSSTAT_IPGOFF (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_IPGOFF)) |
mbed_official | 146:f64d43ff0c18 | 1309 | #endif |
mbed_official | 146:f64d43ff0c18 | 1310 | //@} |
mbed_official | 146:f64d43ff0c18 | 1311 | |
mbed_official | 146:f64d43ff0c18 | 1312 | /*! |
mbed_official | 146:f64d43ff0c18 | 1313 | * @name Register SDHC_PRSSTAT, field HCKOFF[5] (RO) |
mbed_official | 146:f64d43ff0c18 | 1314 | * |
mbed_official | 146:f64d43ff0c18 | 1315 | * Indicates that the system clock is internally gated off. This bit is for the |
mbed_official | 146:f64d43ff0c18 | 1316 | * host driver to debug during a data transfer. |
mbed_official | 146:f64d43ff0c18 | 1317 | * |
mbed_official | 146:f64d43ff0c18 | 1318 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1319 | * - 0 - System clock is active. |
mbed_official | 146:f64d43ff0c18 | 1320 | * - 1 - System clock is gated off. |
mbed_official | 146:f64d43ff0c18 | 1321 | */ |
mbed_official | 146:f64d43ff0c18 | 1322 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1323 | #define BP_SDHC_PRSSTAT_HCKOFF (5U) //!< Bit position for SDHC_PRSSTAT_HCKOFF. |
mbed_official | 146:f64d43ff0c18 | 1324 | #define BM_SDHC_PRSSTAT_HCKOFF (0x00000020U) //!< Bit mask for SDHC_PRSSTAT_HCKOFF. |
mbed_official | 146:f64d43ff0c18 | 1325 | #define BS_SDHC_PRSSTAT_HCKOFF (1U) //!< Bit field size in bits for SDHC_PRSSTAT_HCKOFF. |
mbed_official | 146:f64d43ff0c18 | 1326 | |
mbed_official | 146:f64d43ff0c18 | 1327 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1328 | //! @brief Read current value of the SDHC_PRSSTAT_HCKOFF field. |
mbed_official | 146:f64d43ff0c18 | 1329 | #define BR_SDHC_PRSSTAT_HCKOFF (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_HCKOFF)) |
mbed_official | 146:f64d43ff0c18 | 1330 | #endif |
mbed_official | 146:f64d43ff0c18 | 1331 | //@} |
mbed_official | 146:f64d43ff0c18 | 1332 | |
mbed_official | 146:f64d43ff0c18 | 1333 | /*! |
mbed_official | 146:f64d43ff0c18 | 1334 | * @name Register SDHC_PRSSTAT, field PEROFF[6] (RO) |
mbed_official | 146:f64d43ff0c18 | 1335 | * |
mbed_official | 146:f64d43ff0c18 | 1336 | * Indicates that the is internally gated off. This bit is for the host driver |
mbed_official | 146:f64d43ff0c18 | 1337 | * to debug transaction on the SD bus. When INITA bit is set, SDHC sending 80 |
mbed_official | 146:f64d43ff0c18 | 1338 | * clock cycles to the card, SDCLKEN must be 1 to enable the output card clock, |
mbed_official | 146:f64d43ff0c18 | 1339 | * otherwise the will never be gate off, so and will be always active. SDHC clock SDHC |
mbed_official | 146:f64d43ff0c18 | 1340 | * clock SDHC clock bus clock |
mbed_official | 146:f64d43ff0c18 | 1341 | * |
mbed_official | 146:f64d43ff0c18 | 1342 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1343 | * - 0 - SDHC clock is active. |
mbed_official | 146:f64d43ff0c18 | 1344 | * - 1 - SDHC clock is gated off. |
mbed_official | 146:f64d43ff0c18 | 1345 | */ |
mbed_official | 146:f64d43ff0c18 | 1346 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1347 | #define BP_SDHC_PRSSTAT_PEROFF (6U) //!< Bit position for SDHC_PRSSTAT_PEROFF. |
mbed_official | 146:f64d43ff0c18 | 1348 | #define BM_SDHC_PRSSTAT_PEROFF (0x00000040U) //!< Bit mask for SDHC_PRSSTAT_PEROFF. |
mbed_official | 146:f64d43ff0c18 | 1349 | #define BS_SDHC_PRSSTAT_PEROFF (1U) //!< Bit field size in bits for SDHC_PRSSTAT_PEROFF. |
mbed_official | 146:f64d43ff0c18 | 1350 | |
mbed_official | 146:f64d43ff0c18 | 1351 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1352 | //! @brief Read current value of the SDHC_PRSSTAT_PEROFF field. |
mbed_official | 146:f64d43ff0c18 | 1353 | #define BR_SDHC_PRSSTAT_PEROFF (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_PEROFF)) |
mbed_official | 146:f64d43ff0c18 | 1354 | #endif |
mbed_official | 146:f64d43ff0c18 | 1355 | //@} |
mbed_official | 146:f64d43ff0c18 | 1356 | |
mbed_official | 146:f64d43ff0c18 | 1357 | /*! |
mbed_official | 146:f64d43ff0c18 | 1358 | * @name Register SDHC_PRSSTAT, field SDOFF[7] (RO) |
mbed_official | 146:f64d43ff0c18 | 1359 | * |
mbed_official | 146:f64d43ff0c18 | 1360 | * Indicates that the SD clock is internally gated off, because of buffer |
mbed_official | 146:f64d43ff0c18 | 1361 | * over/under-run or read pause without read wait assertion, or the driver has cleared |
mbed_official | 146:f64d43ff0c18 | 1362 | * SYSCTL[SDCLKEN] to stop the SD clock. This bit is for the host driver to debug |
mbed_official | 146:f64d43ff0c18 | 1363 | * data transaction on the SD bus. |
mbed_official | 146:f64d43ff0c18 | 1364 | * |
mbed_official | 146:f64d43ff0c18 | 1365 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1366 | * - 0 - SD clock is active. |
mbed_official | 146:f64d43ff0c18 | 1367 | * - 1 - SD clock is gated off. |
mbed_official | 146:f64d43ff0c18 | 1368 | */ |
mbed_official | 146:f64d43ff0c18 | 1369 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1370 | #define BP_SDHC_PRSSTAT_SDOFF (7U) //!< Bit position for SDHC_PRSSTAT_SDOFF. |
mbed_official | 146:f64d43ff0c18 | 1371 | #define BM_SDHC_PRSSTAT_SDOFF (0x00000080U) //!< Bit mask for SDHC_PRSSTAT_SDOFF. |
mbed_official | 146:f64d43ff0c18 | 1372 | #define BS_SDHC_PRSSTAT_SDOFF (1U) //!< Bit field size in bits for SDHC_PRSSTAT_SDOFF. |
mbed_official | 146:f64d43ff0c18 | 1373 | |
mbed_official | 146:f64d43ff0c18 | 1374 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1375 | //! @brief Read current value of the SDHC_PRSSTAT_SDOFF field. |
mbed_official | 146:f64d43ff0c18 | 1376 | #define BR_SDHC_PRSSTAT_SDOFF (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_SDOFF)) |
mbed_official | 146:f64d43ff0c18 | 1377 | #endif |
mbed_official | 146:f64d43ff0c18 | 1378 | //@} |
mbed_official | 146:f64d43ff0c18 | 1379 | |
mbed_official | 146:f64d43ff0c18 | 1380 | /*! |
mbed_official | 146:f64d43ff0c18 | 1381 | * @name Register SDHC_PRSSTAT, field WTA[8] (RO) |
mbed_official | 146:f64d43ff0c18 | 1382 | * |
mbed_official | 146:f64d43ff0c18 | 1383 | * Indicates that a write transfer is active. If this bit is 0, it means no |
mbed_official | 146:f64d43ff0c18 | 1384 | * valid write data exists in the SDHC. This bit is set in either of the following |
mbed_official | 146:f64d43ff0c18 | 1385 | * cases: After the end bit of the write command. When writing 1 to PROCTL[CREQ] to |
mbed_official | 146:f64d43ff0c18 | 1386 | * restart a write transfer. This bit is cleared in either of the following |
mbed_official | 146:f64d43ff0c18 | 1387 | * cases: After getting the CRC status of the last data block as specified by the |
mbed_official | 146:f64d43ff0c18 | 1388 | * transfer count (single and multiple). After getting the CRC status of any block |
mbed_official | 146:f64d43ff0c18 | 1389 | * where data transmission is about to be stopped by a stop at block gap request. |
mbed_official | 146:f64d43ff0c18 | 1390 | * During a write transaction, a block gap event interrupt is generated when this |
mbed_official | 146:f64d43ff0c18 | 1391 | * bit is changed to 0, as result of the stop at block gap request being set. |
mbed_official | 146:f64d43ff0c18 | 1392 | * This status is useful for the host driver in determining when to issue commands |
mbed_official | 146:f64d43ff0c18 | 1393 | * during write busy state. |
mbed_official | 146:f64d43ff0c18 | 1394 | * |
mbed_official | 146:f64d43ff0c18 | 1395 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1396 | * - 0 - No valid data. |
mbed_official | 146:f64d43ff0c18 | 1397 | * - 1 - Transferring data. |
mbed_official | 146:f64d43ff0c18 | 1398 | */ |
mbed_official | 146:f64d43ff0c18 | 1399 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1400 | #define BP_SDHC_PRSSTAT_WTA (8U) //!< Bit position for SDHC_PRSSTAT_WTA. |
mbed_official | 146:f64d43ff0c18 | 1401 | #define BM_SDHC_PRSSTAT_WTA (0x00000100U) //!< Bit mask for SDHC_PRSSTAT_WTA. |
mbed_official | 146:f64d43ff0c18 | 1402 | #define BS_SDHC_PRSSTAT_WTA (1U) //!< Bit field size in bits for SDHC_PRSSTAT_WTA. |
mbed_official | 146:f64d43ff0c18 | 1403 | |
mbed_official | 146:f64d43ff0c18 | 1404 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1405 | //! @brief Read current value of the SDHC_PRSSTAT_WTA field. |
mbed_official | 146:f64d43ff0c18 | 1406 | #define BR_SDHC_PRSSTAT_WTA (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_WTA)) |
mbed_official | 146:f64d43ff0c18 | 1407 | #endif |
mbed_official | 146:f64d43ff0c18 | 1408 | //@} |
mbed_official | 146:f64d43ff0c18 | 1409 | |
mbed_official | 146:f64d43ff0c18 | 1410 | /*! |
mbed_official | 146:f64d43ff0c18 | 1411 | * @name Register SDHC_PRSSTAT, field RTA[9] (RO) |
mbed_official | 146:f64d43ff0c18 | 1412 | * |
mbed_official | 146:f64d43ff0c18 | 1413 | * Used for detecting completion of a read transfer. This bit is set for either |
mbed_official | 146:f64d43ff0c18 | 1414 | * of the following conditions: After the end bit of the read command. When |
mbed_official | 146:f64d43ff0c18 | 1415 | * writing a 1 to PROCTL[CREQ] to restart a read transfer. A transfer complete |
mbed_official | 146:f64d43ff0c18 | 1416 | * interrupt is generated when this bit changes to 0. This bit is cleared for either of |
mbed_official | 146:f64d43ff0c18 | 1417 | * the following conditions: When the last data block as specified by block |
mbed_official | 146:f64d43ff0c18 | 1418 | * length is transferred to the system, that is, all data are read away from SDHC |
mbed_official | 146:f64d43ff0c18 | 1419 | * internal buffer. When all valid data blocks have been transferred from SDHC |
mbed_official | 146:f64d43ff0c18 | 1420 | * internal buffer to the system and no current block transfers are being sent as a |
mbed_official | 146:f64d43ff0c18 | 1421 | * result of the stop at block gap request being set to 1. |
mbed_official | 146:f64d43ff0c18 | 1422 | * |
mbed_official | 146:f64d43ff0c18 | 1423 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1424 | * - 0 - No valid data. |
mbed_official | 146:f64d43ff0c18 | 1425 | * - 1 - Transferring data. |
mbed_official | 146:f64d43ff0c18 | 1426 | */ |
mbed_official | 146:f64d43ff0c18 | 1427 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1428 | #define BP_SDHC_PRSSTAT_RTA (9U) //!< Bit position for SDHC_PRSSTAT_RTA. |
mbed_official | 146:f64d43ff0c18 | 1429 | #define BM_SDHC_PRSSTAT_RTA (0x00000200U) //!< Bit mask for SDHC_PRSSTAT_RTA. |
mbed_official | 146:f64d43ff0c18 | 1430 | #define BS_SDHC_PRSSTAT_RTA (1U) //!< Bit field size in bits for SDHC_PRSSTAT_RTA. |
mbed_official | 146:f64d43ff0c18 | 1431 | |
mbed_official | 146:f64d43ff0c18 | 1432 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1433 | //! @brief Read current value of the SDHC_PRSSTAT_RTA field. |
mbed_official | 146:f64d43ff0c18 | 1434 | #define BR_SDHC_PRSSTAT_RTA (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_RTA)) |
mbed_official | 146:f64d43ff0c18 | 1435 | #endif |
mbed_official | 146:f64d43ff0c18 | 1436 | //@} |
mbed_official | 146:f64d43ff0c18 | 1437 | |
mbed_official | 146:f64d43ff0c18 | 1438 | /*! |
mbed_official | 146:f64d43ff0c18 | 1439 | * @name Register SDHC_PRSSTAT, field BWEN[10] (RO) |
mbed_official | 146:f64d43ff0c18 | 1440 | * |
mbed_official | 146:f64d43ff0c18 | 1441 | * Used for non-DMA write transfers. The SDHC can implement multiple buffers to |
mbed_official | 146:f64d43ff0c18 | 1442 | * transfer data efficiently. This read-only flag indicates whether space is |
mbed_official | 146:f64d43ff0c18 | 1443 | * available for write data. If this bit is 1, valid data greater than the watermark |
mbed_official | 146:f64d43ff0c18 | 1444 | * level can be written to the buffer. This read-only flag indicates whether |
mbed_official | 146:f64d43ff0c18 | 1445 | * space is available for write data. |
mbed_official | 146:f64d43ff0c18 | 1446 | * |
mbed_official | 146:f64d43ff0c18 | 1447 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1448 | * - 0 - Write disable, the buffer can hold valid data less than the write |
mbed_official | 146:f64d43ff0c18 | 1449 | * watermark level. |
mbed_official | 146:f64d43ff0c18 | 1450 | * - 1 - Write enable, the buffer can hold valid data greater than the write |
mbed_official | 146:f64d43ff0c18 | 1451 | * watermark level. |
mbed_official | 146:f64d43ff0c18 | 1452 | */ |
mbed_official | 146:f64d43ff0c18 | 1453 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1454 | #define BP_SDHC_PRSSTAT_BWEN (10U) //!< Bit position for SDHC_PRSSTAT_BWEN. |
mbed_official | 146:f64d43ff0c18 | 1455 | #define BM_SDHC_PRSSTAT_BWEN (0x00000400U) //!< Bit mask for SDHC_PRSSTAT_BWEN. |
mbed_official | 146:f64d43ff0c18 | 1456 | #define BS_SDHC_PRSSTAT_BWEN (1U) //!< Bit field size in bits for SDHC_PRSSTAT_BWEN. |
mbed_official | 146:f64d43ff0c18 | 1457 | |
mbed_official | 146:f64d43ff0c18 | 1458 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1459 | //! @brief Read current value of the SDHC_PRSSTAT_BWEN field. |
mbed_official | 146:f64d43ff0c18 | 1460 | #define BR_SDHC_PRSSTAT_BWEN (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_BWEN)) |
mbed_official | 146:f64d43ff0c18 | 1461 | #endif |
mbed_official | 146:f64d43ff0c18 | 1462 | //@} |
mbed_official | 146:f64d43ff0c18 | 1463 | |
mbed_official | 146:f64d43ff0c18 | 1464 | /*! |
mbed_official | 146:f64d43ff0c18 | 1465 | * @name Register SDHC_PRSSTAT, field BREN[11] (RO) |
mbed_official | 146:f64d43ff0c18 | 1466 | * |
mbed_official | 146:f64d43ff0c18 | 1467 | * Used for non-DMA read transfers. The SDHC may implement multiple buffers to |
mbed_official | 146:f64d43ff0c18 | 1468 | * transfer data efficiently. This read-only flag indicates that valid data exists |
mbed_official | 146:f64d43ff0c18 | 1469 | * in the host side buffer. If this bit is high, valid data greater than the |
mbed_official | 146:f64d43ff0c18 | 1470 | * watermark level exist in the buffer. This read-only flag indicates that valid |
mbed_official | 146:f64d43ff0c18 | 1471 | * data exists in the host side buffer. |
mbed_official | 146:f64d43ff0c18 | 1472 | * |
mbed_official | 146:f64d43ff0c18 | 1473 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1474 | * - 0 - Read disable, valid data less than the watermark level exist in the |
mbed_official | 146:f64d43ff0c18 | 1475 | * buffer. |
mbed_official | 146:f64d43ff0c18 | 1476 | * - 1 - Read enable, valid data greater than the watermark level exist in the |
mbed_official | 146:f64d43ff0c18 | 1477 | * buffer. |
mbed_official | 146:f64d43ff0c18 | 1478 | */ |
mbed_official | 146:f64d43ff0c18 | 1479 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1480 | #define BP_SDHC_PRSSTAT_BREN (11U) //!< Bit position for SDHC_PRSSTAT_BREN. |
mbed_official | 146:f64d43ff0c18 | 1481 | #define BM_SDHC_PRSSTAT_BREN (0x00000800U) //!< Bit mask for SDHC_PRSSTAT_BREN. |
mbed_official | 146:f64d43ff0c18 | 1482 | #define BS_SDHC_PRSSTAT_BREN (1U) //!< Bit field size in bits for SDHC_PRSSTAT_BREN. |
mbed_official | 146:f64d43ff0c18 | 1483 | |
mbed_official | 146:f64d43ff0c18 | 1484 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1485 | //! @brief Read current value of the SDHC_PRSSTAT_BREN field. |
mbed_official | 146:f64d43ff0c18 | 1486 | #define BR_SDHC_PRSSTAT_BREN (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_BREN)) |
mbed_official | 146:f64d43ff0c18 | 1487 | #endif |
mbed_official | 146:f64d43ff0c18 | 1488 | //@} |
mbed_official | 146:f64d43ff0c18 | 1489 | |
mbed_official | 146:f64d43ff0c18 | 1490 | /*! |
mbed_official | 146:f64d43ff0c18 | 1491 | * @name Register SDHC_PRSSTAT, field CINS[16] (RO) |
mbed_official | 146:f64d43ff0c18 | 1492 | * |
mbed_official | 146:f64d43ff0c18 | 1493 | * Indicates whether a card has been inserted. The SDHC debounces this signal so |
mbed_official | 146:f64d43ff0c18 | 1494 | * that the host driver will not need to wait for it to stabilize. Changing from |
mbed_official | 146:f64d43ff0c18 | 1495 | * a 0 to 1 generates a card insertion interrupt in the Interrupt Status |
mbed_official | 146:f64d43ff0c18 | 1496 | * register. Changing from a 1 to 0 generates a card removal interrupt in the Interrupt |
mbed_official | 146:f64d43ff0c18 | 1497 | * Status register. A write to the force event register does not effect this bit. |
mbed_official | 146:f64d43ff0c18 | 1498 | * SYSCTL[RSTA] does not effect this bit. A software reset does not effect this |
mbed_official | 146:f64d43ff0c18 | 1499 | * bit. |
mbed_official | 146:f64d43ff0c18 | 1500 | * |
mbed_official | 146:f64d43ff0c18 | 1501 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1502 | * - 0 - Power on reset or no card. |
mbed_official | 146:f64d43ff0c18 | 1503 | * - 1 - Card inserted. |
mbed_official | 146:f64d43ff0c18 | 1504 | */ |
mbed_official | 146:f64d43ff0c18 | 1505 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1506 | #define BP_SDHC_PRSSTAT_CINS (16U) //!< Bit position for SDHC_PRSSTAT_CINS. |
mbed_official | 146:f64d43ff0c18 | 1507 | #define BM_SDHC_PRSSTAT_CINS (0x00010000U) //!< Bit mask for SDHC_PRSSTAT_CINS. |
mbed_official | 146:f64d43ff0c18 | 1508 | #define BS_SDHC_PRSSTAT_CINS (1U) //!< Bit field size in bits for SDHC_PRSSTAT_CINS. |
mbed_official | 146:f64d43ff0c18 | 1509 | |
mbed_official | 146:f64d43ff0c18 | 1510 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1511 | //! @brief Read current value of the SDHC_PRSSTAT_CINS field. |
mbed_official | 146:f64d43ff0c18 | 1512 | #define BR_SDHC_PRSSTAT_CINS (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_CINS)) |
mbed_official | 146:f64d43ff0c18 | 1513 | #endif |
mbed_official | 146:f64d43ff0c18 | 1514 | //@} |
mbed_official | 146:f64d43ff0c18 | 1515 | |
mbed_official | 146:f64d43ff0c18 | 1516 | /*! |
mbed_official | 146:f64d43ff0c18 | 1517 | * @name Register SDHC_PRSSTAT, field CLSL[23] (RO) |
mbed_official | 146:f64d43ff0c18 | 1518 | * |
mbed_official | 146:f64d43ff0c18 | 1519 | * Used to check the CMD line level to recover from errors, and for debugging. |
mbed_official | 146:f64d43ff0c18 | 1520 | * The reset value is effected by the external pullup/pulldown resistor, by |
mbed_official | 146:f64d43ff0c18 | 1521 | * default, the read value of this bit after reset is 1b, when the command line is |
mbed_official | 146:f64d43ff0c18 | 1522 | * pulled up. |
mbed_official | 146:f64d43ff0c18 | 1523 | */ |
mbed_official | 146:f64d43ff0c18 | 1524 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1525 | #define BP_SDHC_PRSSTAT_CLSL (23U) //!< Bit position for SDHC_PRSSTAT_CLSL. |
mbed_official | 146:f64d43ff0c18 | 1526 | #define BM_SDHC_PRSSTAT_CLSL (0x00800000U) //!< Bit mask for SDHC_PRSSTAT_CLSL. |
mbed_official | 146:f64d43ff0c18 | 1527 | #define BS_SDHC_PRSSTAT_CLSL (1U) //!< Bit field size in bits for SDHC_PRSSTAT_CLSL. |
mbed_official | 146:f64d43ff0c18 | 1528 | |
mbed_official | 146:f64d43ff0c18 | 1529 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1530 | //! @brief Read current value of the SDHC_PRSSTAT_CLSL field. |
mbed_official | 146:f64d43ff0c18 | 1531 | #define BR_SDHC_PRSSTAT_CLSL (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_CLSL)) |
mbed_official | 146:f64d43ff0c18 | 1532 | #endif |
mbed_official | 146:f64d43ff0c18 | 1533 | //@} |
mbed_official | 146:f64d43ff0c18 | 1534 | |
mbed_official | 146:f64d43ff0c18 | 1535 | /*! |
mbed_official | 146:f64d43ff0c18 | 1536 | * @name Register SDHC_PRSSTAT, field DLSL[31:24] (RO) |
mbed_official | 146:f64d43ff0c18 | 1537 | * |
mbed_official | 146:f64d43ff0c18 | 1538 | * Used to check the DAT line level to recover from errors, and for debugging. |
mbed_official | 146:f64d43ff0c18 | 1539 | * This is especially useful in detecting the busy signal level from DAT[0]. The |
mbed_official | 146:f64d43ff0c18 | 1540 | * reset value is effected by the external pullup/pulldown resistors. By default, |
mbed_official | 146:f64d43ff0c18 | 1541 | * the read value of this field after reset is 8'b11110111, when DAT[3] is pulled |
mbed_official | 146:f64d43ff0c18 | 1542 | * down and the other lines are pulled up. |
mbed_official | 146:f64d43ff0c18 | 1543 | */ |
mbed_official | 146:f64d43ff0c18 | 1544 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1545 | #define BP_SDHC_PRSSTAT_DLSL (24U) //!< Bit position for SDHC_PRSSTAT_DLSL. |
mbed_official | 146:f64d43ff0c18 | 1546 | #define BM_SDHC_PRSSTAT_DLSL (0xFF000000U) //!< Bit mask for SDHC_PRSSTAT_DLSL. |
mbed_official | 146:f64d43ff0c18 | 1547 | #define BS_SDHC_PRSSTAT_DLSL (8U) //!< Bit field size in bits for SDHC_PRSSTAT_DLSL. |
mbed_official | 146:f64d43ff0c18 | 1548 | |
mbed_official | 146:f64d43ff0c18 | 1549 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1550 | //! @brief Read current value of the SDHC_PRSSTAT_DLSL field. |
mbed_official | 146:f64d43ff0c18 | 1551 | #define BR_SDHC_PRSSTAT_DLSL (HW_SDHC_PRSSTAT.B.DLSL) |
mbed_official | 146:f64d43ff0c18 | 1552 | #endif |
mbed_official | 146:f64d43ff0c18 | 1553 | //@} |
mbed_official | 146:f64d43ff0c18 | 1554 | |
mbed_official | 146:f64d43ff0c18 | 1555 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1556 | // HW_SDHC_PROCTL - Protocol Control register |
mbed_official | 146:f64d43ff0c18 | 1557 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1558 | |
mbed_official | 146:f64d43ff0c18 | 1559 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1560 | /*! |
mbed_official | 146:f64d43ff0c18 | 1561 | * @brief HW_SDHC_PROCTL - Protocol Control register (RW) |
mbed_official | 146:f64d43ff0c18 | 1562 | * |
mbed_official | 146:f64d43ff0c18 | 1563 | * Reset value: 0x00000020U |
mbed_official | 146:f64d43ff0c18 | 1564 | * |
mbed_official | 146:f64d43ff0c18 | 1565 | * There are three cases to restart the transfer after stop at the block gap. |
mbed_official | 146:f64d43ff0c18 | 1566 | * Which case is appropriate depends on whether the SDHC issues a suspend command |
mbed_official | 146:f64d43ff0c18 | 1567 | * or the SD card accepts the suspend command: If the host driver does not issue a |
mbed_official | 146:f64d43ff0c18 | 1568 | * suspend command, the continue request shall be used to restart the transfer. |
mbed_official | 146:f64d43ff0c18 | 1569 | * If the host driver issues a suspend command and the SD card accepts it, a |
mbed_official | 146:f64d43ff0c18 | 1570 | * resume command shall be used to restart the transfer. If the host driver issues a |
mbed_official | 146:f64d43ff0c18 | 1571 | * suspend command and the SD card does not accept it, the continue request shall |
mbed_official | 146:f64d43ff0c18 | 1572 | * be used to restart the transfer. Any time stop at block gap request stops the |
mbed_official | 146:f64d43ff0c18 | 1573 | * data transfer, the host driver shall wait for a transfer complete (in the |
mbed_official | 146:f64d43ff0c18 | 1574 | * interrupt status register), before attempting to restart the transfer. When |
mbed_official | 146:f64d43ff0c18 | 1575 | * restarting the data transfer by continue request, the host driver shall clear the |
mbed_official | 146:f64d43ff0c18 | 1576 | * stop at block gap request before or simultaneously. |
mbed_official | 146:f64d43ff0c18 | 1577 | */ |
mbed_official | 146:f64d43ff0c18 | 1578 | typedef union _hw_sdhc_proctl |
mbed_official | 146:f64d43ff0c18 | 1579 | { |
mbed_official | 146:f64d43ff0c18 | 1580 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 1581 | struct _hw_sdhc_proctl_bitfields |
mbed_official | 146:f64d43ff0c18 | 1582 | { |
mbed_official | 146:f64d43ff0c18 | 1583 | uint32_t LCTL : 1; //!< [0] LED Control |
mbed_official | 146:f64d43ff0c18 | 1584 | uint32_t DTW : 2; //!< [2:1] Data Transfer Width |
mbed_official | 146:f64d43ff0c18 | 1585 | uint32_t D3CD : 1; //!< [3] DAT3 As Card Detection Pin |
mbed_official | 146:f64d43ff0c18 | 1586 | uint32_t EMODE : 2; //!< [5:4] Endian Mode |
mbed_official | 146:f64d43ff0c18 | 1587 | uint32_t CDTL : 1; //!< [6] Card Detect Test Level |
mbed_official | 146:f64d43ff0c18 | 1588 | uint32_t CDSS : 1; //!< [7] Card Detect Signal Selection |
mbed_official | 146:f64d43ff0c18 | 1589 | uint32_t DMAS : 2; //!< [9:8] DMA Select |
mbed_official | 146:f64d43ff0c18 | 1590 | uint32_t RESERVED0 : 6; //!< [15:10] |
mbed_official | 146:f64d43ff0c18 | 1591 | uint32_t SABGREQ : 1; //!< [16] Stop At Block Gap Request |
mbed_official | 146:f64d43ff0c18 | 1592 | uint32_t CREQ : 1; //!< [17] Continue Request |
mbed_official | 146:f64d43ff0c18 | 1593 | uint32_t RWCTL : 1; //!< [18] Read Wait Control |
mbed_official | 146:f64d43ff0c18 | 1594 | uint32_t IABG : 1; //!< [19] Interrupt At Block Gap |
mbed_official | 146:f64d43ff0c18 | 1595 | uint32_t RESERVED1 : 4; //!< [23:20] |
mbed_official | 146:f64d43ff0c18 | 1596 | uint32_t WECINT : 1; //!< [24] Wakeup Event Enable On Card Interrupt |
mbed_official | 146:f64d43ff0c18 | 1597 | uint32_t WECINS : 1; //!< [25] Wakeup Event Enable On SD Card |
mbed_official | 146:f64d43ff0c18 | 1598 | //! Insertion |
mbed_official | 146:f64d43ff0c18 | 1599 | uint32_t WECRM : 1; //!< [26] Wakeup Event Enable On SD Card Removal |
mbed_official | 146:f64d43ff0c18 | 1600 | uint32_t RESERVED2 : 5; //!< [31:27] |
mbed_official | 146:f64d43ff0c18 | 1601 | } B; |
mbed_official | 146:f64d43ff0c18 | 1602 | } hw_sdhc_proctl_t; |
mbed_official | 146:f64d43ff0c18 | 1603 | #endif |
mbed_official | 146:f64d43ff0c18 | 1604 | |
mbed_official | 146:f64d43ff0c18 | 1605 | /*! |
mbed_official | 146:f64d43ff0c18 | 1606 | * @name Constants and macros for entire SDHC_PROCTL register |
mbed_official | 146:f64d43ff0c18 | 1607 | */ |
mbed_official | 146:f64d43ff0c18 | 1608 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1609 | #define HW_SDHC_PROCTL_ADDR (REGS_SDHC_BASE + 0x28U) |
mbed_official | 146:f64d43ff0c18 | 1610 | |
mbed_official | 146:f64d43ff0c18 | 1611 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1612 | #define HW_SDHC_PROCTL (*(__IO hw_sdhc_proctl_t *) HW_SDHC_PROCTL_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1613 | #define HW_SDHC_PROCTL_RD() (HW_SDHC_PROCTL.U) |
mbed_official | 146:f64d43ff0c18 | 1614 | #define HW_SDHC_PROCTL_WR(v) (HW_SDHC_PROCTL.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1615 | #define HW_SDHC_PROCTL_SET(v) (HW_SDHC_PROCTL_WR(HW_SDHC_PROCTL_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1616 | #define HW_SDHC_PROCTL_CLR(v) (HW_SDHC_PROCTL_WR(HW_SDHC_PROCTL_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1617 | #define HW_SDHC_PROCTL_TOG(v) (HW_SDHC_PROCTL_WR(HW_SDHC_PROCTL_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1618 | #endif |
mbed_official | 146:f64d43ff0c18 | 1619 | //@} |
mbed_official | 146:f64d43ff0c18 | 1620 | |
mbed_official | 146:f64d43ff0c18 | 1621 | /* |
mbed_official | 146:f64d43ff0c18 | 1622 | * Constants & macros for individual SDHC_PROCTL bitfields |
mbed_official | 146:f64d43ff0c18 | 1623 | */ |
mbed_official | 146:f64d43ff0c18 | 1624 | |
mbed_official | 146:f64d43ff0c18 | 1625 | /*! |
mbed_official | 146:f64d43ff0c18 | 1626 | * @name Register SDHC_PROCTL, field LCTL[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1627 | * |
mbed_official | 146:f64d43ff0c18 | 1628 | * This bit, fully controlled by the host driver, is used to caution the user |
mbed_official | 146:f64d43ff0c18 | 1629 | * not to remove the card while the card is being accessed. If the software is |
mbed_official | 146:f64d43ff0c18 | 1630 | * going to issue multiple SD commands, this bit can be set during all these |
mbed_official | 146:f64d43ff0c18 | 1631 | * transactions. It is not necessary to change for each transaction. When the software |
mbed_official | 146:f64d43ff0c18 | 1632 | * issues multiple SD commands, setting the bit once before the first command is |
mbed_official | 146:f64d43ff0c18 | 1633 | * sufficient: it is not necessary to reset the bit between commands. |
mbed_official | 146:f64d43ff0c18 | 1634 | * |
mbed_official | 146:f64d43ff0c18 | 1635 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1636 | * - 0 - LED off. |
mbed_official | 146:f64d43ff0c18 | 1637 | * - 1 - LED on. |
mbed_official | 146:f64d43ff0c18 | 1638 | */ |
mbed_official | 146:f64d43ff0c18 | 1639 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1640 | #define BP_SDHC_PROCTL_LCTL (0U) //!< Bit position for SDHC_PROCTL_LCTL. |
mbed_official | 146:f64d43ff0c18 | 1641 | #define BM_SDHC_PROCTL_LCTL (0x00000001U) //!< Bit mask for SDHC_PROCTL_LCTL. |
mbed_official | 146:f64d43ff0c18 | 1642 | #define BS_SDHC_PROCTL_LCTL (1U) //!< Bit field size in bits for SDHC_PROCTL_LCTL. |
mbed_official | 146:f64d43ff0c18 | 1643 | |
mbed_official | 146:f64d43ff0c18 | 1644 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1645 | //! @brief Read current value of the SDHC_PROCTL_LCTL field. |
mbed_official | 146:f64d43ff0c18 | 1646 | #define BR_SDHC_PROCTL_LCTL (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_LCTL)) |
mbed_official | 146:f64d43ff0c18 | 1647 | #endif |
mbed_official | 146:f64d43ff0c18 | 1648 | |
mbed_official | 146:f64d43ff0c18 | 1649 | //! @brief Format value for bitfield SDHC_PROCTL_LCTL. |
mbed_official | 146:f64d43ff0c18 | 1650 | #define BF_SDHC_PROCTL_LCTL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_LCTL), uint32_t) & BM_SDHC_PROCTL_LCTL) |
mbed_official | 146:f64d43ff0c18 | 1651 | |
mbed_official | 146:f64d43ff0c18 | 1652 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1653 | //! @brief Set the LCTL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1654 | #define BW_SDHC_PROCTL_LCTL(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_LCTL) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1655 | #endif |
mbed_official | 146:f64d43ff0c18 | 1656 | //@} |
mbed_official | 146:f64d43ff0c18 | 1657 | |
mbed_official | 146:f64d43ff0c18 | 1658 | /*! |
mbed_official | 146:f64d43ff0c18 | 1659 | * @name Register SDHC_PROCTL, field DTW[2:1] (RW) |
mbed_official | 146:f64d43ff0c18 | 1660 | * |
mbed_official | 146:f64d43ff0c18 | 1661 | * Selects the data width of the SD bus for a data transfer. The host driver |
mbed_official | 146:f64d43ff0c18 | 1662 | * shall set it to match the data width of the card. Possible data transfer width is |
mbed_official | 146:f64d43ff0c18 | 1663 | * 1-bit, 4-bits or 8-bits. |
mbed_official | 146:f64d43ff0c18 | 1664 | * |
mbed_official | 146:f64d43ff0c18 | 1665 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1666 | * - 00 - 1-bit mode |
mbed_official | 146:f64d43ff0c18 | 1667 | * - 01 - 4-bit mode |
mbed_official | 146:f64d43ff0c18 | 1668 | * - 10 - 8-bit mode |
mbed_official | 146:f64d43ff0c18 | 1669 | * - 11 - Reserved |
mbed_official | 146:f64d43ff0c18 | 1670 | */ |
mbed_official | 146:f64d43ff0c18 | 1671 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1672 | #define BP_SDHC_PROCTL_DTW (1U) //!< Bit position for SDHC_PROCTL_DTW. |
mbed_official | 146:f64d43ff0c18 | 1673 | #define BM_SDHC_PROCTL_DTW (0x00000006U) //!< Bit mask for SDHC_PROCTL_DTW. |
mbed_official | 146:f64d43ff0c18 | 1674 | #define BS_SDHC_PROCTL_DTW (2U) //!< Bit field size in bits for SDHC_PROCTL_DTW. |
mbed_official | 146:f64d43ff0c18 | 1675 | |
mbed_official | 146:f64d43ff0c18 | 1676 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1677 | //! @brief Read current value of the SDHC_PROCTL_DTW field. |
mbed_official | 146:f64d43ff0c18 | 1678 | #define BR_SDHC_PROCTL_DTW (HW_SDHC_PROCTL.B.DTW) |
mbed_official | 146:f64d43ff0c18 | 1679 | #endif |
mbed_official | 146:f64d43ff0c18 | 1680 | |
mbed_official | 146:f64d43ff0c18 | 1681 | //! @brief Format value for bitfield SDHC_PROCTL_DTW. |
mbed_official | 146:f64d43ff0c18 | 1682 | #define BF_SDHC_PROCTL_DTW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_DTW), uint32_t) & BM_SDHC_PROCTL_DTW) |
mbed_official | 146:f64d43ff0c18 | 1683 | |
mbed_official | 146:f64d43ff0c18 | 1684 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1685 | //! @brief Set the DTW field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1686 | #define BW_SDHC_PROCTL_DTW(v) (HW_SDHC_PROCTL_WR((HW_SDHC_PROCTL_RD() & ~BM_SDHC_PROCTL_DTW) | BF_SDHC_PROCTL_DTW(v))) |
mbed_official | 146:f64d43ff0c18 | 1687 | #endif |
mbed_official | 146:f64d43ff0c18 | 1688 | //@} |
mbed_official | 146:f64d43ff0c18 | 1689 | |
mbed_official | 146:f64d43ff0c18 | 1690 | /*! |
mbed_official | 146:f64d43ff0c18 | 1691 | * @name Register SDHC_PROCTL, field D3CD[3] (RW) |
mbed_official | 146:f64d43ff0c18 | 1692 | * |
mbed_official | 146:f64d43ff0c18 | 1693 | * If this bit is set, DAT3 should be pulled down to act as a card detection |
mbed_official | 146:f64d43ff0c18 | 1694 | * pin. Be cautious when using this feature, because DAT3 is also a chip-select for |
mbed_official | 146:f64d43ff0c18 | 1695 | * the SPI mode. A pulldown on this pin and CMD0 may set the card into the SPI |
mbed_official | 146:f64d43ff0c18 | 1696 | * mode, which the SDHC does not support. Note: Keep this bit set if SDIO interrupt |
mbed_official | 146:f64d43ff0c18 | 1697 | * is used. |
mbed_official | 146:f64d43ff0c18 | 1698 | * |
mbed_official | 146:f64d43ff0c18 | 1699 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1700 | * - 0 - DAT3 does not monitor card Insertion. |
mbed_official | 146:f64d43ff0c18 | 1701 | * - 1 - DAT3 as card detection pin. |
mbed_official | 146:f64d43ff0c18 | 1702 | */ |
mbed_official | 146:f64d43ff0c18 | 1703 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1704 | #define BP_SDHC_PROCTL_D3CD (3U) //!< Bit position for SDHC_PROCTL_D3CD. |
mbed_official | 146:f64d43ff0c18 | 1705 | #define BM_SDHC_PROCTL_D3CD (0x00000008U) //!< Bit mask for SDHC_PROCTL_D3CD. |
mbed_official | 146:f64d43ff0c18 | 1706 | #define BS_SDHC_PROCTL_D3CD (1U) //!< Bit field size in bits for SDHC_PROCTL_D3CD. |
mbed_official | 146:f64d43ff0c18 | 1707 | |
mbed_official | 146:f64d43ff0c18 | 1708 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1709 | //! @brief Read current value of the SDHC_PROCTL_D3CD field. |
mbed_official | 146:f64d43ff0c18 | 1710 | #define BR_SDHC_PROCTL_D3CD (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_D3CD)) |
mbed_official | 146:f64d43ff0c18 | 1711 | #endif |
mbed_official | 146:f64d43ff0c18 | 1712 | |
mbed_official | 146:f64d43ff0c18 | 1713 | //! @brief Format value for bitfield SDHC_PROCTL_D3CD. |
mbed_official | 146:f64d43ff0c18 | 1714 | #define BF_SDHC_PROCTL_D3CD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_D3CD), uint32_t) & BM_SDHC_PROCTL_D3CD) |
mbed_official | 146:f64d43ff0c18 | 1715 | |
mbed_official | 146:f64d43ff0c18 | 1716 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1717 | //! @brief Set the D3CD field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1718 | #define BW_SDHC_PROCTL_D3CD(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_D3CD) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1719 | #endif |
mbed_official | 146:f64d43ff0c18 | 1720 | //@} |
mbed_official | 146:f64d43ff0c18 | 1721 | |
mbed_official | 146:f64d43ff0c18 | 1722 | /*! |
mbed_official | 146:f64d43ff0c18 | 1723 | * @name Register SDHC_PROCTL, field EMODE[5:4] (RW) |
mbed_official | 146:f64d43ff0c18 | 1724 | * |
mbed_official | 146:f64d43ff0c18 | 1725 | * The SDHC supports all four endian modes in data transfer. |
mbed_official | 146:f64d43ff0c18 | 1726 | * |
mbed_official | 146:f64d43ff0c18 | 1727 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1728 | * - 00 - Big endian mode |
mbed_official | 146:f64d43ff0c18 | 1729 | * - 01 - Half word big endian mode |
mbed_official | 146:f64d43ff0c18 | 1730 | * - 10 - Little endian mode |
mbed_official | 146:f64d43ff0c18 | 1731 | * - 11 - Reserved |
mbed_official | 146:f64d43ff0c18 | 1732 | */ |
mbed_official | 146:f64d43ff0c18 | 1733 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1734 | #define BP_SDHC_PROCTL_EMODE (4U) //!< Bit position for SDHC_PROCTL_EMODE. |
mbed_official | 146:f64d43ff0c18 | 1735 | #define BM_SDHC_PROCTL_EMODE (0x00000030U) //!< Bit mask for SDHC_PROCTL_EMODE. |
mbed_official | 146:f64d43ff0c18 | 1736 | #define BS_SDHC_PROCTL_EMODE (2U) //!< Bit field size in bits for SDHC_PROCTL_EMODE. |
mbed_official | 146:f64d43ff0c18 | 1737 | |
mbed_official | 146:f64d43ff0c18 | 1738 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1739 | //! @brief Read current value of the SDHC_PROCTL_EMODE field. |
mbed_official | 146:f64d43ff0c18 | 1740 | #define BR_SDHC_PROCTL_EMODE (HW_SDHC_PROCTL.B.EMODE) |
mbed_official | 146:f64d43ff0c18 | 1741 | #endif |
mbed_official | 146:f64d43ff0c18 | 1742 | |
mbed_official | 146:f64d43ff0c18 | 1743 | //! @brief Format value for bitfield SDHC_PROCTL_EMODE. |
mbed_official | 146:f64d43ff0c18 | 1744 | #define BF_SDHC_PROCTL_EMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_EMODE), uint32_t) & BM_SDHC_PROCTL_EMODE) |
mbed_official | 146:f64d43ff0c18 | 1745 | |
mbed_official | 146:f64d43ff0c18 | 1746 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1747 | //! @brief Set the EMODE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1748 | #define BW_SDHC_PROCTL_EMODE(v) (HW_SDHC_PROCTL_WR((HW_SDHC_PROCTL_RD() & ~BM_SDHC_PROCTL_EMODE) | BF_SDHC_PROCTL_EMODE(v))) |
mbed_official | 146:f64d43ff0c18 | 1749 | #endif |
mbed_official | 146:f64d43ff0c18 | 1750 | //@} |
mbed_official | 146:f64d43ff0c18 | 1751 | |
mbed_official | 146:f64d43ff0c18 | 1752 | /*! |
mbed_official | 146:f64d43ff0c18 | 1753 | * @name Register SDHC_PROCTL, field CDTL[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 1754 | * |
mbed_official | 146:f64d43ff0c18 | 1755 | * Enabled while the CDSS is set to 1 and it indicates card insertion. |
mbed_official | 146:f64d43ff0c18 | 1756 | * |
mbed_official | 146:f64d43ff0c18 | 1757 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1758 | * - 0 - Card detect test level is 0, no card inserted. |
mbed_official | 146:f64d43ff0c18 | 1759 | * - 1 - Card detect test level is 1, card inserted. |
mbed_official | 146:f64d43ff0c18 | 1760 | */ |
mbed_official | 146:f64d43ff0c18 | 1761 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1762 | #define BP_SDHC_PROCTL_CDTL (6U) //!< Bit position for SDHC_PROCTL_CDTL. |
mbed_official | 146:f64d43ff0c18 | 1763 | #define BM_SDHC_PROCTL_CDTL (0x00000040U) //!< Bit mask for SDHC_PROCTL_CDTL. |
mbed_official | 146:f64d43ff0c18 | 1764 | #define BS_SDHC_PROCTL_CDTL (1U) //!< Bit field size in bits for SDHC_PROCTL_CDTL. |
mbed_official | 146:f64d43ff0c18 | 1765 | |
mbed_official | 146:f64d43ff0c18 | 1766 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1767 | //! @brief Read current value of the SDHC_PROCTL_CDTL field. |
mbed_official | 146:f64d43ff0c18 | 1768 | #define BR_SDHC_PROCTL_CDTL (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CDTL)) |
mbed_official | 146:f64d43ff0c18 | 1769 | #endif |
mbed_official | 146:f64d43ff0c18 | 1770 | |
mbed_official | 146:f64d43ff0c18 | 1771 | //! @brief Format value for bitfield SDHC_PROCTL_CDTL. |
mbed_official | 146:f64d43ff0c18 | 1772 | #define BF_SDHC_PROCTL_CDTL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_CDTL), uint32_t) & BM_SDHC_PROCTL_CDTL) |
mbed_official | 146:f64d43ff0c18 | 1773 | |
mbed_official | 146:f64d43ff0c18 | 1774 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1775 | //! @brief Set the CDTL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1776 | #define BW_SDHC_PROCTL_CDTL(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CDTL) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1777 | #endif |
mbed_official | 146:f64d43ff0c18 | 1778 | //@} |
mbed_official | 146:f64d43ff0c18 | 1779 | |
mbed_official | 146:f64d43ff0c18 | 1780 | /*! |
mbed_official | 146:f64d43ff0c18 | 1781 | * @name Register SDHC_PROCTL, field CDSS[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 1782 | * |
mbed_official | 146:f64d43ff0c18 | 1783 | * Selects the source for the card detection. |
mbed_official | 146:f64d43ff0c18 | 1784 | * |
mbed_official | 146:f64d43ff0c18 | 1785 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1786 | * - 0 - Card detection level is selected for normal purpose. |
mbed_official | 146:f64d43ff0c18 | 1787 | * - 1 - Card detection test level is selected for test purpose. |
mbed_official | 146:f64d43ff0c18 | 1788 | */ |
mbed_official | 146:f64d43ff0c18 | 1789 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1790 | #define BP_SDHC_PROCTL_CDSS (7U) //!< Bit position for SDHC_PROCTL_CDSS. |
mbed_official | 146:f64d43ff0c18 | 1791 | #define BM_SDHC_PROCTL_CDSS (0x00000080U) //!< Bit mask for SDHC_PROCTL_CDSS. |
mbed_official | 146:f64d43ff0c18 | 1792 | #define BS_SDHC_PROCTL_CDSS (1U) //!< Bit field size in bits for SDHC_PROCTL_CDSS. |
mbed_official | 146:f64d43ff0c18 | 1793 | |
mbed_official | 146:f64d43ff0c18 | 1794 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1795 | //! @brief Read current value of the SDHC_PROCTL_CDSS field. |
mbed_official | 146:f64d43ff0c18 | 1796 | #define BR_SDHC_PROCTL_CDSS (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CDSS)) |
mbed_official | 146:f64d43ff0c18 | 1797 | #endif |
mbed_official | 146:f64d43ff0c18 | 1798 | |
mbed_official | 146:f64d43ff0c18 | 1799 | //! @brief Format value for bitfield SDHC_PROCTL_CDSS. |
mbed_official | 146:f64d43ff0c18 | 1800 | #define BF_SDHC_PROCTL_CDSS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_CDSS), uint32_t) & BM_SDHC_PROCTL_CDSS) |
mbed_official | 146:f64d43ff0c18 | 1801 | |
mbed_official | 146:f64d43ff0c18 | 1802 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1803 | //! @brief Set the CDSS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1804 | #define BW_SDHC_PROCTL_CDSS(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CDSS) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1805 | #endif |
mbed_official | 146:f64d43ff0c18 | 1806 | //@} |
mbed_official | 146:f64d43ff0c18 | 1807 | |
mbed_official | 146:f64d43ff0c18 | 1808 | /*! |
mbed_official | 146:f64d43ff0c18 | 1809 | * @name Register SDHC_PROCTL, field DMAS[9:8] (RW) |
mbed_official | 146:f64d43ff0c18 | 1810 | * |
mbed_official | 146:f64d43ff0c18 | 1811 | * This field is valid while DMA (SDMA or ADMA) is enabled and selects the DMA |
mbed_official | 146:f64d43ff0c18 | 1812 | * operation. |
mbed_official | 146:f64d43ff0c18 | 1813 | * |
mbed_official | 146:f64d43ff0c18 | 1814 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1815 | * - 00 - No DMA or simple DMA is selected. |
mbed_official | 146:f64d43ff0c18 | 1816 | * - 01 - ADMA1 is selected. |
mbed_official | 146:f64d43ff0c18 | 1817 | * - 10 - ADMA2 is selected. |
mbed_official | 146:f64d43ff0c18 | 1818 | * - 11 - Reserved |
mbed_official | 146:f64d43ff0c18 | 1819 | */ |
mbed_official | 146:f64d43ff0c18 | 1820 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1821 | #define BP_SDHC_PROCTL_DMAS (8U) //!< Bit position for SDHC_PROCTL_DMAS. |
mbed_official | 146:f64d43ff0c18 | 1822 | #define BM_SDHC_PROCTL_DMAS (0x00000300U) //!< Bit mask for SDHC_PROCTL_DMAS. |
mbed_official | 146:f64d43ff0c18 | 1823 | #define BS_SDHC_PROCTL_DMAS (2U) //!< Bit field size in bits for SDHC_PROCTL_DMAS. |
mbed_official | 146:f64d43ff0c18 | 1824 | |
mbed_official | 146:f64d43ff0c18 | 1825 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1826 | //! @brief Read current value of the SDHC_PROCTL_DMAS field. |
mbed_official | 146:f64d43ff0c18 | 1827 | #define BR_SDHC_PROCTL_DMAS (HW_SDHC_PROCTL.B.DMAS) |
mbed_official | 146:f64d43ff0c18 | 1828 | #endif |
mbed_official | 146:f64d43ff0c18 | 1829 | |
mbed_official | 146:f64d43ff0c18 | 1830 | //! @brief Format value for bitfield SDHC_PROCTL_DMAS. |
mbed_official | 146:f64d43ff0c18 | 1831 | #define BF_SDHC_PROCTL_DMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_DMAS), uint32_t) & BM_SDHC_PROCTL_DMAS) |
mbed_official | 146:f64d43ff0c18 | 1832 | |
mbed_official | 146:f64d43ff0c18 | 1833 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1834 | //! @brief Set the DMAS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1835 | #define BW_SDHC_PROCTL_DMAS(v) (HW_SDHC_PROCTL_WR((HW_SDHC_PROCTL_RD() & ~BM_SDHC_PROCTL_DMAS) | BF_SDHC_PROCTL_DMAS(v))) |
mbed_official | 146:f64d43ff0c18 | 1836 | #endif |
mbed_official | 146:f64d43ff0c18 | 1837 | //@} |
mbed_official | 146:f64d43ff0c18 | 1838 | |
mbed_official | 146:f64d43ff0c18 | 1839 | /*! |
mbed_official | 146:f64d43ff0c18 | 1840 | * @name Register SDHC_PROCTL, field SABGREQ[16] (RW) |
mbed_official | 146:f64d43ff0c18 | 1841 | * |
mbed_official | 146:f64d43ff0c18 | 1842 | * Used to stop executing a transaction at the next block gap for both DMA and |
mbed_official | 146:f64d43ff0c18 | 1843 | * non-DMA transfers. Until the IRQSTATEN[TCSEN] is set to 1, indicating a |
mbed_official | 146:f64d43ff0c18 | 1844 | * transfer completion, the host driver shall leave this bit set to 1. Clearing both |
mbed_official | 146:f64d43ff0c18 | 1845 | * PROCTL[SABGREQ] and PROCTL[CREQ] does not cause the transaction to restart. Read |
mbed_official | 146:f64d43ff0c18 | 1846 | * Wait is used to stop the read transaction at the block gap. The SDHC will |
mbed_official | 146:f64d43ff0c18 | 1847 | * honor the PROCTL[SABGREQ] for write transfers, but for read transfers it requires |
mbed_official | 146:f64d43ff0c18 | 1848 | * that SDIO card support read wait. Therefore, the host driver shall not set |
mbed_official | 146:f64d43ff0c18 | 1849 | * this bit during read transfers unless the SDIO card supports read wait and has |
mbed_official | 146:f64d43ff0c18 | 1850 | * set PROCTL[RWCTL] to 1, otherwise the SDHC will stop the SD bus clock to pause |
mbed_official | 146:f64d43ff0c18 | 1851 | * the read operation during block gap. In the case of write transfers in which |
mbed_official | 146:f64d43ff0c18 | 1852 | * the host driver writes data to the data port register, the host driver shall set |
mbed_official | 146:f64d43ff0c18 | 1853 | * this bit after all block data is written. If this bit is set to 1, the host |
mbed_official | 146:f64d43ff0c18 | 1854 | * driver shall not write data to the Data Port register after a block is sent. |
mbed_official | 146:f64d43ff0c18 | 1855 | * Once this bit is set, the host driver shall not clear this bit before |
mbed_official | 146:f64d43ff0c18 | 1856 | * IRQSTATEN[TCSEN] is set, otherwise the SDHC's behavior is undefined. This bit effects |
mbed_official | 146:f64d43ff0c18 | 1857 | * PRSSTAT[RTA], PRSSTAT[WTA], and PRSSTAT[CDIHB]. |
mbed_official | 146:f64d43ff0c18 | 1858 | * |
mbed_official | 146:f64d43ff0c18 | 1859 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1860 | * - 0 - Transfer |
mbed_official | 146:f64d43ff0c18 | 1861 | * - 1 - Stop |
mbed_official | 146:f64d43ff0c18 | 1862 | */ |
mbed_official | 146:f64d43ff0c18 | 1863 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1864 | #define BP_SDHC_PROCTL_SABGREQ (16U) //!< Bit position for SDHC_PROCTL_SABGREQ. |
mbed_official | 146:f64d43ff0c18 | 1865 | #define BM_SDHC_PROCTL_SABGREQ (0x00010000U) //!< Bit mask for SDHC_PROCTL_SABGREQ. |
mbed_official | 146:f64d43ff0c18 | 1866 | #define BS_SDHC_PROCTL_SABGREQ (1U) //!< Bit field size in bits for SDHC_PROCTL_SABGREQ. |
mbed_official | 146:f64d43ff0c18 | 1867 | |
mbed_official | 146:f64d43ff0c18 | 1868 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1869 | //! @brief Read current value of the SDHC_PROCTL_SABGREQ field. |
mbed_official | 146:f64d43ff0c18 | 1870 | #define BR_SDHC_PROCTL_SABGREQ (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_SABGREQ)) |
mbed_official | 146:f64d43ff0c18 | 1871 | #endif |
mbed_official | 146:f64d43ff0c18 | 1872 | |
mbed_official | 146:f64d43ff0c18 | 1873 | //! @brief Format value for bitfield SDHC_PROCTL_SABGREQ. |
mbed_official | 146:f64d43ff0c18 | 1874 | #define BF_SDHC_PROCTL_SABGREQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_SABGREQ), uint32_t) & BM_SDHC_PROCTL_SABGREQ) |
mbed_official | 146:f64d43ff0c18 | 1875 | |
mbed_official | 146:f64d43ff0c18 | 1876 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1877 | //! @brief Set the SABGREQ field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1878 | #define BW_SDHC_PROCTL_SABGREQ(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_SABGREQ) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1879 | #endif |
mbed_official | 146:f64d43ff0c18 | 1880 | //@} |
mbed_official | 146:f64d43ff0c18 | 1881 | |
mbed_official | 146:f64d43ff0c18 | 1882 | /*! |
mbed_official | 146:f64d43ff0c18 | 1883 | * @name Register SDHC_PROCTL, field CREQ[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 1884 | * |
mbed_official | 146:f64d43ff0c18 | 1885 | * Used to restart a transaction which was stopped using the PROCTL[SABGREQ]. |
mbed_official | 146:f64d43ff0c18 | 1886 | * When a suspend operation is not accepted by the card, it is also by setting this |
mbed_official | 146:f64d43ff0c18 | 1887 | * bit to restart the paused transfer. To cancel stop at the block gap, set |
mbed_official | 146:f64d43ff0c18 | 1888 | * PROCTL[SABGREQ] to 0 and set this bit to 1 to restart the transfer. The SDHC |
mbed_official | 146:f64d43ff0c18 | 1889 | * automatically clears this bit, therefore it is not necessary for the host driver to |
mbed_official | 146:f64d43ff0c18 | 1890 | * set this bit to 0. If both PROCTL[SABGREQ] and this bit are 1, the continue |
mbed_official | 146:f64d43ff0c18 | 1891 | * request is ignored. |
mbed_official | 146:f64d43ff0c18 | 1892 | * |
mbed_official | 146:f64d43ff0c18 | 1893 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1894 | * - 0 - No effect. |
mbed_official | 146:f64d43ff0c18 | 1895 | * - 1 - Restart |
mbed_official | 146:f64d43ff0c18 | 1896 | */ |
mbed_official | 146:f64d43ff0c18 | 1897 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1898 | #define BP_SDHC_PROCTL_CREQ (17U) //!< Bit position for SDHC_PROCTL_CREQ. |
mbed_official | 146:f64d43ff0c18 | 1899 | #define BM_SDHC_PROCTL_CREQ (0x00020000U) //!< Bit mask for SDHC_PROCTL_CREQ. |
mbed_official | 146:f64d43ff0c18 | 1900 | #define BS_SDHC_PROCTL_CREQ (1U) //!< Bit field size in bits for SDHC_PROCTL_CREQ. |
mbed_official | 146:f64d43ff0c18 | 1901 | |
mbed_official | 146:f64d43ff0c18 | 1902 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1903 | //! @brief Read current value of the SDHC_PROCTL_CREQ field. |
mbed_official | 146:f64d43ff0c18 | 1904 | #define BR_SDHC_PROCTL_CREQ (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CREQ)) |
mbed_official | 146:f64d43ff0c18 | 1905 | #endif |
mbed_official | 146:f64d43ff0c18 | 1906 | |
mbed_official | 146:f64d43ff0c18 | 1907 | //! @brief Format value for bitfield SDHC_PROCTL_CREQ. |
mbed_official | 146:f64d43ff0c18 | 1908 | #define BF_SDHC_PROCTL_CREQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_CREQ), uint32_t) & BM_SDHC_PROCTL_CREQ) |
mbed_official | 146:f64d43ff0c18 | 1909 | |
mbed_official | 146:f64d43ff0c18 | 1910 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1911 | //! @brief Set the CREQ field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1912 | #define BW_SDHC_PROCTL_CREQ(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CREQ) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1913 | #endif |
mbed_official | 146:f64d43ff0c18 | 1914 | //@} |
mbed_official | 146:f64d43ff0c18 | 1915 | |
mbed_official | 146:f64d43ff0c18 | 1916 | /*! |
mbed_official | 146:f64d43ff0c18 | 1917 | * @name Register SDHC_PROCTL, field RWCTL[18] (RW) |
mbed_official | 146:f64d43ff0c18 | 1918 | * |
mbed_official | 146:f64d43ff0c18 | 1919 | * The read wait function is optional for SDIO cards. If the card supports read |
mbed_official | 146:f64d43ff0c18 | 1920 | * wait, set this bit to enable use of the read wait protocol to stop read data |
mbed_official | 146:f64d43ff0c18 | 1921 | * using the DAT[2] line. Otherwise, the SDHC has to stop the SD Clock to hold |
mbed_official | 146:f64d43ff0c18 | 1922 | * read data, which restricts commands generation. When the host driver detects an |
mbed_official | 146:f64d43ff0c18 | 1923 | * SDIO card insertion, it shall set this bit according to the CCCR of the card. |
mbed_official | 146:f64d43ff0c18 | 1924 | * If the card does not support read wait, this bit shall never be set to 1, |
mbed_official | 146:f64d43ff0c18 | 1925 | * otherwise DAT line conflicts may occur. If this bit is set to 0, stop at block gap |
mbed_official | 146:f64d43ff0c18 | 1926 | * during read operation is also supported, but the SDHC will stop the SD Clock |
mbed_official | 146:f64d43ff0c18 | 1927 | * to pause reading operation. |
mbed_official | 146:f64d43ff0c18 | 1928 | * |
mbed_official | 146:f64d43ff0c18 | 1929 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1930 | * - 0 - Disable read wait control, and stop SD clock at block gap when SABGREQ |
mbed_official | 146:f64d43ff0c18 | 1931 | * is set. |
mbed_official | 146:f64d43ff0c18 | 1932 | * - 1 - Enable read wait control, and assert read wait without stopping SD |
mbed_official | 146:f64d43ff0c18 | 1933 | * clock at block gap when SABGREQ bit is set. |
mbed_official | 146:f64d43ff0c18 | 1934 | */ |
mbed_official | 146:f64d43ff0c18 | 1935 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1936 | #define BP_SDHC_PROCTL_RWCTL (18U) //!< Bit position for SDHC_PROCTL_RWCTL. |
mbed_official | 146:f64d43ff0c18 | 1937 | #define BM_SDHC_PROCTL_RWCTL (0x00040000U) //!< Bit mask for SDHC_PROCTL_RWCTL. |
mbed_official | 146:f64d43ff0c18 | 1938 | #define BS_SDHC_PROCTL_RWCTL (1U) //!< Bit field size in bits for SDHC_PROCTL_RWCTL. |
mbed_official | 146:f64d43ff0c18 | 1939 | |
mbed_official | 146:f64d43ff0c18 | 1940 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1941 | //! @brief Read current value of the SDHC_PROCTL_RWCTL field. |
mbed_official | 146:f64d43ff0c18 | 1942 | #define BR_SDHC_PROCTL_RWCTL (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_RWCTL)) |
mbed_official | 146:f64d43ff0c18 | 1943 | #endif |
mbed_official | 146:f64d43ff0c18 | 1944 | |
mbed_official | 146:f64d43ff0c18 | 1945 | //! @brief Format value for bitfield SDHC_PROCTL_RWCTL. |
mbed_official | 146:f64d43ff0c18 | 1946 | #define BF_SDHC_PROCTL_RWCTL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_RWCTL), uint32_t) & BM_SDHC_PROCTL_RWCTL) |
mbed_official | 146:f64d43ff0c18 | 1947 | |
mbed_official | 146:f64d43ff0c18 | 1948 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1949 | //! @brief Set the RWCTL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1950 | #define BW_SDHC_PROCTL_RWCTL(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_RWCTL) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1951 | #endif |
mbed_official | 146:f64d43ff0c18 | 1952 | //@} |
mbed_official | 146:f64d43ff0c18 | 1953 | |
mbed_official | 146:f64d43ff0c18 | 1954 | /*! |
mbed_official | 146:f64d43ff0c18 | 1955 | * @name Register SDHC_PROCTL, field IABG[19] (RW) |
mbed_official | 146:f64d43ff0c18 | 1956 | * |
mbed_official | 146:f64d43ff0c18 | 1957 | * Valid only in 4-bit mode, of the SDIO card, and selects a sample point in the |
mbed_official | 146:f64d43ff0c18 | 1958 | * interrupt cycle. Setting to 1 enables interrupt detection at the block gap |
mbed_official | 146:f64d43ff0c18 | 1959 | * for a multiple block transfer. Setting to 0 disables interrupt detection during |
mbed_official | 146:f64d43ff0c18 | 1960 | * a multiple block transfer. If the SDIO card can't signal an interrupt during a |
mbed_official | 146:f64d43ff0c18 | 1961 | * multiple block transfer, this bit must be set to 0 to avoid an inadvertent |
mbed_official | 146:f64d43ff0c18 | 1962 | * interrupt. When the host driver detects an SDIO card insertion, it shall set |
mbed_official | 146:f64d43ff0c18 | 1963 | * this bit according to the CCCR of the card. |
mbed_official | 146:f64d43ff0c18 | 1964 | * |
mbed_official | 146:f64d43ff0c18 | 1965 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1966 | * - 0 - Disabled |
mbed_official | 146:f64d43ff0c18 | 1967 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 1968 | */ |
mbed_official | 146:f64d43ff0c18 | 1969 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1970 | #define BP_SDHC_PROCTL_IABG (19U) //!< Bit position for SDHC_PROCTL_IABG. |
mbed_official | 146:f64d43ff0c18 | 1971 | #define BM_SDHC_PROCTL_IABG (0x00080000U) //!< Bit mask for SDHC_PROCTL_IABG. |
mbed_official | 146:f64d43ff0c18 | 1972 | #define BS_SDHC_PROCTL_IABG (1U) //!< Bit field size in bits for SDHC_PROCTL_IABG. |
mbed_official | 146:f64d43ff0c18 | 1973 | |
mbed_official | 146:f64d43ff0c18 | 1974 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1975 | //! @brief Read current value of the SDHC_PROCTL_IABG field. |
mbed_official | 146:f64d43ff0c18 | 1976 | #define BR_SDHC_PROCTL_IABG (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_IABG)) |
mbed_official | 146:f64d43ff0c18 | 1977 | #endif |
mbed_official | 146:f64d43ff0c18 | 1978 | |
mbed_official | 146:f64d43ff0c18 | 1979 | //! @brief Format value for bitfield SDHC_PROCTL_IABG. |
mbed_official | 146:f64d43ff0c18 | 1980 | #define BF_SDHC_PROCTL_IABG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_IABG), uint32_t) & BM_SDHC_PROCTL_IABG) |
mbed_official | 146:f64d43ff0c18 | 1981 | |
mbed_official | 146:f64d43ff0c18 | 1982 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1983 | //! @brief Set the IABG field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1984 | #define BW_SDHC_PROCTL_IABG(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_IABG) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1985 | #endif |
mbed_official | 146:f64d43ff0c18 | 1986 | //@} |
mbed_official | 146:f64d43ff0c18 | 1987 | |
mbed_official | 146:f64d43ff0c18 | 1988 | /*! |
mbed_official | 146:f64d43ff0c18 | 1989 | * @name Register SDHC_PROCTL, field WECINT[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 1990 | * |
mbed_official | 146:f64d43ff0c18 | 1991 | * Enables a wakeup event, via IRQSTAT[CINT]. This bit can be set to 1 if FN_WUS |
mbed_official | 146:f64d43ff0c18 | 1992 | * (Wake Up Support) in CIS is set to 1. When this bit is set, the card |
mbed_official | 146:f64d43ff0c18 | 1993 | * interrupt status and the SDHC interrupt can be asserted without SD_CLK toggling. When |
mbed_official | 146:f64d43ff0c18 | 1994 | * the wakeup feature is not enabled, the SD_CLK must be active to assert the |
mbed_official | 146:f64d43ff0c18 | 1995 | * card interrupt status and the SDHC interrupt. |
mbed_official | 146:f64d43ff0c18 | 1996 | * |
mbed_official | 146:f64d43ff0c18 | 1997 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1998 | * - 0 - Disabled |
mbed_official | 146:f64d43ff0c18 | 1999 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 2000 | */ |
mbed_official | 146:f64d43ff0c18 | 2001 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2002 | #define BP_SDHC_PROCTL_WECINT (24U) //!< Bit position for SDHC_PROCTL_WECINT. |
mbed_official | 146:f64d43ff0c18 | 2003 | #define BM_SDHC_PROCTL_WECINT (0x01000000U) //!< Bit mask for SDHC_PROCTL_WECINT. |
mbed_official | 146:f64d43ff0c18 | 2004 | #define BS_SDHC_PROCTL_WECINT (1U) //!< Bit field size in bits for SDHC_PROCTL_WECINT. |
mbed_official | 146:f64d43ff0c18 | 2005 | |
mbed_official | 146:f64d43ff0c18 | 2006 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2007 | //! @brief Read current value of the SDHC_PROCTL_WECINT field. |
mbed_official | 146:f64d43ff0c18 | 2008 | #define BR_SDHC_PROCTL_WECINT (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECINT)) |
mbed_official | 146:f64d43ff0c18 | 2009 | #endif |
mbed_official | 146:f64d43ff0c18 | 2010 | |
mbed_official | 146:f64d43ff0c18 | 2011 | //! @brief Format value for bitfield SDHC_PROCTL_WECINT. |
mbed_official | 146:f64d43ff0c18 | 2012 | #define BF_SDHC_PROCTL_WECINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_WECINT), uint32_t) & BM_SDHC_PROCTL_WECINT) |
mbed_official | 146:f64d43ff0c18 | 2013 | |
mbed_official | 146:f64d43ff0c18 | 2014 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2015 | //! @brief Set the WECINT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2016 | #define BW_SDHC_PROCTL_WECINT(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECINT) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2017 | #endif |
mbed_official | 146:f64d43ff0c18 | 2018 | //@} |
mbed_official | 146:f64d43ff0c18 | 2019 | |
mbed_official | 146:f64d43ff0c18 | 2020 | /*! |
mbed_official | 146:f64d43ff0c18 | 2021 | * @name Register SDHC_PROCTL, field WECINS[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 2022 | * |
mbed_official | 146:f64d43ff0c18 | 2023 | * Enables a wakeup event, via IRQSTAT[CINS]. FN_WUS (Wake Up Support) in CIS |
mbed_official | 146:f64d43ff0c18 | 2024 | * does not effect this bit. When this bit is set, IRQSTATEN[CINSEN] and the SDHC |
mbed_official | 146:f64d43ff0c18 | 2025 | * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is |
mbed_official | 146:f64d43ff0c18 | 2026 | * not enabled, the SD_CLK must be active to assert IRQSTATEN[CINSEN] and the SDHC |
mbed_official | 146:f64d43ff0c18 | 2027 | * interrupt. |
mbed_official | 146:f64d43ff0c18 | 2028 | * |
mbed_official | 146:f64d43ff0c18 | 2029 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2030 | * - 0 - Disabled |
mbed_official | 146:f64d43ff0c18 | 2031 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 2032 | */ |
mbed_official | 146:f64d43ff0c18 | 2033 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2034 | #define BP_SDHC_PROCTL_WECINS (25U) //!< Bit position for SDHC_PROCTL_WECINS. |
mbed_official | 146:f64d43ff0c18 | 2035 | #define BM_SDHC_PROCTL_WECINS (0x02000000U) //!< Bit mask for SDHC_PROCTL_WECINS. |
mbed_official | 146:f64d43ff0c18 | 2036 | #define BS_SDHC_PROCTL_WECINS (1U) //!< Bit field size in bits for SDHC_PROCTL_WECINS. |
mbed_official | 146:f64d43ff0c18 | 2037 | |
mbed_official | 146:f64d43ff0c18 | 2038 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2039 | //! @brief Read current value of the SDHC_PROCTL_WECINS field. |
mbed_official | 146:f64d43ff0c18 | 2040 | #define BR_SDHC_PROCTL_WECINS (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECINS)) |
mbed_official | 146:f64d43ff0c18 | 2041 | #endif |
mbed_official | 146:f64d43ff0c18 | 2042 | |
mbed_official | 146:f64d43ff0c18 | 2043 | //! @brief Format value for bitfield SDHC_PROCTL_WECINS. |
mbed_official | 146:f64d43ff0c18 | 2044 | #define BF_SDHC_PROCTL_WECINS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_WECINS), uint32_t) & BM_SDHC_PROCTL_WECINS) |
mbed_official | 146:f64d43ff0c18 | 2045 | |
mbed_official | 146:f64d43ff0c18 | 2046 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2047 | //! @brief Set the WECINS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2048 | #define BW_SDHC_PROCTL_WECINS(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECINS) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2049 | #endif |
mbed_official | 146:f64d43ff0c18 | 2050 | //@} |
mbed_official | 146:f64d43ff0c18 | 2051 | |
mbed_official | 146:f64d43ff0c18 | 2052 | /*! |
mbed_official | 146:f64d43ff0c18 | 2053 | * @name Register SDHC_PROCTL, field WECRM[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 2054 | * |
mbed_official | 146:f64d43ff0c18 | 2055 | * Enables a wakeup event, via IRQSTAT[CRM]. FN_WUS (Wake Up Support) in CIS |
mbed_official | 146:f64d43ff0c18 | 2056 | * does not effect this bit. When this bit is set, IRQSTAT[CRM] and the SDHC |
mbed_official | 146:f64d43ff0c18 | 2057 | * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is not |
mbed_official | 146:f64d43ff0c18 | 2058 | * enabled, the SD_CLK must be active to assert IRQSTAT[CRM] and the SDHC interrupt. |
mbed_official | 146:f64d43ff0c18 | 2059 | * |
mbed_official | 146:f64d43ff0c18 | 2060 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2061 | * - 0 - Disabled |
mbed_official | 146:f64d43ff0c18 | 2062 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 2063 | */ |
mbed_official | 146:f64d43ff0c18 | 2064 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2065 | #define BP_SDHC_PROCTL_WECRM (26U) //!< Bit position for SDHC_PROCTL_WECRM. |
mbed_official | 146:f64d43ff0c18 | 2066 | #define BM_SDHC_PROCTL_WECRM (0x04000000U) //!< Bit mask for SDHC_PROCTL_WECRM. |
mbed_official | 146:f64d43ff0c18 | 2067 | #define BS_SDHC_PROCTL_WECRM (1U) //!< Bit field size in bits for SDHC_PROCTL_WECRM. |
mbed_official | 146:f64d43ff0c18 | 2068 | |
mbed_official | 146:f64d43ff0c18 | 2069 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2070 | //! @brief Read current value of the SDHC_PROCTL_WECRM field. |
mbed_official | 146:f64d43ff0c18 | 2071 | #define BR_SDHC_PROCTL_WECRM (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECRM)) |
mbed_official | 146:f64d43ff0c18 | 2072 | #endif |
mbed_official | 146:f64d43ff0c18 | 2073 | |
mbed_official | 146:f64d43ff0c18 | 2074 | //! @brief Format value for bitfield SDHC_PROCTL_WECRM. |
mbed_official | 146:f64d43ff0c18 | 2075 | #define BF_SDHC_PROCTL_WECRM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_WECRM), uint32_t) & BM_SDHC_PROCTL_WECRM) |
mbed_official | 146:f64d43ff0c18 | 2076 | |
mbed_official | 146:f64d43ff0c18 | 2077 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2078 | //! @brief Set the WECRM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2079 | #define BW_SDHC_PROCTL_WECRM(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECRM) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2080 | #endif |
mbed_official | 146:f64d43ff0c18 | 2081 | //@} |
mbed_official | 146:f64d43ff0c18 | 2082 | |
mbed_official | 146:f64d43ff0c18 | 2083 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2084 | // HW_SDHC_SYSCTL - System Control register |
mbed_official | 146:f64d43ff0c18 | 2085 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2086 | |
mbed_official | 146:f64d43ff0c18 | 2087 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2088 | /*! |
mbed_official | 146:f64d43ff0c18 | 2089 | * @brief HW_SDHC_SYSCTL - System Control register (RW) |
mbed_official | 146:f64d43ff0c18 | 2090 | * |
mbed_official | 146:f64d43ff0c18 | 2091 | * Reset value: 0x00008008U |
mbed_official | 146:f64d43ff0c18 | 2092 | */ |
mbed_official | 146:f64d43ff0c18 | 2093 | typedef union _hw_sdhc_sysctl |
mbed_official | 146:f64d43ff0c18 | 2094 | { |
mbed_official | 146:f64d43ff0c18 | 2095 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 2096 | struct _hw_sdhc_sysctl_bitfields |
mbed_official | 146:f64d43ff0c18 | 2097 | { |
mbed_official | 146:f64d43ff0c18 | 2098 | uint32_t IPGEN : 1; //!< [0] IPG Clock Enable |
mbed_official | 146:f64d43ff0c18 | 2099 | uint32_t HCKEN : 1; //!< [1] System Clock Enable |
mbed_official | 146:f64d43ff0c18 | 2100 | uint32_t PEREN : 1; //!< [2] Peripheral Clock Enable |
mbed_official | 146:f64d43ff0c18 | 2101 | uint32_t SDCLKEN : 1; //!< [3] SD Clock Enable |
mbed_official | 146:f64d43ff0c18 | 2102 | uint32_t DVS : 4; //!< [7:4] Divisor |
mbed_official | 146:f64d43ff0c18 | 2103 | uint32_t SDCLKFS : 8; //!< [15:8] SDCLK Frequency Select |
mbed_official | 146:f64d43ff0c18 | 2104 | uint32_t DTOCV : 4; //!< [19:16] Data Timeout Counter Value |
mbed_official | 146:f64d43ff0c18 | 2105 | uint32_t RESERVED0 : 4; //!< [23:20] |
mbed_official | 146:f64d43ff0c18 | 2106 | uint32_t RSTA : 1; //!< [24] Software Reset For ALL |
mbed_official | 146:f64d43ff0c18 | 2107 | uint32_t RSTC : 1; //!< [25] Software Reset For CMD Line |
mbed_official | 146:f64d43ff0c18 | 2108 | uint32_t RSTD : 1; //!< [26] Software Reset For DAT Line |
mbed_official | 146:f64d43ff0c18 | 2109 | uint32_t INITA : 1; //!< [27] Initialization Active |
mbed_official | 146:f64d43ff0c18 | 2110 | uint32_t RESERVED1 : 4; //!< [31:28] |
mbed_official | 146:f64d43ff0c18 | 2111 | } B; |
mbed_official | 146:f64d43ff0c18 | 2112 | } hw_sdhc_sysctl_t; |
mbed_official | 146:f64d43ff0c18 | 2113 | #endif |
mbed_official | 146:f64d43ff0c18 | 2114 | |
mbed_official | 146:f64d43ff0c18 | 2115 | /*! |
mbed_official | 146:f64d43ff0c18 | 2116 | * @name Constants and macros for entire SDHC_SYSCTL register |
mbed_official | 146:f64d43ff0c18 | 2117 | */ |
mbed_official | 146:f64d43ff0c18 | 2118 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2119 | #define HW_SDHC_SYSCTL_ADDR (REGS_SDHC_BASE + 0x2CU) |
mbed_official | 146:f64d43ff0c18 | 2120 | |
mbed_official | 146:f64d43ff0c18 | 2121 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2122 | #define HW_SDHC_SYSCTL (*(__IO hw_sdhc_sysctl_t *) HW_SDHC_SYSCTL_ADDR) |
mbed_official | 146:f64d43ff0c18 | 2123 | #define HW_SDHC_SYSCTL_RD() (HW_SDHC_SYSCTL.U) |
mbed_official | 146:f64d43ff0c18 | 2124 | #define HW_SDHC_SYSCTL_WR(v) (HW_SDHC_SYSCTL.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 2125 | #define HW_SDHC_SYSCTL_SET(v) (HW_SDHC_SYSCTL_WR(HW_SDHC_SYSCTL_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 2126 | #define HW_SDHC_SYSCTL_CLR(v) (HW_SDHC_SYSCTL_WR(HW_SDHC_SYSCTL_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 2127 | #define HW_SDHC_SYSCTL_TOG(v) (HW_SDHC_SYSCTL_WR(HW_SDHC_SYSCTL_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 2128 | #endif |
mbed_official | 146:f64d43ff0c18 | 2129 | //@} |
mbed_official | 146:f64d43ff0c18 | 2130 | |
mbed_official | 146:f64d43ff0c18 | 2131 | /* |
mbed_official | 146:f64d43ff0c18 | 2132 | * Constants & macros for individual SDHC_SYSCTL bitfields |
mbed_official | 146:f64d43ff0c18 | 2133 | */ |
mbed_official | 146:f64d43ff0c18 | 2134 | |
mbed_official | 146:f64d43ff0c18 | 2135 | /*! |
mbed_official | 146:f64d43ff0c18 | 2136 | * @name Register SDHC_SYSCTL, field IPGEN[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 2137 | * |
mbed_official | 146:f64d43ff0c18 | 2138 | * If this bit is set, bus clock will always be active and no automatic gating |
mbed_official | 146:f64d43ff0c18 | 2139 | * is applied. The bus clock will be internally gated off, if none of the |
mbed_official | 146:f64d43ff0c18 | 2140 | * following factors are met: The cmd part is reset, or Data part is reset, or Soft |
mbed_official | 146:f64d43ff0c18 | 2141 | * reset, or The cmd is about to send, or Clock divisor is just updated, or Continue |
mbed_official | 146:f64d43ff0c18 | 2142 | * request is just set, or This bit is set, or Card insertion is detected, or Card |
mbed_official | 146:f64d43ff0c18 | 2143 | * removal is detected, or Card external interrupt is detected, or The SDHC |
mbed_official | 146:f64d43ff0c18 | 2144 | * clock is not gated off The bus clock will not be auto gated off if the SDHC clock |
mbed_official | 146:f64d43ff0c18 | 2145 | * is not gated off. So clearing only this bit has no effect unless the PEREN bit |
mbed_official | 146:f64d43ff0c18 | 2146 | * is also cleared. |
mbed_official | 146:f64d43ff0c18 | 2147 | * |
mbed_official | 146:f64d43ff0c18 | 2148 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2149 | * - 0 - Bus clock will be internally gated off. |
mbed_official | 146:f64d43ff0c18 | 2150 | * - 1 - Bus clock will not be automatically gated off. |
mbed_official | 146:f64d43ff0c18 | 2151 | */ |
mbed_official | 146:f64d43ff0c18 | 2152 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2153 | #define BP_SDHC_SYSCTL_IPGEN (0U) //!< Bit position for SDHC_SYSCTL_IPGEN. |
mbed_official | 146:f64d43ff0c18 | 2154 | #define BM_SDHC_SYSCTL_IPGEN (0x00000001U) //!< Bit mask for SDHC_SYSCTL_IPGEN. |
mbed_official | 146:f64d43ff0c18 | 2155 | #define BS_SDHC_SYSCTL_IPGEN (1U) //!< Bit field size in bits for SDHC_SYSCTL_IPGEN. |
mbed_official | 146:f64d43ff0c18 | 2156 | |
mbed_official | 146:f64d43ff0c18 | 2157 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2158 | //! @brief Read current value of the SDHC_SYSCTL_IPGEN field. |
mbed_official | 146:f64d43ff0c18 | 2159 | #define BR_SDHC_SYSCTL_IPGEN (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_IPGEN)) |
mbed_official | 146:f64d43ff0c18 | 2160 | #endif |
mbed_official | 146:f64d43ff0c18 | 2161 | |
mbed_official | 146:f64d43ff0c18 | 2162 | //! @brief Format value for bitfield SDHC_SYSCTL_IPGEN. |
mbed_official | 146:f64d43ff0c18 | 2163 | #define BF_SDHC_SYSCTL_IPGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_IPGEN), uint32_t) & BM_SDHC_SYSCTL_IPGEN) |
mbed_official | 146:f64d43ff0c18 | 2164 | |
mbed_official | 146:f64d43ff0c18 | 2165 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2166 | //! @brief Set the IPGEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2167 | #define BW_SDHC_SYSCTL_IPGEN(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_IPGEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2168 | #endif |
mbed_official | 146:f64d43ff0c18 | 2169 | //@} |
mbed_official | 146:f64d43ff0c18 | 2170 | |
mbed_official | 146:f64d43ff0c18 | 2171 | /*! |
mbed_official | 146:f64d43ff0c18 | 2172 | * @name Register SDHC_SYSCTL, field HCKEN[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 2173 | * |
mbed_official | 146:f64d43ff0c18 | 2174 | * If this bit is set, system clock will always be active and no automatic |
mbed_official | 146:f64d43ff0c18 | 2175 | * gating is applied. When this bit is cleared, system clock will be automatically off |
mbed_official | 146:f64d43ff0c18 | 2176 | * when no data transfer is on the SD bus. |
mbed_official | 146:f64d43ff0c18 | 2177 | * |
mbed_official | 146:f64d43ff0c18 | 2178 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2179 | * - 0 - System clock will be internally gated off. |
mbed_official | 146:f64d43ff0c18 | 2180 | * - 1 - System clock will not be automatically gated off. |
mbed_official | 146:f64d43ff0c18 | 2181 | */ |
mbed_official | 146:f64d43ff0c18 | 2182 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2183 | #define BP_SDHC_SYSCTL_HCKEN (1U) //!< Bit position for SDHC_SYSCTL_HCKEN. |
mbed_official | 146:f64d43ff0c18 | 2184 | #define BM_SDHC_SYSCTL_HCKEN (0x00000002U) //!< Bit mask for SDHC_SYSCTL_HCKEN. |
mbed_official | 146:f64d43ff0c18 | 2185 | #define BS_SDHC_SYSCTL_HCKEN (1U) //!< Bit field size in bits for SDHC_SYSCTL_HCKEN. |
mbed_official | 146:f64d43ff0c18 | 2186 | |
mbed_official | 146:f64d43ff0c18 | 2187 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2188 | //! @brief Read current value of the SDHC_SYSCTL_HCKEN field. |
mbed_official | 146:f64d43ff0c18 | 2189 | #define BR_SDHC_SYSCTL_HCKEN (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_HCKEN)) |
mbed_official | 146:f64d43ff0c18 | 2190 | #endif |
mbed_official | 146:f64d43ff0c18 | 2191 | |
mbed_official | 146:f64d43ff0c18 | 2192 | //! @brief Format value for bitfield SDHC_SYSCTL_HCKEN. |
mbed_official | 146:f64d43ff0c18 | 2193 | #define BF_SDHC_SYSCTL_HCKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_HCKEN), uint32_t) & BM_SDHC_SYSCTL_HCKEN) |
mbed_official | 146:f64d43ff0c18 | 2194 | |
mbed_official | 146:f64d43ff0c18 | 2195 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2196 | //! @brief Set the HCKEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2197 | #define BW_SDHC_SYSCTL_HCKEN(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_HCKEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2198 | #endif |
mbed_official | 146:f64d43ff0c18 | 2199 | //@} |
mbed_official | 146:f64d43ff0c18 | 2200 | |
mbed_official | 146:f64d43ff0c18 | 2201 | /*! |
mbed_official | 146:f64d43ff0c18 | 2202 | * @name Register SDHC_SYSCTL, field PEREN[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 2203 | * |
mbed_official | 146:f64d43ff0c18 | 2204 | * If this bit is set, SDHC clock will always be active and no automatic gating |
mbed_official | 146:f64d43ff0c18 | 2205 | * is applied. Thus the SDCLK is active except for when auto gating-off during |
mbed_official | 146:f64d43ff0c18 | 2206 | * buffer danger (buffer about to over-run or under-run). When this bit is cleared, |
mbed_official | 146:f64d43ff0c18 | 2207 | * the SDHC clock will be automatically off whenever there is no transaction on |
mbed_official | 146:f64d43ff0c18 | 2208 | * the SD bus. Because this bit is only a feature enabling bit, clearing this bit |
mbed_official | 146:f64d43ff0c18 | 2209 | * does not stop SDCLK immediately. The SDHC clock will be internally gated off, |
mbed_official | 146:f64d43ff0c18 | 2210 | * if none of the following factors are met: The cmd part is reset, or Data part |
mbed_official | 146:f64d43ff0c18 | 2211 | * is reset, or A soft reset, or The cmd is about to send, or Clock divisor is |
mbed_official | 146:f64d43ff0c18 | 2212 | * just updated, or Continue request is just set, or This bit is set, or Card |
mbed_official | 146:f64d43ff0c18 | 2213 | * insertion is detected, or Card removal is detected, or Card external interrupt is |
mbed_official | 146:f64d43ff0c18 | 2214 | * detected, or 80 clocks for initialization phase is ongoing |
mbed_official | 146:f64d43ff0c18 | 2215 | * |
mbed_official | 146:f64d43ff0c18 | 2216 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2217 | * - 0 - SDHC clock will be internally gated off. |
mbed_official | 146:f64d43ff0c18 | 2218 | * - 1 - SDHC clock will not be automatically gated off. |
mbed_official | 146:f64d43ff0c18 | 2219 | */ |
mbed_official | 146:f64d43ff0c18 | 2220 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2221 | #define BP_SDHC_SYSCTL_PEREN (2U) //!< Bit position for SDHC_SYSCTL_PEREN. |
mbed_official | 146:f64d43ff0c18 | 2222 | #define BM_SDHC_SYSCTL_PEREN (0x00000004U) //!< Bit mask for SDHC_SYSCTL_PEREN. |
mbed_official | 146:f64d43ff0c18 | 2223 | #define BS_SDHC_SYSCTL_PEREN (1U) //!< Bit field size in bits for SDHC_SYSCTL_PEREN. |
mbed_official | 146:f64d43ff0c18 | 2224 | |
mbed_official | 146:f64d43ff0c18 | 2225 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2226 | //! @brief Read current value of the SDHC_SYSCTL_PEREN field. |
mbed_official | 146:f64d43ff0c18 | 2227 | #define BR_SDHC_SYSCTL_PEREN (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_PEREN)) |
mbed_official | 146:f64d43ff0c18 | 2228 | #endif |
mbed_official | 146:f64d43ff0c18 | 2229 | |
mbed_official | 146:f64d43ff0c18 | 2230 | //! @brief Format value for bitfield SDHC_SYSCTL_PEREN. |
mbed_official | 146:f64d43ff0c18 | 2231 | #define BF_SDHC_SYSCTL_PEREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_PEREN), uint32_t) & BM_SDHC_SYSCTL_PEREN) |
mbed_official | 146:f64d43ff0c18 | 2232 | |
mbed_official | 146:f64d43ff0c18 | 2233 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2234 | //! @brief Set the PEREN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2235 | #define BW_SDHC_SYSCTL_PEREN(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_PEREN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2236 | #endif |
mbed_official | 146:f64d43ff0c18 | 2237 | //@} |
mbed_official | 146:f64d43ff0c18 | 2238 | |
mbed_official | 146:f64d43ff0c18 | 2239 | /*! |
mbed_official | 146:f64d43ff0c18 | 2240 | * @name Register SDHC_SYSCTL, field SDCLKEN[3] (RW) |
mbed_official | 146:f64d43ff0c18 | 2241 | * |
mbed_official | 146:f64d43ff0c18 | 2242 | * The host controller shall stop SDCLK when writing this bit to 0. SDCLK |
mbed_official | 146:f64d43ff0c18 | 2243 | * frequency can be changed when this bit is 0. Then, the host controller shall |
mbed_official | 146:f64d43ff0c18 | 2244 | * maintain the same clock frequency until SDCLK is stopped (stop at SDCLK = 0). If the |
mbed_official | 146:f64d43ff0c18 | 2245 | * IRQSTAT[CINS] is cleared, this bit must be cleared by the host driver to save |
mbed_official | 146:f64d43ff0c18 | 2246 | * power. |
mbed_official | 146:f64d43ff0c18 | 2247 | */ |
mbed_official | 146:f64d43ff0c18 | 2248 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2249 | #define BP_SDHC_SYSCTL_SDCLKEN (3U) //!< Bit position for SDHC_SYSCTL_SDCLKEN. |
mbed_official | 146:f64d43ff0c18 | 2250 | #define BM_SDHC_SYSCTL_SDCLKEN (0x00000008U) //!< Bit mask for SDHC_SYSCTL_SDCLKEN. |
mbed_official | 146:f64d43ff0c18 | 2251 | #define BS_SDHC_SYSCTL_SDCLKEN (1U) //!< Bit field size in bits for SDHC_SYSCTL_SDCLKEN. |
mbed_official | 146:f64d43ff0c18 | 2252 | |
mbed_official | 146:f64d43ff0c18 | 2253 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2254 | //! @brief Read current value of the SDHC_SYSCTL_SDCLKEN field. |
mbed_official | 146:f64d43ff0c18 | 2255 | #define BR_SDHC_SYSCTL_SDCLKEN (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_SDCLKEN)) |
mbed_official | 146:f64d43ff0c18 | 2256 | #endif |
mbed_official | 146:f64d43ff0c18 | 2257 | |
mbed_official | 146:f64d43ff0c18 | 2258 | //! @brief Format value for bitfield SDHC_SYSCTL_SDCLKEN. |
mbed_official | 146:f64d43ff0c18 | 2259 | #define BF_SDHC_SYSCTL_SDCLKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_SDCLKEN), uint32_t) & BM_SDHC_SYSCTL_SDCLKEN) |
mbed_official | 146:f64d43ff0c18 | 2260 | |
mbed_official | 146:f64d43ff0c18 | 2261 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2262 | //! @brief Set the SDCLKEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2263 | #define BW_SDHC_SYSCTL_SDCLKEN(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_SDCLKEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2264 | #endif |
mbed_official | 146:f64d43ff0c18 | 2265 | //@} |
mbed_official | 146:f64d43ff0c18 | 2266 | |
mbed_official | 146:f64d43ff0c18 | 2267 | /*! |
mbed_official | 146:f64d43ff0c18 | 2268 | * @name Register SDHC_SYSCTL, field DVS[7:4] (RW) |
mbed_official | 146:f64d43ff0c18 | 2269 | * |
mbed_official | 146:f64d43ff0c18 | 2270 | * Used to provide a more exact divisor to generate the desired SD clock |
mbed_official | 146:f64d43ff0c18 | 2271 | * frequency. Note the divider can even support odd divisor without deterioration of |
mbed_official | 146:f64d43ff0c18 | 2272 | * duty cycle. The setting are as following: |
mbed_official | 146:f64d43ff0c18 | 2273 | * |
mbed_official | 146:f64d43ff0c18 | 2274 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2275 | * - 0 - Divisor by 1. |
mbed_official | 146:f64d43ff0c18 | 2276 | * - 1 - Divisor by 2. |
mbed_official | 146:f64d43ff0c18 | 2277 | * - 1110 - Divisor by 15. |
mbed_official | 146:f64d43ff0c18 | 2278 | * - 1111 - Divisor by 16. |
mbed_official | 146:f64d43ff0c18 | 2279 | */ |
mbed_official | 146:f64d43ff0c18 | 2280 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2281 | #define BP_SDHC_SYSCTL_DVS (4U) //!< Bit position for SDHC_SYSCTL_DVS. |
mbed_official | 146:f64d43ff0c18 | 2282 | #define BM_SDHC_SYSCTL_DVS (0x000000F0U) //!< Bit mask for SDHC_SYSCTL_DVS. |
mbed_official | 146:f64d43ff0c18 | 2283 | #define BS_SDHC_SYSCTL_DVS (4U) //!< Bit field size in bits for SDHC_SYSCTL_DVS. |
mbed_official | 146:f64d43ff0c18 | 2284 | |
mbed_official | 146:f64d43ff0c18 | 2285 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2286 | //! @brief Read current value of the SDHC_SYSCTL_DVS field. |
mbed_official | 146:f64d43ff0c18 | 2287 | #define BR_SDHC_SYSCTL_DVS (HW_SDHC_SYSCTL.B.DVS) |
mbed_official | 146:f64d43ff0c18 | 2288 | #endif |
mbed_official | 146:f64d43ff0c18 | 2289 | |
mbed_official | 146:f64d43ff0c18 | 2290 | //! @brief Format value for bitfield SDHC_SYSCTL_DVS. |
mbed_official | 146:f64d43ff0c18 | 2291 | #define BF_SDHC_SYSCTL_DVS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_DVS), uint32_t) & BM_SDHC_SYSCTL_DVS) |
mbed_official | 146:f64d43ff0c18 | 2292 | |
mbed_official | 146:f64d43ff0c18 | 2293 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2294 | //! @brief Set the DVS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2295 | #define BW_SDHC_SYSCTL_DVS(v) (HW_SDHC_SYSCTL_WR((HW_SDHC_SYSCTL_RD() & ~BM_SDHC_SYSCTL_DVS) | BF_SDHC_SYSCTL_DVS(v))) |
mbed_official | 146:f64d43ff0c18 | 2296 | #endif |
mbed_official | 146:f64d43ff0c18 | 2297 | //@} |
mbed_official | 146:f64d43ff0c18 | 2298 | |
mbed_official | 146:f64d43ff0c18 | 2299 | /*! |
mbed_official | 146:f64d43ff0c18 | 2300 | * @name Register SDHC_SYSCTL, field SDCLKFS[15:8] (RW) |
mbed_official | 146:f64d43ff0c18 | 2301 | * |
mbed_official | 146:f64d43ff0c18 | 2302 | * Used to select the frequency of the SDCLK pin. The frequency is not |
mbed_official | 146:f64d43ff0c18 | 2303 | * programmed directly. Rather this register holds the prescaler (this register) and |
mbed_official | 146:f64d43ff0c18 | 2304 | * divisor (next register) of the base clock frequency register. Setting 00h bypasses |
mbed_official | 146:f64d43ff0c18 | 2305 | * the frequency prescaler of the SD Clock. Multiple bits must not be set, or the |
mbed_official | 146:f64d43ff0c18 | 2306 | * behavior of this prescaler is undefined. The two default divider values can |
mbed_official | 146:f64d43ff0c18 | 2307 | * be calculated by the frequency of SDHC clock and the following divisor bits. |
mbed_official | 146:f64d43ff0c18 | 2308 | * The frequency of SDCLK is set by the following formula: Clock frequency = (Base |
mbed_official | 146:f64d43ff0c18 | 2309 | * clock) / (prescaler x divisor) For example, if the base clock frequency is 96 |
mbed_official | 146:f64d43ff0c18 | 2310 | * MHz, and the target frequency is 25 MHz, then choosing the prescaler value of |
mbed_official | 146:f64d43ff0c18 | 2311 | * 01h and divisor value of 1h will yield 24 MHz, which is the nearest frequency |
mbed_official | 146:f64d43ff0c18 | 2312 | * less than or equal to the target. Similarly, to approach a clock value of 400 |
mbed_official | 146:f64d43ff0c18 | 2313 | * kHz, the prescaler value of 08h and divisor value of eh yields the exact clock |
mbed_official | 146:f64d43ff0c18 | 2314 | * value of 400 kHz. The reset value of this field is 80h, so if the input base |
mbed_official | 146:f64d43ff0c18 | 2315 | * clock ( SDHC clock ) is about 96 MHz, the default SD clock after reset is 375 |
mbed_official | 146:f64d43ff0c18 | 2316 | * kHz. According to the SD Physical Specification Version 1.1 and the SDIO Card |
mbed_official | 146:f64d43ff0c18 | 2317 | * Specification Version 1.2, the maximum SD clock frequency is 50 MHz and shall |
mbed_official | 146:f64d43ff0c18 | 2318 | * never exceed this limit. Only the following settings are allowed: |
mbed_official | 146:f64d43ff0c18 | 2319 | * |
mbed_official | 146:f64d43ff0c18 | 2320 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2321 | * - 1 - Base clock divided by 2. |
mbed_official | 146:f64d43ff0c18 | 2322 | * - 10 - Base clock divided by 4. |
mbed_official | 146:f64d43ff0c18 | 2323 | * - 100 - Base clock divided by 8. |
mbed_official | 146:f64d43ff0c18 | 2324 | * - 1000 - Base clock divided by 16. |
mbed_official | 146:f64d43ff0c18 | 2325 | * - 10000 - Base clock divided by 32. |
mbed_official | 146:f64d43ff0c18 | 2326 | * - 100000 - Base clock divided by 64. |
mbed_official | 146:f64d43ff0c18 | 2327 | * - 1000000 - Base clock divided by 128. |
mbed_official | 146:f64d43ff0c18 | 2328 | * - 10000000 - Base clock divided by 256. |
mbed_official | 146:f64d43ff0c18 | 2329 | */ |
mbed_official | 146:f64d43ff0c18 | 2330 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2331 | #define BP_SDHC_SYSCTL_SDCLKFS (8U) //!< Bit position for SDHC_SYSCTL_SDCLKFS. |
mbed_official | 146:f64d43ff0c18 | 2332 | #define BM_SDHC_SYSCTL_SDCLKFS (0x0000FF00U) //!< Bit mask for SDHC_SYSCTL_SDCLKFS. |
mbed_official | 146:f64d43ff0c18 | 2333 | #define BS_SDHC_SYSCTL_SDCLKFS (8U) //!< Bit field size in bits for SDHC_SYSCTL_SDCLKFS. |
mbed_official | 146:f64d43ff0c18 | 2334 | |
mbed_official | 146:f64d43ff0c18 | 2335 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2336 | //! @brief Read current value of the SDHC_SYSCTL_SDCLKFS field. |
mbed_official | 146:f64d43ff0c18 | 2337 | #define BR_SDHC_SYSCTL_SDCLKFS (HW_SDHC_SYSCTL.B.SDCLKFS) |
mbed_official | 146:f64d43ff0c18 | 2338 | #endif |
mbed_official | 146:f64d43ff0c18 | 2339 | |
mbed_official | 146:f64d43ff0c18 | 2340 | //! @brief Format value for bitfield SDHC_SYSCTL_SDCLKFS. |
mbed_official | 146:f64d43ff0c18 | 2341 | #define BF_SDHC_SYSCTL_SDCLKFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_SDCLKFS), uint32_t) & BM_SDHC_SYSCTL_SDCLKFS) |
mbed_official | 146:f64d43ff0c18 | 2342 | |
mbed_official | 146:f64d43ff0c18 | 2343 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2344 | //! @brief Set the SDCLKFS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2345 | #define BW_SDHC_SYSCTL_SDCLKFS(v) (HW_SDHC_SYSCTL_WR((HW_SDHC_SYSCTL_RD() & ~BM_SDHC_SYSCTL_SDCLKFS) | BF_SDHC_SYSCTL_SDCLKFS(v))) |
mbed_official | 146:f64d43ff0c18 | 2346 | #endif |
mbed_official | 146:f64d43ff0c18 | 2347 | //@} |
mbed_official | 146:f64d43ff0c18 | 2348 | |
mbed_official | 146:f64d43ff0c18 | 2349 | /*! |
mbed_official | 146:f64d43ff0c18 | 2350 | * @name Register SDHC_SYSCTL, field DTOCV[19:16] (RW) |
mbed_official | 146:f64d43ff0c18 | 2351 | * |
mbed_official | 146:f64d43ff0c18 | 2352 | * Determines the interval by which DAT line timeouts are detected. See |
mbed_official | 146:f64d43ff0c18 | 2353 | * IRQSTAT[DTOE] for information on factors that dictate time-out generation. Time-out |
mbed_official | 146:f64d43ff0c18 | 2354 | * clock frequency will be generated by dividing the base clock SDCLK value by this |
mbed_official | 146:f64d43ff0c18 | 2355 | * value. The host driver can clear IRQSTATEN[DTOESEN] to prevent inadvertent |
mbed_official | 146:f64d43ff0c18 | 2356 | * time-out events. |
mbed_official | 146:f64d43ff0c18 | 2357 | * |
mbed_official | 146:f64d43ff0c18 | 2358 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2359 | * - 0000 - SDCLK x 2 13 |
mbed_official | 146:f64d43ff0c18 | 2360 | * - 0001 - SDCLK x 2 14 |
mbed_official | 146:f64d43ff0c18 | 2361 | * - 1110 - SDCLK x 2 27 |
mbed_official | 146:f64d43ff0c18 | 2362 | * - 1111 - Reserved |
mbed_official | 146:f64d43ff0c18 | 2363 | */ |
mbed_official | 146:f64d43ff0c18 | 2364 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2365 | #define BP_SDHC_SYSCTL_DTOCV (16U) //!< Bit position for SDHC_SYSCTL_DTOCV. |
mbed_official | 146:f64d43ff0c18 | 2366 | #define BM_SDHC_SYSCTL_DTOCV (0x000F0000U) //!< Bit mask for SDHC_SYSCTL_DTOCV. |
mbed_official | 146:f64d43ff0c18 | 2367 | #define BS_SDHC_SYSCTL_DTOCV (4U) //!< Bit field size in bits for SDHC_SYSCTL_DTOCV. |
mbed_official | 146:f64d43ff0c18 | 2368 | |
mbed_official | 146:f64d43ff0c18 | 2369 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2370 | //! @brief Read current value of the SDHC_SYSCTL_DTOCV field. |
mbed_official | 146:f64d43ff0c18 | 2371 | #define BR_SDHC_SYSCTL_DTOCV (HW_SDHC_SYSCTL.B.DTOCV) |
mbed_official | 146:f64d43ff0c18 | 2372 | #endif |
mbed_official | 146:f64d43ff0c18 | 2373 | |
mbed_official | 146:f64d43ff0c18 | 2374 | //! @brief Format value for bitfield SDHC_SYSCTL_DTOCV. |
mbed_official | 146:f64d43ff0c18 | 2375 | #define BF_SDHC_SYSCTL_DTOCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_DTOCV), uint32_t) & BM_SDHC_SYSCTL_DTOCV) |
mbed_official | 146:f64d43ff0c18 | 2376 | |
mbed_official | 146:f64d43ff0c18 | 2377 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2378 | //! @brief Set the DTOCV field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2379 | #define BW_SDHC_SYSCTL_DTOCV(v) (HW_SDHC_SYSCTL_WR((HW_SDHC_SYSCTL_RD() & ~BM_SDHC_SYSCTL_DTOCV) | BF_SDHC_SYSCTL_DTOCV(v))) |
mbed_official | 146:f64d43ff0c18 | 2380 | #endif |
mbed_official | 146:f64d43ff0c18 | 2381 | //@} |
mbed_official | 146:f64d43ff0c18 | 2382 | |
mbed_official | 146:f64d43ff0c18 | 2383 | /*! |
mbed_official | 146:f64d43ff0c18 | 2384 | * @name Register SDHC_SYSCTL, field RSTA[24] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 2385 | * |
mbed_official | 146:f64d43ff0c18 | 2386 | * Effects the entire host controller except for the card detection circuit. |
mbed_official | 146:f64d43ff0c18 | 2387 | * Register bits of type ROC, RW, RW1C, RWAC are cleared. During its initialization, |
mbed_official | 146:f64d43ff0c18 | 2388 | * the host driver shall set this bit to 1 to reset the SDHC. The SDHC shall |
mbed_official | 146:f64d43ff0c18 | 2389 | * reset this bit to 0 when the capabilities registers are valid and the host driver |
mbed_official | 146:f64d43ff0c18 | 2390 | * can read them. Additional use of software reset for all does not affect the |
mbed_official | 146:f64d43ff0c18 | 2391 | * value of the capabilities registers. After this bit is set, it is recommended |
mbed_official | 146:f64d43ff0c18 | 2392 | * that the host driver reset the external card and reinitialize it. |
mbed_official | 146:f64d43ff0c18 | 2393 | * |
mbed_official | 146:f64d43ff0c18 | 2394 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2395 | * - 0 - No reset. |
mbed_official | 146:f64d43ff0c18 | 2396 | * - 1 - Reset. |
mbed_official | 146:f64d43ff0c18 | 2397 | */ |
mbed_official | 146:f64d43ff0c18 | 2398 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2399 | #define BP_SDHC_SYSCTL_RSTA (24U) //!< Bit position for SDHC_SYSCTL_RSTA. |
mbed_official | 146:f64d43ff0c18 | 2400 | #define BM_SDHC_SYSCTL_RSTA (0x01000000U) //!< Bit mask for SDHC_SYSCTL_RSTA. |
mbed_official | 146:f64d43ff0c18 | 2401 | #define BS_SDHC_SYSCTL_RSTA (1U) //!< Bit field size in bits for SDHC_SYSCTL_RSTA. |
mbed_official | 146:f64d43ff0c18 | 2402 | |
mbed_official | 146:f64d43ff0c18 | 2403 | //! @brief Format value for bitfield SDHC_SYSCTL_RSTA. |
mbed_official | 146:f64d43ff0c18 | 2404 | #define BF_SDHC_SYSCTL_RSTA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_RSTA), uint32_t) & BM_SDHC_SYSCTL_RSTA) |
mbed_official | 146:f64d43ff0c18 | 2405 | |
mbed_official | 146:f64d43ff0c18 | 2406 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2407 | //! @brief Set the RSTA field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2408 | #define BW_SDHC_SYSCTL_RSTA(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_RSTA) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2409 | #endif |
mbed_official | 146:f64d43ff0c18 | 2410 | //@} |
mbed_official | 146:f64d43ff0c18 | 2411 | |
mbed_official | 146:f64d43ff0c18 | 2412 | /*! |
mbed_official | 146:f64d43ff0c18 | 2413 | * @name Register SDHC_SYSCTL, field RSTC[25] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 2414 | * |
mbed_official | 146:f64d43ff0c18 | 2415 | * Only part of the command circuit is reset. The following registers and bits |
mbed_official | 146:f64d43ff0c18 | 2416 | * are cleared by this bit: PRSSTAT[CIHB] IRQSTAT[CC] |
mbed_official | 146:f64d43ff0c18 | 2417 | * |
mbed_official | 146:f64d43ff0c18 | 2418 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2419 | * - 0 - No reset. |
mbed_official | 146:f64d43ff0c18 | 2420 | * - 1 - Reset. |
mbed_official | 146:f64d43ff0c18 | 2421 | */ |
mbed_official | 146:f64d43ff0c18 | 2422 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2423 | #define BP_SDHC_SYSCTL_RSTC (25U) //!< Bit position for SDHC_SYSCTL_RSTC. |
mbed_official | 146:f64d43ff0c18 | 2424 | #define BM_SDHC_SYSCTL_RSTC (0x02000000U) //!< Bit mask for SDHC_SYSCTL_RSTC. |
mbed_official | 146:f64d43ff0c18 | 2425 | #define BS_SDHC_SYSCTL_RSTC (1U) //!< Bit field size in bits for SDHC_SYSCTL_RSTC. |
mbed_official | 146:f64d43ff0c18 | 2426 | |
mbed_official | 146:f64d43ff0c18 | 2427 | //! @brief Format value for bitfield SDHC_SYSCTL_RSTC. |
mbed_official | 146:f64d43ff0c18 | 2428 | #define BF_SDHC_SYSCTL_RSTC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_RSTC), uint32_t) & BM_SDHC_SYSCTL_RSTC) |
mbed_official | 146:f64d43ff0c18 | 2429 | |
mbed_official | 146:f64d43ff0c18 | 2430 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2431 | //! @brief Set the RSTC field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2432 | #define BW_SDHC_SYSCTL_RSTC(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_RSTC) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2433 | #endif |
mbed_official | 146:f64d43ff0c18 | 2434 | //@} |
mbed_official | 146:f64d43ff0c18 | 2435 | |
mbed_official | 146:f64d43ff0c18 | 2436 | /*! |
mbed_official | 146:f64d43ff0c18 | 2437 | * @name Register SDHC_SYSCTL, field RSTD[26] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 2438 | * |
mbed_official | 146:f64d43ff0c18 | 2439 | * Only part of the data circuit is reset. DMA circuit is also reset. The |
mbed_official | 146:f64d43ff0c18 | 2440 | * following registers and bits are cleared by this bit: Data Port register Buffer Is |
mbed_official | 146:f64d43ff0c18 | 2441 | * Cleared And Initialized.Present State register Buffer Read Enable Buffer Write |
mbed_official | 146:f64d43ff0c18 | 2442 | * Enable Read Transfer Active Write Transfer Active DAT Line Active Command |
mbed_official | 146:f64d43ff0c18 | 2443 | * Inhibit (DAT) Protocol Control register Continue Request Stop At Block Gap Request |
mbed_official | 146:f64d43ff0c18 | 2444 | * Interrupt Status register Buffer Read Ready Buffer Write Ready DMA Interrupt |
mbed_official | 146:f64d43ff0c18 | 2445 | * Block Gap Event Transfer Complete |
mbed_official | 146:f64d43ff0c18 | 2446 | * |
mbed_official | 146:f64d43ff0c18 | 2447 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2448 | * - 0 - No reset. |
mbed_official | 146:f64d43ff0c18 | 2449 | * - 1 - Reset. |
mbed_official | 146:f64d43ff0c18 | 2450 | */ |
mbed_official | 146:f64d43ff0c18 | 2451 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2452 | #define BP_SDHC_SYSCTL_RSTD (26U) //!< Bit position for SDHC_SYSCTL_RSTD. |
mbed_official | 146:f64d43ff0c18 | 2453 | #define BM_SDHC_SYSCTL_RSTD (0x04000000U) //!< Bit mask for SDHC_SYSCTL_RSTD. |
mbed_official | 146:f64d43ff0c18 | 2454 | #define BS_SDHC_SYSCTL_RSTD (1U) //!< Bit field size in bits for SDHC_SYSCTL_RSTD. |
mbed_official | 146:f64d43ff0c18 | 2455 | |
mbed_official | 146:f64d43ff0c18 | 2456 | //! @brief Format value for bitfield SDHC_SYSCTL_RSTD. |
mbed_official | 146:f64d43ff0c18 | 2457 | #define BF_SDHC_SYSCTL_RSTD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_RSTD), uint32_t) & BM_SDHC_SYSCTL_RSTD) |
mbed_official | 146:f64d43ff0c18 | 2458 | |
mbed_official | 146:f64d43ff0c18 | 2459 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2460 | //! @brief Set the RSTD field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2461 | #define BW_SDHC_SYSCTL_RSTD(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_RSTD) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2462 | #endif |
mbed_official | 146:f64d43ff0c18 | 2463 | //@} |
mbed_official | 146:f64d43ff0c18 | 2464 | |
mbed_official | 146:f64d43ff0c18 | 2465 | /*! |
mbed_official | 146:f64d43ff0c18 | 2466 | * @name Register SDHC_SYSCTL, field INITA[27] (RW) |
mbed_official | 146:f64d43ff0c18 | 2467 | * |
mbed_official | 146:f64d43ff0c18 | 2468 | * When this bit is set, 80 SD-clocks are sent to the card. After the 80 clocks |
mbed_official | 146:f64d43ff0c18 | 2469 | * are sent, this bit is self-cleared. This bit is very useful during the card |
mbed_official | 146:f64d43ff0c18 | 2470 | * power-up period when 74 SD-clocks are needed and the clock auto gating feature |
mbed_official | 146:f64d43ff0c18 | 2471 | * is enabled. Writing 1 to this bit when this bit is already 1 has no effect. |
mbed_official | 146:f64d43ff0c18 | 2472 | * Writing 0 to this bit at any time has no effect. When either of the PRSSTAT[CIHB] |
mbed_official | 146:f64d43ff0c18 | 2473 | * and PRSSTAT[CDIHB] bits are set, writing 1 to this bit is ignored, that is, |
mbed_official | 146:f64d43ff0c18 | 2474 | * when command line or data lines are active, write to this bit is not allowed. |
mbed_official | 146:f64d43ff0c18 | 2475 | * On the otherhand, when this bit is set, that is, during intialization active |
mbed_official | 146:f64d43ff0c18 | 2476 | * period, it is allowed to issue command, and the command bit stream will appear |
mbed_official | 146:f64d43ff0c18 | 2477 | * on the CMD pad after all 80 clock cycles are done. So when this command ends, |
mbed_official | 146:f64d43ff0c18 | 2478 | * the driver can make sure the 80 clock cycles are sent out. This is very useful |
mbed_official | 146:f64d43ff0c18 | 2479 | * when the driver needs send 80 cycles to the card and does not want to wait |
mbed_official | 146:f64d43ff0c18 | 2480 | * till this bit is self-cleared. |
mbed_official | 146:f64d43ff0c18 | 2481 | */ |
mbed_official | 146:f64d43ff0c18 | 2482 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2483 | #define BP_SDHC_SYSCTL_INITA (27U) //!< Bit position for SDHC_SYSCTL_INITA. |
mbed_official | 146:f64d43ff0c18 | 2484 | #define BM_SDHC_SYSCTL_INITA (0x08000000U) //!< Bit mask for SDHC_SYSCTL_INITA. |
mbed_official | 146:f64d43ff0c18 | 2485 | #define BS_SDHC_SYSCTL_INITA (1U) //!< Bit field size in bits for SDHC_SYSCTL_INITA. |
mbed_official | 146:f64d43ff0c18 | 2486 | |
mbed_official | 146:f64d43ff0c18 | 2487 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2488 | //! @brief Read current value of the SDHC_SYSCTL_INITA field. |
mbed_official | 146:f64d43ff0c18 | 2489 | #define BR_SDHC_SYSCTL_INITA (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_INITA)) |
mbed_official | 146:f64d43ff0c18 | 2490 | #endif |
mbed_official | 146:f64d43ff0c18 | 2491 | |
mbed_official | 146:f64d43ff0c18 | 2492 | //! @brief Format value for bitfield SDHC_SYSCTL_INITA. |
mbed_official | 146:f64d43ff0c18 | 2493 | #define BF_SDHC_SYSCTL_INITA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_INITA), uint32_t) & BM_SDHC_SYSCTL_INITA) |
mbed_official | 146:f64d43ff0c18 | 2494 | |
mbed_official | 146:f64d43ff0c18 | 2495 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2496 | //! @brief Set the INITA field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2497 | #define BW_SDHC_SYSCTL_INITA(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_INITA) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2498 | #endif |
mbed_official | 146:f64d43ff0c18 | 2499 | //@} |
mbed_official | 146:f64d43ff0c18 | 2500 | |
mbed_official | 146:f64d43ff0c18 | 2501 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2502 | // HW_SDHC_IRQSTAT - Interrupt Status register |
mbed_official | 146:f64d43ff0c18 | 2503 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2504 | |
mbed_official | 146:f64d43ff0c18 | 2505 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2506 | /*! |
mbed_official | 146:f64d43ff0c18 | 2507 | * @brief HW_SDHC_IRQSTAT - Interrupt Status register (RW) |
mbed_official | 146:f64d43ff0c18 | 2508 | * |
mbed_official | 146:f64d43ff0c18 | 2509 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 2510 | * |
mbed_official | 146:f64d43ff0c18 | 2511 | * An interrupt is generated when the Normal Interrupt Signal Enable is enabled |
mbed_official | 146:f64d43ff0c18 | 2512 | * and at least one of the status bits is set to 1. For all bits, writing 1 to a |
mbed_official | 146:f64d43ff0c18 | 2513 | * bit clears it; writing to 0 keeps the bit unchanged. More than one status can |
mbed_official | 146:f64d43ff0c18 | 2514 | * be cleared with a single register write. For Card Interrupt, before writing 1 |
mbed_official | 146:f64d43ff0c18 | 2515 | * to clear, it is required that the card stops asserting the interrupt, meaning |
mbed_official | 146:f64d43ff0c18 | 2516 | * that when the Card Driver services the interrupt condition, otherwise the CINT |
mbed_official | 146:f64d43ff0c18 | 2517 | * bit will be asserted again. The table below shows the relationship between |
mbed_official | 146:f64d43ff0c18 | 2518 | * the CTOE and the CC bits. SDHC status for CTOE/CC bit combinations Command |
mbed_official | 146:f64d43ff0c18 | 2519 | * complete Command timeout error Meaning of the status 0 0 X X 1 Response not |
mbed_official | 146:f64d43ff0c18 | 2520 | * received within 64 SDCLK cycles 1 0 Response received The table below shows the |
mbed_official | 146:f64d43ff0c18 | 2521 | * relationship between the Transfer Complete and the Data Timeout Error. SDHC status |
mbed_official | 146:f64d43ff0c18 | 2522 | * for data timeout error/transfer complete bit combinations Transfer complete |
mbed_official | 146:f64d43ff0c18 | 2523 | * Data timeout error Meaning of the status 0 0 X 0 1 Timeout occurred during |
mbed_official | 146:f64d43ff0c18 | 2524 | * transfer 1 X Data transfer complete The table below shows the relationship between |
mbed_official | 146:f64d43ff0c18 | 2525 | * the command CRC Error (CCE) and Command Timeout Error (CTOE). SDHC status for |
mbed_official | 146:f64d43ff0c18 | 2526 | * CCE/CTOE Bit Combinations Command complete Command timeout error Meaning of |
mbed_official | 146:f64d43ff0c18 | 2527 | * the status 0 0 No error 0 1 Response timeout error 1 0 Response CRC error 1 1 |
mbed_official | 146:f64d43ff0c18 | 2528 | * CMD line conflict |
mbed_official | 146:f64d43ff0c18 | 2529 | */ |
mbed_official | 146:f64d43ff0c18 | 2530 | typedef union _hw_sdhc_irqstat |
mbed_official | 146:f64d43ff0c18 | 2531 | { |
mbed_official | 146:f64d43ff0c18 | 2532 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 2533 | struct _hw_sdhc_irqstat_bitfields |
mbed_official | 146:f64d43ff0c18 | 2534 | { |
mbed_official | 146:f64d43ff0c18 | 2535 | uint32_t CC : 1; //!< [0] Command Complete |
mbed_official | 146:f64d43ff0c18 | 2536 | uint32_t TC : 1; //!< [1] Transfer Complete |
mbed_official | 146:f64d43ff0c18 | 2537 | uint32_t BGE : 1; //!< [2] Block Gap Event |
mbed_official | 146:f64d43ff0c18 | 2538 | uint32_t DINT : 1; //!< [3] DMA Interrupt |
mbed_official | 146:f64d43ff0c18 | 2539 | uint32_t BWR : 1; //!< [4] Buffer Write Ready |
mbed_official | 146:f64d43ff0c18 | 2540 | uint32_t BRR : 1; //!< [5] Buffer Read Ready |
mbed_official | 146:f64d43ff0c18 | 2541 | uint32_t CINS : 1; //!< [6] Card Insertion |
mbed_official | 146:f64d43ff0c18 | 2542 | uint32_t CRM : 1; //!< [7] Card Removal |
mbed_official | 146:f64d43ff0c18 | 2543 | uint32_t CINT : 1; //!< [8] Card Interrupt |
mbed_official | 146:f64d43ff0c18 | 2544 | uint32_t RESERVED0 : 7; //!< [15:9] |
mbed_official | 146:f64d43ff0c18 | 2545 | uint32_t CTOE : 1; //!< [16] Command Timeout Error |
mbed_official | 146:f64d43ff0c18 | 2546 | uint32_t CCE : 1; //!< [17] Command CRC Error |
mbed_official | 146:f64d43ff0c18 | 2547 | uint32_t CEBE : 1; //!< [18] Command End Bit Error |
mbed_official | 146:f64d43ff0c18 | 2548 | uint32_t CIE : 1; //!< [19] Command Index Error |
mbed_official | 146:f64d43ff0c18 | 2549 | uint32_t DTOE : 1; //!< [20] Data Timeout Error |
mbed_official | 146:f64d43ff0c18 | 2550 | uint32_t DCE : 1; //!< [21] Data CRC Error |
mbed_official | 146:f64d43ff0c18 | 2551 | uint32_t DEBE : 1; //!< [22] Data End Bit Error |
mbed_official | 146:f64d43ff0c18 | 2552 | uint32_t RESERVED1 : 1; //!< [23] |
mbed_official | 146:f64d43ff0c18 | 2553 | uint32_t AC12E : 1; //!< [24] Auto CMD12 Error |
mbed_official | 146:f64d43ff0c18 | 2554 | uint32_t RESERVED2 : 3; //!< [27:25] |
mbed_official | 146:f64d43ff0c18 | 2555 | uint32_t DMAE : 1; //!< [28] DMA Error |
mbed_official | 146:f64d43ff0c18 | 2556 | uint32_t RESERVED3 : 3; //!< [31:29] |
mbed_official | 146:f64d43ff0c18 | 2557 | } B; |
mbed_official | 146:f64d43ff0c18 | 2558 | } hw_sdhc_irqstat_t; |
mbed_official | 146:f64d43ff0c18 | 2559 | #endif |
mbed_official | 146:f64d43ff0c18 | 2560 | |
mbed_official | 146:f64d43ff0c18 | 2561 | /*! |
mbed_official | 146:f64d43ff0c18 | 2562 | * @name Constants and macros for entire SDHC_IRQSTAT register |
mbed_official | 146:f64d43ff0c18 | 2563 | */ |
mbed_official | 146:f64d43ff0c18 | 2564 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2565 | #define HW_SDHC_IRQSTAT_ADDR (REGS_SDHC_BASE + 0x30U) |
mbed_official | 146:f64d43ff0c18 | 2566 | |
mbed_official | 146:f64d43ff0c18 | 2567 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2568 | #define HW_SDHC_IRQSTAT (*(__IO hw_sdhc_irqstat_t *) HW_SDHC_IRQSTAT_ADDR) |
mbed_official | 146:f64d43ff0c18 | 2569 | #define HW_SDHC_IRQSTAT_RD() (HW_SDHC_IRQSTAT.U) |
mbed_official | 146:f64d43ff0c18 | 2570 | #define HW_SDHC_IRQSTAT_WR(v) (HW_SDHC_IRQSTAT.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 2571 | #define HW_SDHC_IRQSTAT_SET(v) (HW_SDHC_IRQSTAT_WR(HW_SDHC_IRQSTAT_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 2572 | #define HW_SDHC_IRQSTAT_CLR(v) (HW_SDHC_IRQSTAT_WR(HW_SDHC_IRQSTAT_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 2573 | #define HW_SDHC_IRQSTAT_TOG(v) (HW_SDHC_IRQSTAT_WR(HW_SDHC_IRQSTAT_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 2574 | #endif |
mbed_official | 146:f64d43ff0c18 | 2575 | //@} |
mbed_official | 146:f64d43ff0c18 | 2576 | |
mbed_official | 146:f64d43ff0c18 | 2577 | /* |
mbed_official | 146:f64d43ff0c18 | 2578 | * Constants & macros for individual SDHC_IRQSTAT bitfields |
mbed_official | 146:f64d43ff0c18 | 2579 | */ |
mbed_official | 146:f64d43ff0c18 | 2580 | |
mbed_official | 146:f64d43ff0c18 | 2581 | /*! |
mbed_official | 146:f64d43ff0c18 | 2582 | * @name Register SDHC_IRQSTAT, field CC[0] (W1C) |
mbed_official | 146:f64d43ff0c18 | 2583 | * |
mbed_official | 146:f64d43ff0c18 | 2584 | * This bit is set when you receive the end bit of the command response, except |
mbed_official | 146:f64d43ff0c18 | 2585 | * Auto CMD12. See PRSSTAT[CIHB]. |
mbed_official | 146:f64d43ff0c18 | 2586 | * |
mbed_official | 146:f64d43ff0c18 | 2587 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2588 | * - 0 - Command not complete. |
mbed_official | 146:f64d43ff0c18 | 2589 | * - 1 - Command complete. |
mbed_official | 146:f64d43ff0c18 | 2590 | */ |
mbed_official | 146:f64d43ff0c18 | 2591 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2592 | #define BP_SDHC_IRQSTAT_CC (0U) //!< Bit position for SDHC_IRQSTAT_CC. |
mbed_official | 146:f64d43ff0c18 | 2593 | #define BM_SDHC_IRQSTAT_CC (0x00000001U) //!< Bit mask for SDHC_IRQSTAT_CC. |
mbed_official | 146:f64d43ff0c18 | 2594 | #define BS_SDHC_IRQSTAT_CC (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CC. |
mbed_official | 146:f64d43ff0c18 | 2595 | |
mbed_official | 146:f64d43ff0c18 | 2596 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2597 | //! @brief Read current value of the SDHC_IRQSTAT_CC field. |
mbed_official | 146:f64d43ff0c18 | 2598 | #define BR_SDHC_IRQSTAT_CC (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CC)) |
mbed_official | 146:f64d43ff0c18 | 2599 | #endif |
mbed_official | 146:f64d43ff0c18 | 2600 | |
mbed_official | 146:f64d43ff0c18 | 2601 | //! @brief Format value for bitfield SDHC_IRQSTAT_CC. |
mbed_official | 146:f64d43ff0c18 | 2602 | #define BF_SDHC_IRQSTAT_CC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CC), uint32_t) & BM_SDHC_IRQSTAT_CC) |
mbed_official | 146:f64d43ff0c18 | 2603 | |
mbed_official | 146:f64d43ff0c18 | 2604 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2605 | //! @brief Set the CC field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2606 | #define BW_SDHC_IRQSTAT_CC(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CC) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2607 | #endif |
mbed_official | 146:f64d43ff0c18 | 2608 | //@} |
mbed_official | 146:f64d43ff0c18 | 2609 | |
mbed_official | 146:f64d43ff0c18 | 2610 | /*! |
mbed_official | 146:f64d43ff0c18 | 2611 | * @name Register SDHC_IRQSTAT, field TC[1] (W1C) |
mbed_official | 146:f64d43ff0c18 | 2612 | * |
mbed_official | 146:f64d43ff0c18 | 2613 | * This bit is set when a read or write transfer is completed. In the case of a |
mbed_official | 146:f64d43ff0c18 | 2614 | * read transaction: This bit is set at the falling edge of the read transfer |
mbed_official | 146:f64d43ff0c18 | 2615 | * active status. There are two cases in which this interrupt is generated. The |
mbed_official | 146:f64d43ff0c18 | 2616 | * first is when a data transfer is completed as specified by the data length, after |
mbed_official | 146:f64d43ff0c18 | 2617 | * the last data has been read to the host system. The second is when data has |
mbed_official | 146:f64d43ff0c18 | 2618 | * stopped at the block gap and completed the data transfer by setting |
mbed_official | 146:f64d43ff0c18 | 2619 | * PROCTL[SABGREQ], after valid data has been read to the host system. In the case of a write |
mbed_official | 146:f64d43ff0c18 | 2620 | * transaction: This bit is set at the falling edge of the DAT line active |
mbed_official | 146:f64d43ff0c18 | 2621 | * status. There are two cases in which this interrupt is generated. The first is when |
mbed_official | 146:f64d43ff0c18 | 2622 | * the last data is written to the SD card as specified by the data length and |
mbed_official | 146:f64d43ff0c18 | 2623 | * the busy signal is released. The second is when data transfers are stopped at |
mbed_official | 146:f64d43ff0c18 | 2624 | * the block gap, by setting PROCTL[SABGREQ], and the data transfers are |
mbed_official | 146:f64d43ff0c18 | 2625 | * completed,after valid data is written to the SD card and the busy signal released. |
mbed_official | 146:f64d43ff0c18 | 2626 | * |
mbed_official | 146:f64d43ff0c18 | 2627 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2628 | * - 0 - Transfer not complete. |
mbed_official | 146:f64d43ff0c18 | 2629 | * - 1 - Transfer complete. |
mbed_official | 146:f64d43ff0c18 | 2630 | */ |
mbed_official | 146:f64d43ff0c18 | 2631 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2632 | #define BP_SDHC_IRQSTAT_TC (1U) //!< Bit position for SDHC_IRQSTAT_TC. |
mbed_official | 146:f64d43ff0c18 | 2633 | #define BM_SDHC_IRQSTAT_TC (0x00000002U) //!< Bit mask for SDHC_IRQSTAT_TC. |
mbed_official | 146:f64d43ff0c18 | 2634 | #define BS_SDHC_IRQSTAT_TC (1U) //!< Bit field size in bits for SDHC_IRQSTAT_TC. |
mbed_official | 146:f64d43ff0c18 | 2635 | |
mbed_official | 146:f64d43ff0c18 | 2636 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2637 | //! @brief Read current value of the SDHC_IRQSTAT_TC field. |
mbed_official | 146:f64d43ff0c18 | 2638 | #define BR_SDHC_IRQSTAT_TC (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_TC)) |
mbed_official | 146:f64d43ff0c18 | 2639 | #endif |
mbed_official | 146:f64d43ff0c18 | 2640 | |
mbed_official | 146:f64d43ff0c18 | 2641 | //! @brief Format value for bitfield SDHC_IRQSTAT_TC. |
mbed_official | 146:f64d43ff0c18 | 2642 | #define BF_SDHC_IRQSTAT_TC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_TC), uint32_t) & BM_SDHC_IRQSTAT_TC) |
mbed_official | 146:f64d43ff0c18 | 2643 | |
mbed_official | 146:f64d43ff0c18 | 2644 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2645 | //! @brief Set the TC field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2646 | #define BW_SDHC_IRQSTAT_TC(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_TC) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2647 | #endif |
mbed_official | 146:f64d43ff0c18 | 2648 | //@} |
mbed_official | 146:f64d43ff0c18 | 2649 | |
mbed_official | 146:f64d43ff0c18 | 2650 | /*! |
mbed_official | 146:f64d43ff0c18 | 2651 | * @name Register SDHC_IRQSTAT, field BGE[2] (W1C) |
mbed_official | 146:f64d43ff0c18 | 2652 | * |
mbed_official | 146:f64d43ff0c18 | 2653 | * If PROCTL[SABGREQ] is set, this bit is set when a read or write transaction |
mbed_official | 146:f64d43ff0c18 | 2654 | * is stopped at a block gap. If PROCTL[SABGREQ] is not set to 1, this bit is not |
mbed_official | 146:f64d43ff0c18 | 2655 | * set to 1. In the case of a read transaction: This bit is set at the falling |
mbed_official | 146:f64d43ff0c18 | 2656 | * edge of the DAT line active status, when the transaction is stopped at SD Bus |
mbed_official | 146:f64d43ff0c18 | 2657 | * timing. The read wait must be supported in order to use this function. In the |
mbed_official | 146:f64d43ff0c18 | 2658 | * case of write transaction: This bit is set at the falling edge of write transfer |
mbed_official | 146:f64d43ff0c18 | 2659 | * active status, after getting CRC status at SD bus timing. |
mbed_official | 146:f64d43ff0c18 | 2660 | * |
mbed_official | 146:f64d43ff0c18 | 2661 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2662 | * - 0 - No block gap event. |
mbed_official | 146:f64d43ff0c18 | 2663 | * - 1 - Transaction stopped at block gap. |
mbed_official | 146:f64d43ff0c18 | 2664 | */ |
mbed_official | 146:f64d43ff0c18 | 2665 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2666 | #define BP_SDHC_IRQSTAT_BGE (2U) //!< Bit position for SDHC_IRQSTAT_BGE. |
mbed_official | 146:f64d43ff0c18 | 2667 | #define BM_SDHC_IRQSTAT_BGE (0x00000004U) //!< Bit mask for SDHC_IRQSTAT_BGE. |
mbed_official | 146:f64d43ff0c18 | 2668 | #define BS_SDHC_IRQSTAT_BGE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_BGE. |
mbed_official | 146:f64d43ff0c18 | 2669 | |
mbed_official | 146:f64d43ff0c18 | 2670 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2671 | //! @brief Read current value of the SDHC_IRQSTAT_BGE field. |
mbed_official | 146:f64d43ff0c18 | 2672 | #define BR_SDHC_IRQSTAT_BGE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BGE)) |
mbed_official | 146:f64d43ff0c18 | 2673 | #endif |
mbed_official | 146:f64d43ff0c18 | 2674 | |
mbed_official | 146:f64d43ff0c18 | 2675 | //! @brief Format value for bitfield SDHC_IRQSTAT_BGE. |
mbed_official | 146:f64d43ff0c18 | 2676 | #define BF_SDHC_IRQSTAT_BGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_BGE), uint32_t) & BM_SDHC_IRQSTAT_BGE) |
mbed_official | 146:f64d43ff0c18 | 2677 | |
mbed_official | 146:f64d43ff0c18 | 2678 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2679 | //! @brief Set the BGE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2680 | #define BW_SDHC_IRQSTAT_BGE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BGE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2681 | #endif |
mbed_official | 146:f64d43ff0c18 | 2682 | //@} |
mbed_official | 146:f64d43ff0c18 | 2683 | |
mbed_official | 146:f64d43ff0c18 | 2684 | /*! |
mbed_official | 146:f64d43ff0c18 | 2685 | * @name Register SDHC_IRQSTAT, field DINT[3] (W1C) |
mbed_official | 146:f64d43ff0c18 | 2686 | * |
mbed_official | 146:f64d43ff0c18 | 2687 | * Occurs only when the internal DMA finishes the data transfer successfully. |
mbed_official | 146:f64d43ff0c18 | 2688 | * Whenever errors occur during data transfer, this bit will not be set. Instead, |
mbed_official | 146:f64d43ff0c18 | 2689 | * the DMAE bit will be set. Either Simple DMA or ADMA finishes data transferring, |
mbed_official | 146:f64d43ff0c18 | 2690 | * this bit will be set. |
mbed_official | 146:f64d43ff0c18 | 2691 | * |
mbed_official | 146:f64d43ff0c18 | 2692 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2693 | * - 0 - No DMA Interrupt. |
mbed_official | 146:f64d43ff0c18 | 2694 | * - 1 - DMA Interrupt is generated. |
mbed_official | 146:f64d43ff0c18 | 2695 | */ |
mbed_official | 146:f64d43ff0c18 | 2696 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2697 | #define BP_SDHC_IRQSTAT_DINT (3U) //!< Bit position for SDHC_IRQSTAT_DINT. |
mbed_official | 146:f64d43ff0c18 | 2698 | #define BM_SDHC_IRQSTAT_DINT (0x00000008U) //!< Bit mask for SDHC_IRQSTAT_DINT. |
mbed_official | 146:f64d43ff0c18 | 2699 | #define BS_SDHC_IRQSTAT_DINT (1U) //!< Bit field size in bits for SDHC_IRQSTAT_DINT. |
mbed_official | 146:f64d43ff0c18 | 2700 | |
mbed_official | 146:f64d43ff0c18 | 2701 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2702 | //! @brief Read current value of the SDHC_IRQSTAT_DINT field. |
mbed_official | 146:f64d43ff0c18 | 2703 | #define BR_SDHC_IRQSTAT_DINT (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DINT)) |
mbed_official | 146:f64d43ff0c18 | 2704 | #endif |
mbed_official | 146:f64d43ff0c18 | 2705 | |
mbed_official | 146:f64d43ff0c18 | 2706 | //! @brief Format value for bitfield SDHC_IRQSTAT_DINT. |
mbed_official | 146:f64d43ff0c18 | 2707 | #define BF_SDHC_IRQSTAT_DINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DINT), uint32_t) & BM_SDHC_IRQSTAT_DINT) |
mbed_official | 146:f64d43ff0c18 | 2708 | |
mbed_official | 146:f64d43ff0c18 | 2709 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2710 | //! @brief Set the DINT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2711 | #define BW_SDHC_IRQSTAT_DINT(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DINT) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2712 | #endif |
mbed_official | 146:f64d43ff0c18 | 2713 | //@} |
mbed_official | 146:f64d43ff0c18 | 2714 | |
mbed_official | 146:f64d43ff0c18 | 2715 | /*! |
mbed_official | 146:f64d43ff0c18 | 2716 | * @name Register SDHC_IRQSTAT, field BWR[4] (W1C) |
mbed_official | 146:f64d43ff0c18 | 2717 | * |
mbed_official | 146:f64d43ff0c18 | 2718 | * This status bit is set if the Buffer Write Enable bit, in the Present State |
mbed_official | 146:f64d43ff0c18 | 2719 | * register, changes from 0 to 1. See the Buffer Write Enable bit in the Present |
mbed_official | 146:f64d43ff0c18 | 2720 | * State register for additional information. |
mbed_official | 146:f64d43ff0c18 | 2721 | * |
mbed_official | 146:f64d43ff0c18 | 2722 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2723 | * - 0 - Not ready to write buffer. |
mbed_official | 146:f64d43ff0c18 | 2724 | * - 1 - Ready to write buffer. |
mbed_official | 146:f64d43ff0c18 | 2725 | */ |
mbed_official | 146:f64d43ff0c18 | 2726 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2727 | #define BP_SDHC_IRQSTAT_BWR (4U) //!< Bit position for SDHC_IRQSTAT_BWR. |
mbed_official | 146:f64d43ff0c18 | 2728 | #define BM_SDHC_IRQSTAT_BWR (0x00000010U) //!< Bit mask for SDHC_IRQSTAT_BWR. |
mbed_official | 146:f64d43ff0c18 | 2729 | #define BS_SDHC_IRQSTAT_BWR (1U) //!< Bit field size in bits for SDHC_IRQSTAT_BWR. |
mbed_official | 146:f64d43ff0c18 | 2730 | |
mbed_official | 146:f64d43ff0c18 | 2731 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2732 | //! @brief Read current value of the SDHC_IRQSTAT_BWR field. |
mbed_official | 146:f64d43ff0c18 | 2733 | #define BR_SDHC_IRQSTAT_BWR (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BWR)) |
mbed_official | 146:f64d43ff0c18 | 2734 | #endif |
mbed_official | 146:f64d43ff0c18 | 2735 | |
mbed_official | 146:f64d43ff0c18 | 2736 | //! @brief Format value for bitfield SDHC_IRQSTAT_BWR. |
mbed_official | 146:f64d43ff0c18 | 2737 | #define BF_SDHC_IRQSTAT_BWR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_BWR), uint32_t) & BM_SDHC_IRQSTAT_BWR) |
mbed_official | 146:f64d43ff0c18 | 2738 | |
mbed_official | 146:f64d43ff0c18 | 2739 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2740 | //! @brief Set the BWR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2741 | #define BW_SDHC_IRQSTAT_BWR(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BWR) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2742 | #endif |
mbed_official | 146:f64d43ff0c18 | 2743 | //@} |
mbed_official | 146:f64d43ff0c18 | 2744 | |
mbed_official | 146:f64d43ff0c18 | 2745 | /*! |
mbed_official | 146:f64d43ff0c18 | 2746 | * @name Register SDHC_IRQSTAT, field BRR[5] (W1C) |
mbed_official | 146:f64d43ff0c18 | 2747 | * |
mbed_official | 146:f64d43ff0c18 | 2748 | * This status bit is set if the Buffer Read Enable bit, in the Present State |
mbed_official | 146:f64d43ff0c18 | 2749 | * register, changes from 0 to 1. See the Buffer Read Enable bit in the Present |
mbed_official | 146:f64d43ff0c18 | 2750 | * State register for additional information. |
mbed_official | 146:f64d43ff0c18 | 2751 | * |
mbed_official | 146:f64d43ff0c18 | 2752 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2753 | * - 0 - Not ready to read buffer. |
mbed_official | 146:f64d43ff0c18 | 2754 | * - 1 - Ready to read buffer. |
mbed_official | 146:f64d43ff0c18 | 2755 | */ |
mbed_official | 146:f64d43ff0c18 | 2756 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2757 | #define BP_SDHC_IRQSTAT_BRR (5U) //!< Bit position for SDHC_IRQSTAT_BRR. |
mbed_official | 146:f64d43ff0c18 | 2758 | #define BM_SDHC_IRQSTAT_BRR (0x00000020U) //!< Bit mask for SDHC_IRQSTAT_BRR. |
mbed_official | 146:f64d43ff0c18 | 2759 | #define BS_SDHC_IRQSTAT_BRR (1U) //!< Bit field size in bits for SDHC_IRQSTAT_BRR. |
mbed_official | 146:f64d43ff0c18 | 2760 | |
mbed_official | 146:f64d43ff0c18 | 2761 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2762 | //! @brief Read current value of the SDHC_IRQSTAT_BRR field. |
mbed_official | 146:f64d43ff0c18 | 2763 | #define BR_SDHC_IRQSTAT_BRR (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BRR)) |
mbed_official | 146:f64d43ff0c18 | 2764 | #endif |
mbed_official | 146:f64d43ff0c18 | 2765 | |
mbed_official | 146:f64d43ff0c18 | 2766 | //! @brief Format value for bitfield SDHC_IRQSTAT_BRR. |
mbed_official | 146:f64d43ff0c18 | 2767 | #define BF_SDHC_IRQSTAT_BRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_BRR), uint32_t) & BM_SDHC_IRQSTAT_BRR) |
mbed_official | 146:f64d43ff0c18 | 2768 | |
mbed_official | 146:f64d43ff0c18 | 2769 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2770 | //! @brief Set the BRR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2771 | #define BW_SDHC_IRQSTAT_BRR(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BRR) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2772 | #endif |
mbed_official | 146:f64d43ff0c18 | 2773 | //@} |
mbed_official | 146:f64d43ff0c18 | 2774 | |
mbed_official | 146:f64d43ff0c18 | 2775 | /*! |
mbed_official | 146:f64d43ff0c18 | 2776 | * @name Register SDHC_IRQSTAT, field CINS[6] (W1C) |
mbed_official | 146:f64d43ff0c18 | 2777 | * |
mbed_official | 146:f64d43ff0c18 | 2778 | * This status bit is set if the Card Inserted bit in the Present State register |
mbed_official | 146:f64d43ff0c18 | 2779 | * changes from 0 to 1. When the host driver writes this bit to 1 to clear this |
mbed_official | 146:f64d43ff0c18 | 2780 | * status, the status of the Card Inserted in the Present State register must be |
mbed_official | 146:f64d43ff0c18 | 2781 | * confirmed. Because the card state may possibly be changed when the host driver |
mbed_official | 146:f64d43ff0c18 | 2782 | * clears this bit and the interrupt event may not be generated. When this bit |
mbed_official | 146:f64d43ff0c18 | 2783 | * is cleared, it will be set again if a card is inserted. To leave it cleared, |
mbed_official | 146:f64d43ff0c18 | 2784 | * clear the Card Inserted Status Enable bit in Interrupt Status Enable register. |
mbed_official | 146:f64d43ff0c18 | 2785 | * |
mbed_official | 146:f64d43ff0c18 | 2786 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2787 | * - 0 - Card state unstable or removed. |
mbed_official | 146:f64d43ff0c18 | 2788 | * - 1 - Card inserted. |
mbed_official | 146:f64d43ff0c18 | 2789 | */ |
mbed_official | 146:f64d43ff0c18 | 2790 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2791 | #define BP_SDHC_IRQSTAT_CINS (6U) //!< Bit position for SDHC_IRQSTAT_CINS. |
mbed_official | 146:f64d43ff0c18 | 2792 | #define BM_SDHC_IRQSTAT_CINS (0x00000040U) //!< Bit mask for SDHC_IRQSTAT_CINS. |
mbed_official | 146:f64d43ff0c18 | 2793 | #define BS_SDHC_IRQSTAT_CINS (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CINS. |
mbed_official | 146:f64d43ff0c18 | 2794 | |
mbed_official | 146:f64d43ff0c18 | 2795 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2796 | //! @brief Read current value of the SDHC_IRQSTAT_CINS field. |
mbed_official | 146:f64d43ff0c18 | 2797 | #define BR_SDHC_IRQSTAT_CINS (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CINS)) |
mbed_official | 146:f64d43ff0c18 | 2798 | #endif |
mbed_official | 146:f64d43ff0c18 | 2799 | |
mbed_official | 146:f64d43ff0c18 | 2800 | //! @brief Format value for bitfield SDHC_IRQSTAT_CINS. |
mbed_official | 146:f64d43ff0c18 | 2801 | #define BF_SDHC_IRQSTAT_CINS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CINS), uint32_t) & BM_SDHC_IRQSTAT_CINS) |
mbed_official | 146:f64d43ff0c18 | 2802 | |
mbed_official | 146:f64d43ff0c18 | 2803 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2804 | //! @brief Set the CINS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2805 | #define BW_SDHC_IRQSTAT_CINS(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CINS) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2806 | #endif |
mbed_official | 146:f64d43ff0c18 | 2807 | //@} |
mbed_official | 146:f64d43ff0c18 | 2808 | |
mbed_official | 146:f64d43ff0c18 | 2809 | /*! |
mbed_official | 146:f64d43ff0c18 | 2810 | * @name Register SDHC_IRQSTAT, field CRM[7] (W1C) |
mbed_official | 146:f64d43ff0c18 | 2811 | * |
mbed_official | 146:f64d43ff0c18 | 2812 | * This status bit is set if the Card Inserted bit in the Present State register |
mbed_official | 146:f64d43ff0c18 | 2813 | * changes from 1 to 0. When the host driver writes this bit to 1 to clear this |
mbed_official | 146:f64d43ff0c18 | 2814 | * status, the status of the Card Inserted in the Present State register must be |
mbed_official | 146:f64d43ff0c18 | 2815 | * confirmed. Because the card state may possibly be changed when the host driver |
mbed_official | 146:f64d43ff0c18 | 2816 | * clears this bit and the interrupt event may not be generated. When this bit |
mbed_official | 146:f64d43ff0c18 | 2817 | * is cleared, it will be set again if no card is inserted. To leave it cleared, |
mbed_official | 146:f64d43ff0c18 | 2818 | * clear the Card Removal Status Enable bit in Interrupt Status Enable register. |
mbed_official | 146:f64d43ff0c18 | 2819 | * |
mbed_official | 146:f64d43ff0c18 | 2820 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2821 | * - 0 - Card state unstable or inserted. |
mbed_official | 146:f64d43ff0c18 | 2822 | * - 1 - Card removed. |
mbed_official | 146:f64d43ff0c18 | 2823 | */ |
mbed_official | 146:f64d43ff0c18 | 2824 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2825 | #define BP_SDHC_IRQSTAT_CRM (7U) //!< Bit position for SDHC_IRQSTAT_CRM. |
mbed_official | 146:f64d43ff0c18 | 2826 | #define BM_SDHC_IRQSTAT_CRM (0x00000080U) //!< Bit mask for SDHC_IRQSTAT_CRM. |
mbed_official | 146:f64d43ff0c18 | 2827 | #define BS_SDHC_IRQSTAT_CRM (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CRM. |
mbed_official | 146:f64d43ff0c18 | 2828 | |
mbed_official | 146:f64d43ff0c18 | 2829 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2830 | //! @brief Read current value of the SDHC_IRQSTAT_CRM field. |
mbed_official | 146:f64d43ff0c18 | 2831 | #define BR_SDHC_IRQSTAT_CRM (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CRM)) |
mbed_official | 146:f64d43ff0c18 | 2832 | #endif |
mbed_official | 146:f64d43ff0c18 | 2833 | |
mbed_official | 146:f64d43ff0c18 | 2834 | //! @brief Format value for bitfield SDHC_IRQSTAT_CRM. |
mbed_official | 146:f64d43ff0c18 | 2835 | #define BF_SDHC_IRQSTAT_CRM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CRM), uint32_t) & BM_SDHC_IRQSTAT_CRM) |
mbed_official | 146:f64d43ff0c18 | 2836 | |
mbed_official | 146:f64d43ff0c18 | 2837 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2838 | //! @brief Set the CRM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2839 | #define BW_SDHC_IRQSTAT_CRM(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CRM) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2840 | #endif |
mbed_official | 146:f64d43ff0c18 | 2841 | //@} |
mbed_official | 146:f64d43ff0c18 | 2842 | |
mbed_official | 146:f64d43ff0c18 | 2843 | /*! |
mbed_official | 146:f64d43ff0c18 | 2844 | * @name Register SDHC_IRQSTAT, field CINT[8] (W1C) |
mbed_official | 146:f64d43ff0c18 | 2845 | * |
mbed_official | 146:f64d43ff0c18 | 2846 | * This status bit is set when an interrupt signal is detected from the external |
mbed_official | 146:f64d43ff0c18 | 2847 | * card. In 1-bit mode, the SDHC will detect the Card Interrupt without the SD |
mbed_official | 146:f64d43ff0c18 | 2848 | * Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled |
mbed_official | 146:f64d43ff0c18 | 2849 | * during the interrupt cycle, so the interrupt from card can only be sampled |
mbed_official | 146:f64d43ff0c18 | 2850 | * during interrupt cycle, introducing some delay between the interrupt signal from |
mbed_official | 146:f64d43ff0c18 | 2851 | * the SDIO card and the interrupt to the host system. Writing this bit to 1 can |
mbed_official | 146:f64d43ff0c18 | 2852 | * clear this bit, but as the interrupt factor from the SDIO card does not clear, |
mbed_official | 146:f64d43ff0c18 | 2853 | * this bit is set again. To clear this bit, it is required to reset the interrupt |
mbed_official | 146:f64d43ff0c18 | 2854 | * factor from the external card followed by a writing 1 to this bit. When this |
mbed_official | 146:f64d43ff0c18 | 2855 | * status has been set, and the host driver needs to service this interrupt, the |
mbed_official | 146:f64d43ff0c18 | 2856 | * Card Interrupt Signal Enable in the Interrupt Signal Enable register should be |
mbed_official | 146:f64d43ff0c18 | 2857 | * 0 to stop driving the interrupt signal to the host system. After completion |
mbed_official | 146:f64d43ff0c18 | 2858 | * of the card interrupt service (it must reset the interrupt factors in the SDIO |
mbed_official | 146:f64d43ff0c18 | 2859 | * card and the interrupt signal may not be asserted), write 1 to clear this bit, |
mbed_official | 146:f64d43ff0c18 | 2860 | * set the Card Interrupt Signal Enable to 1, and start sampling the interrupt |
mbed_official | 146:f64d43ff0c18 | 2861 | * signal again. |
mbed_official | 146:f64d43ff0c18 | 2862 | * |
mbed_official | 146:f64d43ff0c18 | 2863 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2864 | * - 0 - No Card Interrupt. |
mbed_official | 146:f64d43ff0c18 | 2865 | * - 1 - Generate Card Interrupt. |
mbed_official | 146:f64d43ff0c18 | 2866 | */ |
mbed_official | 146:f64d43ff0c18 | 2867 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2868 | #define BP_SDHC_IRQSTAT_CINT (8U) //!< Bit position for SDHC_IRQSTAT_CINT. |
mbed_official | 146:f64d43ff0c18 | 2869 | #define BM_SDHC_IRQSTAT_CINT (0x00000100U) //!< Bit mask for SDHC_IRQSTAT_CINT. |
mbed_official | 146:f64d43ff0c18 | 2870 | #define BS_SDHC_IRQSTAT_CINT (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CINT. |
mbed_official | 146:f64d43ff0c18 | 2871 | |
mbed_official | 146:f64d43ff0c18 | 2872 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2873 | //! @brief Read current value of the SDHC_IRQSTAT_CINT field. |
mbed_official | 146:f64d43ff0c18 | 2874 | #define BR_SDHC_IRQSTAT_CINT (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CINT)) |
mbed_official | 146:f64d43ff0c18 | 2875 | #endif |
mbed_official | 146:f64d43ff0c18 | 2876 | |
mbed_official | 146:f64d43ff0c18 | 2877 | //! @brief Format value for bitfield SDHC_IRQSTAT_CINT. |
mbed_official | 146:f64d43ff0c18 | 2878 | #define BF_SDHC_IRQSTAT_CINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CINT), uint32_t) & BM_SDHC_IRQSTAT_CINT) |
mbed_official | 146:f64d43ff0c18 | 2879 | |
mbed_official | 146:f64d43ff0c18 | 2880 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2881 | //! @brief Set the CINT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2882 | #define BW_SDHC_IRQSTAT_CINT(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CINT) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2883 | #endif |
mbed_official | 146:f64d43ff0c18 | 2884 | //@} |
mbed_official | 146:f64d43ff0c18 | 2885 | |
mbed_official | 146:f64d43ff0c18 | 2886 | /*! |
mbed_official | 146:f64d43ff0c18 | 2887 | * @name Register SDHC_IRQSTAT, field CTOE[16] (W1C) |
mbed_official | 146:f64d43ff0c18 | 2888 | * |
mbed_official | 146:f64d43ff0c18 | 2889 | * Occurs only if no response is returned within 64 SDCLK cycles from the end |
mbed_official | 146:f64d43ff0c18 | 2890 | * bit of the command. If the SDHC detects a CMD line conflict, in which case a |
mbed_official | 146:f64d43ff0c18 | 2891 | * Command CRC Error shall also be set, this bit shall be set without waiting for 64 |
mbed_official | 146:f64d43ff0c18 | 2892 | * SDCLK cycles. This is because the command will be aborted by the SDHC. |
mbed_official | 146:f64d43ff0c18 | 2893 | * |
mbed_official | 146:f64d43ff0c18 | 2894 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2895 | * - 0 - No error. |
mbed_official | 146:f64d43ff0c18 | 2896 | * - 1 - Time out. |
mbed_official | 146:f64d43ff0c18 | 2897 | */ |
mbed_official | 146:f64d43ff0c18 | 2898 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2899 | #define BP_SDHC_IRQSTAT_CTOE (16U) //!< Bit position for SDHC_IRQSTAT_CTOE. |
mbed_official | 146:f64d43ff0c18 | 2900 | #define BM_SDHC_IRQSTAT_CTOE (0x00010000U) //!< Bit mask for SDHC_IRQSTAT_CTOE. |
mbed_official | 146:f64d43ff0c18 | 2901 | #define BS_SDHC_IRQSTAT_CTOE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CTOE. |
mbed_official | 146:f64d43ff0c18 | 2902 | |
mbed_official | 146:f64d43ff0c18 | 2903 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2904 | //! @brief Read current value of the SDHC_IRQSTAT_CTOE field. |
mbed_official | 146:f64d43ff0c18 | 2905 | #define BR_SDHC_IRQSTAT_CTOE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CTOE)) |
mbed_official | 146:f64d43ff0c18 | 2906 | #endif |
mbed_official | 146:f64d43ff0c18 | 2907 | |
mbed_official | 146:f64d43ff0c18 | 2908 | //! @brief Format value for bitfield SDHC_IRQSTAT_CTOE. |
mbed_official | 146:f64d43ff0c18 | 2909 | #define BF_SDHC_IRQSTAT_CTOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CTOE), uint32_t) & BM_SDHC_IRQSTAT_CTOE) |
mbed_official | 146:f64d43ff0c18 | 2910 | |
mbed_official | 146:f64d43ff0c18 | 2911 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2912 | //! @brief Set the CTOE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2913 | #define BW_SDHC_IRQSTAT_CTOE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CTOE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2914 | #endif |
mbed_official | 146:f64d43ff0c18 | 2915 | //@} |
mbed_official | 146:f64d43ff0c18 | 2916 | |
mbed_official | 146:f64d43ff0c18 | 2917 | /*! |
mbed_official | 146:f64d43ff0c18 | 2918 | * @name Register SDHC_IRQSTAT, field CCE[17] (W1C) |
mbed_official | 146:f64d43ff0c18 | 2919 | * |
mbed_official | 146:f64d43ff0c18 | 2920 | * Command CRC Error is generated in two cases. If a response is returned and |
mbed_official | 146:f64d43ff0c18 | 2921 | * the Command Timeout Error is set to 0, indicating no time-out, this bit is set |
mbed_official | 146:f64d43ff0c18 | 2922 | * when detecting a CRC error in the command response. The SDHC detects a CMD line |
mbed_official | 146:f64d43ff0c18 | 2923 | * conflict by monitoring the CMD line when a command is issued. If the SDHC |
mbed_official | 146:f64d43ff0c18 | 2924 | * drives the CMD line to 1, but detects 0 on the CMD line at the next SDCLK edge, |
mbed_official | 146:f64d43ff0c18 | 2925 | * then the SDHC shall abort the command (Stop driving CMD line) and set this bit |
mbed_official | 146:f64d43ff0c18 | 2926 | * to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line |
mbed_official | 146:f64d43ff0c18 | 2927 | * conflict. |
mbed_official | 146:f64d43ff0c18 | 2928 | * |
mbed_official | 146:f64d43ff0c18 | 2929 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2930 | * - 0 - No error. |
mbed_official | 146:f64d43ff0c18 | 2931 | * - 1 - CRC Error generated. |
mbed_official | 146:f64d43ff0c18 | 2932 | */ |
mbed_official | 146:f64d43ff0c18 | 2933 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2934 | #define BP_SDHC_IRQSTAT_CCE (17U) //!< Bit position for SDHC_IRQSTAT_CCE. |
mbed_official | 146:f64d43ff0c18 | 2935 | #define BM_SDHC_IRQSTAT_CCE (0x00020000U) //!< Bit mask for SDHC_IRQSTAT_CCE. |
mbed_official | 146:f64d43ff0c18 | 2936 | #define BS_SDHC_IRQSTAT_CCE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CCE. |
mbed_official | 146:f64d43ff0c18 | 2937 | |
mbed_official | 146:f64d43ff0c18 | 2938 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2939 | //! @brief Read current value of the SDHC_IRQSTAT_CCE field. |
mbed_official | 146:f64d43ff0c18 | 2940 | #define BR_SDHC_IRQSTAT_CCE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CCE)) |
mbed_official | 146:f64d43ff0c18 | 2941 | #endif |
mbed_official | 146:f64d43ff0c18 | 2942 | |
mbed_official | 146:f64d43ff0c18 | 2943 | //! @brief Format value for bitfield SDHC_IRQSTAT_CCE. |
mbed_official | 146:f64d43ff0c18 | 2944 | #define BF_SDHC_IRQSTAT_CCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CCE), uint32_t) & BM_SDHC_IRQSTAT_CCE) |
mbed_official | 146:f64d43ff0c18 | 2945 | |
mbed_official | 146:f64d43ff0c18 | 2946 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2947 | //! @brief Set the CCE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2948 | #define BW_SDHC_IRQSTAT_CCE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CCE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2949 | #endif |
mbed_official | 146:f64d43ff0c18 | 2950 | //@} |
mbed_official | 146:f64d43ff0c18 | 2951 | |
mbed_official | 146:f64d43ff0c18 | 2952 | /*! |
mbed_official | 146:f64d43ff0c18 | 2953 | * @name Register SDHC_IRQSTAT, field CEBE[18] (W1C) |
mbed_official | 146:f64d43ff0c18 | 2954 | * |
mbed_official | 146:f64d43ff0c18 | 2955 | * Occurs when detecting that the end bit of a command response is 0. |
mbed_official | 146:f64d43ff0c18 | 2956 | * |
mbed_official | 146:f64d43ff0c18 | 2957 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2958 | * - 0 - No error. |
mbed_official | 146:f64d43ff0c18 | 2959 | * - 1 - End Bit Error generated. |
mbed_official | 146:f64d43ff0c18 | 2960 | */ |
mbed_official | 146:f64d43ff0c18 | 2961 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2962 | #define BP_SDHC_IRQSTAT_CEBE (18U) //!< Bit position for SDHC_IRQSTAT_CEBE. |
mbed_official | 146:f64d43ff0c18 | 2963 | #define BM_SDHC_IRQSTAT_CEBE (0x00040000U) //!< Bit mask for SDHC_IRQSTAT_CEBE. |
mbed_official | 146:f64d43ff0c18 | 2964 | #define BS_SDHC_IRQSTAT_CEBE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CEBE. |
mbed_official | 146:f64d43ff0c18 | 2965 | |
mbed_official | 146:f64d43ff0c18 | 2966 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2967 | //! @brief Read current value of the SDHC_IRQSTAT_CEBE field. |
mbed_official | 146:f64d43ff0c18 | 2968 | #define BR_SDHC_IRQSTAT_CEBE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CEBE)) |
mbed_official | 146:f64d43ff0c18 | 2969 | #endif |
mbed_official | 146:f64d43ff0c18 | 2970 | |
mbed_official | 146:f64d43ff0c18 | 2971 | //! @brief Format value for bitfield SDHC_IRQSTAT_CEBE. |
mbed_official | 146:f64d43ff0c18 | 2972 | #define BF_SDHC_IRQSTAT_CEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CEBE), uint32_t) & BM_SDHC_IRQSTAT_CEBE) |
mbed_official | 146:f64d43ff0c18 | 2973 | |
mbed_official | 146:f64d43ff0c18 | 2974 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2975 | //! @brief Set the CEBE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2976 | #define BW_SDHC_IRQSTAT_CEBE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CEBE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2977 | #endif |
mbed_official | 146:f64d43ff0c18 | 2978 | //@} |
mbed_official | 146:f64d43ff0c18 | 2979 | |
mbed_official | 146:f64d43ff0c18 | 2980 | /*! |
mbed_official | 146:f64d43ff0c18 | 2981 | * @name Register SDHC_IRQSTAT, field CIE[19] (W1C) |
mbed_official | 146:f64d43ff0c18 | 2982 | * |
mbed_official | 146:f64d43ff0c18 | 2983 | * Occurs if a Command Index error occurs in the command response. |
mbed_official | 146:f64d43ff0c18 | 2984 | * |
mbed_official | 146:f64d43ff0c18 | 2985 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2986 | * - 0 - No error. |
mbed_official | 146:f64d43ff0c18 | 2987 | * - 1 - Error. |
mbed_official | 146:f64d43ff0c18 | 2988 | */ |
mbed_official | 146:f64d43ff0c18 | 2989 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2990 | #define BP_SDHC_IRQSTAT_CIE (19U) //!< Bit position for SDHC_IRQSTAT_CIE. |
mbed_official | 146:f64d43ff0c18 | 2991 | #define BM_SDHC_IRQSTAT_CIE (0x00080000U) //!< Bit mask for SDHC_IRQSTAT_CIE. |
mbed_official | 146:f64d43ff0c18 | 2992 | #define BS_SDHC_IRQSTAT_CIE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CIE. |
mbed_official | 146:f64d43ff0c18 | 2993 | |
mbed_official | 146:f64d43ff0c18 | 2994 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2995 | //! @brief Read current value of the SDHC_IRQSTAT_CIE field. |
mbed_official | 146:f64d43ff0c18 | 2996 | #define BR_SDHC_IRQSTAT_CIE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CIE)) |
mbed_official | 146:f64d43ff0c18 | 2997 | #endif |
mbed_official | 146:f64d43ff0c18 | 2998 | |
mbed_official | 146:f64d43ff0c18 | 2999 | //! @brief Format value for bitfield SDHC_IRQSTAT_CIE. |
mbed_official | 146:f64d43ff0c18 | 3000 | #define BF_SDHC_IRQSTAT_CIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CIE), uint32_t) & BM_SDHC_IRQSTAT_CIE) |
mbed_official | 146:f64d43ff0c18 | 3001 | |
mbed_official | 146:f64d43ff0c18 | 3002 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3003 | //! @brief Set the CIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3004 | #define BW_SDHC_IRQSTAT_CIE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3005 | #endif |
mbed_official | 146:f64d43ff0c18 | 3006 | //@} |
mbed_official | 146:f64d43ff0c18 | 3007 | |
mbed_official | 146:f64d43ff0c18 | 3008 | /*! |
mbed_official | 146:f64d43ff0c18 | 3009 | * @name Register SDHC_IRQSTAT, field DTOE[20] (W1C) |
mbed_official | 146:f64d43ff0c18 | 3010 | * |
mbed_official | 146:f64d43ff0c18 | 3011 | * Occurs when detecting one of following time-out conditions. Busy time-out for |
mbed_official | 146:f64d43ff0c18 | 3012 | * R1b,R5b type Busy time-out after Write CRC status Read Data time-out |
mbed_official | 146:f64d43ff0c18 | 3013 | * |
mbed_official | 146:f64d43ff0c18 | 3014 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3015 | * - 0 - No error. |
mbed_official | 146:f64d43ff0c18 | 3016 | * - 1 - Time out. |
mbed_official | 146:f64d43ff0c18 | 3017 | */ |
mbed_official | 146:f64d43ff0c18 | 3018 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3019 | #define BP_SDHC_IRQSTAT_DTOE (20U) //!< Bit position for SDHC_IRQSTAT_DTOE. |
mbed_official | 146:f64d43ff0c18 | 3020 | #define BM_SDHC_IRQSTAT_DTOE (0x00100000U) //!< Bit mask for SDHC_IRQSTAT_DTOE. |
mbed_official | 146:f64d43ff0c18 | 3021 | #define BS_SDHC_IRQSTAT_DTOE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_DTOE. |
mbed_official | 146:f64d43ff0c18 | 3022 | |
mbed_official | 146:f64d43ff0c18 | 3023 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3024 | //! @brief Read current value of the SDHC_IRQSTAT_DTOE field. |
mbed_official | 146:f64d43ff0c18 | 3025 | #define BR_SDHC_IRQSTAT_DTOE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DTOE)) |
mbed_official | 146:f64d43ff0c18 | 3026 | #endif |
mbed_official | 146:f64d43ff0c18 | 3027 | |
mbed_official | 146:f64d43ff0c18 | 3028 | //! @brief Format value for bitfield SDHC_IRQSTAT_DTOE. |
mbed_official | 146:f64d43ff0c18 | 3029 | #define BF_SDHC_IRQSTAT_DTOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DTOE), uint32_t) & BM_SDHC_IRQSTAT_DTOE) |
mbed_official | 146:f64d43ff0c18 | 3030 | |
mbed_official | 146:f64d43ff0c18 | 3031 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3032 | //! @brief Set the DTOE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3033 | #define BW_SDHC_IRQSTAT_DTOE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DTOE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3034 | #endif |
mbed_official | 146:f64d43ff0c18 | 3035 | //@} |
mbed_official | 146:f64d43ff0c18 | 3036 | |
mbed_official | 146:f64d43ff0c18 | 3037 | /*! |
mbed_official | 146:f64d43ff0c18 | 3038 | * @name Register SDHC_IRQSTAT, field DCE[21] (W1C) |
mbed_official | 146:f64d43ff0c18 | 3039 | * |
mbed_official | 146:f64d43ff0c18 | 3040 | * Occurs when detecting a CRC error when transferring read data, which uses the |
mbed_official | 146:f64d43ff0c18 | 3041 | * DAT line, or when detecting the Write CRC status having a value other than |
mbed_official | 146:f64d43ff0c18 | 3042 | * 010. |
mbed_official | 146:f64d43ff0c18 | 3043 | * |
mbed_official | 146:f64d43ff0c18 | 3044 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3045 | * - 0 - No error. |
mbed_official | 146:f64d43ff0c18 | 3046 | * - 1 - Error. |
mbed_official | 146:f64d43ff0c18 | 3047 | */ |
mbed_official | 146:f64d43ff0c18 | 3048 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3049 | #define BP_SDHC_IRQSTAT_DCE (21U) //!< Bit position for SDHC_IRQSTAT_DCE. |
mbed_official | 146:f64d43ff0c18 | 3050 | #define BM_SDHC_IRQSTAT_DCE (0x00200000U) //!< Bit mask for SDHC_IRQSTAT_DCE. |
mbed_official | 146:f64d43ff0c18 | 3051 | #define BS_SDHC_IRQSTAT_DCE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_DCE. |
mbed_official | 146:f64d43ff0c18 | 3052 | |
mbed_official | 146:f64d43ff0c18 | 3053 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3054 | //! @brief Read current value of the SDHC_IRQSTAT_DCE field. |
mbed_official | 146:f64d43ff0c18 | 3055 | #define BR_SDHC_IRQSTAT_DCE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DCE)) |
mbed_official | 146:f64d43ff0c18 | 3056 | #endif |
mbed_official | 146:f64d43ff0c18 | 3057 | |
mbed_official | 146:f64d43ff0c18 | 3058 | //! @brief Format value for bitfield SDHC_IRQSTAT_DCE. |
mbed_official | 146:f64d43ff0c18 | 3059 | #define BF_SDHC_IRQSTAT_DCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DCE), uint32_t) & BM_SDHC_IRQSTAT_DCE) |
mbed_official | 146:f64d43ff0c18 | 3060 | |
mbed_official | 146:f64d43ff0c18 | 3061 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3062 | //! @brief Set the DCE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3063 | #define BW_SDHC_IRQSTAT_DCE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DCE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3064 | #endif |
mbed_official | 146:f64d43ff0c18 | 3065 | //@} |
mbed_official | 146:f64d43ff0c18 | 3066 | |
mbed_official | 146:f64d43ff0c18 | 3067 | /*! |
mbed_official | 146:f64d43ff0c18 | 3068 | * @name Register SDHC_IRQSTAT, field DEBE[22] (W1C) |
mbed_official | 146:f64d43ff0c18 | 3069 | * |
mbed_official | 146:f64d43ff0c18 | 3070 | * Occurs either when detecting 0 at the end bit position of read data, which |
mbed_official | 146:f64d43ff0c18 | 3071 | * uses the DAT line, or at the end bit position of the CRC. |
mbed_official | 146:f64d43ff0c18 | 3072 | * |
mbed_official | 146:f64d43ff0c18 | 3073 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3074 | * - 0 - No error. |
mbed_official | 146:f64d43ff0c18 | 3075 | * - 1 - Error. |
mbed_official | 146:f64d43ff0c18 | 3076 | */ |
mbed_official | 146:f64d43ff0c18 | 3077 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3078 | #define BP_SDHC_IRQSTAT_DEBE (22U) //!< Bit position for SDHC_IRQSTAT_DEBE. |
mbed_official | 146:f64d43ff0c18 | 3079 | #define BM_SDHC_IRQSTAT_DEBE (0x00400000U) //!< Bit mask for SDHC_IRQSTAT_DEBE. |
mbed_official | 146:f64d43ff0c18 | 3080 | #define BS_SDHC_IRQSTAT_DEBE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_DEBE. |
mbed_official | 146:f64d43ff0c18 | 3081 | |
mbed_official | 146:f64d43ff0c18 | 3082 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3083 | //! @brief Read current value of the SDHC_IRQSTAT_DEBE field. |
mbed_official | 146:f64d43ff0c18 | 3084 | #define BR_SDHC_IRQSTAT_DEBE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DEBE)) |
mbed_official | 146:f64d43ff0c18 | 3085 | #endif |
mbed_official | 146:f64d43ff0c18 | 3086 | |
mbed_official | 146:f64d43ff0c18 | 3087 | //! @brief Format value for bitfield SDHC_IRQSTAT_DEBE. |
mbed_official | 146:f64d43ff0c18 | 3088 | #define BF_SDHC_IRQSTAT_DEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DEBE), uint32_t) & BM_SDHC_IRQSTAT_DEBE) |
mbed_official | 146:f64d43ff0c18 | 3089 | |
mbed_official | 146:f64d43ff0c18 | 3090 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3091 | //! @brief Set the DEBE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3092 | #define BW_SDHC_IRQSTAT_DEBE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DEBE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3093 | #endif |
mbed_official | 146:f64d43ff0c18 | 3094 | //@} |
mbed_official | 146:f64d43ff0c18 | 3095 | |
mbed_official | 146:f64d43ff0c18 | 3096 | /*! |
mbed_official | 146:f64d43ff0c18 | 3097 | * @name Register SDHC_IRQSTAT, field AC12E[24] (W1C) |
mbed_official | 146:f64d43ff0c18 | 3098 | * |
mbed_official | 146:f64d43ff0c18 | 3099 | * Occurs when detecting that one of the bits in the Auto CMD12 Error Status |
mbed_official | 146:f64d43ff0c18 | 3100 | * register has changed from 0 to 1. This bit is set to 1, not only when the errors |
mbed_official | 146:f64d43ff0c18 | 3101 | * in Auto CMD12 occur, but also when the Auto CMD12 is not executed due to the |
mbed_official | 146:f64d43ff0c18 | 3102 | * previous command error. |
mbed_official | 146:f64d43ff0c18 | 3103 | * |
mbed_official | 146:f64d43ff0c18 | 3104 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3105 | * - 0 - No error. |
mbed_official | 146:f64d43ff0c18 | 3106 | * - 1 - Error. |
mbed_official | 146:f64d43ff0c18 | 3107 | */ |
mbed_official | 146:f64d43ff0c18 | 3108 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3109 | #define BP_SDHC_IRQSTAT_AC12E (24U) //!< Bit position for SDHC_IRQSTAT_AC12E. |
mbed_official | 146:f64d43ff0c18 | 3110 | #define BM_SDHC_IRQSTAT_AC12E (0x01000000U) //!< Bit mask for SDHC_IRQSTAT_AC12E. |
mbed_official | 146:f64d43ff0c18 | 3111 | #define BS_SDHC_IRQSTAT_AC12E (1U) //!< Bit field size in bits for SDHC_IRQSTAT_AC12E. |
mbed_official | 146:f64d43ff0c18 | 3112 | |
mbed_official | 146:f64d43ff0c18 | 3113 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3114 | //! @brief Read current value of the SDHC_IRQSTAT_AC12E field. |
mbed_official | 146:f64d43ff0c18 | 3115 | #define BR_SDHC_IRQSTAT_AC12E (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_AC12E)) |
mbed_official | 146:f64d43ff0c18 | 3116 | #endif |
mbed_official | 146:f64d43ff0c18 | 3117 | |
mbed_official | 146:f64d43ff0c18 | 3118 | //! @brief Format value for bitfield SDHC_IRQSTAT_AC12E. |
mbed_official | 146:f64d43ff0c18 | 3119 | #define BF_SDHC_IRQSTAT_AC12E(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_AC12E), uint32_t) & BM_SDHC_IRQSTAT_AC12E) |
mbed_official | 146:f64d43ff0c18 | 3120 | |
mbed_official | 146:f64d43ff0c18 | 3121 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3122 | //! @brief Set the AC12E field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3123 | #define BW_SDHC_IRQSTAT_AC12E(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_AC12E) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3124 | #endif |
mbed_official | 146:f64d43ff0c18 | 3125 | //@} |
mbed_official | 146:f64d43ff0c18 | 3126 | |
mbed_official | 146:f64d43ff0c18 | 3127 | /*! |
mbed_official | 146:f64d43ff0c18 | 3128 | * @name Register SDHC_IRQSTAT, field DMAE[28] (W1C) |
mbed_official | 146:f64d43ff0c18 | 3129 | * |
mbed_official | 146:f64d43ff0c18 | 3130 | * Occurs when an Internal DMA transfer has failed. This bit is set to 1, when |
mbed_official | 146:f64d43ff0c18 | 3131 | * some error occurs in the data transfer. This error can be caused by either |
mbed_official | 146:f64d43ff0c18 | 3132 | * Simple DMA or ADMA, depending on which DMA is in use. The value in DMA System |
mbed_official | 146:f64d43ff0c18 | 3133 | * Address register is the next fetch address where the error occurs. Because any |
mbed_official | 146:f64d43ff0c18 | 3134 | * error corrupts the whole data block, the host driver shall restart the transfer |
mbed_official | 146:f64d43ff0c18 | 3135 | * from the corrupted block boundary. The address of the block boundary can be |
mbed_official | 146:f64d43ff0c18 | 3136 | * calculated either from the current DSADDR value or from the remaining number of |
mbed_official | 146:f64d43ff0c18 | 3137 | * blocks and the block size. |
mbed_official | 146:f64d43ff0c18 | 3138 | * |
mbed_official | 146:f64d43ff0c18 | 3139 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3140 | * - 0 - No error. |
mbed_official | 146:f64d43ff0c18 | 3141 | * - 1 - Error. |
mbed_official | 146:f64d43ff0c18 | 3142 | */ |
mbed_official | 146:f64d43ff0c18 | 3143 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3144 | #define BP_SDHC_IRQSTAT_DMAE (28U) //!< Bit position for SDHC_IRQSTAT_DMAE. |
mbed_official | 146:f64d43ff0c18 | 3145 | #define BM_SDHC_IRQSTAT_DMAE (0x10000000U) //!< Bit mask for SDHC_IRQSTAT_DMAE. |
mbed_official | 146:f64d43ff0c18 | 3146 | #define BS_SDHC_IRQSTAT_DMAE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_DMAE. |
mbed_official | 146:f64d43ff0c18 | 3147 | |
mbed_official | 146:f64d43ff0c18 | 3148 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3149 | //! @brief Read current value of the SDHC_IRQSTAT_DMAE field. |
mbed_official | 146:f64d43ff0c18 | 3150 | #define BR_SDHC_IRQSTAT_DMAE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DMAE)) |
mbed_official | 146:f64d43ff0c18 | 3151 | #endif |
mbed_official | 146:f64d43ff0c18 | 3152 | |
mbed_official | 146:f64d43ff0c18 | 3153 | //! @brief Format value for bitfield SDHC_IRQSTAT_DMAE. |
mbed_official | 146:f64d43ff0c18 | 3154 | #define BF_SDHC_IRQSTAT_DMAE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DMAE), uint32_t) & BM_SDHC_IRQSTAT_DMAE) |
mbed_official | 146:f64d43ff0c18 | 3155 | |
mbed_official | 146:f64d43ff0c18 | 3156 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3157 | //! @brief Set the DMAE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3158 | #define BW_SDHC_IRQSTAT_DMAE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DMAE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3159 | #endif |
mbed_official | 146:f64d43ff0c18 | 3160 | //@} |
mbed_official | 146:f64d43ff0c18 | 3161 | |
mbed_official | 146:f64d43ff0c18 | 3162 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 3163 | // HW_SDHC_IRQSTATEN - Interrupt Status Enable register |
mbed_official | 146:f64d43ff0c18 | 3164 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 3165 | |
mbed_official | 146:f64d43ff0c18 | 3166 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3167 | /*! |
mbed_official | 146:f64d43ff0c18 | 3168 | * @brief HW_SDHC_IRQSTATEN - Interrupt Status Enable register (RW) |
mbed_official | 146:f64d43ff0c18 | 3169 | * |
mbed_official | 146:f64d43ff0c18 | 3170 | * Reset value: 0x117F013FU |
mbed_official | 146:f64d43ff0c18 | 3171 | * |
mbed_official | 146:f64d43ff0c18 | 3172 | * Setting the bits in this register to 1 enables the corresponding interrupt |
mbed_official | 146:f64d43ff0c18 | 3173 | * status to be set by the specified event. If any bit is cleared, the |
mbed_official | 146:f64d43ff0c18 | 3174 | * corresponding interrupt status bit is also cleared, that is, when the bit in this register |
mbed_official | 146:f64d43ff0c18 | 3175 | * is cleared, the corresponding bit in interrupt status register is always 0. |
mbed_official | 146:f64d43ff0c18 | 3176 | * Depending on PROCTL[IABG] bit setting, SDHC may be programmed to sample the |
mbed_official | 146:f64d43ff0c18 | 3177 | * card interrupt signal during the interrupt period and hold its value in the |
mbed_official | 146:f64d43ff0c18 | 3178 | * flip-flop. There will be some delays on the card interrupt, asserted from the card, |
mbed_official | 146:f64d43ff0c18 | 3179 | * to the time the host system is informed. To detect a CMD line conflict, the |
mbed_official | 146:f64d43ff0c18 | 3180 | * host driver must set both IRQSTATEN[CTOESEN] and IRQSTATEN[CCESEN] to 1. |
mbed_official | 146:f64d43ff0c18 | 3181 | */ |
mbed_official | 146:f64d43ff0c18 | 3182 | typedef union _hw_sdhc_irqstaten |
mbed_official | 146:f64d43ff0c18 | 3183 | { |
mbed_official | 146:f64d43ff0c18 | 3184 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 3185 | struct _hw_sdhc_irqstaten_bitfields |
mbed_official | 146:f64d43ff0c18 | 3186 | { |
mbed_official | 146:f64d43ff0c18 | 3187 | uint32_t CCSEN : 1; //!< [0] Command Complete Status Enable |
mbed_official | 146:f64d43ff0c18 | 3188 | uint32_t TCSEN : 1; //!< [1] Transfer Complete Status Enable |
mbed_official | 146:f64d43ff0c18 | 3189 | uint32_t BGESEN : 1; //!< [2] Block Gap Event Status Enable |
mbed_official | 146:f64d43ff0c18 | 3190 | uint32_t DINTSEN : 1; //!< [3] DMA Interrupt Status Enable |
mbed_official | 146:f64d43ff0c18 | 3191 | uint32_t BWRSEN : 1; //!< [4] Buffer Write Ready Status Enable |
mbed_official | 146:f64d43ff0c18 | 3192 | uint32_t BRRSEN : 1; //!< [5] Buffer Read Ready Status Enable |
mbed_official | 146:f64d43ff0c18 | 3193 | uint32_t CINSEN : 1; //!< [6] Card Insertion Status Enable |
mbed_official | 146:f64d43ff0c18 | 3194 | uint32_t CRMSEN : 1; //!< [7] Card Removal Status Enable |
mbed_official | 146:f64d43ff0c18 | 3195 | uint32_t CINTSEN : 1; //!< [8] Card Interrupt Status Enable |
mbed_official | 146:f64d43ff0c18 | 3196 | uint32_t RESERVED0 : 7; //!< [15:9] |
mbed_official | 146:f64d43ff0c18 | 3197 | uint32_t CTOESEN : 1; //!< [16] Command Timeout Error Status Enable |
mbed_official | 146:f64d43ff0c18 | 3198 | uint32_t CCESEN : 1; //!< [17] Command CRC Error Status Enable |
mbed_official | 146:f64d43ff0c18 | 3199 | uint32_t CEBESEN : 1; //!< [18] Command End Bit Error Status Enable |
mbed_official | 146:f64d43ff0c18 | 3200 | uint32_t CIESEN : 1; //!< [19] Command Index Error Status Enable |
mbed_official | 146:f64d43ff0c18 | 3201 | uint32_t DTOESEN : 1; //!< [20] Data Timeout Error Status Enable |
mbed_official | 146:f64d43ff0c18 | 3202 | uint32_t DCESEN : 1; //!< [21] Data CRC Error Status Enable |
mbed_official | 146:f64d43ff0c18 | 3203 | uint32_t DEBESEN : 1; //!< [22] Data End Bit Error Status Enable |
mbed_official | 146:f64d43ff0c18 | 3204 | uint32_t RESERVED1 : 1; //!< [23] |
mbed_official | 146:f64d43ff0c18 | 3205 | uint32_t AC12ESEN : 1; //!< [24] Auto CMD12 Error Status Enable |
mbed_official | 146:f64d43ff0c18 | 3206 | uint32_t RESERVED2 : 3; //!< [27:25] |
mbed_official | 146:f64d43ff0c18 | 3207 | uint32_t DMAESEN : 1; //!< [28] DMA Error Status Enable |
mbed_official | 146:f64d43ff0c18 | 3208 | uint32_t RESERVED3 : 3; //!< [31:29] |
mbed_official | 146:f64d43ff0c18 | 3209 | } B; |
mbed_official | 146:f64d43ff0c18 | 3210 | } hw_sdhc_irqstaten_t; |
mbed_official | 146:f64d43ff0c18 | 3211 | #endif |
mbed_official | 146:f64d43ff0c18 | 3212 | |
mbed_official | 146:f64d43ff0c18 | 3213 | /*! |
mbed_official | 146:f64d43ff0c18 | 3214 | * @name Constants and macros for entire SDHC_IRQSTATEN register |
mbed_official | 146:f64d43ff0c18 | 3215 | */ |
mbed_official | 146:f64d43ff0c18 | 3216 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3217 | #define HW_SDHC_IRQSTATEN_ADDR (REGS_SDHC_BASE + 0x34U) |
mbed_official | 146:f64d43ff0c18 | 3218 | |
mbed_official | 146:f64d43ff0c18 | 3219 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3220 | #define HW_SDHC_IRQSTATEN (*(__IO hw_sdhc_irqstaten_t *) HW_SDHC_IRQSTATEN_ADDR) |
mbed_official | 146:f64d43ff0c18 | 3221 | #define HW_SDHC_IRQSTATEN_RD() (HW_SDHC_IRQSTATEN.U) |
mbed_official | 146:f64d43ff0c18 | 3222 | #define HW_SDHC_IRQSTATEN_WR(v) (HW_SDHC_IRQSTATEN.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 3223 | #define HW_SDHC_IRQSTATEN_SET(v) (HW_SDHC_IRQSTATEN_WR(HW_SDHC_IRQSTATEN_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 3224 | #define HW_SDHC_IRQSTATEN_CLR(v) (HW_SDHC_IRQSTATEN_WR(HW_SDHC_IRQSTATEN_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 3225 | #define HW_SDHC_IRQSTATEN_TOG(v) (HW_SDHC_IRQSTATEN_WR(HW_SDHC_IRQSTATEN_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 3226 | #endif |
mbed_official | 146:f64d43ff0c18 | 3227 | //@} |
mbed_official | 146:f64d43ff0c18 | 3228 | |
mbed_official | 146:f64d43ff0c18 | 3229 | /* |
mbed_official | 146:f64d43ff0c18 | 3230 | * Constants & macros for individual SDHC_IRQSTATEN bitfields |
mbed_official | 146:f64d43ff0c18 | 3231 | */ |
mbed_official | 146:f64d43ff0c18 | 3232 | |
mbed_official | 146:f64d43ff0c18 | 3233 | /*! |
mbed_official | 146:f64d43ff0c18 | 3234 | * @name Register SDHC_IRQSTATEN, field CCSEN[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 3235 | * |
mbed_official | 146:f64d43ff0c18 | 3236 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3237 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3238 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3239 | */ |
mbed_official | 146:f64d43ff0c18 | 3240 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3241 | #define BP_SDHC_IRQSTATEN_CCSEN (0U) //!< Bit position for SDHC_IRQSTATEN_CCSEN. |
mbed_official | 146:f64d43ff0c18 | 3242 | #define BM_SDHC_IRQSTATEN_CCSEN (0x00000001U) //!< Bit mask for SDHC_IRQSTATEN_CCSEN. |
mbed_official | 146:f64d43ff0c18 | 3243 | #define BS_SDHC_IRQSTATEN_CCSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CCSEN. |
mbed_official | 146:f64d43ff0c18 | 3244 | |
mbed_official | 146:f64d43ff0c18 | 3245 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3246 | //! @brief Read current value of the SDHC_IRQSTATEN_CCSEN field. |
mbed_official | 146:f64d43ff0c18 | 3247 | #define BR_SDHC_IRQSTATEN_CCSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CCSEN)) |
mbed_official | 146:f64d43ff0c18 | 3248 | #endif |
mbed_official | 146:f64d43ff0c18 | 3249 | |
mbed_official | 146:f64d43ff0c18 | 3250 | //! @brief Format value for bitfield SDHC_IRQSTATEN_CCSEN. |
mbed_official | 146:f64d43ff0c18 | 3251 | #define BF_SDHC_IRQSTATEN_CCSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CCSEN), uint32_t) & BM_SDHC_IRQSTATEN_CCSEN) |
mbed_official | 146:f64d43ff0c18 | 3252 | |
mbed_official | 146:f64d43ff0c18 | 3253 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3254 | //! @brief Set the CCSEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3255 | #define BW_SDHC_IRQSTATEN_CCSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CCSEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3256 | #endif |
mbed_official | 146:f64d43ff0c18 | 3257 | //@} |
mbed_official | 146:f64d43ff0c18 | 3258 | |
mbed_official | 146:f64d43ff0c18 | 3259 | /*! |
mbed_official | 146:f64d43ff0c18 | 3260 | * @name Register SDHC_IRQSTATEN, field TCSEN[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 3261 | * |
mbed_official | 146:f64d43ff0c18 | 3262 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3263 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3264 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3265 | */ |
mbed_official | 146:f64d43ff0c18 | 3266 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3267 | #define BP_SDHC_IRQSTATEN_TCSEN (1U) //!< Bit position for SDHC_IRQSTATEN_TCSEN. |
mbed_official | 146:f64d43ff0c18 | 3268 | #define BM_SDHC_IRQSTATEN_TCSEN (0x00000002U) //!< Bit mask for SDHC_IRQSTATEN_TCSEN. |
mbed_official | 146:f64d43ff0c18 | 3269 | #define BS_SDHC_IRQSTATEN_TCSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_TCSEN. |
mbed_official | 146:f64d43ff0c18 | 3270 | |
mbed_official | 146:f64d43ff0c18 | 3271 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3272 | //! @brief Read current value of the SDHC_IRQSTATEN_TCSEN field. |
mbed_official | 146:f64d43ff0c18 | 3273 | #define BR_SDHC_IRQSTATEN_TCSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_TCSEN)) |
mbed_official | 146:f64d43ff0c18 | 3274 | #endif |
mbed_official | 146:f64d43ff0c18 | 3275 | |
mbed_official | 146:f64d43ff0c18 | 3276 | //! @brief Format value for bitfield SDHC_IRQSTATEN_TCSEN. |
mbed_official | 146:f64d43ff0c18 | 3277 | #define BF_SDHC_IRQSTATEN_TCSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_TCSEN), uint32_t) & BM_SDHC_IRQSTATEN_TCSEN) |
mbed_official | 146:f64d43ff0c18 | 3278 | |
mbed_official | 146:f64d43ff0c18 | 3279 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3280 | //! @brief Set the TCSEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3281 | #define BW_SDHC_IRQSTATEN_TCSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_TCSEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3282 | #endif |
mbed_official | 146:f64d43ff0c18 | 3283 | //@} |
mbed_official | 146:f64d43ff0c18 | 3284 | |
mbed_official | 146:f64d43ff0c18 | 3285 | /*! |
mbed_official | 146:f64d43ff0c18 | 3286 | * @name Register SDHC_IRQSTATEN, field BGESEN[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 3287 | * |
mbed_official | 146:f64d43ff0c18 | 3288 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3289 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3290 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3291 | */ |
mbed_official | 146:f64d43ff0c18 | 3292 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3293 | #define BP_SDHC_IRQSTATEN_BGESEN (2U) //!< Bit position for SDHC_IRQSTATEN_BGESEN. |
mbed_official | 146:f64d43ff0c18 | 3294 | #define BM_SDHC_IRQSTATEN_BGESEN (0x00000004U) //!< Bit mask for SDHC_IRQSTATEN_BGESEN. |
mbed_official | 146:f64d43ff0c18 | 3295 | #define BS_SDHC_IRQSTATEN_BGESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_BGESEN. |
mbed_official | 146:f64d43ff0c18 | 3296 | |
mbed_official | 146:f64d43ff0c18 | 3297 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3298 | //! @brief Read current value of the SDHC_IRQSTATEN_BGESEN field. |
mbed_official | 146:f64d43ff0c18 | 3299 | #define BR_SDHC_IRQSTATEN_BGESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BGESEN)) |
mbed_official | 146:f64d43ff0c18 | 3300 | #endif |
mbed_official | 146:f64d43ff0c18 | 3301 | |
mbed_official | 146:f64d43ff0c18 | 3302 | //! @brief Format value for bitfield SDHC_IRQSTATEN_BGESEN. |
mbed_official | 146:f64d43ff0c18 | 3303 | #define BF_SDHC_IRQSTATEN_BGESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_BGESEN), uint32_t) & BM_SDHC_IRQSTATEN_BGESEN) |
mbed_official | 146:f64d43ff0c18 | 3304 | |
mbed_official | 146:f64d43ff0c18 | 3305 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3306 | //! @brief Set the BGESEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3307 | #define BW_SDHC_IRQSTATEN_BGESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BGESEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3308 | #endif |
mbed_official | 146:f64d43ff0c18 | 3309 | //@} |
mbed_official | 146:f64d43ff0c18 | 3310 | |
mbed_official | 146:f64d43ff0c18 | 3311 | /*! |
mbed_official | 146:f64d43ff0c18 | 3312 | * @name Register SDHC_IRQSTATEN, field DINTSEN[3] (RW) |
mbed_official | 146:f64d43ff0c18 | 3313 | * |
mbed_official | 146:f64d43ff0c18 | 3314 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3315 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3316 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3317 | */ |
mbed_official | 146:f64d43ff0c18 | 3318 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3319 | #define BP_SDHC_IRQSTATEN_DINTSEN (3U) //!< Bit position for SDHC_IRQSTATEN_DINTSEN. |
mbed_official | 146:f64d43ff0c18 | 3320 | #define BM_SDHC_IRQSTATEN_DINTSEN (0x00000008U) //!< Bit mask for SDHC_IRQSTATEN_DINTSEN. |
mbed_official | 146:f64d43ff0c18 | 3321 | #define BS_SDHC_IRQSTATEN_DINTSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_DINTSEN. |
mbed_official | 146:f64d43ff0c18 | 3322 | |
mbed_official | 146:f64d43ff0c18 | 3323 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3324 | //! @brief Read current value of the SDHC_IRQSTATEN_DINTSEN field. |
mbed_official | 146:f64d43ff0c18 | 3325 | #define BR_SDHC_IRQSTATEN_DINTSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DINTSEN)) |
mbed_official | 146:f64d43ff0c18 | 3326 | #endif |
mbed_official | 146:f64d43ff0c18 | 3327 | |
mbed_official | 146:f64d43ff0c18 | 3328 | //! @brief Format value for bitfield SDHC_IRQSTATEN_DINTSEN. |
mbed_official | 146:f64d43ff0c18 | 3329 | #define BF_SDHC_IRQSTATEN_DINTSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DINTSEN), uint32_t) & BM_SDHC_IRQSTATEN_DINTSEN) |
mbed_official | 146:f64d43ff0c18 | 3330 | |
mbed_official | 146:f64d43ff0c18 | 3331 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3332 | //! @brief Set the DINTSEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3333 | #define BW_SDHC_IRQSTATEN_DINTSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DINTSEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3334 | #endif |
mbed_official | 146:f64d43ff0c18 | 3335 | //@} |
mbed_official | 146:f64d43ff0c18 | 3336 | |
mbed_official | 146:f64d43ff0c18 | 3337 | /*! |
mbed_official | 146:f64d43ff0c18 | 3338 | * @name Register SDHC_IRQSTATEN, field BWRSEN[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 3339 | * |
mbed_official | 146:f64d43ff0c18 | 3340 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3341 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3342 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3343 | */ |
mbed_official | 146:f64d43ff0c18 | 3344 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3345 | #define BP_SDHC_IRQSTATEN_BWRSEN (4U) //!< Bit position for SDHC_IRQSTATEN_BWRSEN. |
mbed_official | 146:f64d43ff0c18 | 3346 | #define BM_SDHC_IRQSTATEN_BWRSEN (0x00000010U) //!< Bit mask for SDHC_IRQSTATEN_BWRSEN. |
mbed_official | 146:f64d43ff0c18 | 3347 | #define BS_SDHC_IRQSTATEN_BWRSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_BWRSEN. |
mbed_official | 146:f64d43ff0c18 | 3348 | |
mbed_official | 146:f64d43ff0c18 | 3349 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3350 | //! @brief Read current value of the SDHC_IRQSTATEN_BWRSEN field. |
mbed_official | 146:f64d43ff0c18 | 3351 | #define BR_SDHC_IRQSTATEN_BWRSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BWRSEN)) |
mbed_official | 146:f64d43ff0c18 | 3352 | #endif |
mbed_official | 146:f64d43ff0c18 | 3353 | |
mbed_official | 146:f64d43ff0c18 | 3354 | //! @brief Format value for bitfield SDHC_IRQSTATEN_BWRSEN. |
mbed_official | 146:f64d43ff0c18 | 3355 | #define BF_SDHC_IRQSTATEN_BWRSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_BWRSEN), uint32_t) & BM_SDHC_IRQSTATEN_BWRSEN) |
mbed_official | 146:f64d43ff0c18 | 3356 | |
mbed_official | 146:f64d43ff0c18 | 3357 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3358 | //! @brief Set the BWRSEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3359 | #define BW_SDHC_IRQSTATEN_BWRSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BWRSEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3360 | #endif |
mbed_official | 146:f64d43ff0c18 | 3361 | //@} |
mbed_official | 146:f64d43ff0c18 | 3362 | |
mbed_official | 146:f64d43ff0c18 | 3363 | /*! |
mbed_official | 146:f64d43ff0c18 | 3364 | * @name Register SDHC_IRQSTATEN, field BRRSEN[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 3365 | * |
mbed_official | 146:f64d43ff0c18 | 3366 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3367 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3368 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3369 | */ |
mbed_official | 146:f64d43ff0c18 | 3370 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3371 | #define BP_SDHC_IRQSTATEN_BRRSEN (5U) //!< Bit position for SDHC_IRQSTATEN_BRRSEN. |
mbed_official | 146:f64d43ff0c18 | 3372 | #define BM_SDHC_IRQSTATEN_BRRSEN (0x00000020U) //!< Bit mask for SDHC_IRQSTATEN_BRRSEN. |
mbed_official | 146:f64d43ff0c18 | 3373 | #define BS_SDHC_IRQSTATEN_BRRSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_BRRSEN. |
mbed_official | 146:f64d43ff0c18 | 3374 | |
mbed_official | 146:f64d43ff0c18 | 3375 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3376 | //! @brief Read current value of the SDHC_IRQSTATEN_BRRSEN field. |
mbed_official | 146:f64d43ff0c18 | 3377 | #define BR_SDHC_IRQSTATEN_BRRSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BRRSEN)) |
mbed_official | 146:f64d43ff0c18 | 3378 | #endif |
mbed_official | 146:f64d43ff0c18 | 3379 | |
mbed_official | 146:f64d43ff0c18 | 3380 | //! @brief Format value for bitfield SDHC_IRQSTATEN_BRRSEN. |
mbed_official | 146:f64d43ff0c18 | 3381 | #define BF_SDHC_IRQSTATEN_BRRSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_BRRSEN), uint32_t) & BM_SDHC_IRQSTATEN_BRRSEN) |
mbed_official | 146:f64d43ff0c18 | 3382 | |
mbed_official | 146:f64d43ff0c18 | 3383 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3384 | //! @brief Set the BRRSEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3385 | #define BW_SDHC_IRQSTATEN_BRRSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BRRSEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3386 | #endif |
mbed_official | 146:f64d43ff0c18 | 3387 | //@} |
mbed_official | 146:f64d43ff0c18 | 3388 | |
mbed_official | 146:f64d43ff0c18 | 3389 | /*! |
mbed_official | 146:f64d43ff0c18 | 3390 | * @name Register SDHC_IRQSTATEN, field CINSEN[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 3391 | * |
mbed_official | 146:f64d43ff0c18 | 3392 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3393 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3394 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3395 | */ |
mbed_official | 146:f64d43ff0c18 | 3396 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3397 | #define BP_SDHC_IRQSTATEN_CINSEN (6U) //!< Bit position for SDHC_IRQSTATEN_CINSEN. |
mbed_official | 146:f64d43ff0c18 | 3398 | #define BM_SDHC_IRQSTATEN_CINSEN (0x00000040U) //!< Bit mask for SDHC_IRQSTATEN_CINSEN. |
mbed_official | 146:f64d43ff0c18 | 3399 | #define BS_SDHC_IRQSTATEN_CINSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CINSEN. |
mbed_official | 146:f64d43ff0c18 | 3400 | |
mbed_official | 146:f64d43ff0c18 | 3401 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3402 | //! @brief Read current value of the SDHC_IRQSTATEN_CINSEN field. |
mbed_official | 146:f64d43ff0c18 | 3403 | #define BR_SDHC_IRQSTATEN_CINSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CINSEN)) |
mbed_official | 146:f64d43ff0c18 | 3404 | #endif |
mbed_official | 146:f64d43ff0c18 | 3405 | |
mbed_official | 146:f64d43ff0c18 | 3406 | //! @brief Format value for bitfield SDHC_IRQSTATEN_CINSEN. |
mbed_official | 146:f64d43ff0c18 | 3407 | #define BF_SDHC_IRQSTATEN_CINSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CINSEN), uint32_t) & BM_SDHC_IRQSTATEN_CINSEN) |
mbed_official | 146:f64d43ff0c18 | 3408 | |
mbed_official | 146:f64d43ff0c18 | 3409 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3410 | //! @brief Set the CINSEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3411 | #define BW_SDHC_IRQSTATEN_CINSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CINSEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3412 | #endif |
mbed_official | 146:f64d43ff0c18 | 3413 | //@} |
mbed_official | 146:f64d43ff0c18 | 3414 | |
mbed_official | 146:f64d43ff0c18 | 3415 | /*! |
mbed_official | 146:f64d43ff0c18 | 3416 | * @name Register SDHC_IRQSTATEN, field CRMSEN[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 3417 | * |
mbed_official | 146:f64d43ff0c18 | 3418 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3419 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3420 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3421 | */ |
mbed_official | 146:f64d43ff0c18 | 3422 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3423 | #define BP_SDHC_IRQSTATEN_CRMSEN (7U) //!< Bit position for SDHC_IRQSTATEN_CRMSEN. |
mbed_official | 146:f64d43ff0c18 | 3424 | #define BM_SDHC_IRQSTATEN_CRMSEN (0x00000080U) //!< Bit mask for SDHC_IRQSTATEN_CRMSEN. |
mbed_official | 146:f64d43ff0c18 | 3425 | #define BS_SDHC_IRQSTATEN_CRMSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CRMSEN. |
mbed_official | 146:f64d43ff0c18 | 3426 | |
mbed_official | 146:f64d43ff0c18 | 3427 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3428 | //! @brief Read current value of the SDHC_IRQSTATEN_CRMSEN field. |
mbed_official | 146:f64d43ff0c18 | 3429 | #define BR_SDHC_IRQSTATEN_CRMSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CRMSEN)) |
mbed_official | 146:f64d43ff0c18 | 3430 | #endif |
mbed_official | 146:f64d43ff0c18 | 3431 | |
mbed_official | 146:f64d43ff0c18 | 3432 | //! @brief Format value for bitfield SDHC_IRQSTATEN_CRMSEN. |
mbed_official | 146:f64d43ff0c18 | 3433 | #define BF_SDHC_IRQSTATEN_CRMSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CRMSEN), uint32_t) & BM_SDHC_IRQSTATEN_CRMSEN) |
mbed_official | 146:f64d43ff0c18 | 3434 | |
mbed_official | 146:f64d43ff0c18 | 3435 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3436 | //! @brief Set the CRMSEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3437 | #define BW_SDHC_IRQSTATEN_CRMSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CRMSEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3438 | #endif |
mbed_official | 146:f64d43ff0c18 | 3439 | //@} |
mbed_official | 146:f64d43ff0c18 | 3440 | |
mbed_official | 146:f64d43ff0c18 | 3441 | /*! |
mbed_official | 146:f64d43ff0c18 | 3442 | * @name Register SDHC_IRQSTATEN, field CINTSEN[8] (RW) |
mbed_official | 146:f64d43ff0c18 | 3443 | * |
mbed_official | 146:f64d43ff0c18 | 3444 | * If this bit is set to 0, the SDHC will clear the interrupt request to the |
mbed_official | 146:f64d43ff0c18 | 3445 | * system. The card interrupt detection is stopped when this bit is cleared and |
mbed_official | 146:f64d43ff0c18 | 3446 | * restarted when this bit is set to 1. The host driver must clear the this bit |
mbed_official | 146:f64d43ff0c18 | 3447 | * before servicing the card interrupt and must set this bit again after all interrupt |
mbed_official | 146:f64d43ff0c18 | 3448 | * requests from the card are cleared to prevent inadvertent interrupts. |
mbed_official | 146:f64d43ff0c18 | 3449 | * |
mbed_official | 146:f64d43ff0c18 | 3450 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3451 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3452 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3453 | */ |
mbed_official | 146:f64d43ff0c18 | 3454 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3455 | #define BP_SDHC_IRQSTATEN_CINTSEN (8U) //!< Bit position for SDHC_IRQSTATEN_CINTSEN. |
mbed_official | 146:f64d43ff0c18 | 3456 | #define BM_SDHC_IRQSTATEN_CINTSEN (0x00000100U) //!< Bit mask for SDHC_IRQSTATEN_CINTSEN. |
mbed_official | 146:f64d43ff0c18 | 3457 | #define BS_SDHC_IRQSTATEN_CINTSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CINTSEN. |
mbed_official | 146:f64d43ff0c18 | 3458 | |
mbed_official | 146:f64d43ff0c18 | 3459 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3460 | //! @brief Read current value of the SDHC_IRQSTATEN_CINTSEN field. |
mbed_official | 146:f64d43ff0c18 | 3461 | #define BR_SDHC_IRQSTATEN_CINTSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CINTSEN)) |
mbed_official | 146:f64d43ff0c18 | 3462 | #endif |
mbed_official | 146:f64d43ff0c18 | 3463 | |
mbed_official | 146:f64d43ff0c18 | 3464 | //! @brief Format value for bitfield SDHC_IRQSTATEN_CINTSEN. |
mbed_official | 146:f64d43ff0c18 | 3465 | #define BF_SDHC_IRQSTATEN_CINTSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CINTSEN), uint32_t) & BM_SDHC_IRQSTATEN_CINTSEN) |
mbed_official | 146:f64d43ff0c18 | 3466 | |
mbed_official | 146:f64d43ff0c18 | 3467 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3468 | //! @brief Set the CINTSEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3469 | #define BW_SDHC_IRQSTATEN_CINTSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CINTSEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3470 | #endif |
mbed_official | 146:f64d43ff0c18 | 3471 | //@} |
mbed_official | 146:f64d43ff0c18 | 3472 | |
mbed_official | 146:f64d43ff0c18 | 3473 | /*! |
mbed_official | 146:f64d43ff0c18 | 3474 | * @name Register SDHC_IRQSTATEN, field CTOESEN[16] (RW) |
mbed_official | 146:f64d43ff0c18 | 3475 | * |
mbed_official | 146:f64d43ff0c18 | 3476 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3477 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3478 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3479 | */ |
mbed_official | 146:f64d43ff0c18 | 3480 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3481 | #define BP_SDHC_IRQSTATEN_CTOESEN (16U) //!< Bit position for SDHC_IRQSTATEN_CTOESEN. |
mbed_official | 146:f64d43ff0c18 | 3482 | #define BM_SDHC_IRQSTATEN_CTOESEN (0x00010000U) //!< Bit mask for SDHC_IRQSTATEN_CTOESEN. |
mbed_official | 146:f64d43ff0c18 | 3483 | #define BS_SDHC_IRQSTATEN_CTOESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CTOESEN. |
mbed_official | 146:f64d43ff0c18 | 3484 | |
mbed_official | 146:f64d43ff0c18 | 3485 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3486 | //! @brief Read current value of the SDHC_IRQSTATEN_CTOESEN field. |
mbed_official | 146:f64d43ff0c18 | 3487 | #define BR_SDHC_IRQSTATEN_CTOESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CTOESEN)) |
mbed_official | 146:f64d43ff0c18 | 3488 | #endif |
mbed_official | 146:f64d43ff0c18 | 3489 | |
mbed_official | 146:f64d43ff0c18 | 3490 | //! @brief Format value for bitfield SDHC_IRQSTATEN_CTOESEN. |
mbed_official | 146:f64d43ff0c18 | 3491 | #define BF_SDHC_IRQSTATEN_CTOESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CTOESEN), uint32_t) & BM_SDHC_IRQSTATEN_CTOESEN) |
mbed_official | 146:f64d43ff0c18 | 3492 | |
mbed_official | 146:f64d43ff0c18 | 3493 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3494 | //! @brief Set the CTOESEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3495 | #define BW_SDHC_IRQSTATEN_CTOESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CTOESEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3496 | #endif |
mbed_official | 146:f64d43ff0c18 | 3497 | //@} |
mbed_official | 146:f64d43ff0c18 | 3498 | |
mbed_official | 146:f64d43ff0c18 | 3499 | /*! |
mbed_official | 146:f64d43ff0c18 | 3500 | * @name Register SDHC_IRQSTATEN, field CCESEN[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 3501 | * |
mbed_official | 146:f64d43ff0c18 | 3502 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3503 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3504 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3505 | */ |
mbed_official | 146:f64d43ff0c18 | 3506 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3507 | #define BP_SDHC_IRQSTATEN_CCESEN (17U) //!< Bit position for SDHC_IRQSTATEN_CCESEN. |
mbed_official | 146:f64d43ff0c18 | 3508 | #define BM_SDHC_IRQSTATEN_CCESEN (0x00020000U) //!< Bit mask for SDHC_IRQSTATEN_CCESEN. |
mbed_official | 146:f64d43ff0c18 | 3509 | #define BS_SDHC_IRQSTATEN_CCESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CCESEN. |
mbed_official | 146:f64d43ff0c18 | 3510 | |
mbed_official | 146:f64d43ff0c18 | 3511 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3512 | //! @brief Read current value of the SDHC_IRQSTATEN_CCESEN field. |
mbed_official | 146:f64d43ff0c18 | 3513 | #define BR_SDHC_IRQSTATEN_CCESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CCESEN)) |
mbed_official | 146:f64d43ff0c18 | 3514 | #endif |
mbed_official | 146:f64d43ff0c18 | 3515 | |
mbed_official | 146:f64d43ff0c18 | 3516 | //! @brief Format value for bitfield SDHC_IRQSTATEN_CCESEN. |
mbed_official | 146:f64d43ff0c18 | 3517 | #define BF_SDHC_IRQSTATEN_CCESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CCESEN), uint32_t) & BM_SDHC_IRQSTATEN_CCESEN) |
mbed_official | 146:f64d43ff0c18 | 3518 | |
mbed_official | 146:f64d43ff0c18 | 3519 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3520 | //! @brief Set the CCESEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3521 | #define BW_SDHC_IRQSTATEN_CCESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CCESEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3522 | #endif |
mbed_official | 146:f64d43ff0c18 | 3523 | //@} |
mbed_official | 146:f64d43ff0c18 | 3524 | |
mbed_official | 146:f64d43ff0c18 | 3525 | /*! |
mbed_official | 146:f64d43ff0c18 | 3526 | * @name Register SDHC_IRQSTATEN, field CEBESEN[18] (RW) |
mbed_official | 146:f64d43ff0c18 | 3527 | * |
mbed_official | 146:f64d43ff0c18 | 3528 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3529 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3530 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3531 | */ |
mbed_official | 146:f64d43ff0c18 | 3532 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3533 | #define BP_SDHC_IRQSTATEN_CEBESEN (18U) //!< Bit position for SDHC_IRQSTATEN_CEBESEN. |
mbed_official | 146:f64d43ff0c18 | 3534 | #define BM_SDHC_IRQSTATEN_CEBESEN (0x00040000U) //!< Bit mask for SDHC_IRQSTATEN_CEBESEN. |
mbed_official | 146:f64d43ff0c18 | 3535 | #define BS_SDHC_IRQSTATEN_CEBESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CEBESEN. |
mbed_official | 146:f64d43ff0c18 | 3536 | |
mbed_official | 146:f64d43ff0c18 | 3537 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3538 | //! @brief Read current value of the SDHC_IRQSTATEN_CEBESEN field. |
mbed_official | 146:f64d43ff0c18 | 3539 | #define BR_SDHC_IRQSTATEN_CEBESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CEBESEN)) |
mbed_official | 146:f64d43ff0c18 | 3540 | #endif |
mbed_official | 146:f64d43ff0c18 | 3541 | |
mbed_official | 146:f64d43ff0c18 | 3542 | //! @brief Format value for bitfield SDHC_IRQSTATEN_CEBESEN. |
mbed_official | 146:f64d43ff0c18 | 3543 | #define BF_SDHC_IRQSTATEN_CEBESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CEBESEN), uint32_t) & BM_SDHC_IRQSTATEN_CEBESEN) |
mbed_official | 146:f64d43ff0c18 | 3544 | |
mbed_official | 146:f64d43ff0c18 | 3545 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3546 | //! @brief Set the CEBESEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3547 | #define BW_SDHC_IRQSTATEN_CEBESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CEBESEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3548 | #endif |
mbed_official | 146:f64d43ff0c18 | 3549 | //@} |
mbed_official | 146:f64d43ff0c18 | 3550 | |
mbed_official | 146:f64d43ff0c18 | 3551 | /*! |
mbed_official | 146:f64d43ff0c18 | 3552 | * @name Register SDHC_IRQSTATEN, field CIESEN[19] (RW) |
mbed_official | 146:f64d43ff0c18 | 3553 | * |
mbed_official | 146:f64d43ff0c18 | 3554 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3555 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3556 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3557 | */ |
mbed_official | 146:f64d43ff0c18 | 3558 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3559 | #define BP_SDHC_IRQSTATEN_CIESEN (19U) //!< Bit position for SDHC_IRQSTATEN_CIESEN. |
mbed_official | 146:f64d43ff0c18 | 3560 | #define BM_SDHC_IRQSTATEN_CIESEN (0x00080000U) //!< Bit mask for SDHC_IRQSTATEN_CIESEN. |
mbed_official | 146:f64d43ff0c18 | 3561 | #define BS_SDHC_IRQSTATEN_CIESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CIESEN. |
mbed_official | 146:f64d43ff0c18 | 3562 | |
mbed_official | 146:f64d43ff0c18 | 3563 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3564 | //! @brief Read current value of the SDHC_IRQSTATEN_CIESEN field. |
mbed_official | 146:f64d43ff0c18 | 3565 | #define BR_SDHC_IRQSTATEN_CIESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CIESEN)) |
mbed_official | 146:f64d43ff0c18 | 3566 | #endif |
mbed_official | 146:f64d43ff0c18 | 3567 | |
mbed_official | 146:f64d43ff0c18 | 3568 | //! @brief Format value for bitfield SDHC_IRQSTATEN_CIESEN. |
mbed_official | 146:f64d43ff0c18 | 3569 | #define BF_SDHC_IRQSTATEN_CIESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CIESEN), uint32_t) & BM_SDHC_IRQSTATEN_CIESEN) |
mbed_official | 146:f64d43ff0c18 | 3570 | |
mbed_official | 146:f64d43ff0c18 | 3571 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3572 | //! @brief Set the CIESEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3573 | #define BW_SDHC_IRQSTATEN_CIESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CIESEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3574 | #endif |
mbed_official | 146:f64d43ff0c18 | 3575 | //@} |
mbed_official | 146:f64d43ff0c18 | 3576 | |
mbed_official | 146:f64d43ff0c18 | 3577 | /*! |
mbed_official | 146:f64d43ff0c18 | 3578 | * @name Register SDHC_IRQSTATEN, field DTOESEN[20] (RW) |
mbed_official | 146:f64d43ff0c18 | 3579 | * |
mbed_official | 146:f64d43ff0c18 | 3580 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3581 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3582 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3583 | */ |
mbed_official | 146:f64d43ff0c18 | 3584 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3585 | #define BP_SDHC_IRQSTATEN_DTOESEN (20U) //!< Bit position for SDHC_IRQSTATEN_DTOESEN. |
mbed_official | 146:f64d43ff0c18 | 3586 | #define BM_SDHC_IRQSTATEN_DTOESEN (0x00100000U) //!< Bit mask for SDHC_IRQSTATEN_DTOESEN. |
mbed_official | 146:f64d43ff0c18 | 3587 | #define BS_SDHC_IRQSTATEN_DTOESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_DTOESEN. |
mbed_official | 146:f64d43ff0c18 | 3588 | |
mbed_official | 146:f64d43ff0c18 | 3589 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3590 | //! @brief Read current value of the SDHC_IRQSTATEN_DTOESEN field. |
mbed_official | 146:f64d43ff0c18 | 3591 | #define BR_SDHC_IRQSTATEN_DTOESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DTOESEN)) |
mbed_official | 146:f64d43ff0c18 | 3592 | #endif |
mbed_official | 146:f64d43ff0c18 | 3593 | |
mbed_official | 146:f64d43ff0c18 | 3594 | //! @brief Format value for bitfield SDHC_IRQSTATEN_DTOESEN. |
mbed_official | 146:f64d43ff0c18 | 3595 | #define BF_SDHC_IRQSTATEN_DTOESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DTOESEN), uint32_t) & BM_SDHC_IRQSTATEN_DTOESEN) |
mbed_official | 146:f64d43ff0c18 | 3596 | |
mbed_official | 146:f64d43ff0c18 | 3597 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3598 | //! @brief Set the DTOESEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3599 | #define BW_SDHC_IRQSTATEN_DTOESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DTOESEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3600 | #endif |
mbed_official | 146:f64d43ff0c18 | 3601 | //@} |
mbed_official | 146:f64d43ff0c18 | 3602 | |
mbed_official | 146:f64d43ff0c18 | 3603 | /*! |
mbed_official | 146:f64d43ff0c18 | 3604 | * @name Register SDHC_IRQSTATEN, field DCESEN[21] (RW) |
mbed_official | 146:f64d43ff0c18 | 3605 | * |
mbed_official | 146:f64d43ff0c18 | 3606 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3607 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3608 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3609 | */ |
mbed_official | 146:f64d43ff0c18 | 3610 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3611 | #define BP_SDHC_IRQSTATEN_DCESEN (21U) //!< Bit position for SDHC_IRQSTATEN_DCESEN. |
mbed_official | 146:f64d43ff0c18 | 3612 | #define BM_SDHC_IRQSTATEN_DCESEN (0x00200000U) //!< Bit mask for SDHC_IRQSTATEN_DCESEN. |
mbed_official | 146:f64d43ff0c18 | 3613 | #define BS_SDHC_IRQSTATEN_DCESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_DCESEN. |
mbed_official | 146:f64d43ff0c18 | 3614 | |
mbed_official | 146:f64d43ff0c18 | 3615 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3616 | //! @brief Read current value of the SDHC_IRQSTATEN_DCESEN field. |
mbed_official | 146:f64d43ff0c18 | 3617 | #define BR_SDHC_IRQSTATEN_DCESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DCESEN)) |
mbed_official | 146:f64d43ff0c18 | 3618 | #endif |
mbed_official | 146:f64d43ff0c18 | 3619 | |
mbed_official | 146:f64d43ff0c18 | 3620 | //! @brief Format value for bitfield SDHC_IRQSTATEN_DCESEN. |
mbed_official | 146:f64d43ff0c18 | 3621 | #define BF_SDHC_IRQSTATEN_DCESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DCESEN), uint32_t) & BM_SDHC_IRQSTATEN_DCESEN) |
mbed_official | 146:f64d43ff0c18 | 3622 | |
mbed_official | 146:f64d43ff0c18 | 3623 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3624 | //! @brief Set the DCESEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3625 | #define BW_SDHC_IRQSTATEN_DCESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DCESEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3626 | #endif |
mbed_official | 146:f64d43ff0c18 | 3627 | //@} |
mbed_official | 146:f64d43ff0c18 | 3628 | |
mbed_official | 146:f64d43ff0c18 | 3629 | /*! |
mbed_official | 146:f64d43ff0c18 | 3630 | * @name Register SDHC_IRQSTATEN, field DEBESEN[22] (RW) |
mbed_official | 146:f64d43ff0c18 | 3631 | * |
mbed_official | 146:f64d43ff0c18 | 3632 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3633 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3634 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3635 | */ |
mbed_official | 146:f64d43ff0c18 | 3636 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3637 | #define BP_SDHC_IRQSTATEN_DEBESEN (22U) //!< Bit position for SDHC_IRQSTATEN_DEBESEN. |
mbed_official | 146:f64d43ff0c18 | 3638 | #define BM_SDHC_IRQSTATEN_DEBESEN (0x00400000U) //!< Bit mask for SDHC_IRQSTATEN_DEBESEN. |
mbed_official | 146:f64d43ff0c18 | 3639 | #define BS_SDHC_IRQSTATEN_DEBESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_DEBESEN. |
mbed_official | 146:f64d43ff0c18 | 3640 | |
mbed_official | 146:f64d43ff0c18 | 3641 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3642 | //! @brief Read current value of the SDHC_IRQSTATEN_DEBESEN field. |
mbed_official | 146:f64d43ff0c18 | 3643 | #define BR_SDHC_IRQSTATEN_DEBESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DEBESEN)) |
mbed_official | 146:f64d43ff0c18 | 3644 | #endif |
mbed_official | 146:f64d43ff0c18 | 3645 | |
mbed_official | 146:f64d43ff0c18 | 3646 | //! @brief Format value for bitfield SDHC_IRQSTATEN_DEBESEN. |
mbed_official | 146:f64d43ff0c18 | 3647 | #define BF_SDHC_IRQSTATEN_DEBESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DEBESEN), uint32_t) & BM_SDHC_IRQSTATEN_DEBESEN) |
mbed_official | 146:f64d43ff0c18 | 3648 | |
mbed_official | 146:f64d43ff0c18 | 3649 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3650 | //! @brief Set the DEBESEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3651 | #define BW_SDHC_IRQSTATEN_DEBESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DEBESEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3652 | #endif |
mbed_official | 146:f64d43ff0c18 | 3653 | //@} |
mbed_official | 146:f64d43ff0c18 | 3654 | |
mbed_official | 146:f64d43ff0c18 | 3655 | /*! |
mbed_official | 146:f64d43ff0c18 | 3656 | * @name Register SDHC_IRQSTATEN, field AC12ESEN[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 3657 | * |
mbed_official | 146:f64d43ff0c18 | 3658 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3659 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3660 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3661 | */ |
mbed_official | 146:f64d43ff0c18 | 3662 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3663 | #define BP_SDHC_IRQSTATEN_AC12ESEN (24U) //!< Bit position for SDHC_IRQSTATEN_AC12ESEN. |
mbed_official | 146:f64d43ff0c18 | 3664 | #define BM_SDHC_IRQSTATEN_AC12ESEN (0x01000000U) //!< Bit mask for SDHC_IRQSTATEN_AC12ESEN. |
mbed_official | 146:f64d43ff0c18 | 3665 | #define BS_SDHC_IRQSTATEN_AC12ESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_AC12ESEN. |
mbed_official | 146:f64d43ff0c18 | 3666 | |
mbed_official | 146:f64d43ff0c18 | 3667 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3668 | //! @brief Read current value of the SDHC_IRQSTATEN_AC12ESEN field. |
mbed_official | 146:f64d43ff0c18 | 3669 | #define BR_SDHC_IRQSTATEN_AC12ESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_AC12ESEN)) |
mbed_official | 146:f64d43ff0c18 | 3670 | #endif |
mbed_official | 146:f64d43ff0c18 | 3671 | |
mbed_official | 146:f64d43ff0c18 | 3672 | //! @brief Format value for bitfield SDHC_IRQSTATEN_AC12ESEN. |
mbed_official | 146:f64d43ff0c18 | 3673 | #define BF_SDHC_IRQSTATEN_AC12ESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_AC12ESEN), uint32_t) & BM_SDHC_IRQSTATEN_AC12ESEN) |
mbed_official | 146:f64d43ff0c18 | 3674 | |
mbed_official | 146:f64d43ff0c18 | 3675 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3676 | //! @brief Set the AC12ESEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3677 | #define BW_SDHC_IRQSTATEN_AC12ESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_AC12ESEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3678 | #endif |
mbed_official | 146:f64d43ff0c18 | 3679 | //@} |
mbed_official | 146:f64d43ff0c18 | 3680 | |
mbed_official | 146:f64d43ff0c18 | 3681 | /*! |
mbed_official | 146:f64d43ff0c18 | 3682 | * @name Register SDHC_IRQSTATEN, field DMAESEN[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 3683 | * |
mbed_official | 146:f64d43ff0c18 | 3684 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3685 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3686 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3687 | */ |
mbed_official | 146:f64d43ff0c18 | 3688 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3689 | #define BP_SDHC_IRQSTATEN_DMAESEN (28U) //!< Bit position for SDHC_IRQSTATEN_DMAESEN. |
mbed_official | 146:f64d43ff0c18 | 3690 | #define BM_SDHC_IRQSTATEN_DMAESEN (0x10000000U) //!< Bit mask for SDHC_IRQSTATEN_DMAESEN. |
mbed_official | 146:f64d43ff0c18 | 3691 | #define BS_SDHC_IRQSTATEN_DMAESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_DMAESEN. |
mbed_official | 146:f64d43ff0c18 | 3692 | |
mbed_official | 146:f64d43ff0c18 | 3693 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3694 | //! @brief Read current value of the SDHC_IRQSTATEN_DMAESEN field. |
mbed_official | 146:f64d43ff0c18 | 3695 | #define BR_SDHC_IRQSTATEN_DMAESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DMAESEN)) |
mbed_official | 146:f64d43ff0c18 | 3696 | #endif |
mbed_official | 146:f64d43ff0c18 | 3697 | |
mbed_official | 146:f64d43ff0c18 | 3698 | //! @brief Format value for bitfield SDHC_IRQSTATEN_DMAESEN. |
mbed_official | 146:f64d43ff0c18 | 3699 | #define BF_SDHC_IRQSTATEN_DMAESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DMAESEN), uint32_t) & BM_SDHC_IRQSTATEN_DMAESEN) |
mbed_official | 146:f64d43ff0c18 | 3700 | |
mbed_official | 146:f64d43ff0c18 | 3701 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3702 | //! @brief Set the DMAESEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3703 | #define BW_SDHC_IRQSTATEN_DMAESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DMAESEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3704 | #endif |
mbed_official | 146:f64d43ff0c18 | 3705 | //@} |
mbed_official | 146:f64d43ff0c18 | 3706 | |
mbed_official | 146:f64d43ff0c18 | 3707 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 3708 | // HW_SDHC_IRQSIGEN - Interrupt Signal Enable register |
mbed_official | 146:f64d43ff0c18 | 3709 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 3710 | |
mbed_official | 146:f64d43ff0c18 | 3711 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3712 | /*! |
mbed_official | 146:f64d43ff0c18 | 3713 | * @brief HW_SDHC_IRQSIGEN - Interrupt Signal Enable register (RW) |
mbed_official | 146:f64d43ff0c18 | 3714 | * |
mbed_official | 146:f64d43ff0c18 | 3715 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 3716 | * |
mbed_official | 146:f64d43ff0c18 | 3717 | * This register is used to select which interrupt status is indicated to the |
mbed_official | 146:f64d43ff0c18 | 3718 | * host system as the interrupt. All of these status bits share the same interrupt |
mbed_official | 146:f64d43ff0c18 | 3719 | * line. Setting any of these bits to 1 enables interrupt generation. The |
mbed_official | 146:f64d43ff0c18 | 3720 | * corresponding status register bit will generate an interrupt when the corresponding |
mbed_official | 146:f64d43ff0c18 | 3721 | * interrupt signal enable bit is set. |
mbed_official | 146:f64d43ff0c18 | 3722 | */ |
mbed_official | 146:f64d43ff0c18 | 3723 | typedef union _hw_sdhc_irqsigen |
mbed_official | 146:f64d43ff0c18 | 3724 | { |
mbed_official | 146:f64d43ff0c18 | 3725 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 3726 | struct _hw_sdhc_irqsigen_bitfields |
mbed_official | 146:f64d43ff0c18 | 3727 | { |
mbed_official | 146:f64d43ff0c18 | 3728 | uint32_t CCIEN : 1; //!< [0] Command Complete Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3729 | uint32_t TCIEN : 1; //!< [1] Transfer Complete Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3730 | uint32_t BGEIEN : 1; //!< [2] Block Gap Event Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3731 | uint32_t DINTIEN : 1; //!< [3] DMA Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3732 | uint32_t BWRIEN : 1; //!< [4] Buffer Write Ready Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3733 | uint32_t BRRIEN : 1; //!< [5] Buffer Read Ready Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3734 | uint32_t CINSIEN : 1; //!< [6] Card Insertion Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3735 | uint32_t CRMIEN : 1; //!< [7] Card Removal Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3736 | uint32_t CINTIEN : 1; //!< [8] Card Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3737 | uint32_t RESERVED0 : 7; //!< [15:9] |
mbed_official | 146:f64d43ff0c18 | 3738 | uint32_t CTOEIEN : 1; //!< [16] Command Timeout Error Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3739 | uint32_t CCEIEN : 1; //!< [17] Command CRC Error Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3740 | uint32_t CEBEIEN : 1; //!< [18] Command End Bit Error Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3741 | uint32_t CIEIEN : 1; //!< [19] Command Index Error Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3742 | uint32_t DTOEIEN : 1; //!< [20] Data Timeout Error Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3743 | uint32_t DCEIEN : 1; //!< [21] Data CRC Error Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3744 | uint32_t DEBEIEN : 1; //!< [22] Data End Bit Error Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3745 | uint32_t RESERVED1 : 1; //!< [23] |
mbed_official | 146:f64d43ff0c18 | 3746 | uint32_t AC12EIEN : 1; //!< [24] Auto CMD12 Error Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3747 | uint32_t RESERVED2 : 3; //!< [27:25] |
mbed_official | 146:f64d43ff0c18 | 3748 | uint32_t DMAEIEN : 1; //!< [28] DMA Error Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3749 | uint32_t RESERVED3 : 3; //!< [31:29] |
mbed_official | 146:f64d43ff0c18 | 3750 | } B; |
mbed_official | 146:f64d43ff0c18 | 3751 | } hw_sdhc_irqsigen_t; |
mbed_official | 146:f64d43ff0c18 | 3752 | #endif |
mbed_official | 146:f64d43ff0c18 | 3753 | |
mbed_official | 146:f64d43ff0c18 | 3754 | /*! |
mbed_official | 146:f64d43ff0c18 | 3755 | * @name Constants and macros for entire SDHC_IRQSIGEN register |
mbed_official | 146:f64d43ff0c18 | 3756 | */ |
mbed_official | 146:f64d43ff0c18 | 3757 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3758 | #define HW_SDHC_IRQSIGEN_ADDR (REGS_SDHC_BASE + 0x38U) |
mbed_official | 146:f64d43ff0c18 | 3759 | |
mbed_official | 146:f64d43ff0c18 | 3760 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3761 | #define HW_SDHC_IRQSIGEN (*(__IO hw_sdhc_irqsigen_t *) HW_SDHC_IRQSIGEN_ADDR) |
mbed_official | 146:f64d43ff0c18 | 3762 | #define HW_SDHC_IRQSIGEN_RD() (HW_SDHC_IRQSIGEN.U) |
mbed_official | 146:f64d43ff0c18 | 3763 | #define HW_SDHC_IRQSIGEN_WR(v) (HW_SDHC_IRQSIGEN.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 3764 | #define HW_SDHC_IRQSIGEN_SET(v) (HW_SDHC_IRQSIGEN_WR(HW_SDHC_IRQSIGEN_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 3765 | #define HW_SDHC_IRQSIGEN_CLR(v) (HW_SDHC_IRQSIGEN_WR(HW_SDHC_IRQSIGEN_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 3766 | #define HW_SDHC_IRQSIGEN_TOG(v) (HW_SDHC_IRQSIGEN_WR(HW_SDHC_IRQSIGEN_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 3767 | #endif |
mbed_official | 146:f64d43ff0c18 | 3768 | //@} |
mbed_official | 146:f64d43ff0c18 | 3769 | |
mbed_official | 146:f64d43ff0c18 | 3770 | /* |
mbed_official | 146:f64d43ff0c18 | 3771 | * Constants & macros for individual SDHC_IRQSIGEN bitfields |
mbed_official | 146:f64d43ff0c18 | 3772 | */ |
mbed_official | 146:f64d43ff0c18 | 3773 | |
mbed_official | 146:f64d43ff0c18 | 3774 | /*! |
mbed_official | 146:f64d43ff0c18 | 3775 | * @name Register SDHC_IRQSIGEN, field CCIEN[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 3776 | * |
mbed_official | 146:f64d43ff0c18 | 3777 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3778 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3779 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3780 | */ |
mbed_official | 146:f64d43ff0c18 | 3781 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3782 | #define BP_SDHC_IRQSIGEN_CCIEN (0U) //!< Bit position for SDHC_IRQSIGEN_CCIEN. |
mbed_official | 146:f64d43ff0c18 | 3783 | #define BM_SDHC_IRQSIGEN_CCIEN (0x00000001U) //!< Bit mask for SDHC_IRQSIGEN_CCIEN. |
mbed_official | 146:f64d43ff0c18 | 3784 | #define BS_SDHC_IRQSIGEN_CCIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CCIEN. |
mbed_official | 146:f64d43ff0c18 | 3785 | |
mbed_official | 146:f64d43ff0c18 | 3786 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3787 | //! @brief Read current value of the SDHC_IRQSIGEN_CCIEN field. |
mbed_official | 146:f64d43ff0c18 | 3788 | #define BR_SDHC_IRQSIGEN_CCIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CCIEN)) |
mbed_official | 146:f64d43ff0c18 | 3789 | #endif |
mbed_official | 146:f64d43ff0c18 | 3790 | |
mbed_official | 146:f64d43ff0c18 | 3791 | //! @brief Format value for bitfield SDHC_IRQSIGEN_CCIEN. |
mbed_official | 146:f64d43ff0c18 | 3792 | #define BF_SDHC_IRQSIGEN_CCIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CCIEN), uint32_t) & BM_SDHC_IRQSIGEN_CCIEN) |
mbed_official | 146:f64d43ff0c18 | 3793 | |
mbed_official | 146:f64d43ff0c18 | 3794 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3795 | //! @brief Set the CCIEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3796 | #define BW_SDHC_IRQSIGEN_CCIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CCIEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3797 | #endif |
mbed_official | 146:f64d43ff0c18 | 3798 | //@} |
mbed_official | 146:f64d43ff0c18 | 3799 | |
mbed_official | 146:f64d43ff0c18 | 3800 | /*! |
mbed_official | 146:f64d43ff0c18 | 3801 | * @name Register SDHC_IRQSIGEN, field TCIEN[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 3802 | * |
mbed_official | 146:f64d43ff0c18 | 3803 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3804 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3805 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3806 | */ |
mbed_official | 146:f64d43ff0c18 | 3807 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3808 | #define BP_SDHC_IRQSIGEN_TCIEN (1U) //!< Bit position for SDHC_IRQSIGEN_TCIEN. |
mbed_official | 146:f64d43ff0c18 | 3809 | #define BM_SDHC_IRQSIGEN_TCIEN (0x00000002U) //!< Bit mask for SDHC_IRQSIGEN_TCIEN. |
mbed_official | 146:f64d43ff0c18 | 3810 | #define BS_SDHC_IRQSIGEN_TCIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_TCIEN. |
mbed_official | 146:f64d43ff0c18 | 3811 | |
mbed_official | 146:f64d43ff0c18 | 3812 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3813 | //! @brief Read current value of the SDHC_IRQSIGEN_TCIEN field. |
mbed_official | 146:f64d43ff0c18 | 3814 | #define BR_SDHC_IRQSIGEN_TCIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_TCIEN)) |
mbed_official | 146:f64d43ff0c18 | 3815 | #endif |
mbed_official | 146:f64d43ff0c18 | 3816 | |
mbed_official | 146:f64d43ff0c18 | 3817 | //! @brief Format value for bitfield SDHC_IRQSIGEN_TCIEN. |
mbed_official | 146:f64d43ff0c18 | 3818 | #define BF_SDHC_IRQSIGEN_TCIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_TCIEN), uint32_t) & BM_SDHC_IRQSIGEN_TCIEN) |
mbed_official | 146:f64d43ff0c18 | 3819 | |
mbed_official | 146:f64d43ff0c18 | 3820 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3821 | //! @brief Set the TCIEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3822 | #define BW_SDHC_IRQSIGEN_TCIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_TCIEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3823 | #endif |
mbed_official | 146:f64d43ff0c18 | 3824 | //@} |
mbed_official | 146:f64d43ff0c18 | 3825 | |
mbed_official | 146:f64d43ff0c18 | 3826 | /*! |
mbed_official | 146:f64d43ff0c18 | 3827 | * @name Register SDHC_IRQSIGEN, field BGEIEN[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 3828 | * |
mbed_official | 146:f64d43ff0c18 | 3829 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3830 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3831 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3832 | */ |
mbed_official | 146:f64d43ff0c18 | 3833 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3834 | #define BP_SDHC_IRQSIGEN_BGEIEN (2U) //!< Bit position for SDHC_IRQSIGEN_BGEIEN. |
mbed_official | 146:f64d43ff0c18 | 3835 | #define BM_SDHC_IRQSIGEN_BGEIEN (0x00000004U) //!< Bit mask for SDHC_IRQSIGEN_BGEIEN. |
mbed_official | 146:f64d43ff0c18 | 3836 | #define BS_SDHC_IRQSIGEN_BGEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_BGEIEN. |
mbed_official | 146:f64d43ff0c18 | 3837 | |
mbed_official | 146:f64d43ff0c18 | 3838 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3839 | //! @brief Read current value of the SDHC_IRQSIGEN_BGEIEN field. |
mbed_official | 146:f64d43ff0c18 | 3840 | #define BR_SDHC_IRQSIGEN_BGEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BGEIEN)) |
mbed_official | 146:f64d43ff0c18 | 3841 | #endif |
mbed_official | 146:f64d43ff0c18 | 3842 | |
mbed_official | 146:f64d43ff0c18 | 3843 | //! @brief Format value for bitfield SDHC_IRQSIGEN_BGEIEN. |
mbed_official | 146:f64d43ff0c18 | 3844 | #define BF_SDHC_IRQSIGEN_BGEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_BGEIEN), uint32_t) & BM_SDHC_IRQSIGEN_BGEIEN) |
mbed_official | 146:f64d43ff0c18 | 3845 | |
mbed_official | 146:f64d43ff0c18 | 3846 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3847 | //! @brief Set the BGEIEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3848 | #define BW_SDHC_IRQSIGEN_BGEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BGEIEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3849 | #endif |
mbed_official | 146:f64d43ff0c18 | 3850 | //@} |
mbed_official | 146:f64d43ff0c18 | 3851 | |
mbed_official | 146:f64d43ff0c18 | 3852 | /*! |
mbed_official | 146:f64d43ff0c18 | 3853 | * @name Register SDHC_IRQSIGEN, field DINTIEN[3] (RW) |
mbed_official | 146:f64d43ff0c18 | 3854 | * |
mbed_official | 146:f64d43ff0c18 | 3855 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3856 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3857 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3858 | */ |
mbed_official | 146:f64d43ff0c18 | 3859 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3860 | #define BP_SDHC_IRQSIGEN_DINTIEN (3U) //!< Bit position for SDHC_IRQSIGEN_DINTIEN. |
mbed_official | 146:f64d43ff0c18 | 3861 | #define BM_SDHC_IRQSIGEN_DINTIEN (0x00000008U) //!< Bit mask for SDHC_IRQSIGEN_DINTIEN. |
mbed_official | 146:f64d43ff0c18 | 3862 | #define BS_SDHC_IRQSIGEN_DINTIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_DINTIEN. |
mbed_official | 146:f64d43ff0c18 | 3863 | |
mbed_official | 146:f64d43ff0c18 | 3864 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3865 | //! @brief Read current value of the SDHC_IRQSIGEN_DINTIEN field. |
mbed_official | 146:f64d43ff0c18 | 3866 | #define BR_SDHC_IRQSIGEN_DINTIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DINTIEN)) |
mbed_official | 146:f64d43ff0c18 | 3867 | #endif |
mbed_official | 146:f64d43ff0c18 | 3868 | |
mbed_official | 146:f64d43ff0c18 | 3869 | //! @brief Format value for bitfield SDHC_IRQSIGEN_DINTIEN. |
mbed_official | 146:f64d43ff0c18 | 3870 | #define BF_SDHC_IRQSIGEN_DINTIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DINTIEN), uint32_t) & BM_SDHC_IRQSIGEN_DINTIEN) |
mbed_official | 146:f64d43ff0c18 | 3871 | |
mbed_official | 146:f64d43ff0c18 | 3872 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3873 | //! @brief Set the DINTIEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3874 | #define BW_SDHC_IRQSIGEN_DINTIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DINTIEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3875 | #endif |
mbed_official | 146:f64d43ff0c18 | 3876 | //@} |
mbed_official | 146:f64d43ff0c18 | 3877 | |
mbed_official | 146:f64d43ff0c18 | 3878 | /*! |
mbed_official | 146:f64d43ff0c18 | 3879 | * @name Register SDHC_IRQSIGEN, field BWRIEN[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 3880 | * |
mbed_official | 146:f64d43ff0c18 | 3881 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3882 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3883 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3884 | */ |
mbed_official | 146:f64d43ff0c18 | 3885 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3886 | #define BP_SDHC_IRQSIGEN_BWRIEN (4U) //!< Bit position for SDHC_IRQSIGEN_BWRIEN. |
mbed_official | 146:f64d43ff0c18 | 3887 | #define BM_SDHC_IRQSIGEN_BWRIEN (0x00000010U) //!< Bit mask for SDHC_IRQSIGEN_BWRIEN. |
mbed_official | 146:f64d43ff0c18 | 3888 | #define BS_SDHC_IRQSIGEN_BWRIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_BWRIEN. |
mbed_official | 146:f64d43ff0c18 | 3889 | |
mbed_official | 146:f64d43ff0c18 | 3890 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3891 | //! @brief Read current value of the SDHC_IRQSIGEN_BWRIEN field. |
mbed_official | 146:f64d43ff0c18 | 3892 | #define BR_SDHC_IRQSIGEN_BWRIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BWRIEN)) |
mbed_official | 146:f64d43ff0c18 | 3893 | #endif |
mbed_official | 146:f64d43ff0c18 | 3894 | |
mbed_official | 146:f64d43ff0c18 | 3895 | //! @brief Format value for bitfield SDHC_IRQSIGEN_BWRIEN. |
mbed_official | 146:f64d43ff0c18 | 3896 | #define BF_SDHC_IRQSIGEN_BWRIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_BWRIEN), uint32_t) & BM_SDHC_IRQSIGEN_BWRIEN) |
mbed_official | 146:f64d43ff0c18 | 3897 | |
mbed_official | 146:f64d43ff0c18 | 3898 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3899 | //! @brief Set the BWRIEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3900 | #define BW_SDHC_IRQSIGEN_BWRIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BWRIEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3901 | #endif |
mbed_official | 146:f64d43ff0c18 | 3902 | //@} |
mbed_official | 146:f64d43ff0c18 | 3903 | |
mbed_official | 146:f64d43ff0c18 | 3904 | /*! |
mbed_official | 146:f64d43ff0c18 | 3905 | * @name Register SDHC_IRQSIGEN, field BRRIEN[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 3906 | * |
mbed_official | 146:f64d43ff0c18 | 3907 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3908 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3909 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3910 | */ |
mbed_official | 146:f64d43ff0c18 | 3911 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3912 | #define BP_SDHC_IRQSIGEN_BRRIEN (5U) //!< Bit position for SDHC_IRQSIGEN_BRRIEN. |
mbed_official | 146:f64d43ff0c18 | 3913 | #define BM_SDHC_IRQSIGEN_BRRIEN (0x00000020U) //!< Bit mask for SDHC_IRQSIGEN_BRRIEN. |
mbed_official | 146:f64d43ff0c18 | 3914 | #define BS_SDHC_IRQSIGEN_BRRIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_BRRIEN. |
mbed_official | 146:f64d43ff0c18 | 3915 | |
mbed_official | 146:f64d43ff0c18 | 3916 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3917 | //! @brief Read current value of the SDHC_IRQSIGEN_BRRIEN field. |
mbed_official | 146:f64d43ff0c18 | 3918 | #define BR_SDHC_IRQSIGEN_BRRIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BRRIEN)) |
mbed_official | 146:f64d43ff0c18 | 3919 | #endif |
mbed_official | 146:f64d43ff0c18 | 3920 | |
mbed_official | 146:f64d43ff0c18 | 3921 | //! @brief Format value for bitfield SDHC_IRQSIGEN_BRRIEN. |
mbed_official | 146:f64d43ff0c18 | 3922 | #define BF_SDHC_IRQSIGEN_BRRIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_BRRIEN), uint32_t) & BM_SDHC_IRQSIGEN_BRRIEN) |
mbed_official | 146:f64d43ff0c18 | 3923 | |
mbed_official | 146:f64d43ff0c18 | 3924 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3925 | //! @brief Set the BRRIEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3926 | #define BW_SDHC_IRQSIGEN_BRRIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BRRIEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3927 | #endif |
mbed_official | 146:f64d43ff0c18 | 3928 | //@} |
mbed_official | 146:f64d43ff0c18 | 3929 | |
mbed_official | 146:f64d43ff0c18 | 3930 | /*! |
mbed_official | 146:f64d43ff0c18 | 3931 | * @name Register SDHC_IRQSIGEN, field CINSIEN[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 3932 | * |
mbed_official | 146:f64d43ff0c18 | 3933 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3934 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3935 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3936 | */ |
mbed_official | 146:f64d43ff0c18 | 3937 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3938 | #define BP_SDHC_IRQSIGEN_CINSIEN (6U) //!< Bit position for SDHC_IRQSIGEN_CINSIEN. |
mbed_official | 146:f64d43ff0c18 | 3939 | #define BM_SDHC_IRQSIGEN_CINSIEN (0x00000040U) //!< Bit mask for SDHC_IRQSIGEN_CINSIEN. |
mbed_official | 146:f64d43ff0c18 | 3940 | #define BS_SDHC_IRQSIGEN_CINSIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CINSIEN. |
mbed_official | 146:f64d43ff0c18 | 3941 | |
mbed_official | 146:f64d43ff0c18 | 3942 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3943 | //! @brief Read current value of the SDHC_IRQSIGEN_CINSIEN field. |
mbed_official | 146:f64d43ff0c18 | 3944 | #define BR_SDHC_IRQSIGEN_CINSIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CINSIEN)) |
mbed_official | 146:f64d43ff0c18 | 3945 | #endif |
mbed_official | 146:f64d43ff0c18 | 3946 | |
mbed_official | 146:f64d43ff0c18 | 3947 | //! @brief Format value for bitfield SDHC_IRQSIGEN_CINSIEN. |
mbed_official | 146:f64d43ff0c18 | 3948 | #define BF_SDHC_IRQSIGEN_CINSIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CINSIEN), uint32_t) & BM_SDHC_IRQSIGEN_CINSIEN) |
mbed_official | 146:f64d43ff0c18 | 3949 | |
mbed_official | 146:f64d43ff0c18 | 3950 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3951 | //! @brief Set the CINSIEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3952 | #define BW_SDHC_IRQSIGEN_CINSIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CINSIEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3953 | #endif |
mbed_official | 146:f64d43ff0c18 | 3954 | //@} |
mbed_official | 146:f64d43ff0c18 | 3955 | |
mbed_official | 146:f64d43ff0c18 | 3956 | /*! |
mbed_official | 146:f64d43ff0c18 | 3957 | * @name Register SDHC_IRQSIGEN, field CRMIEN[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 3958 | * |
mbed_official | 146:f64d43ff0c18 | 3959 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3960 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3961 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3962 | */ |
mbed_official | 146:f64d43ff0c18 | 3963 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3964 | #define BP_SDHC_IRQSIGEN_CRMIEN (7U) //!< Bit position for SDHC_IRQSIGEN_CRMIEN. |
mbed_official | 146:f64d43ff0c18 | 3965 | #define BM_SDHC_IRQSIGEN_CRMIEN (0x00000080U) //!< Bit mask for SDHC_IRQSIGEN_CRMIEN. |
mbed_official | 146:f64d43ff0c18 | 3966 | #define BS_SDHC_IRQSIGEN_CRMIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CRMIEN. |
mbed_official | 146:f64d43ff0c18 | 3967 | |
mbed_official | 146:f64d43ff0c18 | 3968 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3969 | //! @brief Read current value of the SDHC_IRQSIGEN_CRMIEN field. |
mbed_official | 146:f64d43ff0c18 | 3970 | #define BR_SDHC_IRQSIGEN_CRMIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CRMIEN)) |
mbed_official | 146:f64d43ff0c18 | 3971 | #endif |
mbed_official | 146:f64d43ff0c18 | 3972 | |
mbed_official | 146:f64d43ff0c18 | 3973 | //! @brief Format value for bitfield SDHC_IRQSIGEN_CRMIEN. |
mbed_official | 146:f64d43ff0c18 | 3974 | #define BF_SDHC_IRQSIGEN_CRMIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CRMIEN), uint32_t) & BM_SDHC_IRQSIGEN_CRMIEN) |
mbed_official | 146:f64d43ff0c18 | 3975 | |
mbed_official | 146:f64d43ff0c18 | 3976 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3977 | //! @brief Set the CRMIEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3978 | #define BW_SDHC_IRQSIGEN_CRMIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CRMIEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3979 | #endif |
mbed_official | 146:f64d43ff0c18 | 3980 | //@} |
mbed_official | 146:f64d43ff0c18 | 3981 | |
mbed_official | 146:f64d43ff0c18 | 3982 | /*! |
mbed_official | 146:f64d43ff0c18 | 3983 | * @name Register SDHC_IRQSIGEN, field CINTIEN[8] (RW) |
mbed_official | 146:f64d43ff0c18 | 3984 | * |
mbed_official | 146:f64d43ff0c18 | 3985 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3986 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 3987 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 3988 | */ |
mbed_official | 146:f64d43ff0c18 | 3989 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3990 | #define BP_SDHC_IRQSIGEN_CINTIEN (8U) //!< Bit position for SDHC_IRQSIGEN_CINTIEN. |
mbed_official | 146:f64d43ff0c18 | 3991 | #define BM_SDHC_IRQSIGEN_CINTIEN (0x00000100U) //!< Bit mask for SDHC_IRQSIGEN_CINTIEN. |
mbed_official | 146:f64d43ff0c18 | 3992 | #define BS_SDHC_IRQSIGEN_CINTIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CINTIEN. |
mbed_official | 146:f64d43ff0c18 | 3993 | |
mbed_official | 146:f64d43ff0c18 | 3994 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3995 | //! @brief Read current value of the SDHC_IRQSIGEN_CINTIEN field. |
mbed_official | 146:f64d43ff0c18 | 3996 | #define BR_SDHC_IRQSIGEN_CINTIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CINTIEN)) |
mbed_official | 146:f64d43ff0c18 | 3997 | #endif |
mbed_official | 146:f64d43ff0c18 | 3998 | |
mbed_official | 146:f64d43ff0c18 | 3999 | //! @brief Format value for bitfield SDHC_IRQSIGEN_CINTIEN. |
mbed_official | 146:f64d43ff0c18 | 4000 | #define BF_SDHC_IRQSIGEN_CINTIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CINTIEN), uint32_t) & BM_SDHC_IRQSIGEN_CINTIEN) |
mbed_official | 146:f64d43ff0c18 | 4001 | |
mbed_official | 146:f64d43ff0c18 | 4002 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4003 | //! @brief Set the CINTIEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4004 | #define BW_SDHC_IRQSIGEN_CINTIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CINTIEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4005 | #endif |
mbed_official | 146:f64d43ff0c18 | 4006 | //@} |
mbed_official | 146:f64d43ff0c18 | 4007 | |
mbed_official | 146:f64d43ff0c18 | 4008 | /*! |
mbed_official | 146:f64d43ff0c18 | 4009 | * @name Register SDHC_IRQSIGEN, field CTOEIEN[16] (RW) |
mbed_official | 146:f64d43ff0c18 | 4010 | * |
mbed_official | 146:f64d43ff0c18 | 4011 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4012 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 4013 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 4014 | */ |
mbed_official | 146:f64d43ff0c18 | 4015 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4016 | #define BP_SDHC_IRQSIGEN_CTOEIEN (16U) //!< Bit position for SDHC_IRQSIGEN_CTOEIEN. |
mbed_official | 146:f64d43ff0c18 | 4017 | #define BM_SDHC_IRQSIGEN_CTOEIEN (0x00010000U) //!< Bit mask for SDHC_IRQSIGEN_CTOEIEN. |
mbed_official | 146:f64d43ff0c18 | 4018 | #define BS_SDHC_IRQSIGEN_CTOEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CTOEIEN. |
mbed_official | 146:f64d43ff0c18 | 4019 | |
mbed_official | 146:f64d43ff0c18 | 4020 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4021 | //! @brief Read current value of the SDHC_IRQSIGEN_CTOEIEN field. |
mbed_official | 146:f64d43ff0c18 | 4022 | #define BR_SDHC_IRQSIGEN_CTOEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CTOEIEN)) |
mbed_official | 146:f64d43ff0c18 | 4023 | #endif |
mbed_official | 146:f64d43ff0c18 | 4024 | |
mbed_official | 146:f64d43ff0c18 | 4025 | //! @brief Format value for bitfield SDHC_IRQSIGEN_CTOEIEN. |
mbed_official | 146:f64d43ff0c18 | 4026 | #define BF_SDHC_IRQSIGEN_CTOEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CTOEIEN), uint32_t) & BM_SDHC_IRQSIGEN_CTOEIEN) |
mbed_official | 146:f64d43ff0c18 | 4027 | |
mbed_official | 146:f64d43ff0c18 | 4028 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4029 | //! @brief Set the CTOEIEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4030 | #define BW_SDHC_IRQSIGEN_CTOEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CTOEIEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4031 | #endif |
mbed_official | 146:f64d43ff0c18 | 4032 | //@} |
mbed_official | 146:f64d43ff0c18 | 4033 | |
mbed_official | 146:f64d43ff0c18 | 4034 | /*! |
mbed_official | 146:f64d43ff0c18 | 4035 | * @name Register SDHC_IRQSIGEN, field CCEIEN[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 4036 | * |
mbed_official | 146:f64d43ff0c18 | 4037 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4038 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 4039 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 4040 | */ |
mbed_official | 146:f64d43ff0c18 | 4041 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4042 | #define BP_SDHC_IRQSIGEN_CCEIEN (17U) //!< Bit position for SDHC_IRQSIGEN_CCEIEN. |
mbed_official | 146:f64d43ff0c18 | 4043 | #define BM_SDHC_IRQSIGEN_CCEIEN (0x00020000U) //!< Bit mask for SDHC_IRQSIGEN_CCEIEN. |
mbed_official | 146:f64d43ff0c18 | 4044 | #define BS_SDHC_IRQSIGEN_CCEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CCEIEN. |
mbed_official | 146:f64d43ff0c18 | 4045 | |
mbed_official | 146:f64d43ff0c18 | 4046 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4047 | //! @brief Read current value of the SDHC_IRQSIGEN_CCEIEN field. |
mbed_official | 146:f64d43ff0c18 | 4048 | #define BR_SDHC_IRQSIGEN_CCEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CCEIEN)) |
mbed_official | 146:f64d43ff0c18 | 4049 | #endif |
mbed_official | 146:f64d43ff0c18 | 4050 | |
mbed_official | 146:f64d43ff0c18 | 4051 | //! @brief Format value for bitfield SDHC_IRQSIGEN_CCEIEN. |
mbed_official | 146:f64d43ff0c18 | 4052 | #define BF_SDHC_IRQSIGEN_CCEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CCEIEN), uint32_t) & BM_SDHC_IRQSIGEN_CCEIEN) |
mbed_official | 146:f64d43ff0c18 | 4053 | |
mbed_official | 146:f64d43ff0c18 | 4054 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4055 | //! @brief Set the CCEIEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4056 | #define BW_SDHC_IRQSIGEN_CCEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CCEIEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4057 | #endif |
mbed_official | 146:f64d43ff0c18 | 4058 | //@} |
mbed_official | 146:f64d43ff0c18 | 4059 | |
mbed_official | 146:f64d43ff0c18 | 4060 | /*! |
mbed_official | 146:f64d43ff0c18 | 4061 | * @name Register SDHC_IRQSIGEN, field CEBEIEN[18] (RW) |
mbed_official | 146:f64d43ff0c18 | 4062 | * |
mbed_official | 146:f64d43ff0c18 | 4063 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4064 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 4065 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 4066 | */ |
mbed_official | 146:f64d43ff0c18 | 4067 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4068 | #define BP_SDHC_IRQSIGEN_CEBEIEN (18U) //!< Bit position for SDHC_IRQSIGEN_CEBEIEN. |
mbed_official | 146:f64d43ff0c18 | 4069 | #define BM_SDHC_IRQSIGEN_CEBEIEN (0x00040000U) //!< Bit mask for SDHC_IRQSIGEN_CEBEIEN. |
mbed_official | 146:f64d43ff0c18 | 4070 | #define BS_SDHC_IRQSIGEN_CEBEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CEBEIEN. |
mbed_official | 146:f64d43ff0c18 | 4071 | |
mbed_official | 146:f64d43ff0c18 | 4072 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4073 | //! @brief Read current value of the SDHC_IRQSIGEN_CEBEIEN field. |
mbed_official | 146:f64d43ff0c18 | 4074 | #define BR_SDHC_IRQSIGEN_CEBEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CEBEIEN)) |
mbed_official | 146:f64d43ff0c18 | 4075 | #endif |
mbed_official | 146:f64d43ff0c18 | 4076 | |
mbed_official | 146:f64d43ff0c18 | 4077 | //! @brief Format value for bitfield SDHC_IRQSIGEN_CEBEIEN. |
mbed_official | 146:f64d43ff0c18 | 4078 | #define BF_SDHC_IRQSIGEN_CEBEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CEBEIEN), uint32_t) & BM_SDHC_IRQSIGEN_CEBEIEN) |
mbed_official | 146:f64d43ff0c18 | 4079 | |
mbed_official | 146:f64d43ff0c18 | 4080 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4081 | //! @brief Set the CEBEIEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4082 | #define BW_SDHC_IRQSIGEN_CEBEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CEBEIEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4083 | #endif |
mbed_official | 146:f64d43ff0c18 | 4084 | //@} |
mbed_official | 146:f64d43ff0c18 | 4085 | |
mbed_official | 146:f64d43ff0c18 | 4086 | /*! |
mbed_official | 146:f64d43ff0c18 | 4087 | * @name Register SDHC_IRQSIGEN, field CIEIEN[19] (RW) |
mbed_official | 146:f64d43ff0c18 | 4088 | * |
mbed_official | 146:f64d43ff0c18 | 4089 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4090 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 4091 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 4092 | */ |
mbed_official | 146:f64d43ff0c18 | 4093 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4094 | #define BP_SDHC_IRQSIGEN_CIEIEN (19U) //!< Bit position for SDHC_IRQSIGEN_CIEIEN. |
mbed_official | 146:f64d43ff0c18 | 4095 | #define BM_SDHC_IRQSIGEN_CIEIEN (0x00080000U) //!< Bit mask for SDHC_IRQSIGEN_CIEIEN. |
mbed_official | 146:f64d43ff0c18 | 4096 | #define BS_SDHC_IRQSIGEN_CIEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CIEIEN. |
mbed_official | 146:f64d43ff0c18 | 4097 | |
mbed_official | 146:f64d43ff0c18 | 4098 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4099 | //! @brief Read current value of the SDHC_IRQSIGEN_CIEIEN field. |
mbed_official | 146:f64d43ff0c18 | 4100 | #define BR_SDHC_IRQSIGEN_CIEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CIEIEN)) |
mbed_official | 146:f64d43ff0c18 | 4101 | #endif |
mbed_official | 146:f64d43ff0c18 | 4102 | |
mbed_official | 146:f64d43ff0c18 | 4103 | //! @brief Format value for bitfield SDHC_IRQSIGEN_CIEIEN. |
mbed_official | 146:f64d43ff0c18 | 4104 | #define BF_SDHC_IRQSIGEN_CIEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CIEIEN), uint32_t) & BM_SDHC_IRQSIGEN_CIEIEN) |
mbed_official | 146:f64d43ff0c18 | 4105 | |
mbed_official | 146:f64d43ff0c18 | 4106 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4107 | //! @brief Set the CIEIEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4108 | #define BW_SDHC_IRQSIGEN_CIEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CIEIEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4109 | #endif |
mbed_official | 146:f64d43ff0c18 | 4110 | //@} |
mbed_official | 146:f64d43ff0c18 | 4111 | |
mbed_official | 146:f64d43ff0c18 | 4112 | /*! |
mbed_official | 146:f64d43ff0c18 | 4113 | * @name Register SDHC_IRQSIGEN, field DTOEIEN[20] (RW) |
mbed_official | 146:f64d43ff0c18 | 4114 | * |
mbed_official | 146:f64d43ff0c18 | 4115 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4116 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 4117 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 4118 | */ |
mbed_official | 146:f64d43ff0c18 | 4119 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4120 | #define BP_SDHC_IRQSIGEN_DTOEIEN (20U) //!< Bit position for SDHC_IRQSIGEN_DTOEIEN. |
mbed_official | 146:f64d43ff0c18 | 4121 | #define BM_SDHC_IRQSIGEN_DTOEIEN (0x00100000U) //!< Bit mask for SDHC_IRQSIGEN_DTOEIEN. |
mbed_official | 146:f64d43ff0c18 | 4122 | #define BS_SDHC_IRQSIGEN_DTOEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_DTOEIEN. |
mbed_official | 146:f64d43ff0c18 | 4123 | |
mbed_official | 146:f64d43ff0c18 | 4124 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4125 | //! @brief Read current value of the SDHC_IRQSIGEN_DTOEIEN field. |
mbed_official | 146:f64d43ff0c18 | 4126 | #define BR_SDHC_IRQSIGEN_DTOEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DTOEIEN)) |
mbed_official | 146:f64d43ff0c18 | 4127 | #endif |
mbed_official | 146:f64d43ff0c18 | 4128 | |
mbed_official | 146:f64d43ff0c18 | 4129 | //! @brief Format value for bitfield SDHC_IRQSIGEN_DTOEIEN. |
mbed_official | 146:f64d43ff0c18 | 4130 | #define BF_SDHC_IRQSIGEN_DTOEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DTOEIEN), uint32_t) & BM_SDHC_IRQSIGEN_DTOEIEN) |
mbed_official | 146:f64d43ff0c18 | 4131 | |
mbed_official | 146:f64d43ff0c18 | 4132 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4133 | //! @brief Set the DTOEIEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4134 | #define BW_SDHC_IRQSIGEN_DTOEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DTOEIEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4135 | #endif |
mbed_official | 146:f64d43ff0c18 | 4136 | //@} |
mbed_official | 146:f64d43ff0c18 | 4137 | |
mbed_official | 146:f64d43ff0c18 | 4138 | /*! |
mbed_official | 146:f64d43ff0c18 | 4139 | * @name Register SDHC_IRQSIGEN, field DCEIEN[21] (RW) |
mbed_official | 146:f64d43ff0c18 | 4140 | * |
mbed_official | 146:f64d43ff0c18 | 4141 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4142 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 4143 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 4144 | */ |
mbed_official | 146:f64d43ff0c18 | 4145 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4146 | #define BP_SDHC_IRQSIGEN_DCEIEN (21U) //!< Bit position for SDHC_IRQSIGEN_DCEIEN. |
mbed_official | 146:f64d43ff0c18 | 4147 | #define BM_SDHC_IRQSIGEN_DCEIEN (0x00200000U) //!< Bit mask for SDHC_IRQSIGEN_DCEIEN. |
mbed_official | 146:f64d43ff0c18 | 4148 | #define BS_SDHC_IRQSIGEN_DCEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_DCEIEN. |
mbed_official | 146:f64d43ff0c18 | 4149 | |
mbed_official | 146:f64d43ff0c18 | 4150 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4151 | //! @brief Read current value of the SDHC_IRQSIGEN_DCEIEN field. |
mbed_official | 146:f64d43ff0c18 | 4152 | #define BR_SDHC_IRQSIGEN_DCEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DCEIEN)) |
mbed_official | 146:f64d43ff0c18 | 4153 | #endif |
mbed_official | 146:f64d43ff0c18 | 4154 | |
mbed_official | 146:f64d43ff0c18 | 4155 | //! @brief Format value for bitfield SDHC_IRQSIGEN_DCEIEN. |
mbed_official | 146:f64d43ff0c18 | 4156 | #define BF_SDHC_IRQSIGEN_DCEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DCEIEN), uint32_t) & BM_SDHC_IRQSIGEN_DCEIEN) |
mbed_official | 146:f64d43ff0c18 | 4157 | |
mbed_official | 146:f64d43ff0c18 | 4158 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4159 | //! @brief Set the DCEIEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4160 | #define BW_SDHC_IRQSIGEN_DCEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DCEIEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4161 | #endif |
mbed_official | 146:f64d43ff0c18 | 4162 | //@} |
mbed_official | 146:f64d43ff0c18 | 4163 | |
mbed_official | 146:f64d43ff0c18 | 4164 | /*! |
mbed_official | 146:f64d43ff0c18 | 4165 | * @name Register SDHC_IRQSIGEN, field DEBEIEN[22] (RW) |
mbed_official | 146:f64d43ff0c18 | 4166 | * |
mbed_official | 146:f64d43ff0c18 | 4167 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4168 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 4169 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 4170 | */ |
mbed_official | 146:f64d43ff0c18 | 4171 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4172 | #define BP_SDHC_IRQSIGEN_DEBEIEN (22U) //!< Bit position for SDHC_IRQSIGEN_DEBEIEN. |
mbed_official | 146:f64d43ff0c18 | 4173 | #define BM_SDHC_IRQSIGEN_DEBEIEN (0x00400000U) //!< Bit mask for SDHC_IRQSIGEN_DEBEIEN. |
mbed_official | 146:f64d43ff0c18 | 4174 | #define BS_SDHC_IRQSIGEN_DEBEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_DEBEIEN. |
mbed_official | 146:f64d43ff0c18 | 4175 | |
mbed_official | 146:f64d43ff0c18 | 4176 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4177 | //! @brief Read current value of the SDHC_IRQSIGEN_DEBEIEN field. |
mbed_official | 146:f64d43ff0c18 | 4178 | #define BR_SDHC_IRQSIGEN_DEBEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DEBEIEN)) |
mbed_official | 146:f64d43ff0c18 | 4179 | #endif |
mbed_official | 146:f64d43ff0c18 | 4180 | |
mbed_official | 146:f64d43ff0c18 | 4181 | //! @brief Format value for bitfield SDHC_IRQSIGEN_DEBEIEN. |
mbed_official | 146:f64d43ff0c18 | 4182 | #define BF_SDHC_IRQSIGEN_DEBEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DEBEIEN), uint32_t) & BM_SDHC_IRQSIGEN_DEBEIEN) |
mbed_official | 146:f64d43ff0c18 | 4183 | |
mbed_official | 146:f64d43ff0c18 | 4184 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4185 | //! @brief Set the DEBEIEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4186 | #define BW_SDHC_IRQSIGEN_DEBEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DEBEIEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4187 | #endif |
mbed_official | 146:f64d43ff0c18 | 4188 | //@} |
mbed_official | 146:f64d43ff0c18 | 4189 | |
mbed_official | 146:f64d43ff0c18 | 4190 | /*! |
mbed_official | 146:f64d43ff0c18 | 4191 | * @name Register SDHC_IRQSIGEN, field AC12EIEN[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 4192 | * |
mbed_official | 146:f64d43ff0c18 | 4193 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4194 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 4195 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 4196 | */ |
mbed_official | 146:f64d43ff0c18 | 4197 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4198 | #define BP_SDHC_IRQSIGEN_AC12EIEN (24U) //!< Bit position for SDHC_IRQSIGEN_AC12EIEN. |
mbed_official | 146:f64d43ff0c18 | 4199 | #define BM_SDHC_IRQSIGEN_AC12EIEN (0x01000000U) //!< Bit mask for SDHC_IRQSIGEN_AC12EIEN. |
mbed_official | 146:f64d43ff0c18 | 4200 | #define BS_SDHC_IRQSIGEN_AC12EIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_AC12EIEN. |
mbed_official | 146:f64d43ff0c18 | 4201 | |
mbed_official | 146:f64d43ff0c18 | 4202 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4203 | //! @brief Read current value of the SDHC_IRQSIGEN_AC12EIEN field. |
mbed_official | 146:f64d43ff0c18 | 4204 | #define BR_SDHC_IRQSIGEN_AC12EIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_AC12EIEN)) |
mbed_official | 146:f64d43ff0c18 | 4205 | #endif |
mbed_official | 146:f64d43ff0c18 | 4206 | |
mbed_official | 146:f64d43ff0c18 | 4207 | //! @brief Format value for bitfield SDHC_IRQSIGEN_AC12EIEN. |
mbed_official | 146:f64d43ff0c18 | 4208 | #define BF_SDHC_IRQSIGEN_AC12EIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_AC12EIEN), uint32_t) & BM_SDHC_IRQSIGEN_AC12EIEN) |
mbed_official | 146:f64d43ff0c18 | 4209 | |
mbed_official | 146:f64d43ff0c18 | 4210 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4211 | //! @brief Set the AC12EIEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4212 | #define BW_SDHC_IRQSIGEN_AC12EIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_AC12EIEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4213 | #endif |
mbed_official | 146:f64d43ff0c18 | 4214 | //@} |
mbed_official | 146:f64d43ff0c18 | 4215 | |
mbed_official | 146:f64d43ff0c18 | 4216 | /*! |
mbed_official | 146:f64d43ff0c18 | 4217 | * @name Register SDHC_IRQSIGEN, field DMAEIEN[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 4218 | * |
mbed_official | 146:f64d43ff0c18 | 4219 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4220 | * - 0 - Masked |
mbed_official | 146:f64d43ff0c18 | 4221 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 4222 | */ |
mbed_official | 146:f64d43ff0c18 | 4223 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4224 | #define BP_SDHC_IRQSIGEN_DMAEIEN (28U) //!< Bit position for SDHC_IRQSIGEN_DMAEIEN. |
mbed_official | 146:f64d43ff0c18 | 4225 | #define BM_SDHC_IRQSIGEN_DMAEIEN (0x10000000U) //!< Bit mask for SDHC_IRQSIGEN_DMAEIEN. |
mbed_official | 146:f64d43ff0c18 | 4226 | #define BS_SDHC_IRQSIGEN_DMAEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_DMAEIEN. |
mbed_official | 146:f64d43ff0c18 | 4227 | |
mbed_official | 146:f64d43ff0c18 | 4228 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4229 | //! @brief Read current value of the SDHC_IRQSIGEN_DMAEIEN field. |
mbed_official | 146:f64d43ff0c18 | 4230 | #define BR_SDHC_IRQSIGEN_DMAEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DMAEIEN)) |
mbed_official | 146:f64d43ff0c18 | 4231 | #endif |
mbed_official | 146:f64d43ff0c18 | 4232 | |
mbed_official | 146:f64d43ff0c18 | 4233 | //! @brief Format value for bitfield SDHC_IRQSIGEN_DMAEIEN. |
mbed_official | 146:f64d43ff0c18 | 4234 | #define BF_SDHC_IRQSIGEN_DMAEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DMAEIEN), uint32_t) & BM_SDHC_IRQSIGEN_DMAEIEN) |
mbed_official | 146:f64d43ff0c18 | 4235 | |
mbed_official | 146:f64d43ff0c18 | 4236 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4237 | //! @brief Set the DMAEIEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4238 | #define BW_SDHC_IRQSIGEN_DMAEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DMAEIEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4239 | #endif |
mbed_official | 146:f64d43ff0c18 | 4240 | //@} |
mbed_official | 146:f64d43ff0c18 | 4241 | |
mbed_official | 146:f64d43ff0c18 | 4242 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4243 | // HW_SDHC_AC12ERR - Auto CMD12 Error Status Register |
mbed_official | 146:f64d43ff0c18 | 4244 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4245 | |
mbed_official | 146:f64d43ff0c18 | 4246 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4247 | /*! |
mbed_official | 146:f64d43ff0c18 | 4248 | * @brief HW_SDHC_AC12ERR - Auto CMD12 Error Status Register (RO) |
mbed_official | 146:f64d43ff0c18 | 4249 | * |
mbed_official | 146:f64d43ff0c18 | 4250 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 4251 | * |
mbed_official | 146:f64d43ff0c18 | 4252 | * When the AC12ESEN bit in the Status register is set, the host driver shall |
mbed_official | 146:f64d43ff0c18 | 4253 | * check this register to identify what kind of error the Auto CMD12 indicated. |
mbed_official | 146:f64d43ff0c18 | 4254 | * This register is valid only when the Auto CMD12 Error status bit is set. The |
mbed_official | 146:f64d43ff0c18 | 4255 | * following table shows the relationship between the Auto CMGD12 CRC error and the |
mbed_official | 146:f64d43ff0c18 | 4256 | * Auto CMD12 command timeout error. Relationship between Command CRC Error and |
mbed_official | 146:f64d43ff0c18 | 4257 | * Command Timeout Error For Auto CMD12 Auto CMD12 CRC error Auto CMD12 timeout |
mbed_official | 146:f64d43ff0c18 | 4258 | * error Type of error 0 0 No error 0 1 Response timeout error 1 0 Response CRC |
mbed_official | 146:f64d43ff0c18 | 4259 | * error 1 1 CMD line conflict Changes in Auto CMD12 Error Status register can be |
mbed_official | 146:f64d43ff0c18 | 4260 | * classified in three scenarios: When the SDHC is going to issue an Auto CMD12: Set |
mbed_official | 146:f64d43ff0c18 | 4261 | * bit 0 to 1 if the Auto CMD12 can't be issued due to an error in the previous |
mbed_official | 146:f64d43ff0c18 | 4262 | * command. Set bit 0 to 0 if the auto CMD12 is issued. At the end bit of an auto |
mbed_official | 146:f64d43ff0c18 | 4263 | * CMD12 response: Check errors corresponding to bits 1-4. Set bits 1-4 |
mbed_official | 146:f64d43ff0c18 | 4264 | * corresponding to detected errors. Clear bits 1-4 corresponding to detected errors. |
mbed_official | 146:f64d43ff0c18 | 4265 | * Before reading the Auto CMD12 error status bit 7: Set bit 7 to 1 if there is a |
mbed_official | 146:f64d43ff0c18 | 4266 | * command that can't be issued. Clear bit 7 if there is no command to issue. The |
mbed_official | 146:f64d43ff0c18 | 4267 | * timing for generating the auto CMD12 error and writing to the command register |
mbed_official | 146:f64d43ff0c18 | 4268 | * are asynchronous. After that, bit 7 shall be sampled when the driver is not |
mbed_official | 146:f64d43ff0c18 | 4269 | * writing to the command register. So it is suggested to read this register only |
mbed_official | 146:f64d43ff0c18 | 4270 | * when IRQSTAT[AC12E] is set. An Auto CMD12 error interrupt is generated when one |
mbed_official | 146:f64d43ff0c18 | 4271 | * of the error bits (0-4) is set to 1. The command not issued by auto CMD12 |
mbed_official | 146:f64d43ff0c18 | 4272 | * error does not generate an interrupt. |
mbed_official | 146:f64d43ff0c18 | 4273 | */ |
mbed_official | 146:f64d43ff0c18 | 4274 | typedef union _hw_sdhc_ac12err |
mbed_official | 146:f64d43ff0c18 | 4275 | { |
mbed_official | 146:f64d43ff0c18 | 4276 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 4277 | struct _hw_sdhc_ac12err_bitfields |
mbed_official | 146:f64d43ff0c18 | 4278 | { |
mbed_official | 146:f64d43ff0c18 | 4279 | uint32_t AC12NE : 1; //!< [0] Auto CMD12 Not Executed |
mbed_official | 146:f64d43ff0c18 | 4280 | uint32_t AC12TOE : 1; //!< [1] Auto CMD12 Timeout Error |
mbed_official | 146:f64d43ff0c18 | 4281 | uint32_t AC12EBE : 1; //!< [2] Auto CMD12 End Bit Error |
mbed_official | 146:f64d43ff0c18 | 4282 | uint32_t AC12CE : 1; //!< [3] Auto CMD12 CRC Error |
mbed_official | 146:f64d43ff0c18 | 4283 | uint32_t AC12IE : 1; //!< [4] Auto CMD12 Index Error |
mbed_official | 146:f64d43ff0c18 | 4284 | uint32_t RESERVED0 : 2; //!< [6:5] |
mbed_official | 146:f64d43ff0c18 | 4285 | uint32_t CNIBAC12E : 1; //!< [7] Command Not Issued By Auto CMD12 |
mbed_official | 146:f64d43ff0c18 | 4286 | //! Error |
mbed_official | 146:f64d43ff0c18 | 4287 | uint32_t RESERVED1 : 24; //!< [31:8] |
mbed_official | 146:f64d43ff0c18 | 4288 | } B; |
mbed_official | 146:f64d43ff0c18 | 4289 | } hw_sdhc_ac12err_t; |
mbed_official | 146:f64d43ff0c18 | 4290 | #endif |
mbed_official | 146:f64d43ff0c18 | 4291 | |
mbed_official | 146:f64d43ff0c18 | 4292 | /*! |
mbed_official | 146:f64d43ff0c18 | 4293 | * @name Constants and macros for entire SDHC_AC12ERR register |
mbed_official | 146:f64d43ff0c18 | 4294 | */ |
mbed_official | 146:f64d43ff0c18 | 4295 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4296 | #define HW_SDHC_AC12ERR_ADDR (REGS_SDHC_BASE + 0x3CU) |
mbed_official | 146:f64d43ff0c18 | 4297 | |
mbed_official | 146:f64d43ff0c18 | 4298 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4299 | #define HW_SDHC_AC12ERR (*(__I hw_sdhc_ac12err_t *) HW_SDHC_AC12ERR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 4300 | #define HW_SDHC_AC12ERR_RD() (HW_SDHC_AC12ERR.U) |
mbed_official | 146:f64d43ff0c18 | 4301 | #endif |
mbed_official | 146:f64d43ff0c18 | 4302 | //@} |
mbed_official | 146:f64d43ff0c18 | 4303 | |
mbed_official | 146:f64d43ff0c18 | 4304 | /* |
mbed_official | 146:f64d43ff0c18 | 4305 | * Constants & macros for individual SDHC_AC12ERR bitfields |
mbed_official | 146:f64d43ff0c18 | 4306 | */ |
mbed_official | 146:f64d43ff0c18 | 4307 | |
mbed_official | 146:f64d43ff0c18 | 4308 | /*! |
mbed_official | 146:f64d43ff0c18 | 4309 | * @name Register SDHC_AC12ERR, field AC12NE[0] (RO) |
mbed_official | 146:f64d43ff0c18 | 4310 | * |
mbed_official | 146:f64d43ff0c18 | 4311 | * If memory multiple block data transfer is not started, due to a command |
mbed_official | 146:f64d43ff0c18 | 4312 | * error, this bit is not set because it is not necessary to issue an auto CMD12. |
mbed_official | 146:f64d43ff0c18 | 4313 | * Setting this bit to 1 means the SDHC cannot issue the auto CMD12 to stop a memory |
mbed_official | 146:f64d43ff0c18 | 4314 | * multiple block data transfer due to some error. If this bit is set to 1, other |
mbed_official | 146:f64d43ff0c18 | 4315 | * error status bits (1-4) have no meaning. |
mbed_official | 146:f64d43ff0c18 | 4316 | * |
mbed_official | 146:f64d43ff0c18 | 4317 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4318 | * - 0 - Executed. |
mbed_official | 146:f64d43ff0c18 | 4319 | * - 1 - Not executed. |
mbed_official | 146:f64d43ff0c18 | 4320 | */ |
mbed_official | 146:f64d43ff0c18 | 4321 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4322 | #define BP_SDHC_AC12ERR_AC12NE (0U) //!< Bit position for SDHC_AC12ERR_AC12NE. |
mbed_official | 146:f64d43ff0c18 | 4323 | #define BM_SDHC_AC12ERR_AC12NE (0x00000001U) //!< Bit mask for SDHC_AC12ERR_AC12NE. |
mbed_official | 146:f64d43ff0c18 | 4324 | #define BS_SDHC_AC12ERR_AC12NE (1U) //!< Bit field size in bits for SDHC_AC12ERR_AC12NE. |
mbed_official | 146:f64d43ff0c18 | 4325 | |
mbed_official | 146:f64d43ff0c18 | 4326 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4327 | //! @brief Read current value of the SDHC_AC12ERR_AC12NE field. |
mbed_official | 146:f64d43ff0c18 | 4328 | #define BR_SDHC_AC12ERR_AC12NE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12NE)) |
mbed_official | 146:f64d43ff0c18 | 4329 | #endif |
mbed_official | 146:f64d43ff0c18 | 4330 | //@} |
mbed_official | 146:f64d43ff0c18 | 4331 | |
mbed_official | 146:f64d43ff0c18 | 4332 | /*! |
mbed_official | 146:f64d43ff0c18 | 4333 | * @name Register SDHC_AC12ERR, field AC12TOE[1] (RO) |
mbed_official | 146:f64d43ff0c18 | 4334 | * |
mbed_official | 146:f64d43ff0c18 | 4335 | * Occurs if no response is returned within 64 SDCLK cycles from the end bit of |
mbed_official | 146:f64d43ff0c18 | 4336 | * the command. If this bit is set to 1, the other error status bits (2-4) have |
mbed_official | 146:f64d43ff0c18 | 4337 | * no meaning. |
mbed_official | 146:f64d43ff0c18 | 4338 | * |
mbed_official | 146:f64d43ff0c18 | 4339 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4340 | * - 0 - No error. |
mbed_official | 146:f64d43ff0c18 | 4341 | * - 1 - Time out. |
mbed_official | 146:f64d43ff0c18 | 4342 | */ |
mbed_official | 146:f64d43ff0c18 | 4343 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4344 | #define BP_SDHC_AC12ERR_AC12TOE (1U) //!< Bit position for SDHC_AC12ERR_AC12TOE. |
mbed_official | 146:f64d43ff0c18 | 4345 | #define BM_SDHC_AC12ERR_AC12TOE (0x00000002U) //!< Bit mask for SDHC_AC12ERR_AC12TOE. |
mbed_official | 146:f64d43ff0c18 | 4346 | #define BS_SDHC_AC12ERR_AC12TOE (1U) //!< Bit field size in bits for SDHC_AC12ERR_AC12TOE. |
mbed_official | 146:f64d43ff0c18 | 4347 | |
mbed_official | 146:f64d43ff0c18 | 4348 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4349 | //! @brief Read current value of the SDHC_AC12ERR_AC12TOE field. |
mbed_official | 146:f64d43ff0c18 | 4350 | #define BR_SDHC_AC12ERR_AC12TOE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12TOE)) |
mbed_official | 146:f64d43ff0c18 | 4351 | #endif |
mbed_official | 146:f64d43ff0c18 | 4352 | //@} |
mbed_official | 146:f64d43ff0c18 | 4353 | |
mbed_official | 146:f64d43ff0c18 | 4354 | /*! |
mbed_official | 146:f64d43ff0c18 | 4355 | * @name Register SDHC_AC12ERR, field AC12EBE[2] (RO) |
mbed_official | 146:f64d43ff0c18 | 4356 | * |
mbed_official | 146:f64d43ff0c18 | 4357 | * Occurs when detecting that the end bit of command response is 0 which must be |
mbed_official | 146:f64d43ff0c18 | 4358 | * 1. |
mbed_official | 146:f64d43ff0c18 | 4359 | * |
mbed_official | 146:f64d43ff0c18 | 4360 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4361 | * - 0 - No error. |
mbed_official | 146:f64d43ff0c18 | 4362 | * - 1 - End bit error generated. |
mbed_official | 146:f64d43ff0c18 | 4363 | */ |
mbed_official | 146:f64d43ff0c18 | 4364 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4365 | #define BP_SDHC_AC12ERR_AC12EBE (2U) //!< Bit position for SDHC_AC12ERR_AC12EBE. |
mbed_official | 146:f64d43ff0c18 | 4366 | #define BM_SDHC_AC12ERR_AC12EBE (0x00000004U) //!< Bit mask for SDHC_AC12ERR_AC12EBE. |
mbed_official | 146:f64d43ff0c18 | 4367 | #define BS_SDHC_AC12ERR_AC12EBE (1U) //!< Bit field size in bits for SDHC_AC12ERR_AC12EBE. |
mbed_official | 146:f64d43ff0c18 | 4368 | |
mbed_official | 146:f64d43ff0c18 | 4369 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4370 | //! @brief Read current value of the SDHC_AC12ERR_AC12EBE field. |
mbed_official | 146:f64d43ff0c18 | 4371 | #define BR_SDHC_AC12ERR_AC12EBE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12EBE)) |
mbed_official | 146:f64d43ff0c18 | 4372 | #endif |
mbed_official | 146:f64d43ff0c18 | 4373 | //@} |
mbed_official | 146:f64d43ff0c18 | 4374 | |
mbed_official | 146:f64d43ff0c18 | 4375 | /*! |
mbed_official | 146:f64d43ff0c18 | 4376 | * @name Register SDHC_AC12ERR, field AC12CE[3] (RO) |
mbed_official | 146:f64d43ff0c18 | 4377 | * |
mbed_official | 146:f64d43ff0c18 | 4378 | * Occurs when detecting a CRC error in the command response. |
mbed_official | 146:f64d43ff0c18 | 4379 | * |
mbed_official | 146:f64d43ff0c18 | 4380 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4381 | * - 0 - No CRC error. |
mbed_official | 146:f64d43ff0c18 | 4382 | * - 1 - CRC error met in Auto CMD12 response. |
mbed_official | 146:f64d43ff0c18 | 4383 | */ |
mbed_official | 146:f64d43ff0c18 | 4384 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4385 | #define BP_SDHC_AC12ERR_AC12CE (3U) //!< Bit position for SDHC_AC12ERR_AC12CE. |
mbed_official | 146:f64d43ff0c18 | 4386 | #define BM_SDHC_AC12ERR_AC12CE (0x00000008U) //!< Bit mask for SDHC_AC12ERR_AC12CE. |
mbed_official | 146:f64d43ff0c18 | 4387 | #define BS_SDHC_AC12ERR_AC12CE (1U) //!< Bit field size in bits for SDHC_AC12ERR_AC12CE. |
mbed_official | 146:f64d43ff0c18 | 4388 | |
mbed_official | 146:f64d43ff0c18 | 4389 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4390 | //! @brief Read current value of the SDHC_AC12ERR_AC12CE field. |
mbed_official | 146:f64d43ff0c18 | 4391 | #define BR_SDHC_AC12ERR_AC12CE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12CE)) |
mbed_official | 146:f64d43ff0c18 | 4392 | #endif |
mbed_official | 146:f64d43ff0c18 | 4393 | //@} |
mbed_official | 146:f64d43ff0c18 | 4394 | |
mbed_official | 146:f64d43ff0c18 | 4395 | /*! |
mbed_official | 146:f64d43ff0c18 | 4396 | * @name Register SDHC_AC12ERR, field AC12IE[4] (RO) |
mbed_official | 146:f64d43ff0c18 | 4397 | * |
mbed_official | 146:f64d43ff0c18 | 4398 | * Occurs if the command index error occurs in response to a command. |
mbed_official | 146:f64d43ff0c18 | 4399 | * |
mbed_official | 146:f64d43ff0c18 | 4400 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4401 | * - 0 - No error. |
mbed_official | 146:f64d43ff0c18 | 4402 | * - 1 - Error, the CMD index in response is not CMD12. |
mbed_official | 146:f64d43ff0c18 | 4403 | */ |
mbed_official | 146:f64d43ff0c18 | 4404 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4405 | #define BP_SDHC_AC12ERR_AC12IE (4U) //!< Bit position for SDHC_AC12ERR_AC12IE. |
mbed_official | 146:f64d43ff0c18 | 4406 | #define BM_SDHC_AC12ERR_AC12IE (0x00000010U) //!< Bit mask for SDHC_AC12ERR_AC12IE. |
mbed_official | 146:f64d43ff0c18 | 4407 | #define BS_SDHC_AC12ERR_AC12IE (1U) //!< Bit field size in bits for SDHC_AC12ERR_AC12IE. |
mbed_official | 146:f64d43ff0c18 | 4408 | |
mbed_official | 146:f64d43ff0c18 | 4409 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4410 | //! @brief Read current value of the SDHC_AC12ERR_AC12IE field. |
mbed_official | 146:f64d43ff0c18 | 4411 | #define BR_SDHC_AC12ERR_AC12IE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12IE)) |
mbed_official | 146:f64d43ff0c18 | 4412 | #endif |
mbed_official | 146:f64d43ff0c18 | 4413 | //@} |
mbed_official | 146:f64d43ff0c18 | 4414 | |
mbed_official | 146:f64d43ff0c18 | 4415 | /*! |
mbed_official | 146:f64d43ff0c18 | 4416 | * @name Register SDHC_AC12ERR, field CNIBAC12E[7] (RO) |
mbed_official | 146:f64d43ff0c18 | 4417 | * |
mbed_official | 146:f64d43ff0c18 | 4418 | * Setting this bit to 1 means CMD_wo_DAT is not executed due to an auto CMD12 |
mbed_official | 146:f64d43ff0c18 | 4419 | * error (D04-D01) in this register. |
mbed_official | 146:f64d43ff0c18 | 4420 | * |
mbed_official | 146:f64d43ff0c18 | 4421 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4422 | * - 0 - No error. |
mbed_official | 146:f64d43ff0c18 | 4423 | * - 1 - Not issued. |
mbed_official | 146:f64d43ff0c18 | 4424 | */ |
mbed_official | 146:f64d43ff0c18 | 4425 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4426 | #define BP_SDHC_AC12ERR_CNIBAC12E (7U) //!< Bit position for SDHC_AC12ERR_CNIBAC12E. |
mbed_official | 146:f64d43ff0c18 | 4427 | #define BM_SDHC_AC12ERR_CNIBAC12E (0x00000080U) //!< Bit mask for SDHC_AC12ERR_CNIBAC12E. |
mbed_official | 146:f64d43ff0c18 | 4428 | #define BS_SDHC_AC12ERR_CNIBAC12E (1U) //!< Bit field size in bits for SDHC_AC12ERR_CNIBAC12E. |
mbed_official | 146:f64d43ff0c18 | 4429 | |
mbed_official | 146:f64d43ff0c18 | 4430 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4431 | //! @brief Read current value of the SDHC_AC12ERR_CNIBAC12E field. |
mbed_official | 146:f64d43ff0c18 | 4432 | #define BR_SDHC_AC12ERR_CNIBAC12E (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_CNIBAC12E)) |
mbed_official | 146:f64d43ff0c18 | 4433 | #endif |
mbed_official | 146:f64d43ff0c18 | 4434 | //@} |
mbed_official | 146:f64d43ff0c18 | 4435 | |
mbed_official | 146:f64d43ff0c18 | 4436 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4437 | // HW_SDHC_HTCAPBLT - Host Controller Capabilities |
mbed_official | 146:f64d43ff0c18 | 4438 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4439 | |
mbed_official | 146:f64d43ff0c18 | 4440 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4441 | /*! |
mbed_official | 146:f64d43ff0c18 | 4442 | * @brief HW_SDHC_HTCAPBLT - Host Controller Capabilities (RO) |
mbed_official | 146:f64d43ff0c18 | 4443 | * |
mbed_official | 146:f64d43ff0c18 | 4444 | * Reset value: 0x07F30000U |
mbed_official | 146:f64d43ff0c18 | 4445 | * |
mbed_official | 146:f64d43ff0c18 | 4446 | * This register provides the host driver with information specific to the SDHC |
mbed_official | 146:f64d43ff0c18 | 4447 | * implementation. The value in this register is the power-on-reset value, and |
mbed_official | 146:f64d43ff0c18 | 4448 | * does not change with a software reset. Any write to this register is ignored. |
mbed_official | 146:f64d43ff0c18 | 4449 | */ |
mbed_official | 146:f64d43ff0c18 | 4450 | typedef union _hw_sdhc_htcapblt |
mbed_official | 146:f64d43ff0c18 | 4451 | { |
mbed_official | 146:f64d43ff0c18 | 4452 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 4453 | struct _hw_sdhc_htcapblt_bitfields |
mbed_official | 146:f64d43ff0c18 | 4454 | { |
mbed_official | 146:f64d43ff0c18 | 4455 | uint32_t RESERVED0 : 16; //!< [15:0] |
mbed_official | 146:f64d43ff0c18 | 4456 | uint32_t MBL : 3; //!< [18:16] Max Block Length |
mbed_official | 146:f64d43ff0c18 | 4457 | uint32_t RESERVED1 : 1; //!< [19] |
mbed_official | 146:f64d43ff0c18 | 4458 | uint32_t ADMAS : 1; //!< [20] ADMA Support |
mbed_official | 146:f64d43ff0c18 | 4459 | uint32_t HSS : 1; //!< [21] High Speed Support |
mbed_official | 146:f64d43ff0c18 | 4460 | uint32_t DMAS : 1; //!< [22] DMA Support |
mbed_official | 146:f64d43ff0c18 | 4461 | uint32_t SRS : 1; //!< [23] Suspend/Resume Support |
mbed_official | 146:f64d43ff0c18 | 4462 | uint32_t VS33 : 1; //!< [24] Voltage Support 3.3 V |
mbed_official | 146:f64d43ff0c18 | 4463 | uint32_t RESERVED2 : 7; //!< [31:25] |
mbed_official | 146:f64d43ff0c18 | 4464 | } B; |
mbed_official | 146:f64d43ff0c18 | 4465 | } hw_sdhc_htcapblt_t; |
mbed_official | 146:f64d43ff0c18 | 4466 | #endif |
mbed_official | 146:f64d43ff0c18 | 4467 | |
mbed_official | 146:f64d43ff0c18 | 4468 | /*! |
mbed_official | 146:f64d43ff0c18 | 4469 | * @name Constants and macros for entire SDHC_HTCAPBLT register |
mbed_official | 146:f64d43ff0c18 | 4470 | */ |
mbed_official | 146:f64d43ff0c18 | 4471 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4472 | #define HW_SDHC_HTCAPBLT_ADDR (REGS_SDHC_BASE + 0x40U) |
mbed_official | 146:f64d43ff0c18 | 4473 | |
mbed_official | 146:f64d43ff0c18 | 4474 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4475 | #define HW_SDHC_HTCAPBLT (*(__I hw_sdhc_htcapblt_t *) HW_SDHC_HTCAPBLT_ADDR) |
mbed_official | 146:f64d43ff0c18 | 4476 | #define HW_SDHC_HTCAPBLT_RD() (HW_SDHC_HTCAPBLT.U) |
mbed_official | 146:f64d43ff0c18 | 4477 | #endif |
mbed_official | 146:f64d43ff0c18 | 4478 | //@} |
mbed_official | 146:f64d43ff0c18 | 4479 | |
mbed_official | 146:f64d43ff0c18 | 4480 | /* |
mbed_official | 146:f64d43ff0c18 | 4481 | * Constants & macros for individual SDHC_HTCAPBLT bitfields |
mbed_official | 146:f64d43ff0c18 | 4482 | */ |
mbed_official | 146:f64d43ff0c18 | 4483 | |
mbed_official | 146:f64d43ff0c18 | 4484 | /*! |
mbed_official | 146:f64d43ff0c18 | 4485 | * @name Register SDHC_HTCAPBLT, field MBL[18:16] (RO) |
mbed_official | 146:f64d43ff0c18 | 4486 | * |
mbed_official | 146:f64d43ff0c18 | 4487 | * This value indicates the maximum block size that the host driver can read and |
mbed_official | 146:f64d43ff0c18 | 4488 | * write to the buffer in the SDHC. The buffer shall transfer block size without |
mbed_official | 146:f64d43ff0c18 | 4489 | * wait cycles. |
mbed_official | 146:f64d43ff0c18 | 4490 | * |
mbed_official | 146:f64d43ff0c18 | 4491 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4492 | * - 000 - 512 bytes |
mbed_official | 146:f64d43ff0c18 | 4493 | * - 001 - 1024 bytes |
mbed_official | 146:f64d43ff0c18 | 4494 | * - 010 - 2048 bytes |
mbed_official | 146:f64d43ff0c18 | 4495 | * - 011 - 4096 bytes |
mbed_official | 146:f64d43ff0c18 | 4496 | */ |
mbed_official | 146:f64d43ff0c18 | 4497 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4498 | #define BP_SDHC_HTCAPBLT_MBL (16U) //!< Bit position for SDHC_HTCAPBLT_MBL. |
mbed_official | 146:f64d43ff0c18 | 4499 | #define BM_SDHC_HTCAPBLT_MBL (0x00070000U) //!< Bit mask for SDHC_HTCAPBLT_MBL. |
mbed_official | 146:f64d43ff0c18 | 4500 | #define BS_SDHC_HTCAPBLT_MBL (3U) //!< Bit field size in bits for SDHC_HTCAPBLT_MBL. |
mbed_official | 146:f64d43ff0c18 | 4501 | |
mbed_official | 146:f64d43ff0c18 | 4502 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4503 | //! @brief Read current value of the SDHC_HTCAPBLT_MBL field. |
mbed_official | 146:f64d43ff0c18 | 4504 | #define BR_SDHC_HTCAPBLT_MBL (HW_SDHC_HTCAPBLT.B.MBL) |
mbed_official | 146:f64d43ff0c18 | 4505 | #endif |
mbed_official | 146:f64d43ff0c18 | 4506 | //@} |
mbed_official | 146:f64d43ff0c18 | 4507 | |
mbed_official | 146:f64d43ff0c18 | 4508 | /*! |
mbed_official | 146:f64d43ff0c18 | 4509 | * @name Register SDHC_HTCAPBLT, field ADMAS[20] (RO) |
mbed_official | 146:f64d43ff0c18 | 4510 | * |
mbed_official | 146:f64d43ff0c18 | 4511 | * This bit indicates whether the SDHC supports the ADMA feature. |
mbed_official | 146:f64d43ff0c18 | 4512 | * |
mbed_official | 146:f64d43ff0c18 | 4513 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4514 | * - 0 - Advanced DMA not supported. |
mbed_official | 146:f64d43ff0c18 | 4515 | * - 1 - Advanced DMA supported. |
mbed_official | 146:f64d43ff0c18 | 4516 | */ |
mbed_official | 146:f64d43ff0c18 | 4517 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4518 | #define BP_SDHC_HTCAPBLT_ADMAS (20U) //!< Bit position for SDHC_HTCAPBLT_ADMAS. |
mbed_official | 146:f64d43ff0c18 | 4519 | #define BM_SDHC_HTCAPBLT_ADMAS (0x00100000U) //!< Bit mask for SDHC_HTCAPBLT_ADMAS. |
mbed_official | 146:f64d43ff0c18 | 4520 | #define BS_SDHC_HTCAPBLT_ADMAS (1U) //!< Bit field size in bits for SDHC_HTCAPBLT_ADMAS. |
mbed_official | 146:f64d43ff0c18 | 4521 | |
mbed_official | 146:f64d43ff0c18 | 4522 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4523 | //! @brief Read current value of the SDHC_HTCAPBLT_ADMAS field. |
mbed_official | 146:f64d43ff0c18 | 4524 | #define BR_SDHC_HTCAPBLT_ADMAS (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_ADMAS)) |
mbed_official | 146:f64d43ff0c18 | 4525 | #endif |
mbed_official | 146:f64d43ff0c18 | 4526 | //@} |
mbed_official | 146:f64d43ff0c18 | 4527 | |
mbed_official | 146:f64d43ff0c18 | 4528 | /*! |
mbed_official | 146:f64d43ff0c18 | 4529 | * @name Register SDHC_HTCAPBLT, field HSS[21] (RO) |
mbed_official | 146:f64d43ff0c18 | 4530 | * |
mbed_official | 146:f64d43ff0c18 | 4531 | * This bit indicates whether the SDHC supports high speed mode and the host |
mbed_official | 146:f64d43ff0c18 | 4532 | * system can supply a SD Clock frequency from 25 MHz to 50 MHz. |
mbed_official | 146:f64d43ff0c18 | 4533 | * |
mbed_official | 146:f64d43ff0c18 | 4534 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4535 | * - 0 - High speed not supported. |
mbed_official | 146:f64d43ff0c18 | 4536 | * - 1 - High speed supported. |
mbed_official | 146:f64d43ff0c18 | 4537 | */ |
mbed_official | 146:f64d43ff0c18 | 4538 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4539 | #define BP_SDHC_HTCAPBLT_HSS (21U) //!< Bit position for SDHC_HTCAPBLT_HSS. |
mbed_official | 146:f64d43ff0c18 | 4540 | #define BM_SDHC_HTCAPBLT_HSS (0x00200000U) //!< Bit mask for SDHC_HTCAPBLT_HSS. |
mbed_official | 146:f64d43ff0c18 | 4541 | #define BS_SDHC_HTCAPBLT_HSS (1U) //!< Bit field size in bits for SDHC_HTCAPBLT_HSS. |
mbed_official | 146:f64d43ff0c18 | 4542 | |
mbed_official | 146:f64d43ff0c18 | 4543 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4544 | //! @brief Read current value of the SDHC_HTCAPBLT_HSS field. |
mbed_official | 146:f64d43ff0c18 | 4545 | #define BR_SDHC_HTCAPBLT_HSS (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_HSS)) |
mbed_official | 146:f64d43ff0c18 | 4546 | #endif |
mbed_official | 146:f64d43ff0c18 | 4547 | //@} |
mbed_official | 146:f64d43ff0c18 | 4548 | |
mbed_official | 146:f64d43ff0c18 | 4549 | /*! |
mbed_official | 146:f64d43ff0c18 | 4550 | * @name Register SDHC_HTCAPBLT, field DMAS[22] (RO) |
mbed_official | 146:f64d43ff0c18 | 4551 | * |
mbed_official | 146:f64d43ff0c18 | 4552 | * This bit indicates whether the SDHC is capable of using the internal DMA to |
mbed_official | 146:f64d43ff0c18 | 4553 | * transfer data between system memory and the data buffer directly. |
mbed_official | 146:f64d43ff0c18 | 4554 | * |
mbed_official | 146:f64d43ff0c18 | 4555 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4556 | * - 0 - DMA not supported. |
mbed_official | 146:f64d43ff0c18 | 4557 | * - 1 - DMA supported. |
mbed_official | 146:f64d43ff0c18 | 4558 | */ |
mbed_official | 146:f64d43ff0c18 | 4559 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4560 | #define BP_SDHC_HTCAPBLT_DMAS (22U) //!< Bit position for SDHC_HTCAPBLT_DMAS. |
mbed_official | 146:f64d43ff0c18 | 4561 | #define BM_SDHC_HTCAPBLT_DMAS (0x00400000U) //!< Bit mask for SDHC_HTCAPBLT_DMAS. |
mbed_official | 146:f64d43ff0c18 | 4562 | #define BS_SDHC_HTCAPBLT_DMAS (1U) //!< Bit field size in bits for SDHC_HTCAPBLT_DMAS. |
mbed_official | 146:f64d43ff0c18 | 4563 | |
mbed_official | 146:f64d43ff0c18 | 4564 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4565 | //! @brief Read current value of the SDHC_HTCAPBLT_DMAS field. |
mbed_official | 146:f64d43ff0c18 | 4566 | #define BR_SDHC_HTCAPBLT_DMAS (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_DMAS)) |
mbed_official | 146:f64d43ff0c18 | 4567 | #endif |
mbed_official | 146:f64d43ff0c18 | 4568 | //@} |
mbed_official | 146:f64d43ff0c18 | 4569 | |
mbed_official | 146:f64d43ff0c18 | 4570 | /*! |
mbed_official | 146:f64d43ff0c18 | 4571 | * @name Register SDHC_HTCAPBLT, field SRS[23] (RO) |
mbed_official | 146:f64d43ff0c18 | 4572 | * |
mbed_official | 146:f64d43ff0c18 | 4573 | * This bit indicates whether the SDHC supports suspend / resume functionality. |
mbed_official | 146:f64d43ff0c18 | 4574 | * If this bit is 0, the suspend and resume mechanism, as well as the read Wwait, |
mbed_official | 146:f64d43ff0c18 | 4575 | * are not supported, and the host driver shall not issue either suspend or |
mbed_official | 146:f64d43ff0c18 | 4576 | * resume commands. |
mbed_official | 146:f64d43ff0c18 | 4577 | * |
mbed_official | 146:f64d43ff0c18 | 4578 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4579 | * - 0 - Not supported. |
mbed_official | 146:f64d43ff0c18 | 4580 | * - 1 - Supported. |
mbed_official | 146:f64d43ff0c18 | 4581 | */ |
mbed_official | 146:f64d43ff0c18 | 4582 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4583 | #define BP_SDHC_HTCAPBLT_SRS (23U) //!< Bit position for SDHC_HTCAPBLT_SRS. |
mbed_official | 146:f64d43ff0c18 | 4584 | #define BM_SDHC_HTCAPBLT_SRS (0x00800000U) //!< Bit mask for SDHC_HTCAPBLT_SRS. |
mbed_official | 146:f64d43ff0c18 | 4585 | #define BS_SDHC_HTCAPBLT_SRS (1U) //!< Bit field size in bits for SDHC_HTCAPBLT_SRS. |
mbed_official | 146:f64d43ff0c18 | 4586 | |
mbed_official | 146:f64d43ff0c18 | 4587 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4588 | //! @brief Read current value of the SDHC_HTCAPBLT_SRS field. |
mbed_official | 146:f64d43ff0c18 | 4589 | #define BR_SDHC_HTCAPBLT_SRS (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_SRS)) |
mbed_official | 146:f64d43ff0c18 | 4590 | #endif |
mbed_official | 146:f64d43ff0c18 | 4591 | //@} |
mbed_official | 146:f64d43ff0c18 | 4592 | |
mbed_official | 146:f64d43ff0c18 | 4593 | /*! |
mbed_official | 146:f64d43ff0c18 | 4594 | * @name Register SDHC_HTCAPBLT, field VS33[24] (RO) |
mbed_official | 146:f64d43ff0c18 | 4595 | * |
mbed_official | 146:f64d43ff0c18 | 4596 | * This bit shall depend on the host system ability. |
mbed_official | 146:f64d43ff0c18 | 4597 | * |
mbed_official | 146:f64d43ff0c18 | 4598 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4599 | * - 0 - 3.3 V not supported. |
mbed_official | 146:f64d43ff0c18 | 4600 | * - 1 - 3.3 V supported. |
mbed_official | 146:f64d43ff0c18 | 4601 | */ |
mbed_official | 146:f64d43ff0c18 | 4602 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4603 | #define BP_SDHC_HTCAPBLT_VS33 (24U) //!< Bit position for SDHC_HTCAPBLT_VS33. |
mbed_official | 146:f64d43ff0c18 | 4604 | #define BM_SDHC_HTCAPBLT_VS33 (0x01000000U) //!< Bit mask for SDHC_HTCAPBLT_VS33. |
mbed_official | 146:f64d43ff0c18 | 4605 | #define BS_SDHC_HTCAPBLT_VS33 (1U) //!< Bit field size in bits for SDHC_HTCAPBLT_VS33. |
mbed_official | 146:f64d43ff0c18 | 4606 | |
mbed_official | 146:f64d43ff0c18 | 4607 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4608 | //! @brief Read current value of the SDHC_HTCAPBLT_VS33 field. |
mbed_official | 146:f64d43ff0c18 | 4609 | #define BR_SDHC_HTCAPBLT_VS33 (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_VS33)) |
mbed_official | 146:f64d43ff0c18 | 4610 | #endif |
mbed_official | 146:f64d43ff0c18 | 4611 | //@} |
mbed_official | 146:f64d43ff0c18 | 4612 | |
mbed_official | 146:f64d43ff0c18 | 4613 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4614 | // HW_SDHC_WML - Watermark Level Register |
mbed_official | 146:f64d43ff0c18 | 4615 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4616 | |
mbed_official | 146:f64d43ff0c18 | 4617 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4618 | /*! |
mbed_official | 146:f64d43ff0c18 | 4619 | * @brief HW_SDHC_WML - Watermark Level Register (RW) |
mbed_official | 146:f64d43ff0c18 | 4620 | * |
mbed_official | 146:f64d43ff0c18 | 4621 | * Reset value: 0x00100010U |
mbed_official | 146:f64d43ff0c18 | 4622 | * |
mbed_official | 146:f64d43ff0c18 | 4623 | * Both write and read watermark levels (FIFO threshold) are configurable. There |
mbed_official | 146:f64d43ff0c18 | 4624 | * value can range from 1 to 128 words. Both write and read burst lengths are |
mbed_official | 146:f64d43ff0c18 | 4625 | * also configurable. There value can range from 1 to 31 words. |
mbed_official | 146:f64d43ff0c18 | 4626 | */ |
mbed_official | 146:f64d43ff0c18 | 4627 | typedef union _hw_sdhc_wml |
mbed_official | 146:f64d43ff0c18 | 4628 | { |
mbed_official | 146:f64d43ff0c18 | 4629 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 4630 | struct _hw_sdhc_wml_bitfields |
mbed_official | 146:f64d43ff0c18 | 4631 | { |
mbed_official | 146:f64d43ff0c18 | 4632 | uint32_t RDWML : 8; //!< [7:0] Read Watermark Level |
mbed_official | 146:f64d43ff0c18 | 4633 | uint32_t RESERVED0 : 8; //!< [15:8] |
mbed_official | 146:f64d43ff0c18 | 4634 | uint32_t WRWML : 8; //!< [23:16] Write Watermark Level |
mbed_official | 146:f64d43ff0c18 | 4635 | uint32_t RESERVED1 : 8; //!< [31:24] |
mbed_official | 146:f64d43ff0c18 | 4636 | } B; |
mbed_official | 146:f64d43ff0c18 | 4637 | } hw_sdhc_wml_t; |
mbed_official | 146:f64d43ff0c18 | 4638 | #endif |
mbed_official | 146:f64d43ff0c18 | 4639 | |
mbed_official | 146:f64d43ff0c18 | 4640 | /*! |
mbed_official | 146:f64d43ff0c18 | 4641 | * @name Constants and macros for entire SDHC_WML register |
mbed_official | 146:f64d43ff0c18 | 4642 | */ |
mbed_official | 146:f64d43ff0c18 | 4643 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4644 | #define HW_SDHC_WML_ADDR (REGS_SDHC_BASE + 0x44U) |
mbed_official | 146:f64d43ff0c18 | 4645 | |
mbed_official | 146:f64d43ff0c18 | 4646 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4647 | #define HW_SDHC_WML (*(__IO hw_sdhc_wml_t *) HW_SDHC_WML_ADDR) |
mbed_official | 146:f64d43ff0c18 | 4648 | #define HW_SDHC_WML_RD() (HW_SDHC_WML.U) |
mbed_official | 146:f64d43ff0c18 | 4649 | #define HW_SDHC_WML_WR(v) (HW_SDHC_WML.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 4650 | #define HW_SDHC_WML_SET(v) (HW_SDHC_WML_WR(HW_SDHC_WML_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 4651 | #define HW_SDHC_WML_CLR(v) (HW_SDHC_WML_WR(HW_SDHC_WML_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 4652 | #define HW_SDHC_WML_TOG(v) (HW_SDHC_WML_WR(HW_SDHC_WML_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 4653 | #endif |
mbed_official | 146:f64d43ff0c18 | 4654 | //@} |
mbed_official | 146:f64d43ff0c18 | 4655 | |
mbed_official | 146:f64d43ff0c18 | 4656 | /* |
mbed_official | 146:f64d43ff0c18 | 4657 | * Constants & macros for individual SDHC_WML bitfields |
mbed_official | 146:f64d43ff0c18 | 4658 | */ |
mbed_official | 146:f64d43ff0c18 | 4659 | |
mbed_official | 146:f64d43ff0c18 | 4660 | /*! |
mbed_official | 146:f64d43ff0c18 | 4661 | * @name Register SDHC_WML, field RDWML[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 4662 | * |
mbed_official | 146:f64d43ff0c18 | 4663 | * The number of words used as the watermark level (FIFO threshold) in a DMA |
mbed_official | 146:f64d43ff0c18 | 4664 | * read operation. Also the number of words as a sequence of read bursts in |
mbed_official | 146:f64d43ff0c18 | 4665 | * back-to-back mode. The maximum legal value for the read water mark level is 128. |
mbed_official | 146:f64d43ff0c18 | 4666 | */ |
mbed_official | 146:f64d43ff0c18 | 4667 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4668 | #define BP_SDHC_WML_RDWML (0U) //!< Bit position for SDHC_WML_RDWML. |
mbed_official | 146:f64d43ff0c18 | 4669 | #define BM_SDHC_WML_RDWML (0x000000FFU) //!< Bit mask for SDHC_WML_RDWML. |
mbed_official | 146:f64d43ff0c18 | 4670 | #define BS_SDHC_WML_RDWML (8U) //!< Bit field size in bits for SDHC_WML_RDWML. |
mbed_official | 146:f64d43ff0c18 | 4671 | |
mbed_official | 146:f64d43ff0c18 | 4672 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4673 | //! @brief Read current value of the SDHC_WML_RDWML field. |
mbed_official | 146:f64d43ff0c18 | 4674 | #define BR_SDHC_WML_RDWML (HW_SDHC_WML.B.RDWML) |
mbed_official | 146:f64d43ff0c18 | 4675 | #endif |
mbed_official | 146:f64d43ff0c18 | 4676 | |
mbed_official | 146:f64d43ff0c18 | 4677 | //! @brief Format value for bitfield SDHC_WML_RDWML. |
mbed_official | 146:f64d43ff0c18 | 4678 | #define BF_SDHC_WML_RDWML(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_WML_RDWML), uint32_t) & BM_SDHC_WML_RDWML) |
mbed_official | 146:f64d43ff0c18 | 4679 | |
mbed_official | 146:f64d43ff0c18 | 4680 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4681 | //! @brief Set the RDWML field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4682 | #define BW_SDHC_WML_RDWML(v) (HW_SDHC_WML_WR((HW_SDHC_WML_RD() & ~BM_SDHC_WML_RDWML) | BF_SDHC_WML_RDWML(v))) |
mbed_official | 146:f64d43ff0c18 | 4683 | #endif |
mbed_official | 146:f64d43ff0c18 | 4684 | //@} |
mbed_official | 146:f64d43ff0c18 | 4685 | |
mbed_official | 146:f64d43ff0c18 | 4686 | /*! |
mbed_official | 146:f64d43ff0c18 | 4687 | * @name Register SDHC_WML, field WRWML[23:16] (RW) |
mbed_official | 146:f64d43ff0c18 | 4688 | * |
mbed_official | 146:f64d43ff0c18 | 4689 | * The number of words used as the watermark level (FIFO threshold) in a DMA |
mbed_official | 146:f64d43ff0c18 | 4690 | * write operation. Also the number of words as a sequence of write bursts in |
mbed_official | 146:f64d43ff0c18 | 4691 | * back-to-back mode. The maximum legal value for the write watermark level is 128. |
mbed_official | 146:f64d43ff0c18 | 4692 | */ |
mbed_official | 146:f64d43ff0c18 | 4693 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4694 | #define BP_SDHC_WML_WRWML (16U) //!< Bit position for SDHC_WML_WRWML. |
mbed_official | 146:f64d43ff0c18 | 4695 | #define BM_SDHC_WML_WRWML (0x00FF0000U) //!< Bit mask for SDHC_WML_WRWML. |
mbed_official | 146:f64d43ff0c18 | 4696 | #define BS_SDHC_WML_WRWML (8U) //!< Bit field size in bits for SDHC_WML_WRWML. |
mbed_official | 146:f64d43ff0c18 | 4697 | |
mbed_official | 146:f64d43ff0c18 | 4698 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4699 | //! @brief Read current value of the SDHC_WML_WRWML field. |
mbed_official | 146:f64d43ff0c18 | 4700 | #define BR_SDHC_WML_WRWML (HW_SDHC_WML.B.WRWML) |
mbed_official | 146:f64d43ff0c18 | 4701 | #endif |
mbed_official | 146:f64d43ff0c18 | 4702 | |
mbed_official | 146:f64d43ff0c18 | 4703 | //! @brief Format value for bitfield SDHC_WML_WRWML. |
mbed_official | 146:f64d43ff0c18 | 4704 | #define BF_SDHC_WML_WRWML(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_WML_WRWML), uint32_t) & BM_SDHC_WML_WRWML) |
mbed_official | 146:f64d43ff0c18 | 4705 | |
mbed_official | 146:f64d43ff0c18 | 4706 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4707 | //! @brief Set the WRWML field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4708 | #define BW_SDHC_WML_WRWML(v) (HW_SDHC_WML_WR((HW_SDHC_WML_RD() & ~BM_SDHC_WML_WRWML) | BF_SDHC_WML_WRWML(v))) |
mbed_official | 146:f64d43ff0c18 | 4709 | #endif |
mbed_official | 146:f64d43ff0c18 | 4710 | //@} |
mbed_official | 146:f64d43ff0c18 | 4711 | |
mbed_official | 146:f64d43ff0c18 | 4712 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4713 | // HW_SDHC_FEVT - Force Event register |
mbed_official | 146:f64d43ff0c18 | 4714 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4715 | |
mbed_official | 146:f64d43ff0c18 | 4716 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4717 | /*! |
mbed_official | 146:f64d43ff0c18 | 4718 | * @brief HW_SDHC_FEVT - Force Event register (WO) |
mbed_official | 146:f64d43ff0c18 | 4719 | * |
mbed_official | 146:f64d43ff0c18 | 4720 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 4721 | * |
mbed_official | 146:f64d43ff0c18 | 4722 | * The Force Event (FEVT) register is not a physically implemented register. |
mbed_official | 146:f64d43ff0c18 | 4723 | * Rather, it is an address at which the Interrupt Status register can be written if |
mbed_official | 146:f64d43ff0c18 | 4724 | * the corresponding bit of the Interrupt Status Enable register is set. This |
mbed_official | 146:f64d43ff0c18 | 4725 | * register is a write only register and writing 0 to it has no effect. Writing 1 |
mbed_official | 146:f64d43ff0c18 | 4726 | * to this register actually sets the corresponding bit of Interrupt Status |
mbed_official | 146:f64d43ff0c18 | 4727 | * register. A read from this register always results in 0's. To change the |
mbed_official | 146:f64d43ff0c18 | 4728 | * corresponding status bits in the interrupt status register, make sure to set |
mbed_official | 146:f64d43ff0c18 | 4729 | * SYSCTL[IPGEN] so that bus clock is always active. Forcing a card interrupt will generate a |
mbed_official | 146:f64d43ff0c18 | 4730 | * short pulse on the DAT[1] line, and the driver may treat this interrupt as a |
mbed_official | 146:f64d43ff0c18 | 4731 | * normal interrupt. The interrupt service routine may skip polling the card |
mbed_official | 146:f64d43ff0c18 | 4732 | * interrupt factor as the interrupt is selfcleared. |
mbed_official | 146:f64d43ff0c18 | 4733 | */ |
mbed_official | 146:f64d43ff0c18 | 4734 | typedef union _hw_sdhc_fevt |
mbed_official | 146:f64d43ff0c18 | 4735 | { |
mbed_official | 146:f64d43ff0c18 | 4736 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 4737 | struct _hw_sdhc_fevt_bitfields |
mbed_official | 146:f64d43ff0c18 | 4738 | { |
mbed_official | 146:f64d43ff0c18 | 4739 | uint32_t AC12NE : 1; //!< [0] Force Event Auto Command 12 Not Executed |
mbed_official | 146:f64d43ff0c18 | 4740 | uint32_t AC12TOE : 1; //!< [1] Force Event Auto Command 12 Time Out |
mbed_official | 146:f64d43ff0c18 | 4741 | //! Error |
mbed_official | 146:f64d43ff0c18 | 4742 | uint32_t AC12CE : 1; //!< [2] Force Event Auto Command 12 CRC Error |
mbed_official | 146:f64d43ff0c18 | 4743 | uint32_t AC12EBE : 1; //!< [3] Force Event Auto Command 12 End Bit |
mbed_official | 146:f64d43ff0c18 | 4744 | //! Error |
mbed_official | 146:f64d43ff0c18 | 4745 | uint32_t AC12IE : 1; //!< [4] Force Event Auto Command 12 Index Error |
mbed_official | 146:f64d43ff0c18 | 4746 | uint32_t RESERVED0 : 2; //!< [6:5] |
mbed_official | 146:f64d43ff0c18 | 4747 | uint32_t CNIBAC12E : 1; //!< [7] Force Event Command Not Executed By |
mbed_official | 146:f64d43ff0c18 | 4748 | //! Auto Command 12 Error |
mbed_official | 146:f64d43ff0c18 | 4749 | uint32_t RESERVED1 : 8; //!< [15:8] |
mbed_official | 146:f64d43ff0c18 | 4750 | uint32_t CTOE : 1; //!< [16] Force Event Command Time Out Error |
mbed_official | 146:f64d43ff0c18 | 4751 | uint32_t CCE : 1; //!< [17] Force Event Command CRC Error |
mbed_official | 146:f64d43ff0c18 | 4752 | uint32_t CEBE : 1; //!< [18] Force Event Command End Bit Error |
mbed_official | 146:f64d43ff0c18 | 4753 | uint32_t CIE : 1; //!< [19] Force Event Command Index Error |
mbed_official | 146:f64d43ff0c18 | 4754 | uint32_t DTOE : 1; //!< [20] Force Event Data Time Out Error |
mbed_official | 146:f64d43ff0c18 | 4755 | uint32_t DCE : 1; //!< [21] Force Event Data CRC Error |
mbed_official | 146:f64d43ff0c18 | 4756 | uint32_t DEBE : 1; //!< [22] Force Event Data End Bit Error |
mbed_official | 146:f64d43ff0c18 | 4757 | uint32_t RESERVED2 : 1; //!< [23] |
mbed_official | 146:f64d43ff0c18 | 4758 | uint32_t AC12E : 1; //!< [24] Force Event Auto Command 12 Error |
mbed_official | 146:f64d43ff0c18 | 4759 | uint32_t RESERVED3 : 3; //!< [27:25] |
mbed_official | 146:f64d43ff0c18 | 4760 | uint32_t DMAE : 1; //!< [28] Force Event DMA Error |
mbed_official | 146:f64d43ff0c18 | 4761 | uint32_t RESERVED4 : 2; //!< [30:29] |
mbed_official | 146:f64d43ff0c18 | 4762 | uint32_t CINT : 1; //!< [31] Force Event Card Interrupt |
mbed_official | 146:f64d43ff0c18 | 4763 | } B; |
mbed_official | 146:f64d43ff0c18 | 4764 | } hw_sdhc_fevt_t; |
mbed_official | 146:f64d43ff0c18 | 4765 | #endif |
mbed_official | 146:f64d43ff0c18 | 4766 | |
mbed_official | 146:f64d43ff0c18 | 4767 | /*! |
mbed_official | 146:f64d43ff0c18 | 4768 | * @name Constants and macros for entire SDHC_FEVT register |
mbed_official | 146:f64d43ff0c18 | 4769 | */ |
mbed_official | 146:f64d43ff0c18 | 4770 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4771 | #define HW_SDHC_FEVT_ADDR (REGS_SDHC_BASE + 0x50U) |
mbed_official | 146:f64d43ff0c18 | 4772 | |
mbed_official | 146:f64d43ff0c18 | 4773 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4774 | #define HW_SDHC_FEVT (*(__O hw_sdhc_fevt_t *) HW_SDHC_FEVT_ADDR) |
mbed_official | 146:f64d43ff0c18 | 4775 | #define HW_SDHC_FEVT_RD() (HW_SDHC_FEVT.U) |
mbed_official | 146:f64d43ff0c18 | 4776 | #define HW_SDHC_FEVT_WR(v) (HW_SDHC_FEVT.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 4777 | #endif |
mbed_official | 146:f64d43ff0c18 | 4778 | //@} |
mbed_official | 146:f64d43ff0c18 | 4779 | |
mbed_official | 146:f64d43ff0c18 | 4780 | /* |
mbed_official | 146:f64d43ff0c18 | 4781 | * Constants & macros for individual SDHC_FEVT bitfields |
mbed_official | 146:f64d43ff0c18 | 4782 | */ |
mbed_official | 146:f64d43ff0c18 | 4783 | |
mbed_official | 146:f64d43ff0c18 | 4784 | /*! |
mbed_official | 146:f64d43ff0c18 | 4785 | * @name Register SDHC_FEVT, field AC12NE[0] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 4786 | * |
mbed_official | 146:f64d43ff0c18 | 4787 | * Forces AC12ERR[AC12NE] to be set. |
mbed_official | 146:f64d43ff0c18 | 4788 | */ |
mbed_official | 146:f64d43ff0c18 | 4789 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4790 | #define BP_SDHC_FEVT_AC12NE (0U) //!< Bit position for SDHC_FEVT_AC12NE. |
mbed_official | 146:f64d43ff0c18 | 4791 | #define BM_SDHC_FEVT_AC12NE (0x00000001U) //!< Bit mask for SDHC_FEVT_AC12NE. |
mbed_official | 146:f64d43ff0c18 | 4792 | #define BS_SDHC_FEVT_AC12NE (1U) //!< Bit field size in bits for SDHC_FEVT_AC12NE. |
mbed_official | 146:f64d43ff0c18 | 4793 | |
mbed_official | 146:f64d43ff0c18 | 4794 | //! @brief Format value for bitfield SDHC_FEVT_AC12NE. |
mbed_official | 146:f64d43ff0c18 | 4795 | #define BF_SDHC_FEVT_AC12NE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12NE), uint32_t) & BM_SDHC_FEVT_AC12NE) |
mbed_official | 146:f64d43ff0c18 | 4796 | |
mbed_official | 146:f64d43ff0c18 | 4797 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4798 | //! @brief Set the AC12NE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4799 | #define BW_SDHC_FEVT_AC12NE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12NE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4800 | #endif |
mbed_official | 146:f64d43ff0c18 | 4801 | //@} |
mbed_official | 146:f64d43ff0c18 | 4802 | |
mbed_official | 146:f64d43ff0c18 | 4803 | /*! |
mbed_official | 146:f64d43ff0c18 | 4804 | * @name Register SDHC_FEVT, field AC12TOE[1] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 4805 | * |
mbed_official | 146:f64d43ff0c18 | 4806 | * Forces AC12ERR[AC12TOE] to be set. |
mbed_official | 146:f64d43ff0c18 | 4807 | */ |
mbed_official | 146:f64d43ff0c18 | 4808 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4809 | #define BP_SDHC_FEVT_AC12TOE (1U) //!< Bit position for SDHC_FEVT_AC12TOE. |
mbed_official | 146:f64d43ff0c18 | 4810 | #define BM_SDHC_FEVT_AC12TOE (0x00000002U) //!< Bit mask for SDHC_FEVT_AC12TOE. |
mbed_official | 146:f64d43ff0c18 | 4811 | #define BS_SDHC_FEVT_AC12TOE (1U) //!< Bit field size in bits for SDHC_FEVT_AC12TOE. |
mbed_official | 146:f64d43ff0c18 | 4812 | |
mbed_official | 146:f64d43ff0c18 | 4813 | //! @brief Format value for bitfield SDHC_FEVT_AC12TOE. |
mbed_official | 146:f64d43ff0c18 | 4814 | #define BF_SDHC_FEVT_AC12TOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12TOE), uint32_t) & BM_SDHC_FEVT_AC12TOE) |
mbed_official | 146:f64d43ff0c18 | 4815 | |
mbed_official | 146:f64d43ff0c18 | 4816 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4817 | //! @brief Set the AC12TOE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4818 | #define BW_SDHC_FEVT_AC12TOE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12TOE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4819 | #endif |
mbed_official | 146:f64d43ff0c18 | 4820 | //@} |
mbed_official | 146:f64d43ff0c18 | 4821 | |
mbed_official | 146:f64d43ff0c18 | 4822 | /*! |
mbed_official | 146:f64d43ff0c18 | 4823 | * @name Register SDHC_FEVT, field AC12CE[2] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 4824 | * |
mbed_official | 146:f64d43ff0c18 | 4825 | * Forces AC12ERR[AC12CE] to be set. |
mbed_official | 146:f64d43ff0c18 | 4826 | */ |
mbed_official | 146:f64d43ff0c18 | 4827 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4828 | #define BP_SDHC_FEVT_AC12CE (2U) //!< Bit position for SDHC_FEVT_AC12CE. |
mbed_official | 146:f64d43ff0c18 | 4829 | #define BM_SDHC_FEVT_AC12CE (0x00000004U) //!< Bit mask for SDHC_FEVT_AC12CE. |
mbed_official | 146:f64d43ff0c18 | 4830 | #define BS_SDHC_FEVT_AC12CE (1U) //!< Bit field size in bits for SDHC_FEVT_AC12CE. |
mbed_official | 146:f64d43ff0c18 | 4831 | |
mbed_official | 146:f64d43ff0c18 | 4832 | //! @brief Format value for bitfield SDHC_FEVT_AC12CE. |
mbed_official | 146:f64d43ff0c18 | 4833 | #define BF_SDHC_FEVT_AC12CE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12CE), uint32_t) & BM_SDHC_FEVT_AC12CE) |
mbed_official | 146:f64d43ff0c18 | 4834 | |
mbed_official | 146:f64d43ff0c18 | 4835 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4836 | //! @brief Set the AC12CE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4837 | #define BW_SDHC_FEVT_AC12CE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12CE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4838 | #endif |
mbed_official | 146:f64d43ff0c18 | 4839 | //@} |
mbed_official | 146:f64d43ff0c18 | 4840 | |
mbed_official | 146:f64d43ff0c18 | 4841 | /*! |
mbed_official | 146:f64d43ff0c18 | 4842 | * @name Register SDHC_FEVT, field AC12EBE[3] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 4843 | * |
mbed_official | 146:f64d43ff0c18 | 4844 | * Forces AC12ERR[AC12EBE] to be set. |
mbed_official | 146:f64d43ff0c18 | 4845 | */ |
mbed_official | 146:f64d43ff0c18 | 4846 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4847 | #define BP_SDHC_FEVT_AC12EBE (3U) //!< Bit position for SDHC_FEVT_AC12EBE. |
mbed_official | 146:f64d43ff0c18 | 4848 | #define BM_SDHC_FEVT_AC12EBE (0x00000008U) //!< Bit mask for SDHC_FEVT_AC12EBE. |
mbed_official | 146:f64d43ff0c18 | 4849 | #define BS_SDHC_FEVT_AC12EBE (1U) //!< Bit field size in bits for SDHC_FEVT_AC12EBE. |
mbed_official | 146:f64d43ff0c18 | 4850 | |
mbed_official | 146:f64d43ff0c18 | 4851 | //! @brief Format value for bitfield SDHC_FEVT_AC12EBE. |
mbed_official | 146:f64d43ff0c18 | 4852 | #define BF_SDHC_FEVT_AC12EBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12EBE), uint32_t) & BM_SDHC_FEVT_AC12EBE) |
mbed_official | 146:f64d43ff0c18 | 4853 | |
mbed_official | 146:f64d43ff0c18 | 4854 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4855 | //! @brief Set the AC12EBE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4856 | #define BW_SDHC_FEVT_AC12EBE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12EBE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4857 | #endif |
mbed_official | 146:f64d43ff0c18 | 4858 | //@} |
mbed_official | 146:f64d43ff0c18 | 4859 | |
mbed_official | 146:f64d43ff0c18 | 4860 | /*! |
mbed_official | 146:f64d43ff0c18 | 4861 | * @name Register SDHC_FEVT, field AC12IE[4] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 4862 | * |
mbed_official | 146:f64d43ff0c18 | 4863 | * Forces AC12ERR[AC12IE] to be set. |
mbed_official | 146:f64d43ff0c18 | 4864 | */ |
mbed_official | 146:f64d43ff0c18 | 4865 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4866 | #define BP_SDHC_FEVT_AC12IE (4U) //!< Bit position for SDHC_FEVT_AC12IE. |
mbed_official | 146:f64d43ff0c18 | 4867 | #define BM_SDHC_FEVT_AC12IE (0x00000010U) //!< Bit mask for SDHC_FEVT_AC12IE. |
mbed_official | 146:f64d43ff0c18 | 4868 | #define BS_SDHC_FEVT_AC12IE (1U) //!< Bit field size in bits for SDHC_FEVT_AC12IE. |
mbed_official | 146:f64d43ff0c18 | 4869 | |
mbed_official | 146:f64d43ff0c18 | 4870 | //! @brief Format value for bitfield SDHC_FEVT_AC12IE. |
mbed_official | 146:f64d43ff0c18 | 4871 | #define BF_SDHC_FEVT_AC12IE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12IE), uint32_t) & BM_SDHC_FEVT_AC12IE) |
mbed_official | 146:f64d43ff0c18 | 4872 | |
mbed_official | 146:f64d43ff0c18 | 4873 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4874 | //! @brief Set the AC12IE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4875 | #define BW_SDHC_FEVT_AC12IE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12IE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4876 | #endif |
mbed_official | 146:f64d43ff0c18 | 4877 | //@} |
mbed_official | 146:f64d43ff0c18 | 4878 | |
mbed_official | 146:f64d43ff0c18 | 4879 | /*! |
mbed_official | 146:f64d43ff0c18 | 4880 | * @name Register SDHC_FEVT, field CNIBAC12E[7] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 4881 | * |
mbed_official | 146:f64d43ff0c18 | 4882 | * Forces AC12ERR[CNIBAC12E] to be set. |
mbed_official | 146:f64d43ff0c18 | 4883 | */ |
mbed_official | 146:f64d43ff0c18 | 4884 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4885 | #define BP_SDHC_FEVT_CNIBAC12E (7U) //!< Bit position for SDHC_FEVT_CNIBAC12E. |
mbed_official | 146:f64d43ff0c18 | 4886 | #define BM_SDHC_FEVT_CNIBAC12E (0x00000080U) //!< Bit mask for SDHC_FEVT_CNIBAC12E. |
mbed_official | 146:f64d43ff0c18 | 4887 | #define BS_SDHC_FEVT_CNIBAC12E (1U) //!< Bit field size in bits for SDHC_FEVT_CNIBAC12E. |
mbed_official | 146:f64d43ff0c18 | 4888 | |
mbed_official | 146:f64d43ff0c18 | 4889 | //! @brief Format value for bitfield SDHC_FEVT_CNIBAC12E. |
mbed_official | 146:f64d43ff0c18 | 4890 | #define BF_SDHC_FEVT_CNIBAC12E(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CNIBAC12E), uint32_t) & BM_SDHC_FEVT_CNIBAC12E) |
mbed_official | 146:f64d43ff0c18 | 4891 | |
mbed_official | 146:f64d43ff0c18 | 4892 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4893 | //! @brief Set the CNIBAC12E field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4894 | #define BW_SDHC_FEVT_CNIBAC12E(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CNIBAC12E) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4895 | #endif |
mbed_official | 146:f64d43ff0c18 | 4896 | //@} |
mbed_official | 146:f64d43ff0c18 | 4897 | |
mbed_official | 146:f64d43ff0c18 | 4898 | /*! |
mbed_official | 146:f64d43ff0c18 | 4899 | * @name Register SDHC_FEVT, field CTOE[16] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 4900 | * |
mbed_official | 146:f64d43ff0c18 | 4901 | * Forces IRQSTAT[CTOE] to be set. |
mbed_official | 146:f64d43ff0c18 | 4902 | */ |
mbed_official | 146:f64d43ff0c18 | 4903 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4904 | #define BP_SDHC_FEVT_CTOE (16U) //!< Bit position for SDHC_FEVT_CTOE. |
mbed_official | 146:f64d43ff0c18 | 4905 | #define BM_SDHC_FEVT_CTOE (0x00010000U) //!< Bit mask for SDHC_FEVT_CTOE. |
mbed_official | 146:f64d43ff0c18 | 4906 | #define BS_SDHC_FEVT_CTOE (1U) //!< Bit field size in bits for SDHC_FEVT_CTOE. |
mbed_official | 146:f64d43ff0c18 | 4907 | |
mbed_official | 146:f64d43ff0c18 | 4908 | //! @brief Format value for bitfield SDHC_FEVT_CTOE. |
mbed_official | 146:f64d43ff0c18 | 4909 | #define BF_SDHC_FEVT_CTOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CTOE), uint32_t) & BM_SDHC_FEVT_CTOE) |
mbed_official | 146:f64d43ff0c18 | 4910 | |
mbed_official | 146:f64d43ff0c18 | 4911 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4912 | //! @brief Set the CTOE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4913 | #define BW_SDHC_FEVT_CTOE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CTOE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4914 | #endif |
mbed_official | 146:f64d43ff0c18 | 4915 | //@} |
mbed_official | 146:f64d43ff0c18 | 4916 | |
mbed_official | 146:f64d43ff0c18 | 4917 | /*! |
mbed_official | 146:f64d43ff0c18 | 4918 | * @name Register SDHC_FEVT, field CCE[17] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 4919 | * |
mbed_official | 146:f64d43ff0c18 | 4920 | * Forces IRQSTAT[CCE] to be set. |
mbed_official | 146:f64d43ff0c18 | 4921 | */ |
mbed_official | 146:f64d43ff0c18 | 4922 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4923 | #define BP_SDHC_FEVT_CCE (17U) //!< Bit position for SDHC_FEVT_CCE. |
mbed_official | 146:f64d43ff0c18 | 4924 | #define BM_SDHC_FEVT_CCE (0x00020000U) //!< Bit mask for SDHC_FEVT_CCE. |
mbed_official | 146:f64d43ff0c18 | 4925 | #define BS_SDHC_FEVT_CCE (1U) //!< Bit field size in bits for SDHC_FEVT_CCE. |
mbed_official | 146:f64d43ff0c18 | 4926 | |
mbed_official | 146:f64d43ff0c18 | 4927 | //! @brief Format value for bitfield SDHC_FEVT_CCE. |
mbed_official | 146:f64d43ff0c18 | 4928 | #define BF_SDHC_FEVT_CCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CCE), uint32_t) & BM_SDHC_FEVT_CCE) |
mbed_official | 146:f64d43ff0c18 | 4929 | |
mbed_official | 146:f64d43ff0c18 | 4930 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4931 | //! @brief Set the CCE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4932 | #define BW_SDHC_FEVT_CCE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CCE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4933 | #endif |
mbed_official | 146:f64d43ff0c18 | 4934 | //@} |
mbed_official | 146:f64d43ff0c18 | 4935 | |
mbed_official | 146:f64d43ff0c18 | 4936 | /*! |
mbed_official | 146:f64d43ff0c18 | 4937 | * @name Register SDHC_FEVT, field CEBE[18] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 4938 | * |
mbed_official | 146:f64d43ff0c18 | 4939 | * Forces IRQSTAT[CEBE] to be set. |
mbed_official | 146:f64d43ff0c18 | 4940 | */ |
mbed_official | 146:f64d43ff0c18 | 4941 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4942 | #define BP_SDHC_FEVT_CEBE (18U) //!< Bit position for SDHC_FEVT_CEBE. |
mbed_official | 146:f64d43ff0c18 | 4943 | #define BM_SDHC_FEVT_CEBE (0x00040000U) //!< Bit mask for SDHC_FEVT_CEBE. |
mbed_official | 146:f64d43ff0c18 | 4944 | #define BS_SDHC_FEVT_CEBE (1U) //!< Bit field size in bits for SDHC_FEVT_CEBE. |
mbed_official | 146:f64d43ff0c18 | 4945 | |
mbed_official | 146:f64d43ff0c18 | 4946 | //! @brief Format value for bitfield SDHC_FEVT_CEBE. |
mbed_official | 146:f64d43ff0c18 | 4947 | #define BF_SDHC_FEVT_CEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CEBE), uint32_t) & BM_SDHC_FEVT_CEBE) |
mbed_official | 146:f64d43ff0c18 | 4948 | |
mbed_official | 146:f64d43ff0c18 | 4949 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4950 | //! @brief Set the CEBE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4951 | #define BW_SDHC_FEVT_CEBE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CEBE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4952 | #endif |
mbed_official | 146:f64d43ff0c18 | 4953 | //@} |
mbed_official | 146:f64d43ff0c18 | 4954 | |
mbed_official | 146:f64d43ff0c18 | 4955 | /*! |
mbed_official | 146:f64d43ff0c18 | 4956 | * @name Register SDHC_FEVT, field CIE[19] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 4957 | * |
mbed_official | 146:f64d43ff0c18 | 4958 | * Forces IRQSTAT[CCE] to be set. |
mbed_official | 146:f64d43ff0c18 | 4959 | */ |
mbed_official | 146:f64d43ff0c18 | 4960 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4961 | #define BP_SDHC_FEVT_CIE (19U) //!< Bit position for SDHC_FEVT_CIE. |
mbed_official | 146:f64d43ff0c18 | 4962 | #define BM_SDHC_FEVT_CIE (0x00080000U) //!< Bit mask for SDHC_FEVT_CIE. |
mbed_official | 146:f64d43ff0c18 | 4963 | #define BS_SDHC_FEVT_CIE (1U) //!< Bit field size in bits for SDHC_FEVT_CIE. |
mbed_official | 146:f64d43ff0c18 | 4964 | |
mbed_official | 146:f64d43ff0c18 | 4965 | //! @brief Format value for bitfield SDHC_FEVT_CIE. |
mbed_official | 146:f64d43ff0c18 | 4966 | #define BF_SDHC_FEVT_CIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CIE), uint32_t) & BM_SDHC_FEVT_CIE) |
mbed_official | 146:f64d43ff0c18 | 4967 | |
mbed_official | 146:f64d43ff0c18 | 4968 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4969 | //! @brief Set the CIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4970 | #define BW_SDHC_FEVT_CIE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4971 | #endif |
mbed_official | 146:f64d43ff0c18 | 4972 | //@} |
mbed_official | 146:f64d43ff0c18 | 4973 | |
mbed_official | 146:f64d43ff0c18 | 4974 | /*! |
mbed_official | 146:f64d43ff0c18 | 4975 | * @name Register SDHC_FEVT, field DTOE[20] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 4976 | * |
mbed_official | 146:f64d43ff0c18 | 4977 | * Forces IRQSTAT[DTOE] to be set. |
mbed_official | 146:f64d43ff0c18 | 4978 | */ |
mbed_official | 146:f64d43ff0c18 | 4979 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4980 | #define BP_SDHC_FEVT_DTOE (20U) //!< Bit position for SDHC_FEVT_DTOE. |
mbed_official | 146:f64d43ff0c18 | 4981 | #define BM_SDHC_FEVT_DTOE (0x00100000U) //!< Bit mask for SDHC_FEVT_DTOE. |
mbed_official | 146:f64d43ff0c18 | 4982 | #define BS_SDHC_FEVT_DTOE (1U) //!< Bit field size in bits for SDHC_FEVT_DTOE. |
mbed_official | 146:f64d43ff0c18 | 4983 | |
mbed_official | 146:f64d43ff0c18 | 4984 | //! @brief Format value for bitfield SDHC_FEVT_DTOE. |
mbed_official | 146:f64d43ff0c18 | 4985 | #define BF_SDHC_FEVT_DTOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_DTOE), uint32_t) & BM_SDHC_FEVT_DTOE) |
mbed_official | 146:f64d43ff0c18 | 4986 | |
mbed_official | 146:f64d43ff0c18 | 4987 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4988 | //! @brief Set the DTOE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4989 | #define BW_SDHC_FEVT_DTOE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_DTOE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4990 | #endif |
mbed_official | 146:f64d43ff0c18 | 4991 | //@} |
mbed_official | 146:f64d43ff0c18 | 4992 | |
mbed_official | 146:f64d43ff0c18 | 4993 | /*! |
mbed_official | 146:f64d43ff0c18 | 4994 | * @name Register SDHC_FEVT, field DCE[21] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 4995 | * |
mbed_official | 146:f64d43ff0c18 | 4996 | * Forces IRQSTAT[DCE] to be set. |
mbed_official | 146:f64d43ff0c18 | 4997 | */ |
mbed_official | 146:f64d43ff0c18 | 4998 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4999 | #define BP_SDHC_FEVT_DCE (21U) //!< Bit position for SDHC_FEVT_DCE. |
mbed_official | 146:f64d43ff0c18 | 5000 | #define BM_SDHC_FEVT_DCE (0x00200000U) //!< Bit mask for SDHC_FEVT_DCE. |
mbed_official | 146:f64d43ff0c18 | 5001 | #define BS_SDHC_FEVT_DCE (1U) //!< Bit field size in bits for SDHC_FEVT_DCE. |
mbed_official | 146:f64d43ff0c18 | 5002 | |
mbed_official | 146:f64d43ff0c18 | 5003 | //! @brief Format value for bitfield SDHC_FEVT_DCE. |
mbed_official | 146:f64d43ff0c18 | 5004 | #define BF_SDHC_FEVT_DCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_DCE), uint32_t) & BM_SDHC_FEVT_DCE) |
mbed_official | 146:f64d43ff0c18 | 5005 | |
mbed_official | 146:f64d43ff0c18 | 5006 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5007 | //! @brief Set the DCE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5008 | #define BW_SDHC_FEVT_DCE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_DCE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5009 | #endif |
mbed_official | 146:f64d43ff0c18 | 5010 | //@} |
mbed_official | 146:f64d43ff0c18 | 5011 | |
mbed_official | 146:f64d43ff0c18 | 5012 | /*! |
mbed_official | 146:f64d43ff0c18 | 5013 | * @name Register SDHC_FEVT, field DEBE[22] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 5014 | * |
mbed_official | 146:f64d43ff0c18 | 5015 | * Forces IRQSTAT[DEBE] to be set. |
mbed_official | 146:f64d43ff0c18 | 5016 | */ |
mbed_official | 146:f64d43ff0c18 | 5017 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5018 | #define BP_SDHC_FEVT_DEBE (22U) //!< Bit position for SDHC_FEVT_DEBE. |
mbed_official | 146:f64d43ff0c18 | 5019 | #define BM_SDHC_FEVT_DEBE (0x00400000U) //!< Bit mask for SDHC_FEVT_DEBE. |
mbed_official | 146:f64d43ff0c18 | 5020 | #define BS_SDHC_FEVT_DEBE (1U) //!< Bit field size in bits for SDHC_FEVT_DEBE. |
mbed_official | 146:f64d43ff0c18 | 5021 | |
mbed_official | 146:f64d43ff0c18 | 5022 | //! @brief Format value for bitfield SDHC_FEVT_DEBE. |
mbed_official | 146:f64d43ff0c18 | 5023 | #define BF_SDHC_FEVT_DEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_DEBE), uint32_t) & BM_SDHC_FEVT_DEBE) |
mbed_official | 146:f64d43ff0c18 | 5024 | |
mbed_official | 146:f64d43ff0c18 | 5025 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5026 | //! @brief Set the DEBE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5027 | #define BW_SDHC_FEVT_DEBE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_DEBE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5028 | #endif |
mbed_official | 146:f64d43ff0c18 | 5029 | //@} |
mbed_official | 146:f64d43ff0c18 | 5030 | |
mbed_official | 146:f64d43ff0c18 | 5031 | /*! |
mbed_official | 146:f64d43ff0c18 | 5032 | * @name Register SDHC_FEVT, field AC12E[24] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 5033 | * |
mbed_official | 146:f64d43ff0c18 | 5034 | * Forces IRQSTAT[AC12E] to be set. |
mbed_official | 146:f64d43ff0c18 | 5035 | */ |
mbed_official | 146:f64d43ff0c18 | 5036 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5037 | #define BP_SDHC_FEVT_AC12E (24U) //!< Bit position for SDHC_FEVT_AC12E. |
mbed_official | 146:f64d43ff0c18 | 5038 | #define BM_SDHC_FEVT_AC12E (0x01000000U) //!< Bit mask for SDHC_FEVT_AC12E. |
mbed_official | 146:f64d43ff0c18 | 5039 | #define BS_SDHC_FEVT_AC12E (1U) //!< Bit field size in bits for SDHC_FEVT_AC12E. |
mbed_official | 146:f64d43ff0c18 | 5040 | |
mbed_official | 146:f64d43ff0c18 | 5041 | //! @brief Format value for bitfield SDHC_FEVT_AC12E. |
mbed_official | 146:f64d43ff0c18 | 5042 | #define BF_SDHC_FEVT_AC12E(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12E), uint32_t) & BM_SDHC_FEVT_AC12E) |
mbed_official | 146:f64d43ff0c18 | 5043 | |
mbed_official | 146:f64d43ff0c18 | 5044 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5045 | //! @brief Set the AC12E field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5046 | #define BW_SDHC_FEVT_AC12E(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12E) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5047 | #endif |
mbed_official | 146:f64d43ff0c18 | 5048 | //@} |
mbed_official | 146:f64d43ff0c18 | 5049 | |
mbed_official | 146:f64d43ff0c18 | 5050 | /*! |
mbed_official | 146:f64d43ff0c18 | 5051 | * @name Register SDHC_FEVT, field DMAE[28] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 5052 | * |
mbed_official | 146:f64d43ff0c18 | 5053 | * Forces the DMAE bit of Interrupt Status Register to be set. |
mbed_official | 146:f64d43ff0c18 | 5054 | */ |
mbed_official | 146:f64d43ff0c18 | 5055 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5056 | #define BP_SDHC_FEVT_DMAE (28U) //!< Bit position for SDHC_FEVT_DMAE. |
mbed_official | 146:f64d43ff0c18 | 5057 | #define BM_SDHC_FEVT_DMAE (0x10000000U) //!< Bit mask for SDHC_FEVT_DMAE. |
mbed_official | 146:f64d43ff0c18 | 5058 | #define BS_SDHC_FEVT_DMAE (1U) //!< Bit field size in bits for SDHC_FEVT_DMAE. |
mbed_official | 146:f64d43ff0c18 | 5059 | |
mbed_official | 146:f64d43ff0c18 | 5060 | //! @brief Format value for bitfield SDHC_FEVT_DMAE. |
mbed_official | 146:f64d43ff0c18 | 5061 | #define BF_SDHC_FEVT_DMAE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_DMAE), uint32_t) & BM_SDHC_FEVT_DMAE) |
mbed_official | 146:f64d43ff0c18 | 5062 | |
mbed_official | 146:f64d43ff0c18 | 5063 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5064 | //! @brief Set the DMAE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5065 | #define BW_SDHC_FEVT_DMAE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_DMAE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5066 | #endif |
mbed_official | 146:f64d43ff0c18 | 5067 | //@} |
mbed_official | 146:f64d43ff0c18 | 5068 | |
mbed_official | 146:f64d43ff0c18 | 5069 | /*! |
mbed_official | 146:f64d43ff0c18 | 5070 | * @name Register SDHC_FEVT, field CINT[31] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 5071 | * |
mbed_official | 146:f64d43ff0c18 | 5072 | * Writing 1 to this bit generates a short low-level pulse on the internal |
mbed_official | 146:f64d43ff0c18 | 5073 | * DAT[1] line, as if a self-clearing interrupt was received from the external card. |
mbed_official | 146:f64d43ff0c18 | 5074 | * If enabled, the CINT bit will be set and the interrupt service routine may |
mbed_official | 146:f64d43ff0c18 | 5075 | * treat this interrupt as a normal interrupt from the external card. |
mbed_official | 146:f64d43ff0c18 | 5076 | */ |
mbed_official | 146:f64d43ff0c18 | 5077 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5078 | #define BP_SDHC_FEVT_CINT (31U) //!< Bit position for SDHC_FEVT_CINT. |
mbed_official | 146:f64d43ff0c18 | 5079 | #define BM_SDHC_FEVT_CINT (0x80000000U) //!< Bit mask for SDHC_FEVT_CINT. |
mbed_official | 146:f64d43ff0c18 | 5080 | #define BS_SDHC_FEVT_CINT (1U) //!< Bit field size in bits for SDHC_FEVT_CINT. |
mbed_official | 146:f64d43ff0c18 | 5081 | |
mbed_official | 146:f64d43ff0c18 | 5082 | //! @brief Format value for bitfield SDHC_FEVT_CINT. |
mbed_official | 146:f64d43ff0c18 | 5083 | #define BF_SDHC_FEVT_CINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CINT), uint32_t) & BM_SDHC_FEVT_CINT) |
mbed_official | 146:f64d43ff0c18 | 5084 | |
mbed_official | 146:f64d43ff0c18 | 5085 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5086 | //! @brief Set the CINT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5087 | #define BW_SDHC_FEVT_CINT(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CINT) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5088 | #endif |
mbed_official | 146:f64d43ff0c18 | 5089 | //@} |
mbed_official | 146:f64d43ff0c18 | 5090 | |
mbed_official | 146:f64d43ff0c18 | 5091 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 5092 | // HW_SDHC_ADMAES - ADMA Error Status register |
mbed_official | 146:f64d43ff0c18 | 5093 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 5094 | |
mbed_official | 146:f64d43ff0c18 | 5095 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5096 | /*! |
mbed_official | 146:f64d43ff0c18 | 5097 | * @brief HW_SDHC_ADMAES - ADMA Error Status register (RO) |
mbed_official | 146:f64d43ff0c18 | 5098 | * |
mbed_official | 146:f64d43ff0c18 | 5099 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 5100 | * |
mbed_official | 146:f64d43ff0c18 | 5101 | * When an ADMA error interrupt has occurred, the ADMA Error States field in |
mbed_official | 146:f64d43ff0c18 | 5102 | * this register holds the ADMA state and the ADMA System Address register holds the |
mbed_official | 146:f64d43ff0c18 | 5103 | * address around the error descriptor. For recovering from this error, the host |
mbed_official | 146:f64d43ff0c18 | 5104 | * driver requires the ADMA state to identify the error descriptor address as |
mbed_official | 146:f64d43ff0c18 | 5105 | * follows: ST_STOP: Previous location set in the ADMA System Address register is |
mbed_official | 146:f64d43ff0c18 | 5106 | * the error descriptor address. ST_FDS: Current location set in the ADMA System |
mbed_official | 146:f64d43ff0c18 | 5107 | * Address register is the error descriptor address. ST_CADR: This state is never |
mbed_official | 146:f64d43ff0c18 | 5108 | * set because it only increments the descriptor pointer and doesn't generate an |
mbed_official | 146:f64d43ff0c18 | 5109 | * ADMA error. ST_TFR: Previous location set in the ADMA System Address register |
mbed_official | 146:f64d43ff0c18 | 5110 | * is the error descriptor address. In case of a write operation, the host driver |
mbed_official | 146:f64d43ff0c18 | 5111 | * must use the ACMD22 to get the number of the written block, rather than using |
mbed_official | 146:f64d43ff0c18 | 5112 | * this information, because unwritten data may exist in the host controller. |
mbed_official | 146:f64d43ff0c18 | 5113 | * The host controller generates the ADMA error interrupt when it detects invalid |
mbed_official | 146:f64d43ff0c18 | 5114 | * descriptor data (valid = 0) in the ST_FDS state. The host driver can |
mbed_official | 146:f64d43ff0c18 | 5115 | * distinguish this error by reading the valid bit of the error descriptor. ADMA Error |
mbed_official | 146:f64d43ff0c18 | 5116 | * State coding D01-D00 ADMA Error State when error has occurred Contents of ADMA |
mbed_official | 146:f64d43ff0c18 | 5117 | * System Address register 00 ST_STOP (Stop DMA) Holds the address of the next |
mbed_official | 146:f64d43ff0c18 | 5118 | * executable descriptor command 01 ST_FDS (fetch descriptor) Holds the valid |
mbed_official | 146:f64d43ff0c18 | 5119 | * descriptor address 10 ST_CADR (change address) No ADMA error is generated 11 ST_TFR |
mbed_official | 146:f64d43ff0c18 | 5120 | * (Transfer Data) Holds the address of the next executable descriptor command |
mbed_official | 146:f64d43ff0c18 | 5121 | */ |
mbed_official | 146:f64d43ff0c18 | 5122 | typedef union _hw_sdhc_admaes |
mbed_official | 146:f64d43ff0c18 | 5123 | { |
mbed_official | 146:f64d43ff0c18 | 5124 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 5125 | struct _hw_sdhc_admaes_bitfields |
mbed_official | 146:f64d43ff0c18 | 5126 | { |
mbed_official | 146:f64d43ff0c18 | 5127 | uint32_t ADMAES : 2; //!< [1:0] ADMA Error State (When ADMA Error Is |
mbed_official | 146:f64d43ff0c18 | 5128 | //! Occurred.) |
mbed_official | 146:f64d43ff0c18 | 5129 | uint32_t ADMALME : 1; //!< [2] ADMA Length Mismatch Error |
mbed_official | 146:f64d43ff0c18 | 5130 | uint32_t ADMADCE : 1; //!< [3] ADMA Descriptor Error |
mbed_official | 146:f64d43ff0c18 | 5131 | uint32_t RESERVED0 : 28; //!< [31:4] |
mbed_official | 146:f64d43ff0c18 | 5132 | } B; |
mbed_official | 146:f64d43ff0c18 | 5133 | } hw_sdhc_admaes_t; |
mbed_official | 146:f64d43ff0c18 | 5134 | #endif |
mbed_official | 146:f64d43ff0c18 | 5135 | |
mbed_official | 146:f64d43ff0c18 | 5136 | /*! |
mbed_official | 146:f64d43ff0c18 | 5137 | * @name Constants and macros for entire SDHC_ADMAES register |
mbed_official | 146:f64d43ff0c18 | 5138 | */ |
mbed_official | 146:f64d43ff0c18 | 5139 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5140 | #define HW_SDHC_ADMAES_ADDR (REGS_SDHC_BASE + 0x54U) |
mbed_official | 146:f64d43ff0c18 | 5141 | |
mbed_official | 146:f64d43ff0c18 | 5142 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5143 | #define HW_SDHC_ADMAES (*(__I hw_sdhc_admaes_t *) HW_SDHC_ADMAES_ADDR) |
mbed_official | 146:f64d43ff0c18 | 5144 | #define HW_SDHC_ADMAES_RD() (HW_SDHC_ADMAES.U) |
mbed_official | 146:f64d43ff0c18 | 5145 | #endif |
mbed_official | 146:f64d43ff0c18 | 5146 | //@} |
mbed_official | 146:f64d43ff0c18 | 5147 | |
mbed_official | 146:f64d43ff0c18 | 5148 | /* |
mbed_official | 146:f64d43ff0c18 | 5149 | * Constants & macros for individual SDHC_ADMAES bitfields |
mbed_official | 146:f64d43ff0c18 | 5150 | */ |
mbed_official | 146:f64d43ff0c18 | 5151 | |
mbed_official | 146:f64d43ff0c18 | 5152 | /*! |
mbed_official | 146:f64d43ff0c18 | 5153 | * @name Register SDHC_ADMAES, field ADMAES[1:0] (RO) |
mbed_official | 146:f64d43ff0c18 | 5154 | * |
mbed_official | 146:f64d43ff0c18 | 5155 | * Indicates the state of the ADMA when an error has occurred during an ADMA |
mbed_official | 146:f64d43ff0c18 | 5156 | * data transfer. |
mbed_official | 146:f64d43ff0c18 | 5157 | */ |
mbed_official | 146:f64d43ff0c18 | 5158 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5159 | #define BP_SDHC_ADMAES_ADMAES (0U) //!< Bit position for SDHC_ADMAES_ADMAES. |
mbed_official | 146:f64d43ff0c18 | 5160 | #define BM_SDHC_ADMAES_ADMAES (0x00000003U) //!< Bit mask for SDHC_ADMAES_ADMAES. |
mbed_official | 146:f64d43ff0c18 | 5161 | #define BS_SDHC_ADMAES_ADMAES (2U) //!< Bit field size in bits for SDHC_ADMAES_ADMAES. |
mbed_official | 146:f64d43ff0c18 | 5162 | |
mbed_official | 146:f64d43ff0c18 | 5163 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5164 | //! @brief Read current value of the SDHC_ADMAES_ADMAES field. |
mbed_official | 146:f64d43ff0c18 | 5165 | #define BR_SDHC_ADMAES_ADMAES (HW_SDHC_ADMAES.B.ADMAES) |
mbed_official | 146:f64d43ff0c18 | 5166 | #endif |
mbed_official | 146:f64d43ff0c18 | 5167 | //@} |
mbed_official | 146:f64d43ff0c18 | 5168 | |
mbed_official | 146:f64d43ff0c18 | 5169 | /*! |
mbed_official | 146:f64d43ff0c18 | 5170 | * @name Register SDHC_ADMAES, field ADMALME[2] (RO) |
mbed_official | 146:f64d43ff0c18 | 5171 | * |
mbed_official | 146:f64d43ff0c18 | 5172 | * This error occurs in the following 2 cases: While the block count enable is |
mbed_official | 146:f64d43ff0c18 | 5173 | * being set, the total data length specified by the descriptor table is different |
mbed_official | 146:f64d43ff0c18 | 5174 | * from that specified by the block count and block length. Total data length |
mbed_official | 146:f64d43ff0c18 | 5175 | * can not be divided by the block length. |
mbed_official | 146:f64d43ff0c18 | 5176 | * |
mbed_official | 146:f64d43ff0c18 | 5177 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5178 | * - 0 - No error. |
mbed_official | 146:f64d43ff0c18 | 5179 | * - 1 - Error. |
mbed_official | 146:f64d43ff0c18 | 5180 | */ |
mbed_official | 146:f64d43ff0c18 | 5181 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5182 | #define BP_SDHC_ADMAES_ADMALME (2U) //!< Bit position for SDHC_ADMAES_ADMALME. |
mbed_official | 146:f64d43ff0c18 | 5183 | #define BM_SDHC_ADMAES_ADMALME (0x00000004U) //!< Bit mask for SDHC_ADMAES_ADMALME. |
mbed_official | 146:f64d43ff0c18 | 5184 | #define BS_SDHC_ADMAES_ADMALME (1U) //!< Bit field size in bits for SDHC_ADMAES_ADMALME. |
mbed_official | 146:f64d43ff0c18 | 5185 | |
mbed_official | 146:f64d43ff0c18 | 5186 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5187 | //! @brief Read current value of the SDHC_ADMAES_ADMALME field. |
mbed_official | 146:f64d43ff0c18 | 5188 | #define BR_SDHC_ADMAES_ADMALME (BITBAND_ACCESS32(HW_SDHC_ADMAES_ADDR, BP_SDHC_ADMAES_ADMALME)) |
mbed_official | 146:f64d43ff0c18 | 5189 | #endif |
mbed_official | 146:f64d43ff0c18 | 5190 | //@} |
mbed_official | 146:f64d43ff0c18 | 5191 | |
mbed_official | 146:f64d43ff0c18 | 5192 | /*! |
mbed_official | 146:f64d43ff0c18 | 5193 | * @name Register SDHC_ADMAES, field ADMADCE[3] (RO) |
mbed_official | 146:f64d43ff0c18 | 5194 | * |
mbed_official | 146:f64d43ff0c18 | 5195 | * This error occurs when an invalid descriptor is fetched by ADMA. |
mbed_official | 146:f64d43ff0c18 | 5196 | * |
mbed_official | 146:f64d43ff0c18 | 5197 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5198 | * - 0 - No error. |
mbed_official | 146:f64d43ff0c18 | 5199 | * - 1 - Error. |
mbed_official | 146:f64d43ff0c18 | 5200 | */ |
mbed_official | 146:f64d43ff0c18 | 5201 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5202 | #define BP_SDHC_ADMAES_ADMADCE (3U) //!< Bit position for SDHC_ADMAES_ADMADCE. |
mbed_official | 146:f64d43ff0c18 | 5203 | #define BM_SDHC_ADMAES_ADMADCE (0x00000008U) //!< Bit mask for SDHC_ADMAES_ADMADCE. |
mbed_official | 146:f64d43ff0c18 | 5204 | #define BS_SDHC_ADMAES_ADMADCE (1U) //!< Bit field size in bits for SDHC_ADMAES_ADMADCE. |
mbed_official | 146:f64d43ff0c18 | 5205 | |
mbed_official | 146:f64d43ff0c18 | 5206 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5207 | //! @brief Read current value of the SDHC_ADMAES_ADMADCE field. |
mbed_official | 146:f64d43ff0c18 | 5208 | #define BR_SDHC_ADMAES_ADMADCE (BITBAND_ACCESS32(HW_SDHC_ADMAES_ADDR, BP_SDHC_ADMAES_ADMADCE)) |
mbed_official | 146:f64d43ff0c18 | 5209 | #endif |
mbed_official | 146:f64d43ff0c18 | 5210 | //@} |
mbed_official | 146:f64d43ff0c18 | 5211 | |
mbed_official | 146:f64d43ff0c18 | 5212 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 5213 | // HW_SDHC_ADSADDR - ADMA System Addressregister |
mbed_official | 146:f64d43ff0c18 | 5214 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 5215 | |
mbed_official | 146:f64d43ff0c18 | 5216 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5217 | /*! |
mbed_official | 146:f64d43ff0c18 | 5218 | * @brief HW_SDHC_ADSADDR - ADMA System Addressregister (RW) |
mbed_official | 146:f64d43ff0c18 | 5219 | * |
mbed_official | 146:f64d43ff0c18 | 5220 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 5221 | * |
mbed_official | 146:f64d43ff0c18 | 5222 | * This register contains the physical system memory address used for ADMA |
mbed_official | 146:f64d43ff0c18 | 5223 | * transfers. |
mbed_official | 146:f64d43ff0c18 | 5224 | */ |
mbed_official | 146:f64d43ff0c18 | 5225 | typedef union _hw_sdhc_adsaddr |
mbed_official | 146:f64d43ff0c18 | 5226 | { |
mbed_official | 146:f64d43ff0c18 | 5227 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 5228 | struct _hw_sdhc_adsaddr_bitfields |
mbed_official | 146:f64d43ff0c18 | 5229 | { |
mbed_official | 146:f64d43ff0c18 | 5230 | uint32_t RESERVED0 : 2; //!< [1:0] |
mbed_official | 146:f64d43ff0c18 | 5231 | uint32_t ADSADDR : 30; //!< [31:2] ADMA System Address |
mbed_official | 146:f64d43ff0c18 | 5232 | } B; |
mbed_official | 146:f64d43ff0c18 | 5233 | } hw_sdhc_adsaddr_t; |
mbed_official | 146:f64d43ff0c18 | 5234 | #endif |
mbed_official | 146:f64d43ff0c18 | 5235 | |
mbed_official | 146:f64d43ff0c18 | 5236 | /*! |
mbed_official | 146:f64d43ff0c18 | 5237 | * @name Constants and macros for entire SDHC_ADSADDR register |
mbed_official | 146:f64d43ff0c18 | 5238 | */ |
mbed_official | 146:f64d43ff0c18 | 5239 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5240 | #define HW_SDHC_ADSADDR_ADDR (REGS_SDHC_BASE + 0x58U) |
mbed_official | 146:f64d43ff0c18 | 5241 | |
mbed_official | 146:f64d43ff0c18 | 5242 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5243 | #define HW_SDHC_ADSADDR (*(__IO hw_sdhc_adsaddr_t *) HW_SDHC_ADSADDR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 5244 | #define HW_SDHC_ADSADDR_RD() (HW_SDHC_ADSADDR.U) |
mbed_official | 146:f64d43ff0c18 | 5245 | #define HW_SDHC_ADSADDR_WR(v) (HW_SDHC_ADSADDR.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 5246 | #define HW_SDHC_ADSADDR_SET(v) (HW_SDHC_ADSADDR_WR(HW_SDHC_ADSADDR_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 5247 | #define HW_SDHC_ADSADDR_CLR(v) (HW_SDHC_ADSADDR_WR(HW_SDHC_ADSADDR_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 5248 | #define HW_SDHC_ADSADDR_TOG(v) (HW_SDHC_ADSADDR_WR(HW_SDHC_ADSADDR_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 5249 | #endif |
mbed_official | 146:f64d43ff0c18 | 5250 | //@} |
mbed_official | 146:f64d43ff0c18 | 5251 | |
mbed_official | 146:f64d43ff0c18 | 5252 | /* |
mbed_official | 146:f64d43ff0c18 | 5253 | * Constants & macros for individual SDHC_ADSADDR bitfields |
mbed_official | 146:f64d43ff0c18 | 5254 | */ |
mbed_official | 146:f64d43ff0c18 | 5255 | |
mbed_official | 146:f64d43ff0c18 | 5256 | /*! |
mbed_official | 146:f64d43ff0c18 | 5257 | * @name Register SDHC_ADSADDR, field ADSADDR[31:2] (RW) |
mbed_official | 146:f64d43ff0c18 | 5258 | * |
mbed_official | 146:f64d43ff0c18 | 5259 | * Holds the word address of the executing command in the descriptor table. At |
mbed_official | 146:f64d43ff0c18 | 5260 | * the start of ADMA, the host driver shall set the start address of the |
mbed_official | 146:f64d43ff0c18 | 5261 | * Descriptor table. The ADMA engine increments this register address whenever fetching a |
mbed_official | 146:f64d43ff0c18 | 5262 | * descriptor command. When the ADMA is stopped at the block gap, this register |
mbed_official | 146:f64d43ff0c18 | 5263 | * indicates the address of the next executable descriptor command. When the ADMA |
mbed_official | 146:f64d43ff0c18 | 5264 | * error interrupt is generated, this register shall hold the valid descriptor |
mbed_official | 146:f64d43ff0c18 | 5265 | * address depending on the ADMA state. The lower 2 bits of this register is tied |
mbed_official | 146:f64d43ff0c18 | 5266 | * to '0' so the ADMA address is always word-aligned. Because this register |
mbed_official | 146:f64d43ff0c18 | 5267 | * supports dynamic address reflecting, when TC bit is set, it automatically alters the |
mbed_official | 146:f64d43ff0c18 | 5268 | * value of internal address counter, so SW cannot change this register when TC |
mbed_official | 146:f64d43ff0c18 | 5269 | * bit is set. |
mbed_official | 146:f64d43ff0c18 | 5270 | */ |
mbed_official | 146:f64d43ff0c18 | 5271 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5272 | #define BP_SDHC_ADSADDR_ADSADDR (2U) //!< Bit position for SDHC_ADSADDR_ADSADDR. |
mbed_official | 146:f64d43ff0c18 | 5273 | #define BM_SDHC_ADSADDR_ADSADDR (0xFFFFFFFCU) //!< Bit mask for SDHC_ADSADDR_ADSADDR. |
mbed_official | 146:f64d43ff0c18 | 5274 | #define BS_SDHC_ADSADDR_ADSADDR (30U) //!< Bit field size in bits for SDHC_ADSADDR_ADSADDR. |
mbed_official | 146:f64d43ff0c18 | 5275 | |
mbed_official | 146:f64d43ff0c18 | 5276 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5277 | //! @brief Read current value of the SDHC_ADSADDR_ADSADDR field. |
mbed_official | 146:f64d43ff0c18 | 5278 | #define BR_SDHC_ADSADDR_ADSADDR (HW_SDHC_ADSADDR.B.ADSADDR) |
mbed_official | 146:f64d43ff0c18 | 5279 | #endif |
mbed_official | 146:f64d43ff0c18 | 5280 | |
mbed_official | 146:f64d43ff0c18 | 5281 | //! @brief Format value for bitfield SDHC_ADSADDR_ADSADDR. |
mbed_official | 146:f64d43ff0c18 | 5282 | #define BF_SDHC_ADSADDR_ADSADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_ADSADDR_ADSADDR), uint32_t) & BM_SDHC_ADSADDR_ADSADDR) |
mbed_official | 146:f64d43ff0c18 | 5283 | |
mbed_official | 146:f64d43ff0c18 | 5284 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5285 | //! @brief Set the ADSADDR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5286 | #define BW_SDHC_ADSADDR_ADSADDR(v) (HW_SDHC_ADSADDR_WR((HW_SDHC_ADSADDR_RD() & ~BM_SDHC_ADSADDR_ADSADDR) | BF_SDHC_ADSADDR_ADSADDR(v))) |
mbed_official | 146:f64d43ff0c18 | 5287 | #endif |
mbed_official | 146:f64d43ff0c18 | 5288 | //@} |
mbed_official | 146:f64d43ff0c18 | 5289 | |
mbed_official | 146:f64d43ff0c18 | 5290 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 5291 | // HW_SDHC_VENDOR - Vendor Specific register |
mbed_official | 146:f64d43ff0c18 | 5292 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 5293 | |
mbed_official | 146:f64d43ff0c18 | 5294 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5295 | /*! |
mbed_official | 146:f64d43ff0c18 | 5296 | * @brief HW_SDHC_VENDOR - Vendor Specific register (RW) |
mbed_official | 146:f64d43ff0c18 | 5297 | * |
mbed_official | 146:f64d43ff0c18 | 5298 | * Reset value: 0x00000001U |
mbed_official | 146:f64d43ff0c18 | 5299 | * |
mbed_official | 146:f64d43ff0c18 | 5300 | * This register contains the vendor-specific control/status register. |
mbed_official | 146:f64d43ff0c18 | 5301 | */ |
mbed_official | 146:f64d43ff0c18 | 5302 | typedef union _hw_sdhc_vendor |
mbed_official | 146:f64d43ff0c18 | 5303 | { |
mbed_official | 146:f64d43ff0c18 | 5304 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 5305 | struct _hw_sdhc_vendor_bitfields |
mbed_official | 146:f64d43ff0c18 | 5306 | { |
mbed_official | 146:f64d43ff0c18 | 5307 | uint32_t EXTDMAEN : 1; //!< [0] External DMA Request Enable |
mbed_official | 146:f64d43ff0c18 | 5308 | uint32_t EXBLKNU : 1; //!< [1] Exact Block Number Block Read Enable |
mbed_official | 146:f64d43ff0c18 | 5309 | //! For SDIO CMD53 |
mbed_official | 146:f64d43ff0c18 | 5310 | uint32_t RESERVED0 : 14; //!< [15:2] |
mbed_official | 146:f64d43ff0c18 | 5311 | uint32_t INTSTVAL : 8; //!< [23:16] Internal State Value |
mbed_official | 146:f64d43ff0c18 | 5312 | uint32_t RESERVED1 : 8; //!< [31:24] |
mbed_official | 146:f64d43ff0c18 | 5313 | } B; |
mbed_official | 146:f64d43ff0c18 | 5314 | } hw_sdhc_vendor_t; |
mbed_official | 146:f64d43ff0c18 | 5315 | #endif |
mbed_official | 146:f64d43ff0c18 | 5316 | |
mbed_official | 146:f64d43ff0c18 | 5317 | /*! |
mbed_official | 146:f64d43ff0c18 | 5318 | * @name Constants and macros for entire SDHC_VENDOR register |
mbed_official | 146:f64d43ff0c18 | 5319 | */ |
mbed_official | 146:f64d43ff0c18 | 5320 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5321 | #define HW_SDHC_VENDOR_ADDR (REGS_SDHC_BASE + 0xC0U) |
mbed_official | 146:f64d43ff0c18 | 5322 | |
mbed_official | 146:f64d43ff0c18 | 5323 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5324 | #define HW_SDHC_VENDOR (*(__IO hw_sdhc_vendor_t *) HW_SDHC_VENDOR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 5325 | #define HW_SDHC_VENDOR_RD() (HW_SDHC_VENDOR.U) |
mbed_official | 146:f64d43ff0c18 | 5326 | #define HW_SDHC_VENDOR_WR(v) (HW_SDHC_VENDOR.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 5327 | #define HW_SDHC_VENDOR_SET(v) (HW_SDHC_VENDOR_WR(HW_SDHC_VENDOR_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 5328 | #define HW_SDHC_VENDOR_CLR(v) (HW_SDHC_VENDOR_WR(HW_SDHC_VENDOR_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 5329 | #define HW_SDHC_VENDOR_TOG(v) (HW_SDHC_VENDOR_WR(HW_SDHC_VENDOR_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 5330 | #endif |
mbed_official | 146:f64d43ff0c18 | 5331 | //@} |
mbed_official | 146:f64d43ff0c18 | 5332 | |
mbed_official | 146:f64d43ff0c18 | 5333 | /* |
mbed_official | 146:f64d43ff0c18 | 5334 | * Constants & macros for individual SDHC_VENDOR bitfields |
mbed_official | 146:f64d43ff0c18 | 5335 | */ |
mbed_official | 146:f64d43ff0c18 | 5336 | |
mbed_official | 146:f64d43ff0c18 | 5337 | /*! |
mbed_official | 146:f64d43ff0c18 | 5338 | * @name Register SDHC_VENDOR, field EXTDMAEN[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 5339 | * |
mbed_official | 146:f64d43ff0c18 | 5340 | * Enables the request to external DMA. When the internal DMA (either simple DMA |
mbed_official | 146:f64d43ff0c18 | 5341 | * or advanced DMA) is not in use, and this bit is set, SDHC will send out DMA |
mbed_official | 146:f64d43ff0c18 | 5342 | * request when the internal buffer is ready. This bit is particularly useful when |
mbed_official | 146:f64d43ff0c18 | 5343 | * transferring data by CPU polling mode, and it is not allowed to send out the |
mbed_official | 146:f64d43ff0c18 | 5344 | * external DMA request. By default, this bit is set. |
mbed_official | 146:f64d43ff0c18 | 5345 | * |
mbed_official | 146:f64d43ff0c18 | 5346 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5347 | * - 0 - In any scenario, SDHC does not send out the external DMA request. |
mbed_official | 146:f64d43ff0c18 | 5348 | * - 1 - When internal DMA is not active, the external DMA request will be sent |
mbed_official | 146:f64d43ff0c18 | 5349 | * out. |
mbed_official | 146:f64d43ff0c18 | 5350 | */ |
mbed_official | 146:f64d43ff0c18 | 5351 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5352 | #define BP_SDHC_VENDOR_EXTDMAEN (0U) //!< Bit position for SDHC_VENDOR_EXTDMAEN. |
mbed_official | 146:f64d43ff0c18 | 5353 | #define BM_SDHC_VENDOR_EXTDMAEN (0x00000001U) //!< Bit mask for SDHC_VENDOR_EXTDMAEN. |
mbed_official | 146:f64d43ff0c18 | 5354 | #define BS_SDHC_VENDOR_EXTDMAEN (1U) //!< Bit field size in bits for SDHC_VENDOR_EXTDMAEN. |
mbed_official | 146:f64d43ff0c18 | 5355 | |
mbed_official | 146:f64d43ff0c18 | 5356 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5357 | //! @brief Read current value of the SDHC_VENDOR_EXTDMAEN field. |
mbed_official | 146:f64d43ff0c18 | 5358 | #define BR_SDHC_VENDOR_EXTDMAEN (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR, BP_SDHC_VENDOR_EXTDMAEN)) |
mbed_official | 146:f64d43ff0c18 | 5359 | #endif |
mbed_official | 146:f64d43ff0c18 | 5360 | |
mbed_official | 146:f64d43ff0c18 | 5361 | //! @brief Format value for bitfield SDHC_VENDOR_EXTDMAEN. |
mbed_official | 146:f64d43ff0c18 | 5362 | #define BF_SDHC_VENDOR_EXTDMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_VENDOR_EXTDMAEN), uint32_t) & BM_SDHC_VENDOR_EXTDMAEN) |
mbed_official | 146:f64d43ff0c18 | 5363 | |
mbed_official | 146:f64d43ff0c18 | 5364 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5365 | //! @brief Set the EXTDMAEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5366 | #define BW_SDHC_VENDOR_EXTDMAEN(v) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR, BP_SDHC_VENDOR_EXTDMAEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5367 | #endif |
mbed_official | 146:f64d43ff0c18 | 5368 | //@} |
mbed_official | 146:f64d43ff0c18 | 5369 | |
mbed_official | 146:f64d43ff0c18 | 5370 | /*! |
mbed_official | 146:f64d43ff0c18 | 5371 | * @name Register SDHC_VENDOR, field EXBLKNU[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 5372 | * |
mbed_official | 146:f64d43ff0c18 | 5373 | * This bit must be set before S/W issues CMD53 multi-block read with exact |
mbed_official | 146:f64d43ff0c18 | 5374 | * block number. This bit must not be set if the CMD53 multi-block read is not exact |
mbed_official | 146:f64d43ff0c18 | 5375 | * block number. |
mbed_official | 146:f64d43ff0c18 | 5376 | * |
mbed_official | 146:f64d43ff0c18 | 5377 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5378 | * - 0 - None exact block read. |
mbed_official | 146:f64d43ff0c18 | 5379 | * - 1 - Exact block read for SDIO CMD53. |
mbed_official | 146:f64d43ff0c18 | 5380 | */ |
mbed_official | 146:f64d43ff0c18 | 5381 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5382 | #define BP_SDHC_VENDOR_EXBLKNU (1U) //!< Bit position for SDHC_VENDOR_EXBLKNU. |
mbed_official | 146:f64d43ff0c18 | 5383 | #define BM_SDHC_VENDOR_EXBLKNU (0x00000002U) //!< Bit mask for SDHC_VENDOR_EXBLKNU. |
mbed_official | 146:f64d43ff0c18 | 5384 | #define BS_SDHC_VENDOR_EXBLKNU (1U) //!< Bit field size in bits for SDHC_VENDOR_EXBLKNU. |
mbed_official | 146:f64d43ff0c18 | 5385 | |
mbed_official | 146:f64d43ff0c18 | 5386 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5387 | //! @brief Read current value of the SDHC_VENDOR_EXBLKNU field. |
mbed_official | 146:f64d43ff0c18 | 5388 | #define BR_SDHC_VENDOR_EXBLKNU (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR, BP_SDHC_VENDOR_EXBLKNU)) |
mbed_official | 146:f64d43ff0c18 | 5389 | #endif |
mbed_official | 146:f64d43ff0c18 | 5390 | |
mbed_official | 146:f64d43ff0c18 | 5391 | //! @brief Format value for bitfield SDHC_VENDOR_EXBLKNU. |
mbed_official | 146:f64d43ff0c18 | 5392 | #define BF_SDHC_VENDOR_EXBLKNU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_VENDOR_EXBLKNU), uint32_t) & BM_SDHC_VENDOR_EXBLKNU) |
mbed_official | 146:f64d43ff0c18 | 5393 | |
mbed_official | 146:f64d43ff0c18 | 5394 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5395 | //! @brief Set the EXBLKNU field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5396 | #define BW_SDHC_VENDOR_EXBLKNU(v) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR, BP_SDHC_VENDOR_EXBLKNU) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5397 | #endif |
mbed_official | 146:f64d43ff0c18 | 5398 | //@} |
mbed_official | 146:f64d43ff0c18 | 5399 | |
mbed_official | 146:f64d43ff0c18 | 5400 | /*! |
mbed_official | 146:f64d43ff0c18 | 5401 | * @name Register SDHC_VENDOR, field INTSTVAL[23:16] (RO) |
mbed_official | 146:f64d43ff0c18 | 5402 | * |
mbed_official | 146:f64d43ff0c18 | 5403 | * Internal state value, reflecting the corresponding state value selected by |
mbed_official | 146:f64d43ff0c18 | 5404 | * Debug Select field. This field is read-only and write to this field does not |
mbed_official | 146:f64d43ff0c18 | 5405 | * have effect. |
mbed_official | 146:f64d43ff0c18 | 5406 | */ |
mbed_official | 146:f64d43ff0c18 | 5407 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5408 | #define BP_SDHC_VENDOR_INTSTVAL (16U) //!< Bit position for SDHC_VENDOR_INTSTVAL. |
mbed_official | 146:f64d43ff0c18 | 5409 | #define BM_SDHC_VENDOR_INTSTVAL (0x00FF0000U) //!< Bit mask for SDHC_VENDOR_INTSTVAL. |
mbed_official | 146:f64d43ff0c18 | 5410 | #define BS_SDHC_VENDOR_INTSTVAL (8U) //!< Bit field size in bits for SDHC_VENDOR_INTSTVAL. |
mbed_official | 146:f64d43ff0c18 | 5411 | |
mbed_official | 146:f64d43ff0c18 | 5412 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5413 | //! @brief Read current value of the SDHC_VENDOR_INTSTVAL field. |
mbed_official | 146:f64d43ff0c18 | 5414 | #define BR_SDHC_VENDOR_INTSTVAL (HW_SDHC_VENDOR.B.INTSTVAL) |
mbed_official | 146:f64d43ff0c18 | 5415 | #endif |
mbed_official | 146:f64d43ff0c18 | 5416 | //@} |
mbed_official | 146:f64d43ff0c18 | 5417 | |
mbed_official | 146:f64d43ff0c18 | 5418 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 5419 | // HW_SDHC_MMCBOOT - MMC Boot register |
mbed_official | 146:f64d43ff0c18 | 5420 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 5421 | |
mbed_official | 146:f64d43ff0c18 | 5422 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5423 | /*! |
mbed_official | 146:f64d43ff0c18 | 5424 | * @brief HW_SDHC_MMCBOOT - MMC Boot register (RW) |
mbed_official | 146:f64d43ff0c18 | 5425 | * |
mbed_official | 146:f64d43ff0c18 | 5426 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 5427 | * |
mbed_official | 146:f64d43ff0c18 | 5428 | * This register contains the MMC fast boot control register. |
mbed_official | 146:f64d43ff0c18 | 5429 | */ |
mbed_official | 146:f64d43ff0c18 | 5430 | typedef union _hw_sdhc_mmcboot |
mbed_official | 146:f64d43ff0c18 | 5431 | { |
mbed_official | 146:f64d43ff0c18 | 5432 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 5433 | struct _hw_sdhc_mmcboot_bitfields |
mbed_official | 146:f64d43ff0c18 | 5434 | { |
mbed_official | 146:f64d43ff0c18 | 5435 | uint32_t DTOCVACK : 4; //!< [3:0] Boot ACK Time Out Counter Value |
mbed_official | 146:f64d43ff0c18 | 5436 | uint32_t BOOTACK : 1; //!< [4] Boot Ack Mode Select |
mbed_official | 146:f64d43ff0c18 | 5437 | uint32_t BOOTMODE : 1; //!< [5] Boot Mode Select |
mbed_official | 146:f64d43ff0c18 | 5438 | uint32_t BOOTEN : 1; //!< [6] Boot Mode Enable |
mbed_official | 146:f64d43ff0c18 | 5439 | uint32_t AUTOSABGEN : 1; //!< [7] |
mbed_official | 146:f64d43ff0c18 | 5440 | uint32_t RESERVED0 : 8; //!< [15:8] |
mbed_official | 146:f64d43ff0c18 | 5441 | uint32_t BOOTBLKCNT : 16; //!< [31:16] |
mbed_official | 146:f64d43ff0c18 | 5442 | } B; |
mbed_official | 146:f64d43ff0c18 | 5443 | } hw_sdhc_mmcboot_t; |
mbed_official | 146:f64d43ff0c18 | 5444 | #endif |
mbed_official | 146:f64d43ff0c18 | 5445 | |
mbed_official | 146:f64d43ff0c18 | 5446 | /*! |
mbed_official | 146:f64d43ff0c18 | 5447 | * @name Constants and macros for entire SDHC_MMCBOOT register |
mbed_official | 146:f64d43ff0c18 | 5448 | */ |
mbed_official | 146:f64d43ff0c18 | 5449 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5450 | #define HW_SDHC_MMCBOOT_ADDR (REGS_SDHC_BASE + 0xC4U) |
mbed_official | 146:f64d43ff0c18 | 5451 | |
mbed_official | 146:f64d43ff0c18 | 5452 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5453 | #define HW_SDHC_MMCBOOT (*(__IO hw_sdhc_mmcboot_t *) HW_SDHC_MMCBOOT_ADDR) |
mbed_official | 146:f64d43ff0c18 | 5454 | #define HW_SDHC_MMCBOOT_RD() (HW_SDHC_MMCBOOT.U) |
mbed_official | 146:f64d43ff0c18 | 5455 | #define HW_SDHC_MMCBOOT_WR(v) (HW_SDHC_MMCBOOT.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 5456 | #define HW_SDHC_MMCBOOT_SET(v) (HW_SDHC_MMCBOOT_WR(HW_SDHC_MMCBOOT_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 5457 | #define HW_SDHC_MMCBOOT_CLR(v) (HW_SDHC_MMCBOOT_WR(HW_SDHC_MMCBOOT_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 5458 | #define HW_SDHC_MMCBOOT_TOG(v) (HW_SDHC_MMCBOOT_WR(HW_SDHC_MMCBOOT_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 5459 | #endif |
mbed_official | 146:f64d43ff0c18 | 5460 | //@} |
mbed_official | 146:f64d43ff0c18 | 5461 | |
mbed_official | 146:f64d43ff0c18 | 5462 | /* |
mbed_official | 146:f64d43ff0c18 | 5463 | * Constants & macros for individual SDHC_MMCBOOT bitfields |
mbed_official | 146:f64d43ff0c18 | 5464 | */ |
mbed_official | 146:f64d43ff0c18 | 5465 | |
mbed_official | 146:f64d43ff0c18 | 5466 | /*! |
mbed_official | 146:f64d43ff0c18 | 5467 | * @name Register SDHC_MMCBOOT, field DTOCVACK[3:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 5468 | * |
mbed_official | 146:f64d43ff0c18 | 5469 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5470 | * - 0000 - SDCLK x 2^8 |
mbed_official | 146:f64d43ff0c18 | 5471 | * - 0001 - SDCLK x 2^9 |
mbed_official | 146:f64d43ff0c18 | 5472 | * - 0010 - SDCLK x 2^10 |
mbed_official | 146:f64d43ff0c18 | 5473 | * - 0011 - SDCLK x 2^11 |
mbed_official | 146:f64d43ff0c18 | 5474 | * - 0100 - SDCLK x 2^12 |
mbed_official | 146:f64d43ff0c18 | 5475 | * - 0101 - SDCLK x 2^13 |
mbed_official | 146:f64d43ff0c18 | 5476 | * - 0110 - SDCLK x 2^14 |
mbed_official | 146:f64d43ff0c18 | 5477 | * - 0111 - SDCLK x 2^15 |
mbed_official | 146:f64d43ff0c18 | 5478 | * - 1110 - SDCLK x 2^22 |
mbed_official | 146:f64d43ff0c18 | 5479 | * - 1111 - Reserved |
mbed_official | 146:f64d43ff0c18 | 5480 | */ |
mbed_official | 146:f64d43ff0c18 | 5481 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5482 | #define BP_SDHC_MMCBOOT_DTOCVACK (0U) //!< Bit position for SDHC_MMCBOOT_DTOCVACK. |
mbed_official | 146:f64d43ff0c18 | 5483 | #define BM_SDHC_MMCBOOT_DTOCVACK (0x0000000FU) //!< Bit mask for SDHC_MMCBOOT_DTOCVACK. |
mbed_official | 146:f64d43ff0c18 | 5484 | #define BS_SDHC_MMCBOOT_DTOCVACK (4U) //!< Bit field size in bits for SDHC_MMCBOOT_DTOCVACK. |
mbed_official | 146:f64d43ff0c18 | 5485 | |
mbed_official | 146:f64d43ff0c18 | 5486 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5487 | //! @brief Read current value of the SDHC_MMCBOOT_DTOCVACK field. |
mbed_official | 146:f64d43ff0c18 | 5488 | #define BR_SDHC_MMCBOOT_DTOCVACK (HW_SDHC_MMCBOOT.B.DTOCVACK) |
mbed_official | 146:f64d43ff0c18 | 5489 | #endif |
mbed_official | 146:f64d43ff0c18 | 5490 | |
mbed_official | 146:f64d43ff0c18 | 5491 | //! @brief Format value for bitfield SDHC_MMCBOOT_DTOCVACK. |
mbed_official | 146:f64d43ff0c18 | 5492 | #define BF_SDHC_MMCBOOT_DTOCVACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_DTOCVACK), uint32_t) & BM_SDHC_MMCBOOT_DTOCVACK) |
mbed_official | 146:f64d43ff0c18 | 5493 | |
mbed_official | 146:f64d43ff0c18 | 5494 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5495 | //! @brief Set the DTOCVACK field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5496 | #define BW_SDHC_MMCBOOT_DTOCVACK(v) (HW_SDHC_MMCBOOT_WR((HW_SDHC_MMCBOOT_RD() & ~BM_SDHC_MMCBOOT_DTOCVACK) | BF_SDHC_MMCBOOT_DTOCVACK(v))) |
mbed_official | 146:f64d43ff0c18 | 5497 | #endif |
mbed_official | 146:f64d43ff0c18 | 5498 | //@} |
mbed_official | 146:f64d43ff0c18 | 5499 | |
mbed_official | 146:f64d43ff0c18 | 5500 | /*! |
mbed_official | 146:f64d43ff0c18 | 5501 | * @name Register SDHC_MMCBOOT, field BOOTACK[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 5502 | * |
mbed_official | 146:f64d43ff0c18 | 5503 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5504 | * - 0 - No ack. |
mbed_official | 146:f64d43ff0c18 | 5505 | * - 1 - Ack. |
mbed_official | 146:f64d43ff0c18 | 5506 | */ |
mbed_official | 146:f64d43ff0c18 | 5507 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5508 | #define BP_SDHC_MMCBOOT_BOOTACK (4U) //!< Bit position for SDHC_MMCBOOT_BOOTACK. |
mbed_official | 146:f64d43ff0c18 | 5509 | #define BM_SDHC_MMCBOOT_BOOTACK (0x00000010U) //!< Bit mask for SDHC_MMCBOOT_BOOTACK. |
mbed_official | 146:f64d43ff0c18 | 5510 | #define BS_SDHC_MMCBOOT_BOOTACK (1U) //!< Bit field size in bits for SDHC_MMCBOOT_BOOTACK. |
mbed_official | 146:f64d43ff0c18 | 5511 | |
mbed_official | 146:f64d43ff0c18 | 5512 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5513 | //! @brief Read current value of the SDHC_MMCBOOT_BOOTACK field. |
mbed_official | 146:f64d43ff0c18 | 5514 | #define BR_SDHC_MMCBOOT_BOOTACK (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTACK)) |
mbed_official | 146:f64d43ff0c18 | 5515 | #endif |
mbed_official | 146:f64d43ff0c18 | 5516 | |
mbed_official | 146:f64d43ff0c18 | 5517 | //! @brief Format value for bitfield SDHC_MMCBOOT_BOOTACK. |
mbed_official | 146:f64d43ff0c18 | 5518 | #define BF_SDHC_MMCBOOT_BOOTACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_BOOTACK), uint32_t) & BM_SDHC_MMCBOOT_BOOTACK) |
mbed_official | 146:f64d43ff0c18 | 5519 | |
mbed_official | 146:f64d43ff0c18 | 5520 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5521 | //! @brief Set the BOOTACK field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5522 | #define BW_SDHC_MMCBOOT_BOOTACK(v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTACK) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5523 | #endif |
mbed_official | 146:f64d43ff0c18 | 5524 | //@} |
mbed_official | 146:f64d43ff0c18 | 5525 | |
mbed_official | 146:f64d43ff0c18 | 5526 | /*! |
mbed_official | 146:f64d43ff0c18 | 5527 | * @name Register SDHC_MMCBOOT, field BOOTMODE[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 5528 | * |
mbed_official | 146:f64d43ff0c18 | 5529 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5530 | * - 0 - Normal boot. |
mbed_official | 146:f64d43ff0c18 | 5531 | * - 1 - Alternative boot. |
mbed_official | 146:f64d43ff0c18 | 5532 | */ |
mbed_official | 146:f64d43ff0c18 | 5533 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5534 | #define BP_SDHC_MMCBOOT_BOOTMODE (5U) //!< Bit position for SDHC_MMCBOOT_BOOTMODE. |
mbed_official | 146:f64d43ff0c18 | 5535 | #define BM_SDHC_MMCBOOT_BOOTMODE (0x00000020U) //!< Bit mask for SDHC_MMCBOOT_BOOTMODE. |
mbed_official | 146:f64d43ff0c18 | 5536 | #define BS_SDHC_MMCBOOT_BOOTMODE (1U) //!< Bit field size in bits for SDHC_MMCBOOT_BOOTMODE. |
mbed_official | 146:f64d43ff0c18 | 5537 | |
mbed_official | 146:f64d43ff0c18 | 5538 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5539 | //! @brief Read current value of the SDHC_MMCBOOT_BOOTMODE field. |
mbed_official | 146:f64d43ff0c18 | 5540 | #define BR_SDHC_MMCBOOT_BOOTMODE (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTMODE)) |
mbed_official | 146:f64d43ff0c18 | 5541 | #endif |
mbed_official | 146:f64d43ff0c18 | 5542 | |
mbed_official | 146:f64d43ff0c18 | 5543 | //! @brief Format value for bitfield SDHC_MMCBOOT_BOOTMODE. |
mbed_official | 146:f64d43ff0c18 | 5544 | #define BF_SDHC_MMCBOOT_BOOTMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_BOOTMODE), uint32_t) & BM_SDHC_MMCBOOT_BOOTMODE) |
mbed_official | 146:f64d43ff0c18 | 5545 | |
mbed_official | 146:f64d43ff0c18 | 5546 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5547 | //! @brief Set the BOOTMODE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5548 | #define BW_SDHC_MMCBOOT_BOOTMODE(v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTMODE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5549 | #endif |
mbed_official | 146:f64d43ff0c18 | 5550 | //@} |
mbed_official | 146:f64d43ff0c18 | 5551 | |
mbed_official | 146:f64d43ff0c18 | 5552 | /*! |
mbed_official | 146:f64d43ff0c18 | 5553 | * @name Register SDHC_MMCBOOT, field BOOTEN[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 5554 | * |
mbed_official | 146:f64d43ff0c18 | 5555 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5556 | * - 0 - Fast boot disable. |
mbed_official | 146:f64d43ff0c18 | 5557 | * - 1 - Fast boot enable. |
mbed_official | 146:f64d43ff0c18 | 5558 | */ |
mbed_official | 146:f64d43ff0c18 | 5559 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5560 | #define BP_SDHC_MMCBOOT_BOOTEN (6U) //!< Bit position for SDHC_MMCBOOT_BOOTEN. |
mbed_official | 146:f64d43ff0c18 | 5561 | #define BM_SDHC_MMCBOOT_BOOTEN (0x00000040U) //!< Bit mask for SDHC_MMCBOOT_BOOTEN. |
mbed_official | 146:f64d43ff0c18 | 5562 | #define BS_SDHC_MMCBOOT_BOOTEN (1U) //!< Bit field size in bits for SDHC_MMCBOOT_BOOTEN. |
mbed_official | 146:f64d43ff0c18 | 5563 | |
mbed_official | 146:f64d43ff0c18 | 5564 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5565 | //! @brief Read current value of the SDHC_MMCBOOT_BOOTEN field. |
mbed_official | 146:f64d43ff0c18 | 5566 | #define BR_SDHC_MMCBOOT_BOOTEN (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTEN)) |
mbed_official | 146:f64d43ff0c18 | 5567 | #endif |
mbed_official | 146:f64d43ff0c18 | 5568 | |
mbed_official | 146:f64d43ff0c18 | 5569 | //! @brief Format value for bitfield SDHC_MMCBOOT_BOOTEN. |
mbed_official | 146:f64d43ff0c18 | 5570 | #define BF_SDHC_MMCBOOT_BOOTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_BOOTEN), uint32_t) & BM_SDHC_MMCBOOT_BOOTEN) |
mbed_official | 146:f64d43ff0c18 | 5571 | |
mbed_official | 146:f64d43ff0c18 | 5572 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5573 | //! @brief Set the BOOTEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5574 | #define BW_SDHC_MMCBOOT_BOOTEN(v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5575 | #endif |
mbed_official | 146:f64d43ff0c18 | 5576 | //@} |
mbed_official | 146:f64d43ff0c18 | 5577 | |
mbed_official | 146:f64d43ff0c18 | 5578 | /*! |
mbed_official | 146:f64d43ff0c18 | 5579 | * @name Register SDHC_MMCBOOT, field AUTOSABGEN[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 5580 | * |
mbed_official | 146:f64d43ff0c18 | 5581 | * When boot, enable auto stop at block gap function. This function will be |
mbed_official | 146:f64d43ff0c18 | 5582 | * triggered, and host will stop at block gap when received card block cnt is equal |
mbed_official | 146:f64d43ff0c18 | 5583 | * to BOOTBLKCNT. |
mbed_official | 146:f64d43ff0c18 | 5584 | */ |
mbed_official | 146:f64d43ff0c18 | 5585 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5586 | #define BP_SDHC_MMCBOOT_AUTOSABGEN (7U) //!< Bit position for SDHC_MMCBOOT_AUTOSABGEN. |
mbed_official | 146:f64d43ff0c18 | 5587 | #define BM_SDHC_MMCBOOT_AUTOSABGEN (0x00000080U) //!< Bit mask for SDHC_MMCBOOT_AUTOSABGEN. |
mbed_official | 146:f64d43ff0c18 | 5588 | #define BS_SDHC_MMCBOOT_AUTOSABGEN (1U) //!< Bit field size in bits for SDHC_MMCBOOT_AUTOSABGEN. |
mbed_official | 146:f64d43ff0c18 | 5589 | |
mbed_official | 146:f64d43ff0c18 | 5590 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5591 | //! @brief Read current value of the SDHC_MMCBOOT_AUTOSABGEN field. |
mbed_official | 146:f64d43ff0c18 | 5592 | #define BR_SDHC_MMCBOOT_AUTOSABGEN (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_AUTOSABGEN)) |
mbed_official | 146:f64d43ff0c18 | 5593 | #endif |
mbed_official | 146:f64d43ff0c18 | 5594 | |
mbed_official | 146:f64d43ff0c18 | 5595 | //! @brief Format value for bitfield SDHC_MMCBOOT_AUTOSABGEN. |
mbed_official | 146:f64d43ff0c18 | 5596 | #define BF_SDHC_MMCBOOT_AUTOSABGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_AUTOSABGEN), uint32_t) & BM_SDHC_MMCBOOT_AUTOSABGEN) |
mbed_official | 146:f64d43ff0c18 | 5597 | |
mbed_official | 146:f64d43ff0c18 | 5598 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5599 | //! @brief Set the AUTOSABGEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5600 | #define BW_SDHC_MMCBOOT_AUTOSABGEN(v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_AUTOSABGEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5601 | #endif |
mbed_official | 146:f64d43ff0c18 | 5602 | //@} |
mbed_official | 146:f64d43ff0c18 | 5603 | |
mbed_official | 146:f64d43ff0c18 | 5604 | /*! |
mbed_official | 146:f64d43ff0c18 | 5605 | * @name Register SDHC_MMCBOOT, field BOOTBLKCNT[31:16] (RW) |
mbed_official | 146:f64d43ff0c18 | 5606 | * |
mbed_official | 146:f64d43ff0c18 | 5607 | * Defines the stop at block gap value of automatic mode. When received card |
mbed_official | 146:f64d43ff0c18 | 5608 | * block cnt is equal to BOOTBLKCNT and AUTOSABGEN is 1, then stop at block gap. |
mbed_official | 146:f64d43ff0c18 | 5609 | */ |
mbed_official | 146:f64d43ff0c18 | 5610 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5611 | #define BP_SDHC_MMCBOOT_BOOTBLKCNT (16U) //!< Bit position for SDHC_MMCBOOT_BOOTBLKCNT. |
mbed_official | 146:f64d43ff0c18 | 5612 | #define BM_SDHC_MMCBOOT_BOOTBLKCNT (0xFFFF0000U) //!< Bit mask for SDHC_MMCBOOT_BOOTBLKCNT. |
mbed_official | 146:f64d43ff0c18 | 5613 | #define BS_SDHC_MMCBOOT_BOOTBLKCNT (16U) //!< Bit field size in bits for SDHC_MMCBOOT_BOOTBLKCNT. |
mbed_official | 146:f64d43ff0c18 | 5614 | |
mbed_official | 146:f64d43ff0c18 | 5615 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5616 | //! @brief Read current value of the SDHC_MMCBOOT_BOOTBLKCNT field. |
mbed_official | 146:f64d43ff0c18 | 5617 | #define BR_SDHC_MMCBOOT_BOOTBLKCNT (HW_SDHC_MMCBOOT.B.BOOTBLKCNT) |
mbed_official | 146:f64d43ff0c18 | 5618 | #endif |
mbed_official | 146:f64d43ff0c18 | 5619 | |
mbed_official | 146:f64d43ff0c18 | 5620 | //! @brief Format value for bitfield SDHC_MMCBOOT_BOOTBLKCNT. |
mbed_official | 146:f64d43ff0c18 | 5621 | #define BF_SDHC_MMCBOOT_BOOTBLKCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_BOOTBLKCNT), uint32_t) & BM_SDHC_MMCBOOT_BOOTBLKCNT) |
mbed_official | 146:f64d43ff0c18 | 5622 | |
mbed_official | 146:f64d43ff0c18 | 5623 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5624 | //! @brief Set the BOOTBLKCNT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5625 | #define BW_SDHC_MMCBOOT_BOOTBLKCNT(v) (HW_SDHC_MMCBOOT_WR((HW_SDHC_MMCBOOT_RD() & ~BM_SDHC_MMCBOOT_BOOTBLKCNT) | BF_SDHC_MMCBOOT_BOOTBLKCNT(v))) |
mbed_official | 146:f64d43ff0c18 | 5626 | #endif |
mbed_official | 146:f64d43ff0c18 | 5627 | //@} |
mbed_official | 146:f64d43ff0c18 | 5628 | |
mbed_official | 146:f64d43ff0c18 | 5629 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 5630 | // HW_SDHC_HOSTVER - Host Controller Version |
mbed_official | 146:f64d43ff0c18 | 5631 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 5632 | |
mbed_official | 146:f64d43ff0c18 | 5633 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5634 | /*! |
mbed_official | 146:f64d43ff0c18 | 5635 | * @brief HW_SDHC_HOSTVER - Host Controller Version (RO) |
mbed_official | 146:f64d43ff0c18 | 5636 | * |
mbed_official | 146:f64d43ff0c18 | 5637 | * Reset value: 0x00001201U |
mbed_official | 146:f64d43ff0c18 | 5638 | * |
mbed_official | 146:f64d43ff0c18 | 5639 | * This register contains the vendor host controller version information. All |
mbed_official | 146:f64d43ff0c18 | 5640 | * bits are read only and will read the same as the power-reset value. |
mbed_official | 146:f64d43ff0c18 | 5641 | */ |
mbed_official | 146:f64d43ff0c18 | 5642 | typedef union _hw_sdhc_hostver |
mbed_official | 146:f64d43ff0c18 | 5643 | { |
mbed_official | 146:f64d43ff0c18 | 5644 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 5645 | struct _hw_sdhc_hostver_bitfields |
mbed_official | 146:f64d43ff0c18 | 5646 | { |
mbed_official | 146:f64d43ff0c18 | 5647 | uint32_t SVN : 8; //!< [7:0] Specification Version Number |
mbed_official | 146:f64d43ff0c18 | 5648 | uint32_t VVN : 8; //!< [15:8] Vendor Version Number |
mbed_official | 146:f64d43ff0c18 | 5649 | uint32_t RESERVED0 : 16; //!< [31:16] |
mbed_official | 146:f64d43ff0c18 | 5650 | } B; |
mbed_official | 146:f64d43ff0c18 | 5651 | } hw_sdhc_hostver_t; |
mbed_official | 146:f64d43ff0c18 | 5652 | #endif |
mbed_official | 146:f64d43ff0c18 | 5653 | |
mbed_official | 146:f64d43ff0c18 | 5654 | /*! |
mbed_official | 146:f64d43ff0c18 | 5655 | * @name Constants and macros for entire SDHC_HOSTVER register |
mbed_official | 146:f64d43ff0c18 | 5656 | */ |
mbed_official | 146:f64d43ff0c18 | 5657 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5658 | #define HW_SDHC_HOSTVER_ADDR (REGS_SDHC_BASE + 0xFCU) |
mbed_official | 146:f64d43ff0c18 | 5659 | |
mbed_official | 146:f64d43ff0c18 | 5660 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5661 | #define HW_SDHC_HOSTVER (*(__I hw_sdhc_hostver_t *) HW_SDHC_HOSTVER_ADDR) |
mbed_official | 146:f64d43ff0c18 | 5662 | #define HW_SDHC_HOSTVER_RD() (HW_SDHC_HOSTVER.U) |
mbed_official | 146:f64d43ff0c18 | 5663 | #endif |
mbed_official | 146:f64d43ff0c18 | 5664 | //@} |
mbed_official | 146:f64d43ff0c18 | 5665 | |
mbed_official | 146:f64d43ff0c18 | 5666 | /* |
mbed_official | 146:f64d43ff0c18 | 5667 | * Constants & macros for individual SDHC_HOSTVER bitfields |
mbed_official | 146:f64d43ff0c18 | 5668 | */ |
mbed_official | 146:f64d43ff0c18 | 5669 | |
mbed_official | 146:f64d43ff0c18 | 5670 | /*! |
mbed_official | 146:f64d43ff0c18 | 5671 | * @name Register SDHC_HOSTVER, field SVN[7:0] (RO) |
mbed_official | 146:f64d43ff0c18 | 5672 | * |
mbed_official | 146:f64d43ff0c18 | 5673 | * These status bits indicate the host controller specification version. |
mbed_official | 146:f64d43ff0c18 | 5674 | * |
mbed_official | 146:f64d43ff0c18 | 5675 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5676 | * - 1 - SD host specification version 2.0, supports test event register and |
mbed_official | 146:f64d43ff0c18 | 5677 | * ADMA. |
mbed_official | 146:f64d43ff0c18 | 5678 | */ |
mbed_official | 146:f64d43ff0c18 | 5679 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5680 | #define BP_SDHC_HOSTVER_SVN (0U) //!< Bit position for SDHC_HOSTVER_SVN. |
mbed_official | 146:f64d43ff0c18 | 5681 | #define BM_SDHC_HOSTVER_SVN (0x000000FFU) //!< Bit mask for SDHC_HOSTVER_SVN. |
mbed_official | 146:f64d43ff0c18 | 5682 | #define BS_SDHC_HOSTVER_SVN (8U) //!< Bit field size in bits for SDHC_HOSTVER_SVN. |
mbed_official | 146:f64d43ff0c18 | 5683 | |
mbed_official | 146:f64d43ff0c18 | 5684 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5685 | //! @brief Read current value of the SDHC_HOSTVER_SVN field. |
mbed_official | 146:f64d43ff0c18 | 5686 | #define BR_SDHC_HOSTVER_SVN (HW_SDHC_HOSTVER.B.SVN) |
mbed_official | 146:f64d43ff0c18 | 5687 | #endif |
mbed_official | 146:f64d43ff0c18 | 5688 | //@} |
mbed_official | 146:f64d43ff0c18 | 5689 | |
mbed_official | 146:f64d43ff0c18 | 5690 | /*! |
mbed_official | 146:f64d43ff0c18 | 5691 | * @name Register SDHC_HOSTVER, field VVN[15:8] (RO) |
mbed_official | 146:f64d43ff0c18 | 5692 | * |
mbed_official | 146:f64d43ff0c18 | 5693 | * These status bits are reserved for the vendor version number. The host driver |
mbed_official | 146:f64d43ff0c18 | 5694 | * shall not use this status. |
mbed_official | 146:f64d43ff0c18 | 5695 | * |
mbed_official | 146:f64d43ff0c18 | 5696 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5697 | * - 0 - Freescale SDHC version 1.0 |
mbed_official | 146:f64d43ff0c18 | 5698 | * - 10000 - Freescale SDHC version 2.0 |
mbed_official | 146:f64d43ff0c18 | 5699 | * - 10001 - Freescale SDHC version 2.1 |
mbed_official | 146:f64d43ff0c18 | 5700 | * - 10010 - Freescale SDHC version 2.2 |
mbed_official | 146:f64d43ff0c18 | 5701 | */ |
mbed_official | 146:f64d43ff0c18 | 5702 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5703 | #define BP_SDHC_HOSTVER_VVN (8U) //!< Bit position for SDHC_HOSTVER_VVN. |
mbed_official | 146:f64d43ff0c18 | 5704 | #define BM_SDHC_HOSTVER_VVN (0x0000FF00U) //!< Bit mask for SDHC_HOSTVER_VVN. |
mbed_official | 146:f64d43ff0c18 | 5705 | #define BS_SDHC_HOSTVER_VVN (8U) //!< Bit field size in bits for SDHC_HOSTVER_VVN. |
mbed_official | 146:f64d43ff0c18 | 5706 | |
mbed_official | 146:f64d43ff0c18 | 5707 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5708 | //! @brief Read current value of the SDHC_HOSTVER_VVN field. |
mbed_official | 146:f64d43ff0c18 | 5709 | #define BR_SDHC_HOSTVER_VVN (HW_SDHC_HOSTVER.B.VVN) |
mbed_official | 146:f64d43ff0c18 | 5710 | #endif |
mbed_official | 146:f64d43ff0c18 | 5711 | //@} |
mbed_official | 146:f64d43ff0c18 | 5712 | |
mbed_official | 146:f64d43ff0c18 | 5713 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 5714 | // hw_sdhc_t - module struct |
mbed_official | 146:f64d43ff0c18 | 5715 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 5716 | /*! |
mbed_official | 146:f64d43ff0c18 | 5717 | * @brief All SDHC module registers. |
mbed_official | 146:f64d43ff0c18 | 5718 | */ |
mbed_official | 146:f64d43ff0c18 | 5719 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5720 | #pragma pack(1) |
mbed_official | 146:f64d43ff0c18 | 5721 | typedef struct _hw_sdhc |
mbed_official | 146:f64d43ff0c18 | 5722 | { |
mbed_official | 146:f64d43ff0c18 | 5723 | __IO hw_sdhc_dsaddr_t DSADDR; //!< [0x0] DMA System Address register |
mbed_official | 146:f64d43ff0c18 | 5724 | __IO hw_sdhc_blkattr_t BLKATTR; //!< [0x4] Block Attributes register |
mbed_official | 146:f64d43ff0c18 | 5725 | __IO hw_sdhc_cmdarg_t CMDARG; //!< [0x8] Command Argument register |
mbed_official | 146:f64d43ff0c18 | 5726 | __IO hw_sdhc_xfertyp_t XFERTYP; //!< [0xC] Transfer Type register |
mbed_official | 146:f64d43ff0c18 | 5727 | __I hw_sdhc_cmdrsp0_t CMDRSP0; //!< [0x10] Command Response 0 |
mbed_official | 146:f64d43ff0c18 | 5728 | __I hw_sdhc_cmdrsp1_t CMDRSP1; //!< [0x14] Command Response 1 |
mbed_official | 146:f64d43ff0c18 | 5729 | __I hw_sdhc_cmdrsp2_t CMDRSP2; //!< [0x18] Command Response 2 |
mbed_official | 146:f64d43ff0c18 | 5730 | __I hw_sdhc_cmdrsp3_t CMDRSP3; //!< [0x1C] Command Response 3 |
mbed_official | 146:f64d43ff0c18 | 5731 | __IO hw_sdhc_datport_t DATPORT; //!< [0x20] Buffer Data Port register |
mbed_official | 146:f64d43ff0c18 | 5732 | __I hw_sdhc_prsstat_t PRSSTAT; //!< [0x24] Present State register |
mbed_official | 146:f64d43ff0c18 | 5733 | __IO hw_sdhc_proctl_t PROCTL; //!< [0x28] Protocol Control register |
mbed_official | 146:f64d43ff0c18 | 5734 | __IO hw_sdhc_sysctl_t SYSCTL; //!< [0x2C] System Control register |
mbed_official | 146:f64d43ff0c18 | 5735 | __IO hw_sdhc_irqstat_t IRQSTAT; //!< [0x30] Interrupt Status register |
mbed_official | 146:f64d43ff0c18 | 5736 | __IO hw_sdhc_irqstaten_t IRQSTATEN; //!< [0x34] Interrupt Status Enable register |
mbed_official | 146:f64d43ff0c18 | 5737 | __IO hw_sdhc_irqsigen_t IRQSIGEN; //!< [0x38] Interrupt Signal Enable register |
mbed_official | 146:f64d43ff0c18 | 5738 | __I hw_sdhc_ac12err_t AC12ERR; //!< [0x3C] Auto CMD12 Error Status Register |
mbed_official | 146:f64d43ff0c18 | 5739 | __I hw_sdhc_htcapblt_t HTCAPBLT; //!< [0x40] Host Controller Capabilities |
mbed_official | 146:f64d43ff0c18 | 5740 | __IO hw_sdhc_wml_t WML; //!< [0x44] Watermark Level Register |
mbed_official | 146:f64d43ff0c18 | 5741 | uint8_t _reserved0[8]; |
mbed_official | 146:f64d43ff0c18 | 5742 | __O hw_sdhc_fevt_t FEVT; //!< [0x50] Force Event register |
mbed_official | 146:f64d43ff0c18 | 5743 | __I hw_sdhc_admaes_t ADMAES; //!< [0x54] ADMA Error Status register |
mbed_official | 146:f64d43ff0c18 | 5744 | __IO hw_sdhc_adsaddr_t ADSADDR; //!< [0x58] ADMA System Addressregister |
mbed_official | 146:f64d43ff0c18 | 5745 | uint8_t _reserved1[100]; |
mbed_official | 146:f64d43ff0c18 | 5746 | __IO hw_sdhc_vendor_t VENDOR; //!< [0xC0] Vendor Specific register |
mbed_official | 146:f64d43ff0c18 | 5747 | __IO hw_sdhc_mmcboot_t MMCBOOT; //!< [0xC4] MMC Boot register |
mbed_official | 146:f64d43ff0c18 | 5748 | uint8_t _reserved2[52]; |
mbed_official | 146:f64d43ff0c18 | 5749 | __I hw_sdhc_hostver_t HOSTVER; //!< [0xFC] Host Controller Version |
mbed_official | 146:f64d43ff0c18 | 5750 | } hw_sdhc_t; |
mbed_official | 146:f64d43ff0c18 | 5751 | #pragma pack() |
mbed_official | 146:f64d43ff0c18 | 5752 | |
mbed_official | 146:f64d43ff0c18 | 5753 | //! @brief Macro to access all SDHC registers. |
mbed_official | 146:f64d43ff0c18 | 5754 | //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, |
mbed_official | 146:f64d43ff0c18 | 5755 | //! use the '&' operator, like <code>&HW_SDHC</code>. |
mbed_official | 146:f64d43ff0c18 | 5756 | #define HW_SDHC (*(hw_sdhc_t *) REGS_SDHC_BASE) |
mbed_official | 146:f64d43ff0c18 | 5757 | #endif |
mbed_official | 146:f64d43ff0c18 | 5758 | |
mbed_official | 146:f64d43ff0c18 | 5759 | #endif // __HW_SDHC_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 5760 | // v22/130726/0.9 |
mbed_official | 146:f64d43ff0c18 | 5761 | // EOF |