shao ziyang / mbed-src-kl05

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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_fb.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
320:be04b2b1e3f2 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 146:f64d43ff0c18 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 146:f64d43ff0c18 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official 146:f64d43ff0c18 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official 146:f64d43ff0c18 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official 146:f64d43ff0c18 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 146:f64d43ff0c18 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 146:f64d43ff0c18 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official 146:f64d43ff0c18 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official 146:f64d43ff0c18 14 * OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 146:f64d43ff0c18 16 /*
mbed_official 146:f64d43ff0c18 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * This file was generated automatically and any changes may be lost.
mbed_official 146:f64d43ff0c18 20 */
mbed_official 146:f64d43ff0c18 21 #ifndef __HW_FB_REGISTERS_H__
mbed_official 146:f64d43ff0c18 22 #define __HW_FB_REGISTERS_H__
mbed_official 146:f64d43ff0c18 23
mbed_official 146:f64d43ff0c18 24 #include "regs.h"
mbed_official 146:f64d43ff0c18 25
mbed_official 146:f64d43ff0c18 26 /*
mbed_official 146:f64d43ff0c18 27 * MK64F12 FB
mbed_official 146:f64d43ff0c18 28 *
mbed_official 146:f64d43ff0c18 29 * FlexBus external bus interface
mbed_official 146:f64d43ff0c18 30 *
mbed_official 146:f64d43ff0c18 31 * Registers defined in this header file:
mbed_official 146:f64d43ff0c18 32 * - HW_FB_CSARn - Chip Select Address Register
mbed_official 146:f64d43ff0c18 33 * - HW_FB_CSMRn - Chip Select Mask Register
mbed_official 146:f64d43ff0c18 34 * - HW_FB_CSCRn - Chip Select Control Register
mbed_official 146:f64d43ff0c18 35 * - HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
mbed_official 146:f64d43ff0c18 36 *
mbed_official 146:f64d43ff0c18 37 * - hw_fb_t - Struct containing all module registers.
mbed_official 146:f64d43ff0c18 38 */
mbed_official 146:f64d43ff0c18 39
mbed_official 146:f64d43ff0c18 40 //! @name Module base addresses
mbed_official 146:f64d43ff0c18 41 //@{
mbed_official 146:f64d43ff0c18 42 #ifndef REGS_FB_BASE
mbed_official 146:f64d43ff0c18 43 #define HW_FB_INSTANCE_COUNT (1U) //!< Number of instances of the FB module.
mbed_official 146:f64d43ff0c18 44 #define REGS_FB_BASE (0x4000C000U) //!< Base address for FB.
mbed_official 146:f64d43ff0c18 45 #endif
mbed_official 146:f64d43ff0c18 46 //@}
mbed_official 146:f64d43ff0c18 47
mbed_official 146:f64d43ff0c18 48 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 49 // HW_FB_CSARn - Chip Select Address Register
mbed_official 146:f64d43ff0c18 50 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 51
mbed_official 146:f64d43ff0c18 52 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 53 /*!
mbed_official 146:f64d43ff0c18 54 * @brief HW_FB_CSARn - Chip Select Address Register (RW)
mbed_official 146:f64d43ff0c18 55 *
mbed_official 146:f64d43ff0c18 56 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 57 *
mbed_official 146:f64d43ff0c18 58 * Specifies the associated chip-select's base address.
mbed_official 146:f64d43ff0c18 59 */
mbed_official 146:f64d43ff0c18 60 typedef union _hw_fb_csarn
mbed_official 146:f64d43ff0c18 61 {
mbed_official 146:f64d43ff0c18 62 uint32_t U;
mbed_official 146:f64d43ff0c18 63 struct _hw_fb_csarn_bitfields
mbed_official 146:f64d43ff0c18 64 {
mbed_official 146:f64d43ff0c18 65 uint32_t RESERVED0 : 16; //!< [15:0]
mbed_official 146:f64d43ff0c18 66 uint32_t BA : 16; //!< [31:16] Base Address
mbed_official 146:f64d43ff0c18 67 } B;
mbed_official 146:f64d43ff0c18 68 } hw_fb_csarn_t;
mbed_official 146:f64d43ff0c18 69 #endif
mbed_official 146:f64d43ff0c18 70
mbed_official 146:f64d43ff0c18 71 /*!
mbed_official 146:f64d43ff0c18 72 * @name Constants and macros for entire FB_CSARn register
mbed_official 146:f64d43ff0c18 73 */
mbed_official 146:f64d43ff0c18 74 //@{
mbed_official 146:f64d43ff0c18 75 #define HW_FB_CSARn_COUNT (6U)
mbed_official 146:f64d43ff0c18 76
mbed_official 146:f64d43ff0c18 77 #define HW_FB_CSARn_ADDR(n) (REGS_FB_BASE + 0x0U + (0xCU * n))
mbed_official 146:f64d43ff0c18 78
mbed_official 146:f64d43ff0c18 79 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 80 #define HW_FB_CSARn(n) (*(__IO hw_fb_csarn_t *) HW_FB_CSARn_ADDR(n))
mbed_official 146:f64d43ff0c18 81 #define HW_FB_CSARn_RD(n) (HW_FB_CSARn(n).U)
mbed_official 146:f64d43ff0c18 82 #define HW_FB_CSARn_WR(n, v) (HW_FB_CSARn(n).U = (v))
mbed_official 146:f64d43ff0c18 83 #define HW_FB_CSARn_SET(n, v) (HW_FB_CSARn_WR(n, HW_FB_CSARn_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 84 #define HW_FB_CSARn_CLR(n, v) (HW_FB_CSARn_WR(n, HW_FB_CSARn_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 85 #define HW_FB_CSARn_TOG(n, v) (HW_FB_CSARn_WR(n, HW_FB_CSARn_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 86 #endif
mbed_official 146:f64d43ff0c18 87 //@}
mbed_official 146:f64d43ff0c18 88
mbed_official 146:f64d43ff0c18 89 /*
mbed_official 146:f64d43ff0c18 90 * Constants & macros for individual FB_CSARn bitfields
mbed_official 146:f64d43ff0c18 91 */
mbed_official 146:f64d43ff0c18 92
mbed_official 146:f64d43ff0c18 93 /*!
mbed_official 146:f64d43ff0c18 94 * @name Register FB_CSARn, field BA[31:16] (RW)
mbed_official 146:f64d43ff0c18 95 *
mbed_official 146:f64d43ff0c18 96 * Defines the base address for memory dedicated to the associated chip-select.
mbed_official 146:f64d43ff0c18 97 * BA is compared to bits 31-16 on the internal address bus to determine if the
mbed_official 146:f64d43ff0c18 98 * associated chip-select's memory is being accessed. Because the FlexBus module
mbed_official 146:f64d43ff0c18 99 * is one of the slaves connected to the crossbar switch, it is only accessible
mbed_official 146:f64d43ff0c18 100 * within a certain memory range. See the chip memory map for the applicable
mbed_official 146:f64d43ff0c18 101 * FlexBus "expansion" address range for which the chip-selects can be active. Set the
mbed_official 146:f64d43ff0c18 102 * CSARn and CSMRn registers appropriately before accessing this region.
mbed_official 146:f64d43ff0c18 103 */
mbed_official 146:f64d43ff0c18 104 //@{
mbed_official 146:f64d43ff0c18 105 #define BP_FB_CSARn_BA (16U) //!< Bit position for FB_CSARn_BA.
mbed_official 146:f64d43ff0c18 106 #define BM_FB_CSARn_BA (0xFFFF0000U) //!< Bit mask for FB_CSARn_BA.
mbed_official 146:f64d43ff0c18 107 #define BS_FB_CSARn_BA (16U) //!< Bit field size in bits for FB_CSARn_BA.
mbed_official 146:f64d43ff0c18 108
mbed_official 146:f64d43ff0c18 109 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 110 //! @brief Read current value of the FB_CSARn_BA field.
mbed_official 146:f64d43ff0c18 111 #define BR_FB_CSARn_BA(n) (HW_FB_CSARn(n).B.BA)
mbed_official 146:f64d43ff0c18 112 #endif
mbed_official 146:f64d43ff0c18 113
mbed_official 146:f64d43ff0c18 114 //! @brief Format value for bitfield FB_CSARn_BA.
mbed_official 146:f64d43ff0c18 115 #define BF_FB_CSARn_BA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSARn_BA), uint32_t) & BM_FB_CSARn_BA)
mbed_official 146:f64d43ff0c18 116
mbed_official 146:f64d43ff0c18 117 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 118 //! @brief Set the BA field to a new value.
mbed_official 146:f64d43ff0c18 119 #define BW_FB_CSARn_BA(n, v) (HW_FB_CSARn_WR(n, (HW_FB_CSARn_RD(n) & ~BM_FB_CSARn_BA) | BF_FB_CSARn_BA(v)))
mbed_official 146:f64d43ff0c18 120 #endif
mbed_official 146:f64d43ff0c18 121 //@}
mbed_official 146:f64d43ff0c18 122 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 123 // HW_FB_CSMRn - Chip Select Mask Register
mbed_official 146:f64d43ff0c18 124 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 125
mbed_official 146:f64d43ff0c18 126 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 127 /*!
mbed_official 146:f64d43ff0c18 128 * @brief HW_FB_CSMRn - Chip Select Mask Register (RW)
mbed_official 146:f64d43ff0c18 129 *
mbed_official 146:f64d43ff0c18 130 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 131 *
mbed_official 146:f64d43ff0c18 132 * Specifies the address mask and allowable access types for the associated
mbed_official 146:f64d43ff0c18 133 * chip-select.
mbed_official 146:f64d43ff0c18 134 */
mbed_official 146:f64d43ff0c18 135 typedef union _hw_fb_csmrn
mbed_official 146:f64d43ff0c18 136 {
mbed_official 146:f64d43ff0c18 137 uint32_t U;
mbed_official 146:f64d43ff0c18 138 struct _hw_fb_csmrn_bitfields
mbed_official 146:f64d43ff0c18 139 {
mbed_official 146:f64d43ff0c18 140 uint32_t V : 1; //!< [0] Valid
mbed_official 146:f64d43ff0c18 141 uint32_t RESERVED0 : 7; //!< [7:1]
mbed_official 146:f64d43ff0c18 142 uint32_t WP : 1; //!< [8] Write Protect
mbed_official 146:f64d43ff0c18 143 uint32_t RESERVED1 : 7; //!< [15:9]
mbed_official 146:f64d43ff0c18 144 uint32_t BAM : 16; //!< [31:16] Base Address Mask
mbed_official 146:f64d43ff0c18 145 } B;
mbed_official 146:f64d43ff0c18 146 } hw_fb_csmrn_t;
mbed_official 146:f64d43ff0c18 147 #endif
mbed_official 146:f64d43ff0c18 148
mbed_official 146:f64d43ff0c18 149 /*!
mbed_official 146:f64d43ff0c18 150 * @name Constants and macros for entire FB_CSMRn register
mbed_official 146:f64d43ff0c18 151 */
mbed_official 146:f64d43ff0c18 152 //@{
mbed_official 146:f64d43ff0c18 153 #define HW_FB_CSMRn_COUNT (6U)
mbed_official 146:f64d43ff0c18 154
mbed_official 146:f64d43ff0c18 155 #define HW_FB_CSMRn_ADDR(n) (REGS_FB_BASE + 0x4U + (0xCU * n))
mbed_official 146:f64d43ff0c18 156
mbed_official 146:f64d43ff0c18 157 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 158 #define HW_FB_CSMRn(n) (*(__IO hw_fb_csmrn_t *) HW_FB_CSMRn_ADDR(n))
mbed_official 146:f64d43ff0c18 159 #define HW_FB_CSMRn_RD(n) (HW_FB_CSMRn(n).U)
mbed_official 146:f64d43ff0c18 160 #define HW_FB_CSMRn_WR(n, v) (HW_FB_CSMRn(n).U = (v))
mbed_official 146:f64d43ff0c18 161 #define HW_FB_CSMRn_SET(n, v) (HW_FB_CSMRn_WR(n, HW_FB_CSMRn_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 162 #define HW_FB_CSMRn_CLR(n, v) (HW_FB_CSMRn_WR(n, HW_FB_CSMRn_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 163 #define HW_FB_CSMRn_TOG(n, v) (HW_FB_CSMRn_WR(n, HW_FB_CSMRn_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 164 #endif
mbed_official 146:f64d43ff0c18 165 //@}
mbed_official 146:f64d43ff0c18 166
mbed_official 146:f64d43ff0c18 167 /*
mbed_official 146:f64d43ff0c18 168 * Constants & macros for individual FB_CSMRn bitfields
mbed_official 146:f64d43ff0c18 169 */
mbed_official 146:f64d43ff0c18 170
mbed_official 146:f64d43ff0c18 171 /*!
mbed_official 146:f64d43ff0c18 172 * @name Register FB_CSMRn, field V[0] (RW)
mbed_official 146:f64d43ff0c18 173 *
mbed_official 146:f64d43ff0c18 174 * Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid.
mbed_official 146:f64d43ff0c18 175 * Programmed chip-selects do not assert until the V bit is 1b (except for
mbed_official 146:f64d43ff0c18 176 * FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any
mbed_official 146:f64d43ff0c18 177 * access to the FlexBus memory region. CSMR0[V] must be set as part of the chip
mbed_official 146:f64d43ff0c18 178 * select initialization sequence to allow other chip selects to function as
mbed_official 146:f64d43ff0c18 179 * programmed.
mbed_official 146:f64d43ff0c18 180 *
mbed_official 146:f64d43ff0c18 181 * Values:
mbed_official 146:f64d43ff0c18 182 * - 0 - Chip-select is invalid.
mbed_official 146:f64d43ff0c18 183 * - 1 - Chip-select is valid.
mbed_official 146:f64d43ff0c18 184 */
mbed_official 146:f64d43ff0c18 185 //@{
mbed_official 146:f64d43ff0c18 186 #define BP_FB_CSMRn_V (0U) //!< Bit position for FB_CSMRn_V.
mbed_official 146:f64d43ff0c18 187 #define BM_FB_CSMRn_V (0x00000001U) //!< Bit mask for FB_CSMRn_V.
mbed_official 146:f64d43ff0c18 188 #define BS_FB_CSMRn_V (1U) //!< Bit field size in bits for FB_CSMRn_V.
mbed_official 146:f64d43ff0c18 189
mbed_official 146:f64d43ff0c18 190 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 191 //! @brief Read current value of the FB_CSMRn_V field.
mbed_official 146:f64d43ff0c18 192 #define BR_FB_CSMRn_V(n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_V))
mbed_official 146:f64d43ff0c18 193 #endif
mbed_official 146:f64d43ff0c18 194
mbed_official 146:f64d43ff0c18 195 //! @brief Format value for bitfield FB_CSMRn_V.
mbed_official 146:f64d43ff0c18 196 #define BF_FB_CSMRn_V(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSMRn_V), uint32_t) & BM_FB_CSMRn_V)
mbed_official 146:f64d43ff0c18 197
mbed_official 146:f64d43ff0c18 198 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 199 //! @brief Set the V field to a new value.
mbed_official 146:f64d43ff0c18 200 #define BW_FB_CSMRn_V(n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_V) = (v))
mbed_official 146:f64d43ff0c18 201 #endif
mbed_official 146:f64d43ff0c18 202 //@}
mbed_official 146:f64d43ff0c18 203
mbed_official 146:f64d43ff0c18 204 /*!
mbed_official 146:f64d43ff0c18 205 * @name Register FB_CSMRn, field WP[8] (RW)
mbed_official 146:f64d43ff0c18 206 *
mbed_official 146:f64d43ff0c18 207 * Controls write accesses to the address range in the corresponding CSAR.
mbed_official 146:f64d43ff0c18 208 *
mbed_official 146:f64d43ff0c18 209 * Values:
mbed_official 146:f64d43ff0c18 210 * - 0 - Write accesses are allowed.
mbed_official 146:f64d43ff0c18 211 * - 1 - Write accesses are not allowed. Attempting to write to the range of
mbed_official 146:f64d43ff0c18 212 * addresses for which the WP bit is set results in a bus error termination of
mbed_official 146:f64d43ff0c18 213 * the internal cycle and no external cycle.
mbed_official 146:f64d43ff0c18 214 */
mbed_official 146:f64d43ff0c18 215 //@{
mbed_official 146:f64d43ff0c18 216 #define BP_FB_CSMRn_WP (8U) //!< Bit position for FB_CSMRn_WP.
mbed_official 146:f64d43ff0c18 217 #define BM_FB_CSMRn_WP (0x00000100U) //!< Bit mask for FB_CSMRn_WP.
mbed_official 146:f64d43ff0c18 218 #define BS_FB_CSMRn_WP (1U) //!< Bit field size in bits for FB_CSMRn_WP.
mbed_official 146:f64d43ff0c18 219
mbed_official 146:f64d43ff0c18 220 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 221 //! @brief Read current value of the FB_CSMRn_WP field.
mbed_official 146:f64d43ff0c18 222 #define BR_FB_CSMRn_WP(n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_WP))
mbed_official 146:f64d43ff0c18 223 #endif
mbed_official 146:f64d43ff0c18 224
mbed_official 146:f64d43ff0c18 225 //! @brief Format value for bitfield FB_CSMRn_WP.
mbed_official 146:f64d43ff0c18 226 #define BF_FB_CSMRn_WP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSMRn_WP), uint32_t) & BM_FB_CSMRn_WP)
mbed_official 146:f64d43ff0c18 227
mbed_official 146:f64d43ff0c18 228 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 229 //! @brief Set the WP field to a new value.
mbed_official 146:f64d43ff0c18 230 #define BW_FB_CSMRn_WP(n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_WP) = (v))
mbed_official 146:f64d43ff0c18 231 #endif
mbed_official 146:f64d43ff0c18 232 //@}
mbed_official 146:f64d43ff0c18 233
mbed_official 146:f64d43ff0c18 234 /*!
mbed_official 146:f64d43ff0c18 235 * @name Register FB_CSMRn, field BAM[31:16] (RW)
mbed_official 146:f64d43ff0c18 236 *
mbed_official 146:f64d43ff0c18 237 * Defines the associated chip-select's block size by masking address bits.
mbed_official 146:f64d43ff0c18 238 *
mbed_official 146:f64d43ff0c18 239 * Values:
mbed_official 146:f64d43ff0c18 240 * - 0 - The corresponding address bit in CSAR is used in the chip-select decode.
mbed_official 146:f64d43ff0c18 241 * - 1 - The corresponding address bit in CSAR is a don't care in the
mbed_official 146:f64d43ff0c18 242 * chip-select decode.
mbed_official 146:f64d43ff0c18 243 */
mbed_official 146:f64d43ff0c18 244 //@{
mbed_official 146:f64d43ff0c18 245 #define BP_FB_CSMRn_BAM (16U) //!< Bit position for FB_CSMRn_BAM.
mbed_official 146:f64d43ff0c18 246 #define BM_FB_CSMRn_BAM (0xFFFF0000U) //!< Bit mask for FB_CSMRn_BAM.
mbed_official 146:f64d43ff0c18 247 #define BS_FB_CSMRn_BAM (16U) //!< Bit field size in bits for FB_CSMRn_BAM.
mbed_official 146:f64d43ff0c18 248
mbed_official 146:f64d43ff0c18 249 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 250 //! @brief Read current value of the FB_CSMRn_BAM field.
mbed_official 146:f64d43ff0c18 251 #define BR_FB_CSMRn_BAM(n) (HW_FB_CSMRn(n).B.BAM)
mbed_official 146:f64d43ff0c18 252 #endif
mbed_official 146:f64d43ff0c18 253
mbed_official 146:f64d43ff0c18 254 //! @brief Format value for bitfield FB_CSMRn_BAM.
mbed_official 146:f64d43ff0c18 255 #define BF_FB_CSMRn_BAM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSMRn_BAM), uint32_t) & BM_FB_CSMRn_BAM)
mbed_official 146:f64d43ff0c18 256
mbed_official 146:f64d43ff0c18 257 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 258 //! @brief Set the BAM field to a new value.
mbed_official 146:f64d43ff0c18 259 #define BW_FB_CSMRn_BAM(n, v) (HW_FB_CSMRn_WR(n, (HW_FB_CSMRn_RD(n) & ~BM_FB_CSMRn_BAM) | BF_FB_CSMRn_BAM(v)))
mbed_official 146:f64d43ff0c18 260 #endif
mbed_official 146:f64d43ff0c18 261 //@}
mbed_official 146:f64d43ff0c18 262 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 263 // HW_FB_CSCRn - Chip Select Control Register
mbed_official 146:f64d43ff0c18 264 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 265
mbed_official 146:f64d43ff0c18 266 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 267 /*!
mbed_official 146:f64d43ff0c18 268 * @brief HW_FB_CSCRn - Chip Select Control Register (RW)
mbed_official 146:f64d43ff0c18 269 *
mbed_official 146:f64d43ff0c18 270 * Reset value: 0x003FFC00U
mbed_official 146:f64d43ff0c18 271 *
mbed_official 146:f64d43ff0c18 272 * Controls the auto-acknowledge, address setup and hold times, port size, burst
mbed_official 146:f64d43ff0c18 273 * capability, and number of wait states for the associated chip select. To
mbed_official 146:f64d43ff0c18 274 * support the global chip-select (FB_CS0), the CSCR0 reset values differ from the
mbed_official 146:f64d43ff0c18 275 * other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3
mbed_official 146:f64d43ff0c18 276 * are chip-dependent Bits 3-0 are 0b See the chip configuration details for your
mbed_official 146:f64d43ff0c18 277 * particular chip for information on the exact CSCR0 reset value.
mbed_official 146:f64d43ff0c18 278 */
mbed_official 146:f64d43ff0c18 279 typedef union _hw_fb_cscrn
mbed_official 146:f64d43ff0c18 280 {
mbed_official 146:f64d43ff0c18 281 uint32_t U;
mbed_official 146:f64d43ff0c18 282 struct _hw_fb_cscrn_bitfields
mbed_official 146:f64d43ff0c18 283 {
mbed_official 146:f64d43ff0c18 284 uint32_t RESERVED0 : 3; //!< [2:0]
mbed_official 146:f64d43ff0c18 285 uint32_t BSTW : 1; //!< [3] Burst-Write Enable
mbed_official 146:f64d43ff0c18 286 uint32_t BSTR : 1; //!< [4] Burst-Read Enable
mbed_official 146:f64d43ff0c18 287 uint32_t BEM : 1; //!< [5] Byte-Enable Mode
mbed_official 146:f64d43ff0c18 288 uint32_t PS : 2; //!< [7:6] Port Size
mbed_official 146:f64d43ff0c18 289 uint32_t AA : 1; //!< [8] Auto-Acknowledge Enable
mbed_official 146:f64d43ff0c18 290 uint32_t BLS : 1; //!< [9] Byte-Lane Shift
mbed_official 146:f64d43ff0c18 291 uint32_t WS : 6; //!< [15:10] Wait States
mbed_official 146:f64d43ff0c18 292 uint32_t WRAH : 2; //!< [17:16] Write Address Hold or Deselect
mbed_official 146:f64d43ff0c18 293 uint32_t RDAH : 2; //!< [19:18] Read Address Hold or Deselect
mbed_official 146:f64d43ff0c18 294 uint32_t ASET : 2; //!< [21:20] Address Setup
mbed_official 146:f64d43ff0c18 295 uint32_t EXTS : 1; //!< [22]
mbed_official 146:f64d43ff0c18 296 uint32_t SWSEN : 1; //!< [23] Secondary Wait State Enable
mbed_official 146:f64d43ff0c18 297 uint32_t RESERVED1 : 2; //!< [25:24]
mbed_official 146:f64d43ff0c18 298 uint32_t SWS : 6; //!< [31:26] Secondary Wait States
mbed_official 146:f64d43ff0c18 299 } B;
mbed_official 146:f64d43ff0c18 300 } hw_fb_cscrn_t;
mbed_official 146:f64d43ff0c18 301 #endif
mbed_official 146:f64d43ff0c18 302
mbed_official 146:f64d43ff0c18 303 /*!
mbed_official 146:f64d43ff0c18 304 * @name Constants and macros for entire FB_CSCRn register
mbed_official 146:f64d43ff0c18 305 */
mbed_official 146:f64d43ff0c18 306 //@{
mbed_official 146:f64d43ff0c18 307 #define HW_FB_CSCRn_COUNT (6U)
mbed_official 146:f64d43ff0c18 308
mbed_official 146:f64d43ff0c18 309 #define HW_FB_CSCRn_ADDR(n) (REGS_FB_BASE + 0x8U + (0xCU * n))
mbed_official 146:f64d43ff0c18 310
mbed_official 146:f64d43ff0c18 311 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 312 #define HW_FB_CSCRn(n) (*(__IO hw_fb_cscrn_t *) HW_FB_CSCRn_ADDR(n))
mbed_official 146:f64d43ff0c18 313 #define HW_FB_CSCRn_RD(n) (HW_FB_CSCRn(n).U)
mbed_official 146:f64d43ff0c18 314 #define HW_FB_CSCRn_WR(n, v) (HW_FB_CSCRn(n).U = (v))
mbed_official 146:f64d43ff0c18 315 #define HW_FB_CSCRn_SET(n, v) (HW_FB_CSCRn_WR(n, HW_FB_CSCRn_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 316 #define HW_FB_CSCRn_CLR(n, v) (HW_FB_CSCRn_WR(n, HW_FB_CSCRn_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 317 #define HW_FB_CSCRn_TOG(n, v) (HW_FB_CSCRn_WR(n, HW_FB_CSCRn_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 318 #endif
mbed_official 146:f64d43ff0c18 319 //@}
mbed_official 146:f64d43ff0c18 320
mbed_official 146:f64d43ff0c18 321 /*
mbed_official 146:f64d43ff0c18 322 * Constants & macros for individual FB_CSCRn bitfields
mbed_official 146:f64d43ff0c18 323 */
mbed_official 146:f64d43ff0c18 324
mbed_official 146:f64d43ff0c18 325 /*!
mbed_official 146:f64d43ff0c18 326 * @name Register FB_CSCRn, field BSTW[3] (RW)
mbed_official 146:f64d43ff0c18 327 *
mbed_official 146:f64d43ff0c18 328 * Specifies whether burst writes are enabled for memory associated with each
mbed_official 146:f64d43ff0c18 329 * chip select.
mbed_official 146:f64d43ff0c18 330 *
mbed_official 146:f64d43ff0c18 331 * Values:
mbed_official 146:f64d43ff0c18 332 * - 0 - Disabled. Data exceeding the specified port size is broken into
mbed_official 146:f64d43ff0c18 333 * individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit
mbed_official 146:f64d43ff0c18 334 * port takes four byte writes.
mbed_official 146:f64d43ff0c18 335 * - 1 - Enabled. Enables burst write of data larger than the specified port
mbed_official 146:f64d43ff0c18 336 * size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit
mbed_official 146:f64d43ff0c18 337 * ports, and line writes to 8-, 16-, and 32-bit ports.
mbed_official 146:f64d43ff0c18 338 */
mbed_official 146:f64d43ff0c18 339 //@{
mbed_official 146:f64d43ff0c18 340 #define BP_FB_CSCRn_BSTW (3U) //!< Bit position for FB_CSCRn_BSTW.
mbed_official 146:f64d43ff0c18 341 #define BM_FB_CSCRn_BSTW (0x00000008U) //!< Bit mask for FB_CSCRn_BSTW.
mbed_official 146:f64d43ff0c18 342 #define BS_FB_CSCRn_BSTW (1U) //!< Bit field size in bits for FB_CSCRn_BSTW.
mbed_official 146:f64d43ff0c18 343
mbed_official 146:f64d43ff0c18 344 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 345 //! @brief Read current value of the FB_CSCRn_BSTW field.
mbed_official 146:f64d43ff0c18 346 #define BR_FB_CSCRn_BSTW(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTW))
mbed_official 146:f64d43ff0c18 347 #endif
mbed_official 146:f64d43ff0c18 348
mbed_official 146:f64d43ff0c18 349 //! @brief Format value for bitfield FB_CSCRn_BSTW.
mbed_official 146:f64d43ff0c18 350 #define BF_FB_CSCRn_BSTW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BSTW), uint32_t) & BM_FB_CSCRn_BSTW)
mbed_official 146:f64d43ff0c18 351
mbed_official 146:f64d43ff0c18 352 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 353 //! @brief Set the BSTW field to a new value.
mbed_official 146:f64d43ff0c18 354 #define BW_FB_CSCRn_BSTW(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTW) = (v))
mbed_official 146:f64d43ff0c18 355 #endif
mbed_official 146:f64d43ff0c18 356 //@}
mbed_official 146:f64d43ff0c18 357
mbed_official 146:f64d43ff0c18 358 /*!
mbed_official 146:f64d43ff0c18 359 * @name Register FB_CSCRn, field BSTR[4] (RW)
mbed_official 146:f64d43ff0c18 360 *
mbed_official 146:f64d43ff0c18 361 * Specifies whether burst reads are enabled for memory associated with each
mbed_official 146:f64d43ff0c18 362 * chip select.
mbed_official 146:f64d43ff0c18 363 *
mbed_official 146:f64d43ff0c18 364 * Values:
mbed_official 146:f64d43ff0c18 365 * - 0 - Disabled. Data exceeding the specified port size is broken into
mbed_official 146:f64d43ff0c18 366 * individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit
mbed_official 146:f64d43ff0c18 367 * port is broken into four 8-bit reads.
mbed_official 146:f64d43ff0c18 368 * - 1 - Enabled. Enables data burst reads larger than the specified port size,
mbed_official 146:f64d43ff0c18 369 * including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit
mbed_official 146:f64d43ff0c18 370 * ports, and line reads from 8-, 16-, and 32-bit ports.
mbed_official 146:f64d43ff0c18 371 */
mbed_official 146:f64d43ff0c18 372 //@{
mbed_official 146:f64d43ff0c18 373 #define BP_FB_CSCRn_BSTR (4U) //!< Bit position for FB_CSCRn_BSTR.
mbed_official 146:f64d43ff0c18 374 #define BM_FB_CSCRn_BSTR (0x00000010U) //!< Bit mask for FB_CSCRn_BSTR.
mbed_official 146:f64d43ff0c18 375 #define BS_FB_CSCRn_BSTR (1U) //!< Bit field size in bits for FB_CSCRn_BSTR.
mbed_official 146:f64d43ff0c18 376
mbed_official 146:f64d43ff0c18 377 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 378 //! @brief Read current value of the FB_CSCRn_BSTR field.
mbed_official 146:f64d43ff0c18 379 #define BR_FB_CSCRn_BSTR(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTR))
mbed_official 146:f64d43ff0c18 380 #endif
mbed_official 146:f64d43ff0c18 381
mbed_official 146:f64d43ff0c18 382 //! @brief Format value for bitfield FB_CSCRn_BSTR.
mbed_official 146:f64d43ff0c18 383 #define BF_FB_CSCRn_BSTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BSTR), uint32_t) & BM_FB_CSCRn_BSTR)
mbed_official 146:f64d43ff0c18 384
mbed_official 146:f64d43ff0c18 385 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 386 //! @brief Set the BSTR field to a new value.
mbed_official 146:f64d43ff0c18 387 #define BW_FB_CSCRn_BSTR(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTR) = (v))
mbed_official 146:f64d43ff0c18 388 #endif
mbed_official 146:f64d43ff0c18 389 //@}
mbed_official 146:f64d43ff0c18 390
mbed_official 146:f64d43ff0c18 391 /*!
mbed_official 146:f64d43ff0c18 392 * @name Register FB_CSCRn, field BEM[5] (RW)
mbed_official 146:f64d43ff0c18 393 *
mbed_official 146:f64d43ff0c18 394 * Specifies whether the corresponding FB_BE is asserted for read accesses.
mbed_official 146:f64d43ff0c18 395 * Certain memories have byte enables that must be asserted during reads and writes.
mbed_official 146:f64d43ff0c18 396 * Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode
mbed_official 146:f64d43ff0c18 397 * of byte enable support for these SRAMs.
mbed_official 146:f64d43ff0c18 398 *
mbed_official 146:f64d43ff0c18 399 * Values:
mbed_official 146:f64d43ff0c18 400 * - 0 - FB_BE is asserted for data write only.
mbed_official 146:f64d43ff0c18 401 * - 1 - FB_BE is asserted for data read and write accesses.
mbed_official 146:f64d43ff0c18 402 */
mbed_official 146:f64d43ff0c18 403 //@{
mbed_official 146:f64d43ff0c18 404 #define BP_FB_CSCRn_BEM (5U) //!< Bit position for FB_CSCRn_BEM.
mbed_official 146:f64d43ff0c18 405 #define BM_FB_CSCRn_BEM (0x00000020U) //!< Bit mask for FB_CSCRn_BEM.
mbed_official 146:f64d43ff0c18 406 #define BS_FB_CSCRn_BEM (1U) //!< Bit field size in bits for FB_CSCRn_BEM.
mbed_official 146:f64d43ff0c18 407
mbed_official 146:f64d43ff0c18 408 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 409 //! @brief Read current value of the FB_CSCRn_BEM field.
mbed_official 146:f64d43ff0c18 410 #define BR_FB_CSCRn_BEM(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BEM))
mbed_official 146:f64d43ff0c18 411 #endif
mbed_official 146:f64d43ff0c18 412
mbed_official 146:f64d43ff0c18 413 //! @brief Format value for bitfield FB_CSCRn_BEM.
mbed_official 146:f64d43ff0c18 414 #define BF_FB_CSCRn_BEM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BEM), uint32_t) & BM_FB_CSCRn_BEM)
mbed_official 146:f64d43ff0c18 415
mbed_official 146:f64d43ff0c18 416 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 417 //! @brief Set the BEM field to a new value.
mbed_official 146:f64d43ff0c18 418 #define BW_FB_CSCRn_BEM(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BEM) = (v))
mbed_official 146:f64d43ff0c18 419 #endif
mbed_official 146:f64d43ff0c18 420 //@}
mbed_official 146:f64d43ff0c18 421
mbed_official 146:f64d43ff0c18 422 /*!
mbed_official 146:f64d43ff0c18 423 * @name Register FB_CSCRn, field PS[7:6] (RW)
mbed_official 146:f64d43ff0c18 424 *
mbed_official 146:f64d43ff0c18 425 * Specifies the data port width of the associated chip-select, and determines
mbed_official 146:f64d43ff0c18 426 * where data is driven during write cycles and where data is sampled during read
mbed_official 146:f64d43ff0c18 427 * cycles.
mbed_official 146:f64d43ff0c18 428 *
mbed_official 146:f64d43ff0c18 429 * Values:
mbed_official 146:f64d43ff0c18 430 * - 00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0].
mbed_official 146:f64d43ff0c18 431 * - 01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when
mbed_official 146:f64d43ff0c18 432 * BLS is 0b, or FB_D[7:0] when BLS is 1b.
mbed_official 146:f64d43ff0c18 433 */
mbed_official 146:f64d43ff0c18 434 //@{
mbed_official 146:f64d43ff0c18 435 #define BP_FB_CSCRn_PS (6U) //!< Bit position for FB_CSCRn_PS.
mbed_official 146:f64d43ff0c18 436 #define BM_FB_CSCRn_PS (0x000000C0U) //!< Bit mask for FB_CSCRn_PS.
mbed_official 146:f64d43ff0c18 437 #define BS_FB_CSCRn_PS (2U) //!< Bit field size in bits for FB_CSCRn_PS.
mbed_official 146:f64d43ff0c18 438
mbed_official 146:f64d43ff0c18 439 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 440 //! @brief Read current value of the FB_CSCRn_PS field.
mbed_official 146:f64d43ff0c18 441 #define BR_FB_CSCRn_PS(n) (HW_FB_CSCRn(n).B.PS)
mbed_official 146:f64d43ff0c18 442 #endif
mbed_official 146:f64d43ff0c18 443
mbed_official 146:f64d43ff0c18 444 //! @brief Format value for bitfield FB_CSCRn_PS.
mbed_official 146:f64d43ff0c18 445 #define BF_FB_CSCRn_PS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_PS), uint32_t) & BM_FB_CSCRn_PS)
mbed_official 146:f64d43ff0c18 446
mbed_official 146:f64d43ff0c18 447 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 448 //! @brief Set the PS field to a new value.
mbed_official 146:f64d43ff0c18 449 #define BW_FB_CSCRn_PS(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_PS) | BF_FB_CSCRn_PS(v)))
mbed_official 146:f64d43ff0c18 450 #endif
mbed_official 146:f64d43ff0c18 451 //@}
mbed_official 146:f64d43ff0c18 452
mbed_official 146:f64d43ff0c18 453 /*!
mbed_official 146:f64d43ff0c18 454 * @name Register FB_CSCRn, field AA[8] (RW)
mbed_official 146:f64d43ff0c18 455 *
mbed_official 146:f64d43ff0c18 456 * Asserts the internal transfer acknowledge for accesses specified by the
mbed_official 146:f64d43ff0c18 457 * chip-select address. If AA is 1b for a corresponding FB_CSn and the external system
mbed_official 146:f64d43ff0c18 458 * asserts an external FB_TA before the wait-state countdown asserts the
mbed_official 146:f64d43ff0c18 459 * internal FB_TA, the cycle is terminated. Burst cycles increment the address bus
mbed_official 146:f64d43ff0c18 460 * between each internal termination. This field must be 1b if CSPMCR disables FB_TA.
mbed_official 146:f64d43ff0c18 461 *
mbed_official 146:f64d43ff0c18 462 * Values:
mbed_official 146:f64d43ff0c18 463 * - 0 - Disabled. No internal transfer acknowledge is asserted and the cycle is
mbed_official 146:f64d43ff0c18 464 * terminated externally.
mbed_official 146:f64d43ff0c18 465 * - 1 - Enabled. Internal transfer acknowledge is asserted as specified by WS.
mbed_official 146:f64d43ff0c18 466 */
mbed_official 146:f64d43ff0c18 467 //@{
mbed_official 146:f64d43ff0c18 468 #define BP_FB_CSCRn_AA (8U) //!< Bit position for FB_CSCRn_AA.
mbed_official 146:f64d43ff0c18 469 #define BM_FB_CSCRn_AA (0x00000100U) //!< Bit mask for FB_CSCRn_AA.
mbed_official 146:f64d43ff0c18 470 #define BS_FB_CSCRn_AA (1U) //!< Bit field size in bits for FB_CSCRn_AA.
mbed_official 146:f64d43ff0c18 471
mbed_official 146:f64d43ff0c18 472 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 473 //! @brief Read current value of the FB_CSCRn_AA field.
mbed_official 146:f64d43ff0c18 474 #define BR_FB_CSCRn_AA(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_AA))
mbed_official 146:f64d43ff0c18 475 #endif
mbed_official 146:f64d43ff0c18 476
mbed_official 146:f64d43ff0c18 477 //! @brief Format value for bitfield FB_CSCRn_AA.
mbed_official 146:f64d43ff0c18 478 #define BF_FB_CSCRn_AA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_AA), uint32_t) & BM_FB_CSCRn_AA)
mbed_official 146:f64d43ff0c18 479
mbed_official 146:f64d43ff0c18 480 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 481 //! @brief Set the AA field to a new value.
mbed_official 146:f64d43ff0c18 482 #define BW_FB_CSCRn_AA(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_AA) = (v))
mbed_official 146:f64d43ff0c18 483 #endif
mbed_official 146:f64d43ff0c18 484 //@}
mbed_official 146:f64d43ff0c18 485
mbed_official 146:f64d43ff0c18 486 /*!
mbed_official 146:f64d43ff0c18 487 * @name Register FB_CSCRn, field BLS[9] (RW)
mbed_official 146:f64d43ff0c18 488 *
mbed_official 146:f64d43ff0c18 489 * Specifies if data on FB_AD appears left-aligned or right-aligned during the
mbed_official 146:f64d43ff0c18 490 * data phase of a FlexBus access.
mbed_official 146:f64d43ff0c18 491 *
mbed_official 146:f64d43ff0c18 492 * Values:
mbed_official 146:f64d43ff0c18 493 * - 0 - Not shifted. Data is left-aligned on FB_AD.
mbed_official 146:f64d43ff0c18 494 * - 1 - Shifted. Data is right-aligned on FB_AD.
mbed_official 146:f64d43ff0c18 495 */
mbed_official 146:f64d43ff0c18 496 //@{
mbed_official 146:f64d43ff0c18 497 #define BP_FB_CSCRn_BLS (9U) //!< Bit position for FB_CSCRn_BLS.
mbed_official 146:f64d43ff0c18 498 #define BM_FB_CSCRn_BLS (0x00000200U) //!< Bit mask for FB_CSCRn_BLS.
mbed_official 146:f64d43ff0c18 499 #define BS_FB_CSCRn_BLS (1U) //!< Bit field size in bits for FB_CSCRn_BLS.
mbed_official 146:f64d43ff0c18 500
mbed_official 146:f64d43ff0c18 501 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 502 //! @brief Read current value of the FB_CSCRn_BLS field.
mbed_official 146:f64d43ff0c18 503 #define BR_FB_CSCRn_BLS(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BLS))
mbed_official 146:f64d43ff0c18 504 #endif
mbed_official 146:f64d43ff0c18 505
mbed_official 146:f64d43ff0c18 506 //! @brief Format value for bitfield FB_CSCRn_BLS.
mbed_official 146:f64d43ff0c18 507 #define BF_FB_CSCRn_BLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BLS), uint32_t) & BM_FB_CSCRn_BLS)
mbed_official 146:f64d43ff0c18 508
mbed_official 146:f64d43ff0c18 509 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 510 //! @brief Set the BLS field to a new value.
mbed_official 146:f64d43ff0c18 511 #define BW_FB_CSCRn_BLS(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BLS) = (v))
mbed_official 146:f64d43ff0c18 512 #endif
mbed_official 146:f64d43ff0c18 513 //@}
mbed_official 146:f64d43ff0c18 514
mbed_official 146:f64d43ff0c18 515 /*!
mbed_official 146:f64d43ff0c18 516 * @name Register FB_CSCRn, field WS[15:10] (RW)
mbed_official 146:f64d43ff0c18 517 *
mbed_official 146:f64d43ff0c18 518 * Specifies the number of wait states inserted after FlexBus asserts the
mbed_official 146:f64d43ff0c18 519 * associated chip-select and before an internal transfer acknowledge is generated (WS
mbed_official 146:f64d43ff0c18 520 * = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states).
mbed_official 146:f64d43ff0c18 521 */
mbed_official 146:f64d43ff0c18 522 //@{
mbed_official 146:f64d43ff0c18 523 #define BP_FB_CSCRn_WS (10U) //!< Bit position for FB_CSCRn_WS.
mbed_official 146:f64d43ff0c18 524 #define BM_FB_CSCRn_WS (0x0000FC00U) //!< Bit mask for FB_CSCRn_WS.
mbed_official 146:f64d43ff0c18 525 #define BS_FB_CSCRn_WS (6U) //!< Bit field size in bits for FB_CSCRn_WS.
mbed_official 146:f64d43ff0c18 526
mbed_official 146:f64d43ff0c18 527 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 528 //! @brief Read current value of the FB_CSCRn_WS field.
mbed_official 146:f64d43ff0c18 529 #define BR_FB_CSCRn_WS(n) (HW_FB_CSCRn(n).B.WS)
mbed_official 146:f64d43ff0c18 530 #endif
mbed_official 146:f64d43ff0c18 531
mbed_official 146:f64d43ff0c18 532 //! @brief Format value for bitfield FB_CSCRn_WS.
mbed_official 146:f64d43ff0c18 533 #define BF_FB_CSCRn_WS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_WS), uint32_t) & BM_FB_CSCRn_WS)
mbed_official 146:f64d43ff0c18 534
mbed_official 146:f64d43ff0c18 535 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 536 //! @brief Set the WS field to a new value.
mbed_official 146:f64d43ff0c18 537 #define BW_FB_CSCRn_WS(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_WS) | BF_FB_CSCRn_WS(v)))
mbed_official 146:f64d43ff0c18 538 #endif
mbed_official 146:f64d43ff0c18 539 //@}
mbed_official 146:f64d43ff0c18 540
mbed_official 146:f64d43ff0c18 541 /*!
mbed_official 146:f64d43ff0c18 542 * @name Register FB_CSCRn, field WRAH[17:16] (RW)
mbed_official 146:f64d43ff0c18 543 *
mbed_official 146:f64d43ff0c18 544 * Controls the address, data, and attribute hold time after the termination of
mbed_official 146:f64d43ff0c18 545 * a write cycle that hits in the associated chip-select's address space. The
mbed_official 146:f64d43ff0c18 546 * hold time applies only at the end of a transfer. Therefore, during a burst
mbed_official 146:f64d43ff0c18 547 * transfer or a transfer to a port size smaller than the transfer size, the hold time
mbed_official 146:f64d43ff0c18 548 * is only added after the last bus cycle.
mbed_official 146:f64d43ff0c18 549 *
mbed_official 146:f64d43ff0c18 550 * Values:
mbed_official 146:f64d43ff0c18 551 * - 00 - 1 cycle (default for all but FB_CS0 )
mbed_official 146:f64d43ff0c18 552 * - 01 - 2 cycles
mbed_official 146:f64d43ff0c18 553 * - 10 - 3 cycles
mbed_official 146:f64d43ff0c18 554 * - 11 - 4 cycles (default for FB_CS0 )
mbed_official 146:f64d43ff0c18 555 */
mbed_official 146:f64d43ff0c18 556 //@{
mbed_official 146:f64d43ff0c18 557 #define BP_FB_CSCRn_WRAH (16U) //!< Bit position for FB_CSCRn_WRAH.
mbed_official 146:f64d43ff0c18 558 #define BM_FB_CSCRn_WRAH (0x00030000U) //!< Bit mask for FB_CSCRn_WRAH.
mbed_official 146:f64d43ff0c18 559 #define BS_FB_CSCRn_WRAH (2U) //!< Bit field size in bits for FB_CSCRn_WRAH.
mbed_official 146:f64d43ff0c18 560
mbed_official 146:f64d43ff0c18 561 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 562 //! @brief Read current value of the FB_CSCRn_WRAH field.
mbed_official 146:f64d43ff0c18 563 #define BR_FB_CSCRn_WRAH(n) (HW_FB_CSCRn(n).B.WRAH)
mbed_official 146:f64d43ff0c18 564 #endif
mbed_official 146:f64d43ff0c18 565
mbed_official 146:f64d43ff0c18 566 //! @brief Format value for bitfield FB_CSCRn_WRAH.
mbed_official 146:f64d43ff0c18 567 #define BF_FB_CSCRn_WRAH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_WRAH), uint32_t) & BM_FB_CSCRn_WRAH)
mbed_official 146:f64d43ff0c18 568
mbed_official 146:f64d43ff0c18 569 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 570 //! @brief Set the WRAH field to a new value.
mbed_official 146:f64d43ff0c18 571 #define BW_FB_CSCRn_WRAH(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_WRAH) | BF_FB_CSCRn_WRAH(v)))
mbed_official 146:f64d43ff0c18 572 #endif
mbed_official 146:f64d43ff0c18 573 //@}
mbed_official 146:f64d43ff0c18 574
mbed_official 146:f64d43ff0c18 575 /*!
mbed_official 146:f64d43ff0c18 576 * @name Register FB_CSCRn, field RDAH[19:18] (RW)
mbed_official 146:f64d43ff0c18 577 *
mbed_official 146:f64d43ff0c18 578 * Controls the address and attribute hold time after the termination during a
mbed_official 146:f64d43ff0c18 579 * read cycle that hits in the associated chip-select's address space. The hold
mbed_official 146:f64d43ff0c18 580 * time applies only at the end of a transfer. Therefore, during a burst transfer
mbed_official 146:f64d43ff0c18 581 * or a transfer to a port size smaller than the transfer size, the hold time is
mbed_official 146:f64d43ff0c18 582 * only added after the last bus cycle. The number of cycles the address and
mbed_official 146:f64d43ff0c18 583 * attributes are held after FB_CSn deassertion depends on the value of the AA bit.
mbed_official 146:f64d43ff0c18 584 *
mbed_official 146:f64d43ff0c18 585 * Values:
mbed_official 146:f64d43ff0c18 586 * - 00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
mbed_official 146:f64d43ff0c18 587 * - 01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
mbed_official 146:f64d43ff0c18 588 * - 10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
mbed_official 146:f64d43ff0c18 589 * - 11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
mbed_official 146:f64d43ff0c18 590 */
mbed_official 146:f64d43ff0c18 591 //@{
mbed_official 146:f64d43ff0c18 592 #define BP_FB_CSCRn_RDAH (18U) //!< Bit position for FB_CSCRn_RDAH.
mbed_official 146:f64d43ff0c18 593 #define BM_FB_CSCRn_RDAH (0x000C0000U) //!< Bit mask for FB_CSCRn_RDAH.
mbed_official 146:f64d43ff0c18 594 #define BS_FB_CSCRn_RDAH (2U) //!< Bit field size in bits for FB_CSCRn_RDAH.
mbed_official 146:f64d43ff0c18 595
mbed_official 146:f64d43ff0c18 596 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 597 //! @brief Read current value of the FB_CSCRn_RDAH field.
mbed_official 146:f64d43ff0c18 598 #define BR_FB_CSCRn_RDAH(n) (HW_FB_CSCRn(n).B.RDAH)
mbed_official 146:f64d43ff0c18 599 #endif
mbed_official 146:f64d43ff0c18 600
mbed_official 146:f64d43ff0c18 601 //! @brief Format value for bitfield FB_CSCRn_RDAH.
mbed_official 146:f64d43ff0c18 602 #define BF_FB_CSCRn_RDAH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_RDAH), uint32_t) & BM_FB_CSCRn_RDAH)
mbed_official 146:f64d43ff0c18 603
mbed_official 146:f64d43ff0c18 604 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 605 //! @brief Set the RDAH field to a new value.
mbed_official 146:f64d43ff0c18 606 #define BW_FB_CSCRn_RDAH(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_RDAH) | BF_FB_CSCRn_RDAH(v)))
mbed_official 146:f64d43ff0c18 607 #endif
mbed_official 146:f64d43ff0c18 608 //@}
mbed_official 146:f64d43ff0c18 609
mbed_official 146:f64d43ff0c18 610 /*!
mbed_official 146:f64d43ff0c18 611 * @name Register FB_CSCRn, field ASET[21:20] (RW)
mbed_official 146:f64d43ff0c18 612 *
mbed_official 146:f64d43ff0c18 613 * Controls when the chip-select is asserted with respect to assertion of a
mbed_official 146:f64d43ff0c18 614 * valid address and attributes.
mbed_official 146:f64d43ff0c18 615 *
mbed_official 146:f64d43ff0c18 616 * Values:
mbed_official 146:f64d43ff0c18 617 * - 00 - Assert FB_CSn on the first rising clock edge after the address is
mbed_official 146:f64d43ff0c18 618 * asserted (default for all but FB_CS0 ).
mbed_official 146:f64d43ff0c18 619 * - 01 - Assert FB_CSn on the second rising clock edge after the address is
mbed_official 146:f64d43ff0c18 620 * asserted.
mbed_official 146:f64d43ff0c18 621 * - 10 - Assert FB_CSn on the third rising clock edge after the address is
mbed_official 146:f64d43ff0c18 622 * asserted.
mbed_official 146:f64d43ff0c18 623 * - 11 - Assert FB_CSn on the fourth rising clock edge after the address is
mbed_official 146:f64d43ff0c18 624 * asserted (default for FB_CS0 ).
mbed_official 146:f64d43ff0c18 625 */
mbed_official 146:f64d43ff0c18 626 //@{
mbed_official 146:f64d43ff0c18 627 #define BP_FB_CSCRn_ASET (20U) //!< Bit position for FB_CSCRn_ASET.
mbed_official 146:f64d43ff0c18 628 #define BM_FB_CSCRn_ASET (0x00300000U) //!< Bit mask for FB_CSCRn_ASET.
mbed_official 146:f64d43ff0c18 629 #define BS_FB_CSCRn_ASET (2U) //!< Bit field size in bits for FB_CSCRn_ASET.
mbed_official 146:f64d43ff0c18 630
mbed_official 146:f64d43ff0c18 631 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 632 //! @brief Read current value of the FB_CSCRn_ASET field.
mbed_official 146:f64d43ff0c18 633 #define BR_FB_CSCRn_ASET(n) (HW_FB_CSCRn(n).B.ASET)
mbed_official 146:f64d43ff0c18 634 #endif
mbed_official 146:f64d43ff0c18 635
mbed_official 146:f64d43ff0c18 636 //! @brief Format value for bitfield FB_CSCRn_ASET.
mbed_official 146:f64d43ff0c18 637 #define BF_FB_CSCRn_ASET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_ASET), uint32_t) & BM_FB_CSCRn_ASET)
mbed_official 146:f64d43ff0c18 638
mbed_official 146:f64d43ff0c18 639 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 640 //! @brief Set the ASET field to a new value.
mbed_official 146:f64d43ff0c18 641 #define BW_FB_CSCRn_ASET(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_ASET) | BF_FB_CSCRn_ASET(v)))
mbed_official 146:f64d43ff0c18 642 #endif
mbed_official 146:f64d43ff0c18 643 //@}
mbed_official 146:f64d43ff0c18 644
mbed_official 146:f64d43ff0c18 645 /*!
mbed_official 146:f64d43ff0c18 646 * @name Register FB_CSCRn, field EXTS[22] (RW)
mbed_official 146:f64d43ff0c18 647 *
mbed_official 146:f64d43ff0c18 648 * Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS
mbed_official 146:f64d43ff0c18 649 * /FB_ALE is asserted.
mbed_official 146:f64d43ff0c18 650 *
mbed_official 146:f64d43ff0c18 651 * Values:
mbed_official 146:f64d43ff0c18 652 * - 0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
mbed_official 146:f64d43ff0c18 653 * - 1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive clock
mbed_official 146:f64d43ff0c18 654 * edge after FB_CSn asserts.
mbed_official 146:f64d43ff0c18 655 */
mbed_official 146:f64d43ff0c18 656 //@{
mbed_official 146:f64d43ff0c18 657 #define BP_FB_CSCRn_EXTS (22U) //!< Bit position for FB_CSCRn_EXTS.
mbed_official 146:f64d43ff0c18 658 #define BM_FB_CSCRn_EXTS (0x00400000U) //!< Bit mask for FB_CSCRn_EXTS.
mbed_official 146:f64d43ff0c18 659 #define BS_FB_CSCRn_EXTS (1U) //!< Bit field size in bits for FB_CSCRn_EXTS.
mbed_official 146:f64d43ff0c18 660
mbed_official 146:f64d43ff0c18 661 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 662 //! @brief Read current value of the FB_CSCRn_EXTS field.
mbed_official 146:f64d43ff0c18 663 #define BR_FB_CSCRn_EXTS(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_EXTS))
mbed_official 146:f64d43ff0c18 664 #endif
mbed_official 146:f64d43ff0c18 665
mbed_official 146:f64d43ff0c18 666 //! @brief Format value for bitfield FB_CSCRn_EXTS.
mbed_official 146:f64d43ff0c18 667 #define BF_FB_CSCRn_EXTS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_EXTS), uint32_t) & BM_FB_CSCRn_EXTS)
mbed_official 146:f64d43ff0c18 668
mbed_official 146:f64d43ff0c18 669 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 670 //! @brief Set the EXTS field to a new value.
mbed_official 146:f64d43ff0c18 671 #define BW_FB_CSCRn_EXTS(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_EXTS) = (v))
mbed_official 146:f64d43ff0c18 672 #endif
mbed_official 146:f64d43ff0c18 673 //@}
mbed_official 146:f64d43ff0c18 674
mbed_official 146:f64d43ff0c18 675 /*!
mbed_official 146:f64d43ff0c18 676 * @name Register FB_CSCRn, field SWSEN[23] (RW)
mbed_official 146:f64d43ff0c18 677 *
mbed_official 146:f64d43ff0c18 678 * Values:
mbed_official 146:f64d43ff0c18 679 * - 0 - Disabled. A number of wait states (specified by WS) are inserted before
mbed_official 146:f64d43ff0c18 680 * an internal transfer acknowledge is generated for all transfers.
mbed_official 146:f64d43ff0c18 681 * - 1 - Enabled. A number of wait states (specified by SWS) are inserted before
mbed_official 146:f64d43ff0c18 682 * an internal transfer acknowledge is generated for burst transfer
mbed_official 146:f64d43ff0c18 683 * secondary terminations.
mbed_official 146:f64d43ff0c18 684 */
mbed_official 146:f64d43ff0c18 685 //@{
mbed_official 146:f64d43ff0c18 686 #define BP_FB_CSCRn_SWSEN (23U) //!< Bit position for FB_CSCRn_SWSEN.
mbed_official 146:f64d43ff0c18 687 #define BM_FB_CSCRn_SWSEN (0x00800000U) //!< Bit mask for FB_CSCRn_SWSEN.
mbed_official 146:f64d43ff0c18 688 #define BS_FB_CSCRn_SWSEN (1U) //!< Bit field size in bits for FB_CSCRn_SWSEN.
mbed_official 146:f64d43ff0c18 689
mbed_official 146:f64d43ff0c18 690 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 691 //! @brief Read current value of the FB_CSCRn_SWSEN field.
mbed_official 146:f64d43ff0c18 692 #define BR_FB_CSCRn_SWSEN(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_SWSEN))
mbed_official 146:f64d43ff0c18 693 #endif
mbed_official 146:f64d43ff0c18 694
mbed_official 146:f64d43ff0c18 695 //! @brief Format value for bitfield FB_CSCRn_SWSEN.
mbed_official 146:f64d43ff0c18 696 #define BF_FB_CSCRn_SWSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_SWSEN), uint32_t) & BM_FB_CSCRn_SWSEN)
mbed_official 146:f64d43ff0c18 697
mbed_official 146:f64d43ff0c18 698 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 699 //! @brief Set the SWSEN field to a new value.
mbed_official 146:f64d43ff0c18 700 #define BW_FB_CSCRn_SWSEN(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_SWSEN) = (v))
mbed_official 146:f64d43ff0c18 701 #endif
mbed_official 146:f64d43ff0c18 702 //@}
mbed_official 146:f64d43ff0c18 703
mbed_official 146:f64d43ff0c18 704 /*!
mbed_official 146:f64d43ff0c18 705 * @name Register FB_CSCRn, field SWS[31:26] (RW)
mbed_official 146:f64d43ff0c18 706 *
mbed_official 146:f64d43ff0c18 707 * Used only when the SWSEN bit is 1b. Specifies the number of wait states
mbed_official 146:f64d43ff0c18 708 * inserted before an internal transfer acknowledge is generated for a burst transfer
mbed_official 146:f64d43ff0c18 709 * (except for the first termination, which is controlled by WS).
mbed_official 146:f64d43ff0c18 710 */
mbed_official 146:f64d43ff0c18 711 //@{
mbed_official 146:f64d43ff0c18 712 #define BP_FB_CSCRn_SWS (26U) //!< Bit position for FB_CSCRn_SWS.
mbed_official 146:f64d43ff0c18 713 #define BM_FB_CSCRn_SWS (0xFC000000U) //!< Bit mask for FB_CSCRn_SWS.
mbed_official 146:f64d43ff0c18 714 #define BS_FB_CSCRn_SWS (6U) //!< Bit field size in bits for FB_CSCRn_SWS.
mbed_official 146:f64d43ff0c18 715
mbed_official 146:f64d43ff0c18 716 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 717 //! @brief Read current value of the FB_CSCRn_SWS field.
mbed_official 146:f64d43ff0c18 718 #define BR_FB_CSCRn_SWS(n) (HW_FB_CSCRn(n).B.SWS)
mbed_official 146:f64d43ff0c18 719 #endif
mbed_official 146:f64d43ff0c18 720
mbed_official 146:f64d43ff0c18 721 //! @brief Format value for bitfield FB_CSCRn_SWS.
mbed_official 146:f64d43ff0c18 722 #define BF_FB_CSCRn_SWS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_SWS), uint32_t) & BM_FB_CSCRn_SWS)
mbed_official 146:f64d43ff0c18 723
mbed_official 146:f64d43ff0c18 724 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 725 //! @brief Set the SWS field to a new value.
mbed_official 146:f64d43ff0c18 726 #define BW_FB_CSCRn_SWS(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_SWS) | BF_FB_CSCRn_SWS(v)))
mbed_official 146:f64d43ff0c18 727 #endif
mbed_official 146:f64d43ff0c18 728 //@}
mbed_official 146:f64d43ff0c18 729
mbed_official 146:f64d43ff0c18 730 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 731 // HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
mbed_official 146:f64d43ff0c18 732 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 733
mbed_official 146:f64d43ff0c18 734 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 735 /*!
mbed_official 146:f64d43ff0c18 736 * @brief HW_FB_CSPMCR - Chip Select port Multiplexing Control Register (RW)
mbed_official 146:f64d43ff0c18 737 *
mbed_official 146:f64d43ff0c18 738 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 739 *
mbed_official 146:f64d43ff0c18 740 * Controls the multiplexing of the FlexBus signals. A bus error occurs when you
mbed_official 146:f64d43ff0c18 741 * do any of the following: Write to a reserved address Write to a reserved
mbed_official 146:f64d43ff0c18 742 * field in this register, or Access this register using a size other than 32 bits.
mbed_official 146:f64d43ff0c18 743 */
mbed_official 146:f64d43ff0c18 744 typedef union _hw_fb_cspmcr
mbed_official 146:f64d43ff0c18 745 {
mbed_official 146:f64d43ff0c18 746 uint32_t U;
mbed_official 146:f64d43ff0c18 747 struct _hw_fb_cspmcr_bitfields
mbed_official 146:f64d43ff0c18 748 {
mbed_official 146:f64d43ff0c18 749 uint32_t RESERVED0 : 12; //!< [11:0]
mbed_official 146:f64d43ff0c18 750 uint32_t GROUP5 : 4; //!< [15:12] FlexBus Signal Group 5 Multiplex
mbed_official 146:f64d43ff0c18 751 //! control
mbed_official 146:f64d43ff0c18 752 uint32_t GROUP4 : 4; //!< [19:16] FlexBus Signal Group 4 Multiplex
mbed_official 146:f64d43ff0c18 753 //! control
mbed_official 146:f64d43ff0c18 754 uint32_t GROUP3 : 4; //!< [23:20] FlexBus Signal Group 3 Multiplex
mbed_official 146:f64d43ff0c18 755 //! control
mbed_official 146:f64d43ff0c18 756 uint32_t GROUP2 : 4; //!< [27:24] FlexBus Signal Group 2 Multiplex
mbed_official 146:f64d43ff0c18 757 //! control
mbed_official 146:f64d43ff0c18 758 uint32_t GROUP1 : 4; //!< [31:28] FlexBus Signal Group 1 Multiplex
mbed_official 146:f64d43ff0c18 759 //! control
mbed_official 146:f64d43ff0c18 760 } B;
mbed_official 146:f64d43ff0c18 761 } hw_fb_cspmcr_t;
mbed_official 146:f64d43ff0c18 762 #endif
mbed_official 146:f64d43ff0c18 763
mbed_official 146:f64d43ff0c18 764 /*!
mbed_official 146:f64d43ff0c18 765 * @name Constants and macros for entire FB_CSPMCR register
mbed_official 146:f64d43ff0c18 766 */
mbed_official 146:f64d43ff0c18 767 //@{
mbed_official 146:f64d43ff0c18 768 #define HW_FB_CSPMCR_ADDR (REGS_FB_BASE + 0x60U)
mbed_official 146:f64d43ff0c18 769
mbed_official 146:f64d43ff0c18 770 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 771 #define HW_FB_CSPMCR (*(__IO hw_fb_cspmcr_t *) HW_FB_CSPMCR_ADDR)
mbed_official 146:f64d43ff0c18 772 #define HW_FB_CSPMCR_RD() (HW_FB_CSPMCR.U)
mbed_official 146:f64d43ff0c18 773 #define HW_FB_CSPMCR_WR(v) (HW_FB_CSPMCR.U = (v))
mbed_official 146:f64d43ff0c18 774 #define HW_FB_CSPMCR_SET(v) (HW_FB_CSPMCR_WR(HW_FB_CSPMCR_RD() | (v)))
mbed_official 146:f64d43ff0c18 775 #define HW_FB_CSPMCR_CLR(v) (HW_FB_CSPMCR_WR(HW_FB_CSPMCR_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 776 #define HW_FB_CSPMCR_TOG(v) (HW_FB_CSPMCR_WR(HW_FB_CSPMCR_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 777 #endif
mbed_official 146:f64d43ff0c18 778 //@}
mbed_official 146:f64d43ff0c18 779
mbed_official 146:f64d43ff0c18 780 /*
mbed_official 146:f64d43ff0c18 781 * Constants & macros for individual FB_CSPMCR bitfields
mbed_official 146:f64d43ff0c18 782 */
mbed_official 146:f64d43ff0c18 783
mbed_official 146:f64d43ff0c18 784 /*!
mbed_official 146:f64d43ff0c18 785 * @name Register FB_CSPMCR, field GROUP5[15:12] (RW)
mbed_official 146:f64d43ff0c18 786 *
mbed_official 146:f64d43ff0c18 787 * Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When
mbed_official 146:f64d43ff0c18 788 * GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the
mbed_official 146:f64d43ff0c18 789 * bus hangs during a transfer.
mbed_official 146:f64d43ff0c18 790 *
mbed_official 146:f64d43ff0c18 791 * Values:
mbed_official 146:f64d43ff0c18 792 * - 0000 - FB_TA
mbed_official 146:f64d43ff0c18 793 * - 0001 - FB_CS3 . You must also write 1b to CSCR[AA].
mbed_official 146:f64d43ff0c18 794 * - 0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA].
mbed_official 146:f64d43ff0c18 795 */
mbed_official 146:f64d43ff0c18 796 //@{
mbed_official 146:f64d43ff0c18 797 #define BP_FB_CSPMCR_GROUP5 (12U) //!< Bit position for FB_CSPMCR_GROUP5.
mbed_official 146:f64d43ff0c18 798 #define BM_FB_CSPMCR_GROUP5 (0x0000F000U) //!< Bit mask for FB_CSPMCR_GROUP5.
mbed_official 146:f64d43ff0c18 799 #define BS_FB_CSPMCR_GROUP5 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP5.
mbed_official 146:f64d43ff0c18 800
mbed_official 146:f64d43ff0c18 801 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 802 //! @brief Read current value of the FB_CSPMCR_GROUP5 field.
mbed_official 146:f64d43ff0c18 803 #define BR_FB_CSPMCR_GROUP5 (HW_FB_CSPMCR.B.GROUP5)
mbed_official 146:f64d43ff0c18 804 #endif
mbed_official 146:f64d43ff0c18 805
mbed_official 146:f64d43ff0c18 806 //! @brief Format value for bitfield FB_CSPMCR_GROUP5.
mbed_official 146:f64d43ff0c18 807 #define BF_FB_CSPMCR_GROUP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP5), uint32_t) & BM_FB_CSPMCR_GROUP5)
mbed_official 146:f64d43ff0c18 808
mbed_official 146:f64d43ff0c18 809 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 810 //! @brief Set the GROUP5 field to a new value.
mbed_official 146:f64d43ff0c18 811 #define BW_FB_CSPMCR_GROUP5(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP5) | BF_FB_CSPMCR_GROUP5(v)))
mbed_official 146:f64d43ff0c18 812 #endif
mbed_official 146:f64d43ff0c18 813 //@}
mbed_official 146:f64d43ff0c18 814
mbed_official 146:f64d43ff0c18 815 /*!
mbed_official 146:f64d43ff0c18 816 * @name Register FB_CSPMCR, field GROUP4[19:16] (RW)
mbed_official 146:f64d43ff0c18 817 *
mbed_official 146:f64d43ff0c18 818 * Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals.
mbed_official 146:f64d43ff0c18 819 *
mbed_official 146:f64d43ff0c18 820 * Values:
mbed_official 146:f64d43ff0c18 821 * - 0000 - FB_TBST
mbed_official 146:f64d43ff0c18 822 * - 0001 - FB_CS2
mbed_official 146:f64d43ff0c18 823 * - 0010 - FB_BE_15_8
mbed_official 146:f64d43ff0c18 824 */
mbed_official 146:f64d43ff0c18 825 //@{
mbed_official 146:f64d43ff0c18 826 #define BP_FB_CSPMCR_GROUP4 (16U) //!< Bit position for FB_CSPMCR_GROUP4.
mbed_official 146:f64d43ff0c18 827 #define BM_FB_CSPMCR_GROUP4 (0x000F0000U) //!< Bit mask for FB_CSPMCR_GROUP4.
mbed_official 146:f64d43ff0c18 828 #define BS_FB_CSPMCR_GROUP4 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP4.
mbed_official 146:f64d43ff0c18 829
mbed_official 146:f64d43ff0c18 830 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 831 //! @brief Read current value of the FB_CSPMCR_GROUP4 field.
mbed_official 146:f64d43ff0c18 832 #define BR_FB_CSPMCR_GROUP4 (HW_FB_CSPMCR.B.GROUP4)
mbed_official 146:f64d43ff0c18 833 #endif
mbed_official 146:f64d43ff0c18 834
mbed_official 146:f64d43ff0c18 835 //! @brief Format value for bitfield FB_CSPMCR_GROUP4.
mbed_official 146:f64d43ff0c18 836 #define BF_FB_CSPMCR_GROUP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP4), uint32_t) & BM_FB_CSPMCR_GROUP4)
mbed_official 146:f64d43ff0c18 837
mbed_official 146:f64d43ff0c18 838 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 839 //! @brief Set the GROUP4 field to a new value.
mbed_official 146:f64d43ff0c18 840 #define BW_FB_CSPMCR_GROUP4(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP4) | BF_FB_CSPMCR_GROUP4(v)))
mbed_official 146:f64d43ff0c18 841 #endif
mbed_official 146:f64d43ff0c18 842 //@}
mbed_official 146:f64d43ff0c18 843
mbed_official 146:f64d43ff0c18 844 /*!
mbed_official 146:f64d43ff0c18 845 * @name Register FB_CSPMCR, field GROUP3[23:20] (RW)
mbed_official 146:f64d43ff0c18 846 *
mbed_official 146:f64d43ff0c18 847 * Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals.
mbed_official 146:f64d43ff0c18 848 *
mbed_official 146:f64d43ff0c18 849 * Values:
mbed_official 146:f64d43ff0c18 850 * - 0000 - FB_CS5
mbed_official 146:f64d43ff0c18 851 * - 0001 - FB_TSIZ1
mbed_official 146:f64d43ff0c18 852 * - 0010 - FB_BE_23_16
mbed_official 146:f64d43ff0c18 853 */
mbed_official 146:f64d43ff0c18 854 //@{
mbed_official 146:f64d43ff0c18 855 #define BP_FB_CSPMCR_GROUP3 (20U) //!< Bit position for FB_CSPMCR_GROUP3.
mbed_official 146:f64d43ff0c18 856 #define BM_FB_CSPMCR_GROUP3 (0x00F00000U) //!< Bit mask for FB_CSPMCR_GROUP3.
mbed_official 146:f64d43ff0c18 857 #define BS_FB_CSPMCR_GROUP3 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP3.
mbed_official 146:f64d43ff0c18 858
mbed_official 146:f64d43ff0c18 859 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 860 //! @brief Read current value of the FB_CSPMCR_GROUP3 field.
mbed_official 146:f64d43ff0c18 861 #define BR_FB_CSPMCR_GROUP3 (HW_FB_CSPMCR.B.GROUP3)
mbed_official 146:f64d43ff0c18 862 #endif
mbed_official 146:f64d43ff0c18 863
mbed_official 146:f64d43ff0c18 864 //! @brief Format value for bitfield FB_CSPMCR_GROUP3.
mbed_official 146:f64d43ff0c18 865 #define BF_FB_CSPMCR_GROUP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP3), uint32_t) & BM_FB_CSPMCR_GROUP3)
mbed_official 146:f64d43ff0c18 866
mbed_official 146:f64d43ff0c18 867 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 868 //! @brief Set the GROUP3 field to a new value.
mbed_official 146:f64d43ff0c18 869 #define BW_FB_CSPMCR_GROUP3(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP3) | BF_FB_CSPMCR_GROUP3(v)))
mbed_official 146:f64d43ff0c18 870 #endif
mbed_official 146:f64d43ff0c18 871 //@}
mbed_official 146:f64d43ff0c18 872
mbed_official 146:f64d43ff0c18 873 /*!
mbed_official 146:f64d43ff0c18 874 * @name Register FB_CSPMCR, field GROUP2[27:24] (RW)
mbed_official 146:f64d43ff0c18 875 *
mbed_official 146:f64d43ff0c18 876 * Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals.
mbed_official 146:f64d43ff0c18 877 *
mbed_official 146:f64d43ff0c18 878 * Values:
mbed_official 146:f64d43ff0c18 879 * - 0000 - FB_CS4
mbed_official 146:f64d43ff0c18 880 * - 0001 - FB_TSIZ0
mbed_official 146:f64d43ff0c18 881 * - 0010 - FB_BE_31_24
mbed_official 146:f64d43ff0c18 882 */
mbed_official 146:f64d43ff0c18 883 //@{
mbed_official 146:f64d43ff0c18 884 #define BP_FB_CSPMCR_GROUP2 (24U) //!< Bit position for FB_CSPMCR_GROUP2.
mbed_official 146:f64d43ff0c18 885 #define BM_FB_CSPMCR_GROUP2 (0x0F000000U) //!< Bit mask for FB_CSPMCR_GROUP2.
mbed_official 146:f64d43ff0c18 886 #define BS_FB_CSPMCR_GROUP2 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP2.
mbed_official 146:f64d43ff0c18 887
mbed_official 146:f64d43ff0c18 888 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 889 //! @brief Read current value of the FB_CSPMCR_GROUP2 field.
mbed_official 146:f64d43ff0c18 890 #define BR_FB_CSPMCR_GROUP2 (HW_FB_CSPMCR.B.GROUP2)
mbed_official 146:f64d43ff0c18 891 #endif
mbed_official 146:f64d43ff0c18 892
mbed_official 146:f64d43ff0c18 893 //! @brief Format value for bitfield FB_CSPMCR_GROUP2.
mbed_official 146:f64d43ff0c18 894 #define BF_FB_CSPMCR_GROUP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP2), uint32_t) & BM_FB_CSPMCR_GROUP2)
mbed_official 146:f64d43ff0c18 895
mbed_official 146:f64d43ff0c18 896 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 897 //! @brief Set the GROUP2 field to a new value.
mbed_official 146:f64d43ff0c18 898 #define BW_FB_CSPMCR_GROUP2(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP2) | BF_FB_CSPMCR_GROUP2(v)))
mbed_official 146:f64d43ff0c18 899 #endif
mbed_official 146:f64d43ff0c18 900 //@}
mbed_official 146:f64d43ff0c18 901
mbed_official 146:f64d43ff0c18 902 /*!
mbed_official 146:f64d43ff0c18 903 * @name Register FB_CSPMCR, field GROUP1[31:28] (RW)
mbed_official 146:f64d43ff0c18 904 *
mbed_official 146:f64d43ff0c18 905 * Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals.
mbed_official 146:f64d43ff0c18 906 *
mbed_official 146:f64d43ff0c18 907 * Values:
mbed_official 146:f64d43ff0c18 908 * - 0000 - FB_ALE
mbed_official 146:f64d43ff0c18 909 * - 0001 - FB_CS1
mbed_official 146:f64d43ff0c18 910 * - 0010 - FB_TS
mbed_official 146:f64d43ff0c18 911 */
mbed_official 146:f64d43ff0c18 912 //@{
mbed_official 146:f64d43ff0c18 913 #define BP_FB_CSPMCR_GROUP1 (28U) //!< Bit position for FB_CSPMCR_GROUP1.
mbed_official 146:f64d43ff0c18 914 #define BM_FB_CSPMCR_GROUP1 (0xF0000000U) //!< Bit mask for FB_CSPMCR_GROUP1.
mbed_official 146:f64d43ff0c18 915 #define BS_FB_CSPMCR_GROUP1 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP1.
mbed_official 146:f64d43ff0c18 916
mbed_official 146:f64d43ff0c18 917 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 918 //! @brief Read current value of the FB_CSPMCR_GROUP1 field.
mbed_official 146:f64d43ff0c18 919 #define BR_FB_CSPMCR_GROUP1 (HW_FB_CSPMCR.B.GROUP1)
mbed_official 146:f64d43ff0c18 920 #endif
mbed_official 146:f64d43ff0c18 921
mbed_official 146:f64d43ff0c18 922 //! @brief Format value for bitfield FB_CSPMCR_GROUP1.
mbed_official 146:f64d43ff0c18 923 #define BF_FB_CSPMCR_GROUP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP1), uint32_t) & BM_FB_CSPMCR_GROUP1)
mbed_official 146:f64d43ff0c18 924
mbed_official 146:f64d43ff0c18 925 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 926 //! @brief Set the GROUP1 field to a new value.
mbed_official 146:f64d43ff0c18 927 #define BW_FB_CSPMCR_GROUP1(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP1) | BF_FB_CSPMCR_GROUP1(v)))
mbed_official 146:f64d43ff0c18 928 #endif
mbed_official 146:f64d43ff0c18 929 //@}
mbed_official 146:f64d43ff0c18 930
mbed_official 146:f64d43ff0c18 931 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 932 // hw_fb_t - module struct
mbed_official 146:f64d43ff0c18 933 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 934 /*!
mbed_official 146:f64d43ff0c18 935 * @brief All FB module registers.
mbed_official 146:f64d43ff0c18 936 */
mbed_official 146:f64d43ff0c18 937 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 938 #pragma pack(1)
mbed_official 146:f64d43ff0c18 939 typedef struct _hw_fb
mbed_official 146:f64d43ff0c18 940 {
mbed_official 146:f64d43ff0c18 941 struct {
mbed_official 146:f64d43ff0c18 942 __IO hw_fb_csarn_t CSARn; //!< [0x0] Chip Select Address Register
mbed_official 146:f64d43ff0c18 943 __IO hw_fb_csmrn_t CSMRn; //!< [0x4] Chip Select Mask Register
mbed_official 146:f64d43ff0c18 944 __IO hw_fb_cscrn_t CSCRn; //!< [0x8] Chip Select Control Register
mbed_official 146:f64d43ff0c18 945 } CS[6];
mbed_official 146:f64d43ff0c18 946 uint8_t _reserved0[24];
mbed_official 146:f64d43ff0c18 947 __IO hw_fb_cspmcr_t CSPMCR; //!< [0x60] Chip Select port Multiplexing Control Register
mbed_official 146:f64d43ff0c18 948 } hw_fb_t;
mbed_official 146:f64d43ff0c18 949 #pragma pack()
mbed_official 146:f64d43ff0c18 950
mbed_official 146:f64d43ff0c18 951 //! @brief Macro to access all FB registers.
mbed_official 146:f64d43ff0c18 952 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 146:f64d43ff0c18 953 //! use the '&' operator, like <code>&HW_FB</code>.
mbed_official 146:f64d43ff0c18 954 #define HW_FB (*(hw_fb_t *) REGS_FB_BASE)
mbed_official 146:f64d43ff0c18 955 #endif
mbed_official 146:f64d43ff0c18 956
mbed_official 146:f64d43ff0c18 957 #endif // __HW_FB_REGISTERS_H__
mbed_official 146:f64d43ff0c18 958 // v22/130726/0.9
mbed_official 146:f64d43ff0c18 959 // EOF