mbed-src-kl05 - mbed library sources

Users » shaoziyang » Code » mbed-src-kl05

mbed library sources

targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_rcc.c@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:: shaoziyang
Date:: Sat Sep 13 14:25:46 2014 +0000
Revision:: 323:9e901b0a5aa1
Parent:: 106:ced8cbb51063

test with CLOCK_SETUP = 0

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	76:aeb1df146756	1	/**
mbed_official	76:aeb1df146756	2	******************************************************************************
mbed_official	76:aeb1df146756	3	* @file stm32l1xx_rcc.c
mbed_official	76:aeb1df146756	4	* @author MCD Application Team
mbed_official	80:66393a7b209d	5	* @version V1.3.0
mbed_official	80:66393a7b209d	6	* @date 31-January-2014
mbed_official	76:aeb1df146756	7	* @brief This file provides firmware functions to manage the following
mbed_official	76:aeb1df146756	8	* functionalities of the Reset and clock control (RCC) peripheral:
mbed_official	76:aeb1df146756	9	* + Internal/external clocks, PLL, CSS and MCO configuration
mbed_official	76:aeb1df146756	10	* + System, AHB and APB busses clocks configuration
mbed_official	76:aeb1df146756	11	* + Peripheral clocks configuration
mbed_official	76:aeb1df146756	12	* + Interrupts and flags management
mbed_official	76:aeb1df146756	13	*
mbed_official	76:aeb1df146756	14	@verbatim
mbed_official	76:aeb1df146756	15
mbed_official	76:aeb1df146756	16	===============================================================================
mbed_official	76:aeb1df146756	17	##### RCC specific features #####
mbed_official	76:aeb1df146756	18	===============================================================================
mbed_official	76:aeb1df146756	19	[..] After reset the device is running from MSI (2 MHz) with Flash 0 WS,
mbed_official	76:aeb1df146756	20	all peripherals are off except internal SRAM, Flash and JTAG.
mbed_official	76:aeb1df146756	21	(#) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
mbed_official	76:aeb1df146756	22	all peripherals mapped on these busses are running at MSI speed.
mbed_official	76:aeb1df146756	23	(#) The clock for all peripherals is switched off, except the SRAM and
mbed_official	76:aeb1df146756	24	FLASH.
mbed_official	76:aeb1df146756	25	(#) All GPIOs are in input floating state, except the JTAG pins which
mbed_official	76:aeb1df146756	26	are assigned to be used for debug purpose.
mbed_official	76:aeb1df146756	27	[..] Once the device started from reset, the user application has to:
mbed_official	76:aeb1df146756	28	(#) Configure the clock source to be used to drive the System clock
mbed_official	76:aeb1df146756	29	(if the application needs higher frequency/performance)
mbed_official	76:aeb1df146756	30	(#) Configure the System clock frequency and Flash settings
mbed_official	76:aeb1df146756	31	(#) Configure the AHB and APB busses prescalers
mbed_official	76:aeb1df146756	32	(#) Enable the clock for the peripheral(s) to be used
mbed_official	76:aeb1df146756	33	(#) Configure the clock source(s) for peripherals whose clocks are not
mbed_official	76:aeb1df146756	34	derived from the System clock (ADC, RTC/LCD and IWDG)
mbed_official	76:aeb1df146756	35
mbed_official	76:aeb1df146756	36	@endverbatim
mbed_official	76:aeb1df146756	37
mbed_official	76:aeb1df146756	38	******************************************************************************
mbed_official	76:aeb1df146756	39	* @attention
mbed_official	76:aeb1df146756	40	*
mbed_official	106:ced8cbb51063	41	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	76:aeb1df146756	42	*
mbed_official	106:ced8cbb51063	43	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	106:ced8cbb51063	44	* are permitted provided that the following conditions are met:
mbed_official	106:ced8cbb51063	45	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	106:ced8cbb51063	46	* this list of conditions and the following disclaimer.
mbed_official	106:ced8cbb51063	47	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	106:ced8cbb51063	48	* this list of conditions and the following disclaimer in the documentation
mbed_official	106:ced8cbb51063	49	* and/or other materials provided with the distribution.
mbed_official	106:ced8cbb51063	50	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	106:ced8cbb51063	51	* may be used to endorse or promote products derived from this software
mbed_official	106:ced8cbb51063	52	* without specific prior written permission.
mbed_official	76:aeb1df146756	53	*
mbed_official	106:ced8cbb51063	54	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	106:ced8cbb51063	55	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	106:ced8cbb51063	56	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	106:ced8cbb51063	57	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	106:ced8cbb51063	58	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	106:ced8cbb51063	59	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	106:ced8cbb51063	60	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	106:ced8cbb51063	61	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	106:ced8cbb51063	62	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	106:ced8cbb51063	63	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	76:aeb1df146756	64	*
mbed_official	76:aeb1df146756	65	******************************************************************************
mbed_official	76:aeb1df146756	66	*/
mbed_official	76:aeb1df146756	67
mbed_official	76:aeb1df146756	68	/* Includes ------------------------------------------------------------------*/
mbed_official	76:aeb1df146756	69	#include "stm32l1xx_rcc.h"
mbed_official	76:aeb1df146756	70
mbed_official	76:aeb1df146756	71	/** @addtogroup STM32L1xx_StdPeriph_Driver
mbed_official	76:aeb1df146756	72	* @{
mbed_official	76:aeb1df146756	73	*/
mbed_official	76:aeb1df146756	74
mbed_official	76:aeb1df146756	75	/** @defgroup RCC
mbed_official	76:aeb1df146756	76	* @brief RCC driver modules
mbed_official	76:aeb1df146756	77	* @{
mbed_official	76:aeb1df146756	78	*/
mbed_official	76:aeb1df146756	79
mbed_official	76:aeb1df146756	80	/* Private typedef -----------------------------------------------------------*/
mbed_official	76:aeb1df146756	81	/* Private define ------------------------------------------------------------*/
mbed_official	76:aeb1df146756	82
mbed_official	76:aeb1df146756	83	/* ------------ RCC registers bit address in the alias region ----------- */
mbed_official	76:aeb1df146756	84	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
mbed_official	76:aeb1df146756	85
mbed_official	76:aeb1df146756	86	/* --- CR Register ---*/
mbed_official	76:aeb1df146756	87
mbed_official	76:aeb1df146756	88	/* Alias word address of HSION bit */
mbed_official	76:aeb1df146756	89	#define CR_OFFSET (RCC_OFFSET + 0x00)
mbed_official	76:aeb1df146756	90	#define HSION_BitNumber 0x00
mbed_official	76:aeb1df146756	91	#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
mbed_official	76:aeb1df146756	92
mbed_official	76:aeb1df146756	93	/* Alias word address of MSION bit */
mbed_official	76:aeb1df146756	94	#define MSION_BitNumber 0x08
mbed_official	76:aeb1df146756	95	#define CR_MSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MSION_BitNumber * 4))
mbed_official	76:aeb1df146756	96
mbed_official	76:aeb1df146756	97	/* Alias word address of PLLON bit */
mbed_official	76:aeb1df146756	98	#define PLLON_BitNumber 0x18
mbed_official	76:aeb1df146756	99	#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
mbed_official	76:aeb1df146756	100
mbed_official	76:aeb1df146756	101	/* Alias word address of CSSON bit */
mbed_official	76:aeb1df146756	102	#define CSSON_BitNumber 0x1C
mbed_official	76:aeb1df146756	103	#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
mbed_official	76:aeb1df146756	104
mbed_official	76:aeb1df146756	105	/* --- CSR Register ---*/
mbed_official	76:aeb1df146756	106
mbed_official	76:aeb1df146756	107	/* Alias word address of LSION bit */
mbed_official	76:aeb1df146756	108	#define CSR_OFFSET (RCC_OFFSET + 0x34)
mbed_official	76:aeb1df146756	109	#define LSION_BitNumber 0x00
mbed_official	76:aeb1df146756	110	#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
mbed_official	76:aeb1df146756	111
mbed_official	76:aeb1df146756	112	/* Alias word address of LSECSSON bit */
mbed_official	76:aeb1df146756	113	#define LSECSSON_BitNumber 0x0B
mbed_official	76:aeb1df146756	114	#define CSR_LSECSSON_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSECSSON_BitNumber * 4))
mbed_official	76:aeb1df146756	115
mbed_official	76:aeb1df146756	116	/* Alias word address of RTCEN bit */
mbed_official	76:aeb1df146756	117	#define RTCEN_BitNumber 0x16
mbed_official	76:aeb1df146756	118	#define CSR_RTCEN_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCEN_BitNumber * 4))
mbed_official	76:aeb1df146756	119
mbed_official	76:aeb1df146756	120	/* Alias word address of RTCRST bit */
mbed_official	76:aeb1df146756	121	#define RTCRST_BitNumber 0x17
mbed_official	76:aeb1df146756	122	#define CSR_RTCRST_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCRST_BitNumber * 4))
mbed_official	76:aeb1df146756	123
mbed_official	76:aeb1df146756	124
mbed_official	76:aeb1df146756	125	/* ---------------------- RCC registers mask -------------------------------- */
mbed_official	76:aeb1df146756	126	/* RCC Flag Mask */
mbed_official	76:aeb1df146756	127	#define FLAG_MASK ((uint8_t)0x1F)
mbed_official	76:aeb1df146756	128
mbed_official	76:aeb1df146756	129	/* CR register byte 3 (Bits[23:16]) base address */
mbed_official	76:aeb1df146756	130	#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
mbed_official	76:aeb1df146756	131
mbed_official	76:aeb1df146756	132	/* ICSCR register byte 4 (Bits[31:24]) base address */
mbed_official	76:aeb1df146756	133	#define ICSCR_BYTE4_ADDRESS ((uint32_t)0x40023807)
mbed_official	76:aeb1df146756	134
mbed_official	76:aeb1df146756	135	/* CFGR register byte 3 (Bits[23:16]) base address */
mbed_official	76:aeb1df146756	136	#define CFGR_BYTE3_ADDRESS ((uint32_t)0x4002380A)
mbed_official	76:aeb1df146756	137
mbed_official	76:aeb1df146756	138	/* CFGR register byte 4 (Bits[31:24]) base address */
mbed_official	76:aeb1df146756	139	#define CFGR_BYTE4_ADDRESS ((uint32_t)0x4002380B)
mbed_official	76:aeb1df146756	140
mbed_official	76:aeb1df146756	141	/* CIR register byte 2 (Bits[15:8]) base address */
mbed_official	76:aeb1df146756	142	#define CIR_BYTE2_ADDRESS ((uint32_t)0x4002380D)
mbed_official	76:aeb1df146756	143
mbed_official	76:aeb1df146756	144	/* CIR register byte 3 (Bits[23:16]) base address */
mbed_official	76:aeb1df146756	145	#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002380E)
mbed_official	76:aeb1df146756	146
mbed_official	76:aeb1df146756	147	/* CSR register byte 2 (Bits[15:8]) base address */
mbed_official	76:aeb1df146756	148	#define CSR_BYTE2_ADDRESS ((uint32_t)0x40023835)
mbed_official	76:aeb1df146756	149
mbed_official	76:aeb1df146756	150	/* Private macro -------------------------------------------------------------*/
mbed_official	76:aeb1df146756	151	/* Private variables ---------------------------------------------------------*/
mbed_official	76:aeb1df146756	152
mbed_official	76:aeb1df146756	153	static __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
mbed_official	76:aeb1df146756	154	static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official	76:aeb1df146756	155
mbed_official	76:aeb1df146756	156	/* Private function prototypes -----------------------------------------------*/
mbed_official	76:aeb1df146756	157	/* Private functions ---------------------------------------------------------*/
mbed_official	76:aeb1df146756	158
mbed_official	76:aeb1df146756	159	/** @defgroup RCC_Private_Functions
mbed_official	76:aeb1df146756	160	* @{
mbed_official	76:aeb1df146756	161	*/
mbed_official	76:aeb1df146756	162
mbed_official	76:aeb1df146756	163	/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
mbed_official	76:aeb1df146756	164	* @brief Internal and external clocks, PLL, CSS and MCO configuration functions
mbed_official	76:aeb1df146756	165	*
mbed_official	76:aeb1df146756	166	@verbatim
mbed_official	76:aeb1df146756	167	===============================================================================
mbed_official	76:aeb1df146756	168	##### Internal-external clocks, PLL, CSS and MCO configuration functions #####
mbed_official	76:aeb1df146756	169	===============================================================================
mbed_official	76:aeb1df146756	170	[..] This section provide functions allowing to configure the internal/external
mbed_official	76:aeb1df146756	171	clocks, PLL, CSS and MCO.
mbed_official	76:aeb1df146756	172	(#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly
mbed_official	76:aeb1df146756	173	or through the PLL as System clock source.
mbed_official	76:aeb1df146756	174	(#) MSI (multi-speed internal), multispeed low power RC
mbed_official	76:aeb1df146756	175	(65.536 KHz to 4.194 MHz) MHz used as System clock source.
mbed_official	76:aeb1df146756	176	(#) LSI (low-speed internal), 37 KHz low consumption RC used as IWDG
mbed_official	76:aeb1df146756	177	and/or RTC clock source.
mbed_official	76:aeb1df146756	178	(#) HSE (high-speed external), 1 to 24 MHz crystal oscillator used
mbed_official	76:aeb1df146756	179	directly or through the PLL as System clock source. Can be used
mbed_official	76:aeb1df146756	180	also as RTC clock source.
mbed_official	76:aeb1df146756	181	(#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
mbed_official	76:aeb1df146756	182	(#) PLL (clocked by HSI or HSE), for System clock and USB (48 MHz).
mbed_official	76:aeb1df146756	183	(#) CSS (Clock security system), once enable and if a HSE clock failure
mbed_official	76:aeb1df146756	184	occurs (HSE used directly or through PLL as System clock source),
mbed_official	76:aeb1df146756	185	the System clock is automatically switched to MSI and an interrupt
mbed_official	76:aeb1df146756	186	is generated if enabled.
mbed_official	76:aeb1df146756	187	The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt)
mbed_official	76:aeb1df146756	188	exception vector.
mbed_official	76:aeb1df146756	189	(#) MCO (microcontroller clock output), used to output SYSCLK, HSI, MSI,
mbed_official	76:aeb1df146756	190	HSE, PLL, LSI or LSE clock (through a configurable prescaler) on
mbed_official	76:aeb1df146756	191	PA8 pin.
mbed_official	76:aeb1df146756	192
mbed_official	76:aeb1df146756	193	@endverbatim
mbed_official	76:aeb1df146756	194	* @{
mbed_official	76:aeb1df146756	195	*/
mbed_official	76:aeb1df146756	196
mbed_official	76:aeb1df146756	197	/**
mbed_official	76:aeb1df146756	198	* @brief Resets the RCC clock configuration to the default reset state.
mbed_official	76:aeb1df146756	199	* @note The default reset state of the clock configuration is given below:
mbed_official	76:aeb1df146756	200	* @note MSI ON and used as system clock source (MSI range is not modified
mbed_official	76:aeb1df146756	201	* by this function, it keep the value configured by user application)
mbed_official	76:aeb1df146756	202	* @note HSI, HSE and PLL OFF
mbed_official	76:aeb1df146756	203	* @note AHB, APB1 and APB2 prescaler set to 1.
mbed_official	76:aeb1df146756	204	* @note CSS and MCO OFF
mbed_official	76:aeb1df146756	205	* @note All interrupts disabled
mbed_official	76:aeb1df146756	206	* @note However, this function doesn't modify the configuration of the
mbed_official	76:aeb1df146756	207	* @note Peripheral clocks
mbed_official	76:aeb1df146756	208	* @note LSI, LSE and RTC clocks
mbed_official	76:aeb1df146756	209	* @param None
mbed_official	76:aeb1df146756	210	* @retval None
mbed_official	76:aeb1df146756	211	*/
mbed_official	76:aeb1df146756	212	void RCC_DeInit(void)
mbed_official	76:aeb1df146756	213	{
mbed_official	76:aeb1df146756	214
mbed_official	76:aeb1df146756	215	/* Set MSION bit */
mbed_official	76:aeb1df146756	216	RCC->CR \|= (uint32_t)0x00000100;
mbed_official	76:aeb1df146756	217
mbed_official	76:aeb1df146756	218	/* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
mbed_official	76:aeb1df146756	219	RCC->CFGR &= (uint32_t)0x88FFC00C;
mbed_official	76:aeb1df146756	220
mbed_official	76:aeb1df146756	221	/* Reset HSION, HSEON, CSSON and PLLON bits */
mbed_official	76:aeb1df146756	222	RCC->CR &= (uint32_t)0xEEFEFFFE;
mbed_official	76:aeb1df146756	223
mbed_official	76:aeb1df146756	224	/* Reset HSEBYP bit */
mbed_official	76:aeb1df146756	225	RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official	76:aeb1df146756	226
mbed_official	76:aeb1df146756	227	/* Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
mbed_official	76:aeb1df146756	228	RCC->CFGR &= (uint32_t)0xFF02FFFF;
mbed_official	76:aeb1df146756	229
mbed_official	76:aeb1df146756	230	/* Disable all interrupts */
mbed_official	76:aeb1df146756	231	RCC->CIR = 0x00000000;
mbed_official	76:aeb1df146756	232	}
mbed_official	76:aeb1df146756	233
mbed_official	76:aeb1df146756	234	/**
mbed_official	76:aeb1df146756	235	* @brief Configures the External High Speed oscillator (HSE).
mbed_official	76:aeb1df146756	236	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
mbed_official	76:aeb1df146756	237	* software should wait on HSERDY flag to be set indicating that HSE clock
mbed_official	76:aeb1df146756	238	* is stable and can be used to clock the PLL and/or system clock.
mbed_official	76:aeb1df146756	239	* @note HSE state can not be changed if it is used directly or through the
mbed_official	76:aeb1df146756	240	* PLL as system clock. In this case, you have to select another source
mbed_official	76:aeb1df146756	241	* of the system clock then change the HSE state (ex. disable it).
mbed_official	76:aeb1df146756	242	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	76:aeb1df146756	243	* @note This function reset the CSSON bit, so if the Clock security system(CSS)
mbed_official	76:aeb1df146756	244	* was previously enabled you have to enable it again after calling this
mbed_official	76:aeb1df146756	245	* function.
mbed_official	76:aeb1df146756	246	* @param RCC_HSE: specifies the new state of the HSE.
mbed_official	76:aeb1df146756	247	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	248	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
mbed_official	76:aeb1df146756	249	* 6 HSE oscillator clock cycles.
mbed_official	76:aeb1df146756	250	* @arg RCC_HSE_ON: turn ON the HSE oscillator
mbed_official	76:aeb1df146756	251	* @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
mbed_official	76:aeb1df146756	252	* @retval None
mbed_official	76:aeb1df146756	253	*/
mbed_official	76:aeb1df146756	254	void RCC_HSEConfig(uint8_t RCC_HSE)
mbed_official	76:aeb1df146756	255	{
mbed_official	76:aeb1df146756	256	/* Check the parameters */
mbed_official	76:aeb1df146756	257	assert_param(IS_RCC_HSE(RCC_HSE));
mbed_official	76:aeb1df146756	258
mbed_official	76:aeb1df146756	259	/* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
mbed_official	76:aeb1df146756	260	(__IO uint8_t ) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
mbed_official	76:aeb1df146756	261
mbed_official	76:aeb1df146756	262	/* Set the new HSE configuration -------------------------------------------*/
mbed_official	76:aeb1df146756	263	(__IO uint8_t ) CR_BYTE3_ADDRESS = RCC_HSE;
mbed_official	76:aeb1df146756	264
mbed_official	76:aeb1df146756	265	}
mbed_official	76:aeb1df146756	266
mbed_official	76:aeb1df146756	267	/**
mbed_official	76:aeb1df146756	268	* @brief Waits for HSE start-up.
mbed_official	76:aeb1df146756	269	* @note This functions waits on HSERDY flag to be set and return SUCCESS if
mbed_official	76:aeb1df146756	270	* this flag is set, otherwise returns ERROR if the timeout is reached
mbed_official	76:aeb1df146756	271	* and this flag is not set. The timeout value is defined by the constant
mbed_official	76:aeb1df146756	272	* HSE_STARTUP_TIMEOUT in stm32l1xx.h file. You can tailor it depending
mbed_official	76:aeb1df146756	273	* on the HSE crystal used in your application.
mbed_official	76:aeb1df146756	274	* @param None
mbed_official	76:aeb1df146756	275	* @retval An ErrorStatus enumeration value:
mbed_official	76:aeb1df146756	276	* - SUCCESS: HSE oscillator is stable and ready to use
mbed_official	76:aeb1df146756	277	* - ERROR: HSE oscillator not yet ready
mbed_official	76:aeb1df146756	278	*/
mbed_official	76:aeb1df146756	279	ErrorStatus RCC_WaitForHSEStartUp(void)
mbed_official	76:aeb1df146756	280	{
mbed_official	76:aeb1df146756	281	__IO uint32_t StartUpCounter = 0;
mbed_official	76:aeb1df146756	282	ErrorStatus status = ERROR;
mbed_official	76:aeb1df146756	283	FlagStatus HSEStatus = RESET;
mbed_official	76:aeb1df146756	284
mbed_official	76:aeb1df146756	285	/* Wait till HSE is ready and if timeout is reached exit */
mbed_official	76:aeb1df146756	286	do
mbed_official	76:aeb1df146756	287	{
mbed_official	76:aeb1df146756	288	HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
mbed_official	76:aeb1df146756	289	StartUpCounter++;
mbed_official	76:aeb1df146756	290	} while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
mbed_official	76:aeb1df146756	291
mbed_official	76:aeb1df146756	292	if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
mbed_official	76:aeb1df146756	293	{
mbed_official	76:aeb1df146756	294	status = SUCCESS;
mbed_official	76:aeb1df146756	295	}
mbed_official	76:aeb1df146756	296	else
mbed_official	76:aeb1df146756	297	{
mbed_official	76:aeb1df146756	298	status = ERROR;
mbed_official	76:aeb1df146756	299	}
mbed_official	76:aeb1df146756	300	return (status);
mbed_official	76:aeb1df146756	301	}
mbed_official	76:aeb1df146756	302
mbed_official	76:aeb1df146756	303	/**
mbed_official	76:aeb1df146756	304	* @brief Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
mbed_official	76:aeb1df146756	305	* @note The calibration is used to compensate for the variations in voltage
mbed_official	76:aeb1df146756	306	* and temperature that influence the frequency of the internal MSI RC.
mbed_official	76:aeb1df146756	307	* Refer to the Application Note AN3300 for more details on how to
mbed_official	76:aeb1df146756	308	* calibrate the MSI.
mbed_official	76:aeb1df146756	309	* @param MSICalibrationValue: specifies the MSI calibration trimming value.
mbed_official	76:aeb1df146756	310	* This parameter must be a number between 0 and 0xFF.
mbed_official	76:aeb1df146756	311	* @retval None
mbed_official	76:aeb1df146756	312	*/
mbed_official	76:aeb1df146756	313	void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue)
mbed_official	76:aeb1df146756	314	{
mbed_official	76:aeb1df146756	315
mbed_official	76:aeb1df146756	316	/* Check the parameters */
mbed_official	76:aeb1df146756	317	assert_param(IS_RCC_MSI_CALIBRATION_VALUE(MSICalibrationValue));
mbed_official	76:aeb1df146756	318
mbed_official	76:aeb1df146756	319	(__IO uint8_t ) ICSCR_BYTE4_ADDRESS = MSICalibrationValue;
mbed_official	76:aeb1df146756	320	}
mbed_official	76:aeb1df146756	321
mbed_official	76:aeb1df146756	322	/**
mbed_official	76:aeb1df146756	323	* @brief Configures the Internal Multi Speed oscillator (MSI) clock range.
mbed_official	76:aeb1df146756	324	* @note After restart from Reset or wakeup from STANDBY, the MSI clock is
mbed_official	76:aeb1df146756	325	* around 2.097 MHz. The MSI clock does not change after wake-up from
mbed_official	76:aeb1df146756	326	* STOP mode.
mbed_official	76:aeb1df146756	327	* @note The MSI clock range can be modified on the fly.
mbed_official	76:aeb1df146756	328	* @param RCC_MSIRange: specifies the MSI Clock range.
mbed_official	76:aeb1df146756	329	* This parameter must be one of the following values:
mbed_official	76:aeb1df146756	330	* @arg RCC_MSIRange_0: MSI clock is around 65.536 KHz
mbed_official	76:aeb1df146756	331	* @arg RCC_MSIRange_1: MSI clock is around 131.072 KHz
mbed_official	76:aeb1df146756	332	* @arg RCC_MSIRange_2: MSI clock is around 262.144 KHz
mbed_official	76:aeb1df146756	333	* @arg RCC_MSIRange_3: MSI clock is around 524.288 KHz
mbed_official	76:aeb1df146756	334	* @arg RCC_MSIRange_4: MSI clock is around 1.048 MHz
mbed_official	76:aeb1df146756	335	* @arg RCC_MSIRange_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
mbed_official	76:aeb1df146756	336	* @arg RCC_MSIRange_6: MSI clock is around 4.194 MHz
mbed_official	76:aeb1df146756	337	*
mbed_official	76:aeb1df146756	338	* @retval None
mbed_official	76:aeb1df146756	339	*/
mbed_official	76:aeb1df146756	340	void RCC_MSIRangeConfig(uint32_t RCC_MSIRange)
mbed_official	76:aeb1df146756	341	{
mbed_official	76:aeb1df146756	342	uint32_t tmpreg = 0;
mbed_official	76:aeb1df146756	343
mbed_official	76:aeb1df146756	344	/* Check the parameters */
mbed_official	76:aeb1df146756	345	assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_MSIRange));
mbed_official	76:aeb1df146756	346
mbed_official	76:aeb1df146756	347	tmpreg = RCC->ICSCR;
mbed_official	76:aeb1df146756	348
mbed_official	76:aeb1df146756	349	/* Clear MSIRANGE[2:0] bits */
mbed_official	76:aeb1df146756	350	tmpreg &= ~RCC_ICSCR_MSIRANGE;
mbed_official	76:aeb1df146756	351
mbed_official	76:aeb1df146756	352	/* Set the MSIRANGE[2:0] bits according to RCC_MSIRange value */
mbed_official	76:aeb1df146756	353	tmpreg \|= (uint32_t)RCC_MSIRange;
mbed_official	76:aeb1df146756	354
mbed_official	76:aeb1df146756	355	/* Store the new value */
mbed_official	76:aeb1df146756	356	RCC->ICSCR = tmpreg;
mbed_official	76:aeb1df146756	357	}
mbed_official	76:aeb1df146756	358
mbed_official	76:aeb1df146756	359	/**
mbed_official	76:aeb1df146756	360	* @brief Enables or disables the Internal Multi Speed oscillator (MSI).
mbed_official	76:aeb1df146756	361	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	76:aeb1df146756	362	* It is used (enabled by hardware) as system clock source after
mbed_official	76:aeb1df146756	363	* startup from Reset, wakeup from STOP and STANDBY mode, or in case
mbed_official	76:aeb1df146756	364	* of failure of the HSE used directly or indirectly as system clock
mbed_official	76:aeb1df146756	365	* (if the Clock Security System CSS is enabled).
mbed_official	76:aeb1df146756	366	* @note MSI can not be stopped if it is used as system clock source.
mbed_official	76:aeb1df146756	367	* In this case, you have to select another source of the system
mbed_official	76:aeb1df146756	368	* clock then stop the MSI.
mbed_official	76:aeb1df146756	369	* @note After enabling the MSI, the application software should wait on
mbed_official	76:aeb1df146756	370	* MSIRDY flag to be set indicating that MSI clock is stable and can
mbed_official	76:aeb1df146756	371	* be used as system clock source.
mbed_official	76:aeb1df146756	372	* @param NewState: new state of the MSI.
mbed_official	76:aeb1df146756	373	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	374	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
mbed_official	76:aeb1df146756	375	* clock cycles.
mbed_official	76:aeb1df146756	376	* @retval None
mbed_official	76:aeb1df146756	377	*/
mbed_official	76:aeb1df146756	378	void RCC_MSICmd(FunctionalState NewState)
mbed_official	76:aeb1df146756	379	{
mbed_official	76:aeb1df146756	380	/* Check the parameters */
mbed_official	76:aeb1df146756	381	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	382
mbed_official	76:aeb1df146756	383	(__IO uint32_t ) CR_MSION_BB = (uint32_t)NewState;
mbed_official	76:aeb1df146756	384	}
mbed_official	76:aeb1df146756	385
mbed_official	76:aeb1df146756	386	/**
mbed_official	76:aeb1df146756	387	* @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
mbed_official	76:aeb1df146756	388	* @note The calibration is used to compensate for the variations in voltage
mbed_official	76:aeb1df146756	389	* and temperature that influence the frequency of the internal HSI RC.
mbed_official	76:aeb1df146756	390	* Refer to the Application Note AN3300 for more details on how to
mbed_official	76:aeb1df146756	391	* calibrate the HSI.
mbed_official	76:aeb1df146756	392	* @param HSICalibrationValue: specifies the HSI calibration trimming value.
mbed_official	76:aeb1df146756	393	* This parameter must be a number between 0 and 0x1F.
mbed_official	76:aeb1df146756	394	* @retval None
mbed_official	76:aeb1df146756	395	*/
mbed_official	76:aeb1df146756	396	void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
mbed_official	76:aeb1df146756	397	{
mbed_official	76:aeb1df146756	398	uint32_t tmpreg = 0;
mbed_official	76:aeb1df146756	399
mbed_official	76:aeb1df146756	400	/* Check the parameters */
mbed_official	76:aeb1df146756	401	assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
mbed_official	76:aeb1df146756	402
mbed_official	76:aeb1df146756	403	tmpreg = RCC->ICSCR;
mbed_official	76:aeb1df146756	404
mbed_official	76:aeb1df146756	405	/* Clear HSITRIM[4:0] bits */
mbed_official	76:aeb1df146756	406	tmpreg &= ~RCC_ICSCR_HSITRIM;
mbed_official	76:aeb1df146756	407
mbed_official	76:aeb1df146756	408	/* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
mbed_official	76:aeb1df146756	409	tmpreg \|= (uint32_t)HSICalibrationValue << 8;
mbed_official	76:aeb1df146756	410
mbed_official	76:aeb1df146756	411	/* Store the new value */
mbed_official	76:aeb1df146756	412	RCC->ICSCR = tmpreg;
mbed_official	76:aeb1df146756	413	}
mbed_official	76:aeb1df146756	414
mbed_official	76:aeb1df146756	415	/**
mbed_official	76:aeb1df146756	416	* @brief Enables or disables the Internal High Speed oscillator (HSI).
mbed_official	76:aeb1df146756	417	* @note After enabling the HSI, the application software should wait on
mbed_official	76:aeb1df146756	418	* HSIRDY flag to be set indicating that HSI clock is stable and can
mbed_official	76:aeb1df146756	419	* be used to clock the PLL and/or system clock.
mbed_official	76:aeb1df146756	420	* @note HSI can not be stopped if it is used directly or through the PLL
mbed_official	76:aeb1df146756	421	* as system clock. In this case, you have to select another source
mbed_official	76:aeb1df146756	422	* of the system clock then stop the HSI.
mbed_official	76:aeb1df146756	423	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	76:aeb1df146756	424	* @param NewState: new state of the HSI.
mbed_official	76:aeb1df146756	425	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	426	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
mbed_official	76:aeb1df146756	427	* clock cycles.
mbed_official	76:aeb1df146756	428	* @retval None
mbed_official	76:aeb1df146756	429	*/
mbed_official	76:aeb1df146756	430	void RCC_HSICmd(FunctionalState NewState)
mbed_official	76:aeb1df146756	431	{
mbed_official	76:aeb1df146756	432	/* Check the parameters */
mbed_official	76:aeb1df146756	433	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	434
mbed_official	76:aeb1df146756	435	(__IO uint32_t ) CR_HSION_BB = (uint32_t)NewState;
mbed_official	76:aeb1df146756	436	}
mbed_official	76:aeb1df146756	437
mbed_official	76:aeb1df146756	438	/**
mbed_official	76:aeb1df146756	439	* @brief Configures the External Low Speed oscillator (LSE).
mbed_official	76:aeb1df146756	440	* @note As the LSE is in the RTC domain and write access is denied to this
mbed_official	76:aeb1df146756	441	* domain after reset, you have to enable write access using
mbed_official	76:aeb1df146756	442	* PWR_RTCAccessCmd(ENABLE) function before to configure the LSE
mbed_official	76:aeb1df146756	443	* (to be done once after reset).
mbed_official	76:aeb1df146756	444	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
mbed_official	76:aeb1df146756	445	* software should wait on LSERDY flag to be set indicating that LSE clock
mbed_official	76:aeb1df146756	446	* is stable and can be used to clock the RTC.
mbed_official	76:aeb1df146756	447	* @param RCC_LSE: specifies the new state of the LSE.
mbed_official	76:aeb1df146756	448	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	449	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
mbed_official	76:aeb1df146756	450	* 6 LSE oscillator clock cycles.
mbed_official	76:aeb1df146756	451	* @arg RCC_LSE_ON: turn ON the LSE oscillator
mbed_official	76:aeb1df146756	452	* @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
mbed_official	76:aeb1df146756	453	* @retval None
mbed_official	76:aeb1df146756	454	*/
mbed_official	76:aeb1df146756	455	void RCC_LSEConfig(uint8_t RCC_LSE)
mbed_official	76:aeb1df146756	456	{
mbed_official	76:aeb1df146756	457	/* Check the parameters */
mbed_official	76:aeb1df146756	458	assert_param(IS_RCC_LSE(RCC_LSE));
mbed_official	76:aeb1df146756	459
mbed_official	76:aeb1df146756	460	/* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
mbed_official	76:aeb1df146756	461	(__IO uint8_t ) CSR_BYTE2_ADDRESS = RCC_LSE_OFF;
mbed_official	76:aeb1df146756	462
mbed_official	76:aeb1df146756	463	/* Set the new LSE configuration -------------------------------------------*/
mbed_official	76:aeb1df146756	464	(__IO uint8_t ) CSR_BYTE2_ADDRESS = RCC_LSE;
mbed_official	76:aeb1df146756	465	}
mbed_official	76:aeb1df146756	466
mbed_official	76:aeb1df146756	467	/**
mbed_official	76:aeb1df146756	468	* @brief Enables or disables the Internal Low Speed oscillator (LSI).
mbed_official	76:aeb1df146756	469	* @note After enabling the LSI, the application software should wait on
mbed_official	76:aeb1df146756	470	* LSIRDY flag to be set indicating that LSI clock is stable and can
mbed_official	76:aeb1df146756	471	* be used to clock the IWDG and/or the RTC.
mbed_official	76:aeb1df146756	472	* @note LSI can not be disabled if the IWDG is running.
mbed_official	76:aeb1df146756	473	* @param NewState: new state of the LSI.
mbed_official	76:aeb1df146756	474	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	475	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
mbed_official	76:aeb1df146756	476	* clock cycles.
mbed_official	76:aeb1df146756	477	* @retval None
mbed_official	76:aeb1df146756	478	*/
mbed_official	76:aeb1df146756	479	void RCC_LSICmd(FunctionalState NewState)
mbed_official	76:aeb1df146756	480	{
mbed_official	76:aeb1df146756	481	/* Check the parameters */
mbed_official	76:aeb1df146756	482	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	483
mbed_official	76:aeb1df146756	484	(__IO uint32_t ) CSR_LSION_BB = (uint32_t)NewState;
mbed_official	76:aeb1df146756	485	}
mbed_official	76:aeb1df146756	486
mbed_official	76:aeb1df146756	487	/**
mbed_official	76:aeb1df146756	488	* @brief Configures the PLL clock source and multiplication factor.
mbed_official	76:aeb1df146756	489	* @note This function must be used only when the PLL is disabled.
mbed_official	76:aeb1df146756	490	*
mbed_official	76:aeb1df146756	491	* @param RCC_PLLSource: specifies the PLL entry clock source.
mbed_official	76:aeb1df146756	492	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	493	* @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock source
mbed_official	76:aeb1df146756	494	* @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock source
mbed_official	76:aeb1df146756	495	* @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as
mbed_official	76:aeb1df146756	496	* PLL source).
mbed_official	76:aeb1df146756	497	*
mbed_official	76:aeb1df146756	498	* @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
mbed_official	76:aeb1df146756	499	* This parameter can be:
mbed_official	76:aeb1df146756	500	* @arg RCC_PLLMul_3: PLL clock source multiplied by 3
mbed_official	76:aeb1df146756	501	* @arg RCC_PLLMul_4: PLL clock source multiplied by 4
mbed_official	76:aeb1df146756	502	* @arg RCC_PLLMul_6: PLL clock source multiplied by 6
mbed_official	76:aeb1df146756	503	* @arg RCC_PLLMul_8: PLL clock source multiplied by 8
mbed_official	76:aeb1df146756	504	* @arg RCC_PLLMul_12: PLL clock source multiplied by 12
mbed_official	76:aeb1df146756	505	* @arg RCC_PLLMul_16: PLL clock source multiplied by 16
mbed_official	76:aeb1df146756	506	* @arg RCC_PLLMul_24: PLL clock source multiplied by 24
mbed_official	76:aeb1df146756	507	* @arg RCC_PLLMul_32: PLL clock source multiplied by 32
mbed_official	76:aeb1df146756	508	* @arg RCC_PLLMul_48: PLL clock source multiplied by 48
mbed_official	76:aeb1df146756	509	* @note The application software must set correctly the PLL multiplication
mbed_official	76:aeb1df146756	510	* factor to avoid exceeding:
mbed_official	76:aeb1df146756	511	* - 96 MHz as PLLVCO when the product is in range 1
mbed_official	76:aeb1df146756	512	* - 48 MHz as PLLVCO when the product is in range 2
mbed_official	76:aeb1df146756	513	* - 24 MHz when the product is in range 3
mbed_official	76:aeb1df146756	514	* @note When using the USB the PLLVCO should be 96MHz
mbed_official	76:aeb1df146756	515	*
mbed_official	76:aeb1df146756	516	* @param RCC_PLLDiv: specifies the PLL division factor.
mbed_official	76:aeb1df146756	517	* This parameter can be:
mbed_official	76:aeb1df146756	518	* @arg RCC_PLLDiv_2: PLL Clock output divided by 2
mbed_official	76:aeb1df146756	519	* @arg RCC_PLLDiv_3: PLL Clock output divided by 3
mbed_official	76:aeb1df146756	520	* @arg RCC_PLLDiv_4: PLL Clock output divided by 4
mbed_official	76:aeb1df146756	521	* @note The application software must set correctly the output division to avoid
mbed_official	76:aeb1df146756	522	* exceeding 32 MHz as SYSCLK.
mbed_official	76:aeb1df146756	523	*
mbed_official	76:aeb1df146756	524	* @retval None
mbed_official	76:aeb1df146756	525	*/
mbed_official	76:aeb1df146756	526	void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv)
mbed_official	76:aeb1df146756	527	{
mbed_official	76:aeb1df146756	528	/* Check the parameters */
mbed_official	76:aeb1df146756	529	assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
mbed_official	76:aeb1df146756	530	assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
mbed_official	76:aeb1df146756	531	assert_param(IS_RCC_PLL_DIV(RCC_PLLDiv));
mbed_official	76:aeb1df146756	532
mbed_official	76:aeb1df146756	533	(__IO uint8_t ) CFGR_BYTE3_ADDRESS = (uint8_t)(RCC_PLLSource \| ((uint8_t)(RCC_PLLMul \| (uint8_t)(RCC_PLLDiv))));
mbed_official	76:aeb1df146756	534	}
mbed_official	76:aeb1df146756	535
mbed_official	76:aeb1df146756	536	/**
mbed_official	76:aeb1df146756	537	* @brief Enables or disables the PLL.
mbed_official	76:aeb1df146756	538	* @note After enabling the PLL, the application software should wait on
mbed_official	76:aeb1df146756	539	* PLLRDY flag to be set indicating that PLL clock is stable and can
mbed_official	76:aeb1df146756	540	* be used as system clock source.
mbed_official	76:aeb1df146756	541	* @note The PLL can not be disabled if it is used as system clock source
mbed_official	76:aeb1df146756	542	* @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	76:aeb1df146756	543	* @param NewState: new state of the PLL.
mbed_official	76:aeb1df146756	544	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	545	* @retval None
mbed_official	76:aeb1df146756	546	*/
mbed_official	76:aeb1df146756	547	void RCC_PLLCmd(FunctionalState NewState)
mbed_official	76:aeb1df146756	548	{
mbed_official	76:aeb1df146756	549	/* Check the parameters */
mbed_official	76:aeb1df146756	550	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	551
mbed_official	76:aeb1df146756	552	(__IO uint32_t ) CR_PLLON_BB = (uint32_t)NewState;
mbed_official	76:aeb1df146756	553	}
mbed_official	76:aeb1df146756	554
mbed_official	76:aeb1df146756	555	/**
mbed_official	76:aeb1df146756	556	* @brief Enables or disables the Clock Security System.
mbed_official	76:aeb1df146756	557	* @note If a failure is detected on the HSE oscillator clock, this oscillator
mbed_official	76:aeb1df146756	558	* is automatically disabled and an interrupt is generated to inform the
mbed_official	76:aeb1df146756	559	* software about the failure (Clock Security System Interrupt, CSSI),
mbed_official	76:aeb1df146756	560	* allowing the MCU to perform rescue operations. The CSSI is linked to
mbed_official	76:aeb1df146756	561	* the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
mbed_official	76:aeb1df146756	562	* @param NewState: new state of the Clock Security System.
mbed_official	76:aeb1df146756	563	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	564	* @retval None
mbed_official	76:aeb1df146756	565	*/
mbed_official	76:aeb1df146756	566	void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
mbed_official	76:aeb1df146756	567	{
mbed_official	76:aeb1df146756	568	/* Check the parameters */
mbed_official	76:aeb1df146756	569	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	570
mbed_official	76:aeb1df146756	571	(__IO uint32_t ) CR_CSSON_BB = (uint32_t)NewState;
mbed_official	76:aeb1df146756	572	}
mbed_official	76:aeb1df146756	573
mbed_official	76:aeb1df146756	574	/**
mbed_official	76:aeb1df146756	575	* @brief Enables or disables the LSE Clock Security System.
mbed_official	76:aeb1df146756	576	* @param NewState: new state of the Clock Security System.
mbed_official	76:aeb1df146756	577	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	578	* @retval None
mbed_official	76:aeb1df146756	579	*/
mbed_official	76:aeb1df146756	580	void RCC_LSEClockSecuritySystemCmd(FunctionalState NewState)
mbed_official	76:aeb1df146756	581	{
mbed_official	76:aeb1df146756	582	/* Check the parameters */
mbed_official	76:aeb1df146756	583	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	584
mbed_official	76:aeb1df146756	585	(__IO uint32_t ) CSR_LSECSSON_BB = (uint32_t)NewState;
mbed_official	76:aeb1df146756	586	}
mbed_official	76:aeb1df146756	587
mbed_official	76:aeb1df146756	588	/**
mbed_official	76:aeb1df146756	589	* @brief Selects the clock source to output on MCO pin (PA8).
mbed_official	76:aeb1df146756	590	* @note PA8 should be configured in alternate function mode.
mbed_official	76:aeb1df146756	591	* @param RCC_MCOSource: specifies the clock source to output.
mbed_official	76:aeb1df146756	592	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	593	* @arg RCC_MCOSource_NoClock: No clock selected
mbed_official	76:aeb1df146756	594	* @arg RCC_MCOSource_SYSCLK: System clock selected
mbed_official	76:aeb1df146756	595	* @arg RCC_MCOSource_HSI: HSI oscillator clock selected
mbed_official	76:aeb1df146756	596	* @arg RCC_MCOSource_MSI: MSI oscillator clock selected
mbed_official	76:aeb1df146756	597	* @arg RCC_MCOSource_HSE: HSE oscillator clock selected
mbed_official	76:aeb1df146756	598	* @arg RCC_MCOSource_PLLCLK: PLL clock selected
mbed_official	76:aeb1df146756	599	* @arg RCC_MCOSource_LSI: LSI clock selected
mbed_official	76:aeb1df146756	600	* @arg RCC_MCOSource_LSE: LSE clock selected
mbed_official	76:aeb1df146756	601	* @param RCC_MCODiv: specifies the MCO prescaler.
mbed_official	76:aeb1df146756	602	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	603	* @arg RCC_MCODiv_1: no division applied to MCO clock
mbed_official	76:aeb1df146756	604	* @arg RCC_MCODiv_2: division by 2 applied to MCO clock
mbed_official	76:aeb1df146756	605	* @arg RCC_MCODiv_4: division by 4 applied to MCO clock
mbed_official	76:aeb1df146756	606	* @arg RCC_MCODiv_8: division by 8 applied to MCO clock
mbed_official	76:aeb1df146756	607	* @arg RCC_MCODiv_16: division by 16 applied to MCO clock
mbed_official	76:aeb1df146756	608	* @retval None
mbed_official	76:aeb1df146756	609	*/
mbed_official	76:aeb1df146756	610	void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv)
mbed_official	76:aeb1df146756	611	{
mbed_official	76:aeb1df146756	612	/* Check the parameters */
mbed_official	76:aeb1df146756	613	assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
mbed_official	76:aeb1df146756	614	assert_param(IS_RCC_MCO_DIV(RCC_MCODiv));
mbed_official	76:aeb1df146756	615
mbed_official	76:aeb1df146756	616	/* Select MCO clock source and prescaler */
mbed_official	76:aeb1df146756	617	(__IO uint8_t ) CFGR_BYTE4_ADDRESS = RCC_MCOSource \| RCC_MCODiv;
mbed_official	76:aeb1df146756	618	}
mbed_official	76:aeb1df146756	619
mbed_official	76:aeb1df146756	620	/**
mbed_official	76:aeb1df146756	621	* @}
mbed_official	76:aeb1df146756	622	*/
mbed_official	76:aeb1df146756	623
mbed_official	76:aeb1df146756	624	/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
mbed_official	76:aeb1df146756	625	* @brief System, AHB and APB busses clocks configuration functions
mbed_official	76:aeb1df146756	626	*
mbed_official	76:aeb1df146756	627	@verbatim
mbed_official	76:aeb1df146756	628	===============================================================================
mbed_official	76:aeb1df146756	629	##### System, AHB and APB busses clocks configuration functions #####
mbed_official	76:aeb1df146756	630	===============================================================================
mbed_official	76:aeb1df146756	631	[..] This section provide functions allowing to configure the System, AHB,
mbed_official	76:aeb1df146756	632	APB1 and APB2 busses clocks.
mbed_official	76:aeb1df146756	633	(#) Several clock sources can be used to drive the System clock (SYSCLK):
mbed_official	76:aeb1df146756	634	MSI, HSI, HSE and PLL.
mbed_official	76:aeb1df146756	635	The AHB clock (HCLK) is derived from System clock through configurable
mbed_official	76:aeb1df146756	636	prescaler and used to clock the CPU, memory and peripherals mapped
mbed_official	76:aeb1df146756	637	on AHB bus (DMA and GPIO).APB1 (PCLK1) and APB2 (PCLK2) clocks are
mbed_official	76:aeb1df146756	638	derived from AHB clock through configurable prescalers and used to
mbed_official	76:aeb1df146756	639	clock the peripherals mapped on these busses. You can use
mbed_official	76:aeb1df146756	640	"RCC_GetClocksFreq()" function to retrieve the frequencies of these
mbed_official	76:aeb1df146756	641	clocks.
mbed_official	76:aeb1df146756	642
mbed_official	76:aeb1df146756	643	-@- All the peripheral clocks are derived from the System clock (SYSCLK)
mbed_official	76:aeb1df146756	644	except:
mbed_official	76:aeb1df146756	645	(+@) The USB 48 MHz clock which is derived from the PLL VCO clock.
mbed_official	76:aeb1df146756	646	(+@) The ADC clock which is always the HSI clock. A divider by 1, 2
mbed_official	76:aeb1df146756	647	or 4 allows to adapt the clock frequency to the device operating
mbed_official	76:aeb1df146756	648	conditions.
mbed_official	76:aeb1df146756	649	(+@) The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz
mbed_official	76:aeb1df146756	650	HSE_RTC (HSE divided by a programmable prescaler).
mbed_official	76:aeb1df146756	651	The System clock (SYSCLK) frequency must be higher or equal to
mbed_official	76:aeb1df146756	652	the RTC/LCD clock frequency.
mbed_official	76:aeb1df146756	653	(+@) IWDG clock which is always the LSI clock.
mbed_official	76:aeb1df146756	654
mbed_official	76:aeb1df146756	655	(#) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 32 MHz.
mbed_official	76:aeb1df146756	656	Depending on the device voltage range, the maximum frequency should
mbed_official	76:aeb1df146756	657	be adapted accordingly:
mbed_official	76:aeb1df146756	658
mbed_official	76:aeb1df146756	659	+----------------------------------------------------------------+
mbed_official	76:aeb1df146756	660	\| Wait states \| HCLK clock frequency (MHz) \|
mbed_official	76:aeb1df146756	661	\| \|------------------------------------------------\|
mbed_official	76:aeb1df146756	662	\| (Latency) \| voltage range \| voltage range \|
mbed_official	76:aeb1df146756	663	\| \| 1.65 V - 3.6 V \| 2.0 V - 3.6 V \|
mbed_official	76:aeb1df146756	664	\| \|----------------\|---------------\|---------------\|
mbed_official	76:aeb1df146756	665	\| \| VCORE = 1.2 V \| VCORE = 1.5 V \| VCORE = 1.8 V \|
mbed_official	76:aeb1df146756	666	\|-------------- \|----------------\|---------------\|---------------\|
mbed_official	76:aeb1df146756	667	\|0WS(1CPU cycle)\|0 < HCLK <= 2 \|0 < HCLK <= 8 \|0 < HCLK <= 16 \|
mbed_official	76:aeb1df146756	668	\|---------------\|----------------\|---------------\|---------------\|
mbed_official	76:aeb1df146756	669	\|1WS(2CPU cycle)\|2 < HCLK <= 4 \|8 < HCLK <= 16 \|16 < HCLK <= 32\|
mbed_official	76:aeb1df146756	670	+----------------------------------------------------------------+
mbed_official	76:aeb1df146756	671
mbed_official	76:aeb1df146756	672	(#) After reset, the System clock source is the MSI (2 MHz) with 0 WS,
mbed_official	76:aeb1df146756	673	Flash 32-bit access is enabled and prefetch is disabled.
mbed_official	76:aeb1df146756	674	[..] It is recommended to use the following software sequences to tune the
mbed_official	76:aeb1df146756	675	number of wait states needed to access the Flash memory with the CPU
mbed_official	76:aeb1df146756	676	frequency (HCLK).
mbed_official	76:aeb1df146756	677	(+) Increasing the CPU frequency (in the same voltage range)
mbed_official	76:aeb1df146756	678	(+) Program the Flash 64-bit access, using "FLASH_ReadAccess64Cmd(ENABLE)"
mbed_official	76:aeb1df146756	679	function
mbed_official	76:aeb1df146756	680	(+) Check that 64-bit access is taken into account by reading FLASH_ACR
mbed_official	76:aeb1df146756	681	(+) Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)"
mbed_official	76:aeb1df146756	682	function
mbed_official	76:aeb1df146756	683	(+) Check that the new number of WS is taken into account by reading
mbed_official	76:aeb1df146756	684	FLASH_ACR
mbed_official	76:aeb1df146756	685	(+) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
mbed_official	76:aeb1df146756	686	(+) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()"
mbed_official	76:aeb1df146756	687	function
mbed_official	76:aeb1df146756	688	(+) Check that the new CPU clock source is taken into account by reading
mbed_official	76:aeb1df146756	689	the clock source status, using "RCC_GetSYSCLKSource()" function
mbed_official	76:aeb1df146756	690	(+) Decreasing the CPU frequency (in the same voltage range)
mbed_official	76:aeb1df146756	691	(+) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
mbed_official	76:aeb1df146756	692	(+) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()"
mbed_official	76:aeb1df146756	693	function
mbed_official	76:aeb1df146756	694	(+) Check that the new CPU clock source is taken into account by reading
mbed_official	76:aeb1df146756	695	the clock source status, using "RCC_GetSYSCLKSource()" function
mbed_official	76:aeb1df146756	696	(+) Program the new number of WS, using "FLASH_SetLatency()" function
mbed_official	76:aeb1df146756	697	(+) Check that the new number of WS is taken into account by reading
mbed_official	76:aeb1df146756	698	FLASH_ACR
mbed_official	76:aeb1df146756	699	(+) Enable the Flash 32-bit access, using "FLASH_ReadAccess64Cmd(DISABLE)"
mbed_official	76:aeb1df146756	700	function
mbed_official	76:aeb1df146756	701	(+) Check that 32-bit access is taken into account by reading FLASH_ACR
mbed_official	76:aeb1df146756	702
mbed_official	76:aeb1df146756	703	@endverbatim
mbed_official	76:aeb1df146756	704	* @{
mbed_official	76:aeb1df146756	705	*/
mbed_official	76:aeb1df146756	706
mbed_official	76:aeb1df146756	707	/**
mbed_official	76:aeb1df146756	708	* @brief Configures the system clock (SYSCLK).
mbed_official	76:aeb1df146756	709	* @note The MSI is used (enabled by hardware) as system clock source after
mbed_official	76:aeb1df146756	710	* startup from Reset, wake-up from STOP and STANDBY mode, or in case
mbed_official	76:aeb1df146756	711	* of failure of the HSE used directly or indirectly as system clock
mbed_official	76:aeb1df146756	712	* (if the Clock Security System CSS is enabled).
mbed_official	76:aeb1df146756	713	* @note A switch from one clock source to another occurs only if the target
mbed_official	76:aeb1df146756	714	* clock source is ready (clock stable after startup delay or PLL locked).
mbed_official	76:aeb1df146756	715	* If a clock source which is not yet ready is selected, the switch will
mbed_official	76:aeb1df146756	716	* occur when the clock source will be ready.
mbed_official	76:aeb1df146756	717	* You can use RCC_GetSYSCLKSource() function to know which clock is
mbed_official	76:aeb1df146756	718	* currently used as system clock source.
mbed_official	76:aeb1df146756	719	* @param RCC_SYSCLKSource: specifies the clock source used as system clock source
mbed_official	76:aeb1df146756	720	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	721	* @arg RCC_SYSCLKSource_MSI: MSI selected as system clock source
mbed_official	76:aeb1df146756	722	* @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
mbed_official	76:aeb1df146756	723	* @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
mbed_official	76:aeb1df146756	724	* @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
mbed_official	76:aeb1df146756	725	* @retval None
mbed_official	76:aeb1df146756	726	*/
mbed_official	76:aeb1df146756	727	void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
mbed_official	76:aeb1df146756	728	{
mbed_official	76:aeb1df146756	729	uint32_t tmpreg = 0;
mbed_official	76:aeb1df146756	730
mbed_official	76:aeb1df146756	731	/* Check the parameters */
mbed_official	76:aeb1df146756	732	assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
mbed_official	76:aeb1df146756	733
mbed_official	76:aeb1df146756	734	tmpreg = RCC->CFGR;
mbed_official	76:aeb1df146756	735
mbed_official	76:aeb1df146756	736	/* Clear SW[1:0] bits */
mbed_official	76:aeb1df146756	737	tmpreg &= ~RCC_CFGR_SW;
mbed_official	76:aeb1df146756	738
mbed_official	76:aeb1df146756	739	/* Set SW[1:0] bits according to RCC_SYSCLKSource value */
mbed_official	76:aeb1df146756	740	tmpreg \|= RCC_SYSCLKSource;
mbed_official	76:aeb1df146756	741
mbed_official	76:aeb1df146756	742	/* Store the new value */
mbed_official	76:aeb1df146756	743	RCC->CFGR = tmpreg;
mbed_official	76:aeb1df146756	744	}
mbed_official	76:aeb1df146756	745
mbed_official	76:aeb1df146756	746	/**
mbed_official	76:aeb1df146756	747	* @brief Returns the clock source used as system clock.
mbed_official	76:aeb1df146756	748	* @param None
mbed_official	76:aeb1df146756	749	* @retval The clock source used as system clock. The returned value can be one
mbed_official	76:aeb1df146756	750	* of the following values:
mbed_official	76:aeb1df146756	751	* - 0x00: MSI used as system clock
mbed_official	76:aeb1df146756	752	* - 0x04: HSI used as system clock
mbed_official	76:aeb1df146756	753	* - 0x08: HSE used as system clock
mbed_official	76:aeb1df146756	754	* - 0x0C: PLL used as system clock
mbed_official	76:aeb1df146756	755	*/
mbed_official	76:aeb1df146756	756	uint8_t RCC_GetSYSCLKSource(void)
mbed_official	76:aeb1df146756	757	{
mbed_official	76:aeb1df146756	758	return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
mbed_official	76:aeb1df146756	759	}
mbed_official	76:aeb1df146756	760
mbed_official	76:aeb1df146756	761	/**
mbed_official	76:aeb1df146756	762	* @brief Configures the AHB clock (HCLK).
mbed_official	76:aeb1df146756	763	* @note Depending on the device voltage range, the software has to set correctly
mbed_official	76:aeb1df146756	764	* these bits to ensure that the system frequency does not exceed the
mbed_official	76:aeb1df146756	765	* maximum allowed frequency (for more details refer to section above
mbed_official	76:aeb1df146756	766	* "CPU, AHB and APB busses clocks configuration functions")
mbed_official	76:aeb1df146756	767	* @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
mbed_official	76:aeb1df146756	768	* the system clock (SYSCLK).
mbed_official	76:aeb1df146756	769	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	770	* @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
mbed_official	76:aeb1df146756	771	* @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
mbed_official	76:aeb1df146756	772	* @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
mbed_official	76:aeb1df146756	773	* @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
mbed_official	76:aeb1df146756	774	* @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
mbed_official	76:aeb1df146756	775	* @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
mbed_official	76:aeb1df146756	776	* @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
mbed_official	76:aeb1df146756	777	* @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
mbed_official	76:aeb1df146756	778	* @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
mbed_official	76:aeb1df146756	779	* @retval None
mbed_official	76:aeb1df146756	780	*/
mbed_official	76:aeb1df146756	781	void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
mbed_official	76:aeb1df146756	782	{
mbed_official	76:aeb1df146756	783	uint32_t tmpreg = 0;
mbed_official	76:aeb1df146756	784
mbed_official	76:aeb1df146756	785	/* Check the parameters */
mbed_official	76:aeb1df146756	786	assert_param(IS_RCC_HCLK(RCC_SYSCLK));
mbed_official	76:aeb1df146756	787
mbed_official	76:aeb1df146756	788	tmpreg = RCC->CFGR;
mbed_official	76:aeb1df146756	789
mbed_official	76:aeb1df146756	790	/* Clear HPRE[3:0] bits */
mbed_official	76:aeb1df146756	791	tmpreg &= ~RCC_CFGR_HPRE;
mbed_official	76:aeb1df146756	792
mbed_official	76:aeb1df146756	793	/* Set HPRE[3:0] bits according to RCC_SYSCLK value */
mbed_official	76:aeb1df146756	794	tmpreg \|= RCC_SYSCLK;
mbed_official	76:aeb1df146756	795
mbed_official	76:aeb1df146756	796	/* Store the new value */
mbed_official	76:aeb1df146756	797	RCC->CFGR = tmpreg;
mbed_official	76:aeb1df146756	798	}
mbed_official	76:aeb1df146756	799
mbed_official	76:aeb1df146756	800	/**
mbed_official	76:aeb1df146756	801	* @brief Configures the Low Speed APB clock (PCLK1).
mbed_official	76:aeb1df146756	802	* @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
mbed_official	76:aeb1df146756	803	* the AHB clock (HCLK).
mbed_official	76:aeb1df146756	804	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	805	* @arg RCC_HCLK_Div1: APB1 clock = HCLK
mbed_official	76:aeb1df146756	806	* @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
mbed_official	76:aeb1df146756	807	* @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
mbed_official	76:aeb1df146756	808	* @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
mbed_official	76:aeb1df146756	809	* @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
mbed_official	76:aeb1df146756	810	* @retval None
mbed_official	76:aeb1df146756	811	*/
mbed_official	76:aeb1df146756	812	void RCC_PCLK1Config(uint32_t RCC_HCLK)
mbed_official	76:aeb1df146756	813	{
mbed_official	76:aeb1df146756	814	uint32_t tmpreg = 0;
mbed_official	76:aeb1df146756	815
mbed_official	76:aeb1df146756	816	/* Check the parameters */
mbed_official	76:aeb1df146756	817	assert_param(IS_RCC_PCLK(RCC_HCLK));
mbed_official	76:aeb1df146756	818
mbed_official	76:aeb1df146756	819	tmpreg = RCC->CFGR;
mbed_official	76:aeb1df146756	820
mbed_official	76:aeb1df146756	821	/* Clear PPRE1[2:0] bits */
mbed_official	76:aeb1df146756	822	tmpreg &= ~RCC_CFGR_PPRE1;
mbed_official	76:aeb1df146756	823
mbed_official	76:aeb1df146756	824	/* Set PPRE1[2:0] bits according to RCC_HCLK value */
mbed_official	76:aeb1df146756	825	tmpreg \|= RCC_HCLK;
mbed_official	76:aeb1df146756	826
mbed_official	76:aeb1df146756	827	/* Store the new value */
mbed_official	76:aeb1df146756	828	RCC->CFGR = tmpreg;
mbed_official	76:aeb1df146756	829	}
mbed_official	76:aeb1df146756	830
mbed_official	76:aeb1df146756	831	/**
mbed_official	76:aeb1df146756	832	* @brief Configures the High Speed APB clock (PCLK2).
mbed_official	76:aeb1df146756	833	* @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
mbed_official	76:aeb1df146756	834	* the AHB clock (HCLK).
mbed_official	76:aeb1df146756	835	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	836	* @arg RCC_HCLK_Div1: APB2 clock = HCLK
mbed_official	76:aeb1df146756	837	* @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
mbed_official	76:aeb1df146756	838	* @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
mbed_official	76:aeb1df146756	839	* @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
mbed_official	76:aeb1df146756	840	* @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
mbed_official	76:aeb1df146756	841	* @retval None
mbed_official	76:aeb1df146756	842	*/
mbed_official	76:aeb1df146756	843	void RCC_PCLK2Config(uint32_t RCC_HCLK)
mbed_official	76:aeb1df146756	844	{
mbed_official	76:aeb1df146756	845	uint32_t tmpreg = 0;
mbed_official	76:aeb1df146756	846
mbed_official	76:aeb1df146756	847	/* Check the parameters */
mbed_official	76:aeb1df146756	848	assert_param(IS_RCC_PCLK(RCC_HCLK));
mbed_official	76:aeb1df146756	849
mbed_official	76:aeb1df146756	850	tmpreg = RCC->CFGR;
mbed_official	76:aeb1df146756	851
mbed_official	76:aeb1df146756	852	/* Clear PPRE2[2:0] bits */
mbed_official	76:aeb1df146756	853	tmpreg &= ~RCC_CFGR_PPRE2;
mbed_official	76:aeb1df146756	854
mbed_official	76:aeb1df146756	855	/* Set PPRE2[2:0] bits according to RCC_HCLK value */
mbed_official	76:aeb1df146756	856	tmpreg \|= RCC_HCLK << 3;
mbed_official	76:aeb1df146756	857
mbed_official	76:aeb1df146756	858	/* Store the new value */
mbed_official	76:aeb1df146756	859	RCC->CFGR = tmpreg;
mbed_official	76:aeb1df146756	860	}
mbed_official	76:aeb1df146756	861
mbed_official	76:aeb1df146756	862	/**
mbed_official	76:aeb1df146756	863	* @brief Returns the frequencies of the System, AHB and APB busses clocks.
mbed_official	76:aeb1df146756	864	* @note The frequency returned by this function is not the real frequency
mbed_official	76:aeb1df146756	865	* in the chip. It is calculated based on the predefined constant and
mbed_official	76:aeb1df146756	866	* the source selected by RCC_SYSCLKConfig():
mbed_official	76:aeb1df146756	867	*
mbed_official	76:aeb1df146756	868	* @note If SYSCLK source is MSI, function returns values based on MSI
mbed_official	76:aeb1df146756	869	* Value as defined by the MSI range, refer to RCC_MSIRangeConfig()
mbed_official	76:aeb1df146756	870	*
mbed_official	76:aeb1df146756	871	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
mbed_official	76:aeb1df146756	872	*
mbed_official	76:aeb1df146756	873	* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
mbed_official	76:aeb1df146756	874	*
mbed_official	76:aeb1df146756	875	* @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
mbed_official	76:aeb1df146756	876	* or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official	76:aeb1df146756	877	*
mbed_official	76:aeb1df146756	878	* (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
mbed_official	76:aeb1df146756	879	* 16 MHz) but the real value may vary depending on the variations
mbed_official	76:aeb1df146756	880	* in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().
mbed_official	76:aeb1df146756	881	*
mbed_official	76:aeb1df146756	882	* (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
mbed_official	76:aeb1df146756	883	* 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official	76:aeb1df146756	884	* frequency of the crystal used. Otherwise, this function may
mbed_official	76:aeb1df146756	885	* return wrong result.
mbed_official	76:aeb1df146756	886	*
mbed_official	76:aeb1df146756	887	* - The result of this function could be not correct when using fractional
mbed_official	76:aeb1df146756	888	* value for HSE crystal.
mbed_official	76:aeb1df146756	889	*
mbed_official	76:aeb1df146756	890	* @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
mbed_official	76:aeb1df146756	891	* the clocks frequencies.
mbed_official	76:aeb1df146756	892	*
mbed_official	76:aeb1df146756	893	* @note This function can be used by the user application to compute the
mbed_official	76:aeb1df146756	894	* baudrate for the communication peripherals or configure other parameters.
mbed_official	76:aeb1df146756	895	* @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
mbed_official	76:aeb1df146756	896	* must be called to update the structure's field. Otherwise, any
mbed_official	76:aeb1df146756	897	* configuration based on this function will be incorrect.
mbed_official	76:aeb1df146756	898	*
mbed_official	76:aeb1df146756	899	* @retval None
mbed_official	76:aeb1df146756	900	*/
mbed_official	76:aeb1df146756	901	void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
mbed_official	76:aeb1df146756	902	{
mbed_official	76:aeb1df146756	903	uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, presc = 0, msirange = 0;
mbed_official	76:aeb1df146756	904
mbed_official	76:aeb1df146756	905	/* Get SYSCLK source -------------------------------------------------------*/
mbed_official	76:aeb1df146756	906	tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official	76:aeb1df146756	907
mbed_official	76:aeb1df146756	908	switch (tmp)
mbed_official	76:aeb1df146756	909	{
mbed_official	76:aeb1df146756	910	case 0x00: /* MSI used as system clock */
mbed_official	76:aeb1df146756	911	msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;
mbed_official	76:aeb1df146756	912	RCC_Clocks->SYSCLK_Frequency = (32768 * (1 << (msirange + 1)));
mbed_official	76:aeb1df146756	913	break;
mbed_official	76:aeb1df146756	914	case 0x04: /* HSI used as system clock */
mbed_official	76:aeb1df146756	915	RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
mbed_official	76:aeb1df146756	916	break;
mbed_official	76:aeb1df146756	917	case 0x08: /* HSE used as system clock */
mbed_official	76:aeb1df146756	918	RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
mbed_official	76:aeb1df146756	919	break;
mbed_official	76:aeb1df146756	920	case 0x0C: /* PLL used as system clock */
mbed_official	76:aeb1df146756	921	/* Get PLL clock source and multiplication factor ----------------------*/
mbed_official	76:aeb1df146756	922	pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
mbed_official	76:aeb1df146756	923	plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
mbed_official	76:aeb1df146756	924	pllmul = PLLMulTable[(pllmul >> 18)];
mbed_official	76:aeb1df146756	925	plldiv = (plldiv >> 22) + 1;
mbed_official	76:aeb1df146756	926
mbed_official	76:aeb1df146756	927	pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official	76:aeb1df146756	928
mbed_official	76:aeb1df146756	929	if (pllsource == 0x00)
mbed_official	76:aeb1df146756	930	{
mbed_official	76:aeb1df146756	931	/* HSI oscillator clock selected as PLL clock source */
mbed_official	76:aeb1df146756	932	RCC_Clocks->SYSCLK_Frequency = (((HSI_VALUE) * pllmul) / plldiv);
mbed_official	76:aeb1df146756	933	}
mbed_official	76:aeb1df146756	934	else
mbed_official	76:aeb1df146756	935	{
mbed_official	76:aeb1df146756	936	/* HSE selected as PLL clock source */
mbed_official	76:aeb1df146756	937	RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE) * pllmul) / plldiv);
mbed_official	76:aeb1df146756	938	}
mbed_official	76:aeb1df146756	939	break;
mbed_official	76:aeb1df146756	940	default: /* MSI used as system clock */
mbed_official	76:aeb1df146756	941	msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;
mbed_official	76:aeb1df146756	942	RCC_Clocks->SYSCLK_Frequency = (32768 * (1 << (msirange + 1)));
mbed_official	76:aeb1df146756	943	break;
mbed_official	76:aeb1df146756	944	}
mbed_official	76:aeb1df146756	945	/* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
mbed_official	76:aeb1df146756	946	/* Get HCLK prescaler */
mbed_official	76:aeb1df146756	947	tmp = RCC->CFGR & RCC_CFGR_HPRE;
mbed_official	76:aeb1df146756	948	tmp = tmp >> 4;
mbed_official	76:aeb1df146756	949	presc = APBAHBPrescTable[tmp];
mbed_official	76:aeb1df146756	950	/* HCLK clock frequency */
mbed_official	76:aeb1df146756	951	RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
mbed_official	76:aeb1df146756	952
mbed_official	76:aeb1df146756	953	/* Get PCLK1 prescaler */
mbed_official	76:aeb1df146756	954	tmp = RCC->CFGR & RCC_CFGR_PPRE1;
mbed_official	76:aeb1df146756	955	tmp = tmp >> 8;
mbed_official	76:aeb1df146756	956	presc = APBAHBPrescTable[tmp];
mbed_official	76:aeb1df146756	957	/* PCLK1 clock frequency */
mbed_official	76:aeb1df146756	958	RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
mbed_official	76:aeb1df146756	959
mbed_official	76:aeb1df146756	960	/* Get PCLK2 prescaler */
mbed_official	76:aeb1df146756	961	tmp = RCC->CFGR & RCC_CFGR_PPRE2;
mbed_official	76:aeb1df146756	962	tmp = tmp >> 11;
mbed_official	76:aeb1df146756	963	presc = APBAHBPrescTable[tmp];
mbed_official	76:aeb1df146756	964	/* PCLK2 clock frequency */
mbed_official	76:aeb1df146756	965	RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
mbed_official	76:aeb1df146756	966	}
mbed_official	76:aeb1df146756	967
mbed_official	76:aeb1df146756	968	/**
mbed_official	76:aeb1df146756	969	* @}
mbed_official	76:aeb1df146756	970	*/
mbed_official	76:aeb1df146756	971
mbed_official	76:aeb1df146756	972	/** @defgroup RCC_Group3 Peripheral clocks configuration functions
mbed_official	76:aeb1df146756	973	* @brief Peripheral clocks configuration functions
mbed_official	76:aeb1df146756	974	*
mbed_official	76:aeb1df146756	975	@verbatim
mbed_official	76:aeb1df146756	976	===============================================================================
mbed_official	76:aeb1df146756	977	##### Peripheral clocks configuration functions #####
mbed_official	76:aeb1df146756	978	===============================================================================
mbed_official	76:aeb1df146756	979	[..] This section provide functions allowing to configure the Peripheral clocks.
mbed_official	76:aeb1df146756	980	(#) The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
mbed_official	76:aeb1df146756	981	(HSE divided by a programmable prescaler).
mbed_official	76:aeb1df146756	982	(#) After restart from Reset or wakeup from STANDBY, all peripherals are
mbed_official	76:aeb1df146756	983	off except internal SRAM, Flash and JTAG. Before to start using a
mbed_official	76:aeb1df146756	984	peripheral you have to enable its interface clock. You can do this
mbed_official	76:aeb1df146756	985	using RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and
mbed_official	76:aeb1df146756	986	RCC_APB1PeriphClockCmd() functions.
mbed_official	76:aeb1df146756	987
mbed_official	76:aeb1df146756	988	(#) To reset the peripherals configuration (to the default state after
mbed_official	76:aeb1df146756	989	device reset) you can use RCC_AHBPeriphResetCmd(),
mbed_official	76:aeb1df146756	990	RCC_APB2PeriphResetCmd() and RCC_APB1PeriphResetCmd() functions.
mbed_official	76:aeb1df146756	991	(#) To further reduce power consumption in SLEEP mode the peripheral
mbed_official	76:aeb1df146756	992	clocks can be disabled prior to executing the WFI or WFE instructions.
mbed_official	76:aeb1df146756	993	You can do this using RCC_AHBPeriphClockLPModeCmd(),
mbed_official	76:aeb1df146756	994	RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd()
mbed_official	76:aeb1df146756	995	functions.
mbed_official	76:aeb1df146756	996
mbed_official	76:aeb1df146756	997	@endverbatim
mbed_official	76:aeb1df146756	998	* @{
mbed_official	76:aeb1df146756	999	*/
mbed_official	76:aeb1df146756	1000
mbed_official	76:aeb1df146756	1001	/**
mbed_official	76:aeb1df146756	1002	* @brief Configures the RTC and LCD clock (RTCCLK / LCDCLK).
mbed_official	76:aeb1df146756	1003	* @note As the RTC clock configuration bits are in the RTC domain and write
mbed_official	76:aeb1df146756	1004	* access is denied to this domain after reset, you have to enable write
mbed_official	76:aeb1df146756	1005	* access using PWR_RTCAccessCmd(ENABLE) function before to configure
mbed_official	76:aeb1df146756	1006	* the RTC clock source (to be done once after reset).
mbed_official	76:aeb1df146756	1007	* @note Once the RTC clock is configured it can't be changed unless the RTC
mbed_official	76:aeb1df146756	1008	* is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)
mbed_official	76:aeb1df146756	1009	* @note The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).
mbed_official	76:aeb1df146756	1010	*
mbed_official	76:aeb1df146756	1011	* @param RCC_RTCCLKSource: specifies the RTC clock source.
mbed_official	76:aeb1df146756	1012	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	1013	* @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
mbed_official	76:aeb1df146756	1014	* @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
mbed_official	76:aeb1df146756	1015	* @arg RCC_RTCCLKSource_HSE_Div2: HSE divided by 2 selected as RTC clock
mbed_official	76:aeb1df146756	1016	* @arg RCC_RTCCLKSource_HSE_Div4: HSE divided by 4 selected as RTC clock
mbed_official	76:aeb1df146756	1017	* @arg RCC_RTCCLKSource_HSE_Div8: HSE divided by 8 selected as RTC clock
mbed_official	76:aeb1df146756	1018	* @arg RCC_RTCCLKSource_HSE_Div16: HSE divided by 16 selected as RTC clock
mbed_official	76:aeb1df146756	1019	*
mbed_official	76:aeb1df146756	1020	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
mbed_official	76:aeb1df146756	1021	* work in STOP and STANDBY modes, and can be used as wakeup source.
mbed_official	76:aeb1df146756	1022	* However, when the HSE clock is used as RTC clock source, the RTC
mbed_official	76:aeb1df146756	1023	* cannot be used in STOP and STANDBY modes.
mbed_official	76:aeb1df146756	1024	*
mbed_official	76:aeb1df146756	1025	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
mbed_official	76:aeb1df146756	1026	* RTC clock source).
mbed_official	76:aeb1df146756	1027	*
mbed_official	76:aeb1df146756	1028	* @retval None
mbed_official	76:aeb1df146756	1029	*/
mbed_official	76:aeb1df146756	1030	void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
mbed_official	76:aeb1df146756	1031	{
mbed_official	76:aeb1df146756	1032	uint32_t tmpreg = 0;
mbed_official	76:aeb1df146756	1033
mbed_official	76:aeb1df146756	1034	/* Check the parameters */
mbed_official	76:aeb1df146756	1035	assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
mbed_official	76:aeb1df146756	1036
mbed_official	76:aeb1df146756	1037	if ((RCC_RTCCLKSource & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE)
mbed_official	76:aeb1df146756	1038	{
mbed_official	76:aeb1df146756	1039	/* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
mbed_official	76:aeb1df146756	1040	tmpreg = RCC->CR;
mbed_official	76:aeb1df146756	1041
mbed_official	76:aeb1df146756	1042	/* Clear RTCPRE[1:0] bits */
mbed_official	76:aeb1df146756	1043	tmpreg &= ~RCC_CR_RTCPRE;
mbed_official	76:aeb1df146756	1044
mbed_official	76:aeb1df146756	1045	/* Configure HSE division factor for RTC clock */
mbed_official	76:aeb1df146756	1046	tmpreg \|= (RCC_RTCCLKSource & RCC_CR_RTCPRE);
mbed_official	76:aeb1df146756	1047
mbed_official	76:aeb1df146756	1048	/* Store the new value */
mbed_official	76:aeb1df146756	1049	RCC->CR = tmpreg;
mbed_official	76:aeb1df146756	1050	}
mbed_official	76:aeb1df146756	1051
mbed_official	76:aeb1df146756	1052	RCC->CSR &= ~RCC_CSR_RTCSEL;
mbed_official	76:aeb1df146756	1053
mbed_official	76:aeb1df146756	1054	/* Select the RTC clock source */
mbed_official	76:aeb1df146756	1055	RCC->CSR \|= (RCC_RTCCLKSource & RCC_CSR_RTCSEL);
mbed_official	76:aeb1df146756	1056	}
mbed_official	76:aeb1df146756	1057
mbed_official	76:aeb1df146756	1058	/**
mbed_official	76:aeb1df146756	1059	* @brief Enables or disables the RTC clock.
mbed_official	76:aeb1df146756	1060	* @note This function must be used only after the RTC clock source was selected
mbed_official	76:aeb1df146756	1061	* using the RCC_RTCCLKConfig function.
mbed_official	76:aeb1df146756	1062	* @param NewState: new state of the RTC clock.
mbed_official	76:aeb1df146756	1063	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	1064	* @retval None
mbed_official	76:aeb1df146756	1065	*/
mbed_official	76:aeb1df146756	1066	void RCC_RTCCLKCmd(FunctionalState NewState)
mbed_official	76:aeb1df146756	1067	{
mbed_official	76:aeb1df146756	1068	/* Check the parameters */
mbed_official	76:aeb1df146756	1069	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	1070
mbed_official	76:aeb1df146756	1071	(__IO uint32_t ) CSR_RTCEN_BB = (uint32_t)NewState;
mbed_official	76:aeb1df146756	1072	}
mbed_official	76:aeb1df146756	1073
mbed_official	76:aeb1df146756	1074	/**
mbed_official	76:aeb1df146756	1075	* @brief Forces or releases the RTC peripheral and associated resources reset.
mbed_official	76:aeb1df146756	1076	* @note This function resets the RTC peripheral, RTC clock source selection
mbed_official	76:aeb1df146756	1077	* (in RCC_CSR) and the backup registers.
mbed_official	76:aeb1df146756	1078	* @param NewState: new state of the RTC reset.
mbed_official	76:aeb1df146756	1079	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	1080	* @retval None
mbed_official	76:aeb1df146756	1081	*/
mbed_official	76:aeb1df146756	1082	void RCC_RTCResetCmd(FunctionalState NewState)
mbed_official	76:aeb1df146756	1083	{
mbed_official	76:aeb1df146756	1084	/* Check the parameters */
mbed_official	76:aeb1df146756	1085	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	1086
mbed_official	76:aeb1df146756	1087	(__IO uint32_t ) CSR_RTCRST_BB = (uint32_t)NewState;
mbed_official	76:aeb1df146756	1088	}
mbed_official	76:aeb1df146756	1089
mbed_official	76:aeb1df146756	1090	/**
mbed_official	76:aeb1df146756	1091	* @brief Enables or disables the AHB peripheral clock.
mbed_official	76:aeb1df146756	1092	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	76:aeb1df146756	1093	* is disabled and the application software has to enable this clock before
mbed_official	76:aeb1df146756	1094	* using it.
mbed_official	76:aeb1df146756	1095	* @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
mbed_official	76:aeb1df146756	1096	* This parameter can be any combination of the following values:
mbed_official	76:aeb1df146756	1097	* @arg RCC_AHBPeriph_GPIOA: GPIOA clock
mbed_official	76:aeb1df146756	1098	* @arg RCC_AHBPeriph_GPIOB: GPIOB clock
mbed_official	76:aeb1df146756	1099	* @arg RCC_AHBPeriph_GPIOC: GPIOC clock
mbed_official	76:aeb1df146756	1100	* @arg RCC_AHBPeriph_GPIOD: GPIOD clock
mbed_official	76:aeb1df146756	1101	* @arg RCC_AHBPeriph_GPIOE: GPIOE clock
mbed_official	76:aeb1df146756	1102	* @arg RCC_AHBPeriph_GPIOH: GPIOH clock
mbed_official	76:aeb1df146756	1103	* @arg RCC_AHBPeriph_GPIOF: GPIOF clock
mbed_official	76:aeb1df146756	1104	* @arg RCC_AHBPeriph_GPIOG: GPIOG clock
mbed_official	76:aeb1df146756	1105	* @arg RCC_AHBPeriph_CRC: CRC clock
mbed_official	76:aeb1df146756	1106	* @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
mbed_official	76:aeb1df146756	1107	* @arg RCC_AHBPeriph_DMA1: DMA1 clock
mbed_official	76:aeb1df146756	1108	* @arg RCC_AHBPeriph_DMA2: DMA2 clock
mbed_official	76:aeb1df146756	1109	* @arg RCC_AHBPeriph_AES: AES clock
mbed_official	76:aeb1df146756	1110	* @arg RCC_AHBPeriph_FSMC: FSMC clock
mbed_official	76:aeb1df146756	1111	* @param NewState: new state of the specified peripheral clock.
mbed_official	76:aeb1df146756	1112	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	1113	* @retval None
mbed_official	76:aeb1df146756	1114	*/
mbed_official	76:aeb1df146756	1115	void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
mbed_official	76:aeb1df146756	1116	{
mbed_official	76:aeb1df146756	1117	/* Check the parameters */
mbed_official	76:aeb1df146756	1118	assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
mbed_official	76:aeb1df146756	1119	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	1120
mbed_official	76:aeb1df146756	1121	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	1122	{
mbed_official	76:aeb1df146756	1123	RCC->AHBENR \|= RCC_AHBPeriph;
mbed_official	76:aeb1df146756	1124	}
mbed_official	76:aeb1df146756	1125	else
mbed_official	76:aeb1df146756	1126	{
mbed_official	76:aeb1df146756	1127	RCC->AHBENR &= ~RCC_AHBPeriph;
mbed_official	76:aeb1df146756	1128	}
mbed_official	76:aeb1df146756	1129	}
mbed_official	76:aeb1df146756	1130
mbed_official	76:aeb1df146756	1131	/**
mbed_official	76:aeb1df146756	1132	* @brief Enables or disables the High Speed APB (APB2) peripheral clock.
mbed_official	76:aeb1df146756	1133	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	76:aeb1df146756	1134	* is disabled and the application software has to enable this clock before
mbed_official	76:aeb1df146756	1135	* using it.
mbed_official	76:aeb1df146756	1136	* @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
mbed_official	76:aeb1df146756	1137	* This parameter can be any combination of the following values:
mbed_official	76:aeb1df146756	1138	* @arg RCC_APB2Periph_SYSCFG: SYSCFG APB2 Clock.
mbed_official	76:aeb1df146756	1139	* @arg RCC_APB2Periph_TIM9: TIM9 APB2 Clock.
mbed_official	76:aeb1df146756	1140	* @arg RCC_APB2Periph_TIM10: TIM10 APB2 Clock.
mbed_official	76:aeb1df146756	1141	* @arg RCC_APB2Periph_TIM11: TIM11 APB2 Clock.
mbed_official	76:aeb1df146756	1142	* @arg RCC_APB2Periph_ADC1: ADC1 APB2 Clock.
mbed_official	76:aeb1df146756	1143	* @arg RCC_APB2Periph_SDIO: SDIO APB2 Clock.
mbed_official	76:aeb1df146756	1144	* @arg RCC_APB2Periph_SPI1: SPI1 APB2 Clock.
mbed_official	76:aeb1df146756	1145	* @arg RCC_APB2Periph_USART1: USART1 APB2 Clock.
mbed_official	76:aeb1df146756	1146	* @param NewState: new state of the specified peripheral clock.
mbed_official	76:aeb1df146756	1147	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	1148	* @retval None
mbed_official	76:aeb1df146756	1149	*/
mbed_official	76:aeb1df146756	1150	void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
mbed_official	76:aeb1df146756	1151	{
mbed_official	76:aeb1df146756	1152	/* Check the parameters */
mbed_official	76:aeb1df146756	1153	assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
mbed_official	76:aeb1df146756	1154	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	1155
mbed_official	76:aeb1df146756	1156	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	1157	{
mbed_official	76:aeb1df146756	1158	RCC->APB2ENR \|= RCC_APB2Periph;
mbed_official	76:aeb1df146756	1159	}
mbed_official	76:aeb1df146756	1160	else
mbed_official	76:aeb1df146756	1161	{
mbed_official	76:aeb1df146756	1162	RCC->APB2ENR &= ~RCC_APB2Periph;
mbed_official	76:aeb1df146756	1163	}
mbed_official	76:aeb1df146756	1164	}
mbed_official	76:aeb1df146756	1165
mbed_official	76:aeb1df146756	1166	/**
mbed_official	76:aeb1df146756	1167	* @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
mbed_official	76:aeb1df146756	1168	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	76:aeb1df146756	1169	* is disabled and the application software has to enable this clock before
mbed_official	76:aeb1df146756	1170	* using it.
mbed_official	76:aeb1df146756	1171	* @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
mbed_official	76:aeb1df146756	1172	* This parameter can be any combination of the following values:
mbed_official	76:aeb1df146756	1173	* @arg RCC_APB1Periph_TIM2: TIM2 clock
mbed_official	76:aeb1df146756	1174	* @arg RCC_APB1Periph_TIM3: TIM3 clock
mbed_official	76:aeb1df146756	1175	* @arg RCC_APB1Periph_TIM4: TIM4 clock
mbed_official	76:aeb1df146756	1176	* @arg RCC_APB1Periph_TIM5: TIM5 clock
mbed_official	76:aeb1df146756	1177	* @arg RCC_APB1Periph_TIM6: TIM6 clock
mbed_official	76:aeb1df146756	1178	* @arg RCC_APB1Periph_TIM7: TIM7 clock
mbed_official	76:aeb1df146756	1179	* @arg RCC_APB1Periph_LCD: LCD clock
mbed_official	76:aeb1df146756	1180	* @arg RCC_APB1Periph_WWDG: WWDG clock
mbed_official	76:aeb1df146756	1181	* @arg RCC_APB1Periph_SPI2: SPI2 clock
mbed_official	76:aeb1df146756	1182	* @arg RCC_APB1Periph_SPI3: SPI3 clock
mbed_official	76:aeb1df146756	1183	* @arg RCC_APB1Periph_USART2: USART2 clock
mbed_official	76:aeb1df146756	1184	* @arg RCC_APB1Periph_USART3: USART3 clock
mbed_official	76:aeb1df146756	1185	* @arg RCC_APB1Periph_UART4: UART4 clock
mbed_official	76:aeb1df146756	1186	* @arg RCC_APB1Periph_UART5: UART5 clock
mbed_official	76:aeb1df146756	1187	* @arg RCC_APB1Periph_I2C1: I2C1 clock
mbed_official	76:aeb1df146756	1188	* @arg RCC_APB1Periph_I2C2: I2C2 clock
mbed_official	76:aeb1df146756	1189	* @arg RCC_APB1Periph_USB: USB clock
mbed_official	76:aeb1df146756	1190	* @arg RCC_APB1Periph_PWR: PWR clock
mbed_official	76:aeb1df146756	1191	* @arg RCC_APB1Periph_DAC: DAC clock
mbed_official	76:aeb1df146756	1192	* @arg RCC_APB1Periph_COMP COMP clock
mbed_official	76:aeb1df146756	1193	* @param NewState: new state of the specified peripheral clock.
mbed_official	76:aeb1df146756	1194	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	1195	* @retval None
mbed_official	76:aeb1df146756	1196	*/
mbed_official	76:aeb1df146756	1197	void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
mbed_official	76:aeb1df146756	1198	{
mbed_official	76:aeb1df146756	1199	/* Check the parameters */
mbed_official	76:aeb1df146756	1200	assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
mbed_official	76:aeb1df146756	1201	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	1202
mbed_official	76:aeb1df146756	1203	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	1204	{
mbed_official	76:aeb1df146756	1205	RCC->APB1ENR \|= RCC_APB1Periph;
mbed_official	76:aeb1df146756	1206	}
mbed_official	76:aeb1df146756	1207	else
mbed_official	76:aeb1df146756	1208	{
mbed_official	76:aeb1df146756	1209	RCC->APB1ENR &= ~RCC_APB1Periph;
mbed_official	76:aeb1df146756	1210	}
mbed_official	76:aeb1df146756	1211	}
mbed_official	76:aeb1df146756	1212
mbed_official	76:aeb1df146756	1213	/**
mbed_official	76:aeb1df146756	1214	* @brief Forces or releases AHB peripheral reset.
mbed_official	76:aeb1df146756	1215	* @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
mbed_official	76:aeb1df146756	1216	* This parameter can be any combination of the following values:
mbed_official	76:aeb1df146756	1217	* @arg RCC_AHBPeriph_GPIOA: GPIOA clock
mbed_official	76:aeb1df146756	1218	* @arg RCC_AHBPeriph_GPIOB: GPIOB clock
mbed_official	76:aeb1df146756	1219	* @arg RCC_AHBPeriph_GPIOC: GPIOC clock
mbed_official	76:aeb1df146756	1220	* @arg RCC_AHBPeriph_GPIOD: GPIOD clock
mbed_official	76:aeb1df146756	1221	* @arg RCC_AHBPeriph_GPIOE: GPIOE clock
mbed_official	76:aeb1df146756	1222	* @arg RCC_AHBPeriph_GPIOH: GPIOH clock
mbed_official	76:aeb1df146756	1223	* @arg RCC_AHBPeriph_GPIOF: GPIOF clock
mbed_official	76:aeb1df146756	1224	* @arg RCC_AHBPeriph_GPIOG: GPIOG clock
mbed_official	76:aeb1df146756	1225	* @arg RCC_AHBPeriph_CRC: CRC clock
mbed_official	76:aeb1df146756	1226	* @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
mbed_official	76:aeb1df146756	1227	* @arg RCC_AHBPeriph_DMA1: DMA1 clock
mbed_official	76:aeb1df146756	1228	* @arg RCC_AHBPeriph_DMA2: DMA2 clock
mbed_official	76:aeb1df146756	1229	* @arg RCC_AHBPeriph_AES: AES clock
mbed_official	76:aeb1df146756	1230	* @arg RCC_AHBPeriph_FSMC: FSMC clock
mbed_official	76:aeb1df146756	1231	* @param NewState: new state of the specified peripheral reset.
mbed_official	76:aeb1df146756	1232	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	1233	* @retval None
mbed_official	76:aeb1df146756	1234	*/
mbed_official	76:aeb1df146756	1235	void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
mbed_official	76:aeb1df146756	1236	{
mbed_official	76:aeb1df146756	1237	/* Check the parameters */
mbed_official	76:aeb1df146756	1238	assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
mbed_official	76:aeb1df146756	1239	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	1240
mbed_official	76:aeb1df146756	1241	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	1242	{
mbed_official	76:aeb1df146756	1243	RCC->AHBRSTR \|= RCC_AHBPeriph;
mbed_official	76:aeb1df146756	1244	}
mbed_official	76:aeb1df146756	1245	else
mbed_official	76:aeb1df146756	1246	{
mbed_official	76:aeb1df146756	1247	RCC->AHBRSTR &= ~RCC_AHBPeriph;
mbed_official	76:aeb1df146756	1248	}
mbed_official	76:aeb1df146756	1249	}
mbed_official	76:aeb1df146756	1250
mbed_official	76:aeb1df146756	1251	/**
mbed_official	76:aeb1df146756	1252	* @brief Forces or releases High Speed APB (APB2) peripheral reset.
mbed_official	76:aeb1df146756	1253	* @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
mbed_official	76:aeb1df146756	1254	* This parameter can be any combination of the following values:
mbed_official	76:aeb1df146756	1255	* @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
mbed_official	76:aeb1df146756	1256	* @arg RCC_APB2Periph_TIM9: TIM9 clock
mbed_official	76:aeb1df146756	1257	* @arg RCC_APB2Periph_TIM10: TIM10 clock
mbed_official	76:aeb1df146756	1258	* @arg RCC_APB2Periph_TIM11: TIM11 clock
mbed_official	76:aeb1df146756	1259	* @arg RCC_APB2Periph_ADC1: ADC1 clock
mbed_official	76:aeb1df146756	1260	* @arg RCC_APB2Periph_SDIO: SDIO clock
mbed_official	76:aeb1df146756	1261	* @arg RCC_APB2Periph_SPI1: SPI1 clock
mbed_official	76:aeb1df146756	1262	* @arg RCC_APB2Periph_USART1: USART1 clock
mbed_official	76:aeb1df146756	1263	* @param NewState: new state of the specified peripheral reset.
mbed_official	76:aeb1df146756	1264	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	1265	* @retval None
mbed_official	76:aeb1df146756	1266	*/
mbed_official	76:aeb1df146756	1267	void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
mbed_official	76:aeb1df146756	1268	{
mbed_official	76:aeb1df146756	1269	/* Check the parameters */
mbed_official	76:aeb1df146756	1270	assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
mbed_official	76:aeb1df146756	1271	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	1272
mbed_official	76:aeb1df146756	1273	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	1274	{
mbed_official	76:aeb1df146756	1275	RCC->APB2RSTR \|= RCC_APB2Periph;
mbed_official	76:aeb1df146756	1276	}
mbed_official	76:aeb1df146756	1277	else
mbed_official	76:aeb1df146756	1278	{
mbed_official	76:aeb1df146756	1279	RCC->APB2RSTR &= ~RCC_APB2Periph;
mbed_official	76:aeb1df146756	1280	}
mbed_official	76:aeb1df146756	1281	}
mbed_official	76:aeb1df146756	1282
mbed_official	76:aeb1df146756	1283	/**
mbed_official	76:aeb1df146756	1284	* @brief Forces or releases Low Speed APB (APB1) peripheral reset.
mbed_official	76:aeb1df146756	1285	* @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
mbed_official	76:aeb1df146756	1286	* This parameter can be any combination of the following values:
mbed_official	76:aeb1df146756	1287	* @arg RCC_APB1Periph_TIM2: TIM2 clock
mbed_official	76:aeb1df146756	1288	* @arg RCC_APB1Periph_TIM3: TIM3 clock
mbed_official	76:aeb1df146756	1289	* @arg RCC_APB1Periph_TIM4: TIM4 clock
mbed_official	76:aeb1df146756	1290	* @arg RCC_APB1Periph_TIM5: TIM5 clock
mbed_official	76:aeb1df146756	1291	* @arg RCC_APB1Periph_TIM6: TIM6 clock
mbed_official	76:aeb1df146756	1292	* @arg RCC_APB1Periph_TIM7: TIM7 clock
mbed_official	76:aeb1df146756	1293	* @arg RCC_APB1Periph_LCD: LCD clock
mbed_official	76:aeb1df146756	1294	* @arg RCC_APB1Periph_WWDG: WWDG clock
mbed_official	76:aeb1df146756	1295	* @arg RCC_APB1Periph_SPI2: SPI2 clock
mbed_official	76:aeb1df146756	1296	* @arg RCC_APB1Periph_SPI3: SPI3 clock
mbed_official	76:aeb1df146756	1297	* @arg RCC_APB1Periph_USART2: USART2 clock
mbed_official	76:aeb1df146756	1298	* @arg RCC_APB1Periph_USART3: USART3 clock
mbed_official	76:aeb1df146756	1299	* @arg RCC_APB1Periph_UART4: UART4 clock
mbed_official	76:aeb1df146756	1300	* @arg RCC_APB1Periph_UART5: UART5 clock
mbed_official	76:aeb1df146756	1301	* @arg RCC_APB1Periph_I2C1: I2C1 clock
mbed_official	76:aeb1df146756	1302	* @arg RCC_APB1Periph_I2C2: I2C2 clock
mbed_official	76:aeb1df146756	1303	* @arg RCC_APB1Periph_USB: USB clock
mbed_official	76:aeb1df146756	1304	* @arg RCC_APB1Periph_PWR: PWR clock
mbed_official	76:aeb1df146756	1305	* @arg RCC_APB1Periph_DAC: DAC clock
mbed_official	76:aeb1df146756	1306	* @arg RCC_APB1Periph_COMP
mbed_official	76:aeb1df146756	1307	* @param NewState: new state of the specified peripheral clock.
mbed_official	76:aeb1df146756	1308	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	1309	* @retval None
mbed_official	76:aeb1df146756	1310	*/
mbed_official	76:aeb1df146756	1311	void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
mbed_official	76:aeb1df146756	1312	{
mbed_official	76:aeb1df146756	1313	/* Check the parameters */
mbed_official	76:aeb1df146756	1314	assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
mbed_official	76:aeb1df146756	1315	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	1316
mbed_official	76:aeb1df146756	1317	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	1318	{
mbed_official	76:aeb1df146756	1319	RCC->APB1RSTR \|= RCC_APB1Periph;
mbed_official	76:aeb1df146756	1320	}
mbed_official	76:aeb1df146756	1321	else
mbed_official	76:aeb1df146756	1322	{
mbed_official	76:aeb1df146756	1323	RCC->APB1RSTR &= ~RCC_APB1Periph;
mbed_official	76:aeb1df146756	1324	}
mbed_official	76:aeb1df146756	1325	}
mbed_official	76:aeb1df146756	1326
mbed_official	76:aeb1df146756	1327	/**
mbed_official	76:aeb1df146756	1328	* @brief Enables or disables the AHB peripheral clock during SLEEP mode.
mbed_official	76:aeb1df146756	1329	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	76:aeb1df146756	1330	* power consumption.
mbed_official	76:aeb1df146756	1331	* - After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	76:aeb1df146756	1332	* - By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	76:aeb1df146756	1333	* @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
mbed_official	76:aeb1df146756	1334	* This parameter can be any combination of the following values:
mbed_official	76:aeb1df146756	1335	* @arg RCC_AHBPeriph_GPIOA: GPIOA clock
mbed_official	76:aeb1df146756	1336	* @arg RCC_AHBPeriph_GPIOB: GPIOB clock
mbed_official	76:aeb1df146756	1337	* @arg RCC_AHBPeriph_GPIOC: GPIOC clock
mbed_official	76:aeb1df146756	1338	* @arg RCC_AHBPeriph_GPIOD: GPIOD clock
mbed_official	76:aeb1df146756	1339	* @arg RCC_AHBPeriph_GPIOE: GPIOE clock
mbed_official	76:aeb1df146756	1340	* @arg RCC_AHBPeriph_GPIOH: GPIOH clock
mbed_official	76:aeb1df146756	1341	* @arg RCC_AHBPeriph_GPIOF: GPIOF clock
mbed_official	76:aeb1df146756	1342	* @arg RCC_AHBPeriph_GPIOG: GPIOG clock
mbed_official	76:aeb1df146756	1343	* @arg RCC_AHBPeriph_CRC: CRC clock
mbed_official	76:aeb1df146756	1344	* @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
mbed_official	76:aeb1df146756	1345	* @arg RCC_AHBPeriph_SRAM: SRAM clock
mbed_official	76:aeb1df146756	1346	* @arg RCC_AHBPeriph_DMA1: DMA1 clock
mbed_official	76:aeb1df146756	1347	* @arg RCC_AHBPeriph_DMA2: DMA2 clock
mbed_official	76:aeb1df146756	1348	* @arg RCC_AHBPeriph_AES: AES clock
mbed_official	76:aeb1df146756	1349	* @arg RCC_AHBPeriph_FSMC: FSMC clock
mbed_official	76:aeb1df146756	1350	* @param NewState: new state of the specified peripheral clock.
mbed_official	76:aeb1df146756	1351	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	1352	* @retval None
mbed_official	76:aeb1df146756	1353	*/
mbed_official	76:aeb1df146756	1354	void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
mbed_official	76:aeb1df146756	1355	{
mbed_official	76:aeb1df146756	1356	/* Check the parameters */
mbed_official	76:aeb1df146756	1357	assert_param(IS_RCC_AHB_LPMODE_PERIPH(RCC_AHBPeriph));
mbed_official	76:aeb1df146756	1358	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	1359
mbed_official	76:aeb1df146756	1360	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	1361	{
mbed_official	76:aeb1df146756	1362	RCC->AHBLPENR \|= RCC_AHBPeriph;
mbed_official	76:aeb1df146756	1363	}
mbed_official	76:aeb1df146756	1364	else
mbed_official	76:aeb1df146756	1365	{
mbed_official	76:aeb1df146756	1366	RCC->AHBLPENR &= ~RCC_AHBPeriph;
mbed_official	76:aeb1df146756	1367	}
mbed_official	76:aeb1df146756	1368	}
mbed_official	76:aeb1df146756	1369
mbed_official	76:aeb1df146756	1370	/**
mbed_official	76:aeb1df146756	1371	* @brief Enables or disables the APB2 peripheral clock during SLEEP mode.
mbed_official	76:aeb1df146756	1372	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	76:aeb1df146756	1373	* power consumption.
mbed_official	76:aeb1df146756	1374	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	76:aeb1df146756	1375	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	76:aeb1df146756	1376	* @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
mbed_official	76:aeb1df146756	1377	* This parameter can be any combination of the following values:
mbed_official	76:aeb1df146756	1378	* @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
mbed_official	76:aeb1df146756	1379	* @arg RCC_APB2Periph_TIM9: TIM9 clock
mbed_official	76:aeb1df146756	1380	* @arg RCC_APB2Periph_TIM10: TIM10 clock
mbed_official	76:aeb1df146756	1381	* @arg RCC_APB2Periph_TIM11: TIM11 clock
mbed_official	76:aeb1df146756	1382	* @arg RCC_APB2Periph_ADC1: ADC1 clock
mbed_official	76:aeb1df146756	1383	* @arg RCC_APB2Periph_SDIO: SDIO clock
mbed_official	76:aeb1df146756	1384	* @arg RCC_APB2Periph_SPI1: SPI1 clock
mbed_official	76:aeb1df146756	1385	* @arg RCC_APB2Periph_USART1: USART1 clock
mbed_official	76:aeb1df146756	1386	* @param NewState: new state of the specified peripheral clock.
mbed_official	76:aeb1df146756	1387	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	1388	* @retval None
mbed_official	76:aeb1df146756	1389	*/
mbed_official	76:aeb1df146756	1390	void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
mbed_official	76:aeb1df146756	1391	{
mbed_official	76:aeb1df146756	1392	/* Check the parameters */
mbed_official	76:aeb1df146756	1393	assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
mbed_official	76:aeb1df146756	1394	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	1395
mbed_official	76:aeb1df146756	1396	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	1397	{
mbed_official	76:aeb1df146756	1398	RCC->APB2LPENR \|= RCC_APB2Periph;
mbed_official	76:aeb1df146756	1399	}
mbed_official	76:aeb1df146756	1400	else
mbed_official	76:aeb1df146756	1401	{
mbed_official	76:aeb1df146756	1402	RCC->APB2LPENR &= ~RCC_APB2Periph;
mbed_official	76:aeb1df146756	1403	}
mbed_official	76:aeb1df146756	1404	}
mbed_official	76:aeb1df146756	1405
mbed_official	76:aeb1df146756	1406	/**
mbed_official	76:aeb1df146756	1407	* @brief Enables or disables the APB1 peripheral clock during SLEEP mode.
mbed_official	76:aeb1df146756	1408	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	76:aeb1df146756	1409	* power consumption.
mbed_official	76:aeb1df146756	1410	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	76:aeb1df146756	1411	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	76:aeb1df146756	1412	* @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
mbed_official	76:aeb1df146756	1413	* This parameter can be any combination of the following values:
mbed_official	76:aeb1df146756	1414	* @arg RCC_APB1Periph_TIM2: TIM2 clock
mbed_official	76:aeb1df146756	1415	* @arg RCC_APB1Periph_TIM3: TIM3 clock
mbed_official	76:aeb1df146756	1416	* @arg RCC_APB1Periph_TIM4: TIM4 clock
mbed_official	76:aeb1df146756	1417	* @arg RCC_APB1Periph_TIM5: TIM5 clock
mbed_official	76:aeb1df146756	1418	* @arg RCC_APB1Periph_TIM6: TIM6 clock
mbed_official	76:aeb1df146756	1419	* @arg RCC_APB1Periph_TIM7: TIM7 clock
mbed_official	76:aeb1df146756	1420	* @arg RCC_APB1Periph_LCD: LCD clock
mbed_official	76:aeb1df146756	1421	* @arg RCC_APB1Periph_WWDG: WWDG clock
mbed_official	76:aeb1df146756	1422	* @arg RCC_APB1Periph_SPI2: SPI2 clock
mbed_official	76:aeb1df146756	1423	* @arg RCC_APB1Periph_SPI3: SPI3 clock
mbed_official	76:aeb1df146756	1424	* @arg RCC_APB1Periph_USART2: USART2 clock
mbed_official	76:aeb1df146756	1425	* @arg RCC_APB1Periph_USART3: USART3 clock
mbed_official	76:aeb1df146756	1426	* @arg RCC_APB1Periph_UART4: UART4 clock
mbed_official	76:aeb1df146756	1427	* @arg RCC_APB1Periph_UART5: UART5 clock
mbed_official	76:aeb1df146756	1428	* @arg RCC_APB1Periph_I2C1: I2C1 clock
mbed_official	76:aeb1df146756	1429	* @arg RCC_APB1Periph_I2C2: I2C2 clock
mbed_official	76:aeb1df146756	1430	* @arg RCC_APB1Periph_USB: USB clock
mbed_official	76:aeb1df146756	1431	* @arg RCC_APB1Periph_PWR: PWR clock
mbed_official	76:aeb1df146756	1432	* @arg RCC_APB1Periph_DAC: DAC clock
mbed_official	76:aeb1df146756	1433	* @arg RCC_APB1Periph_COMP: COMP clock
mbed_official	76:aeb1df146756	1434	* @param NewState: new state
mbed_official	76:aeb1df146756	1435	* @param NewState: new state of the specified peripheral clock.
mbed_official	76:aeb1df146756	1436	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	1437	* @retval None
mbed_official	76:aeb1df146756	1438	*/
mbed_official	76:aeb1df146756	1439	void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
mbed_official	76:aeb1df146756	1440	{
mbed_official	76:aeb1df146756	1441	/* Check the parameters */
mbed_official	76:aeb1df146756	1442	assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
mbed_official	76:aeb1df146756	1443	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	1444
mbed_official	76:aeb1df146756	1445	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	1446	{
mbed_official	76:aeb1df146756	1447	RCC->APB1LPENR \|= RCC_APB1Periph;
mbed_official	76:aeb1df146756	1448	}
mbed_official	76:aeb1df146756	1449	else
mbed_official	76:aeb1df146756	1450	{
mbed_official	76:aeb1df146756	1451	RCC->APB1LPENR &= ~RCC_APB1Periph;
mbed_official	76:aeb1df146756	1452	}
mbed_official	76:aeb1df146756	1453	}
mbed_official	76:aeb1df146756	1454
mbed_official	76:aeb1df146756	1455	/**
mbed_official	76:aeb1df146756	1456	* @}
mbed_official	76:aeb1df146756	1457	*/
mbed_official	76:aeb1df146756	1458
mbed_official	76:aeb1df146756	1459	/** @defgroup RCC_Group4 Interrupts and flags management functions
mbed_official	76:aeb1df146756	1460	* @brief Interrupts and flags management functions
mbed_official	76:aeb1df146756	1461	*
mbed_official	76:aeb1df146756	1462	@verbatim
mbed_official	76:aeb1df146756	1463	===============================================================================
mbed_official	76:aeb1df146756	1464	##### Interrupts and flags management functions #####
mbed_official	76:aeb1df146756	1465	===============================================================================
mbed_official	76:aeb1df146756	1466
mbed_official	76:aeb1df146756	1467	@endverbatim
mbed_official	76:aeb1df146756	1468	* @{
mbed_official	76:aeb1df146756	1469	*/
mbed_official	76:aeb1df146756	1470
mbed_official	76:aeb1df146756	1471	/**
mbed_official	76:aeb1df146756	1472	* @brief Enables or disables the specified RCC interrupts.
mbed_official	76:aeb1df146756	1473	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
mbed_official	76:aeb1df146756	1474	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
mbed_official	76:aeb1df146756	1475	* automatically generated. The NMI will be executed indefinitely, and
mbed_official	76:aeb1df146756	1476	* since NMI has higher priority than any other IRQ (and main program)
mbed_official	76:aeb1df146756	1477	* the application will be stacked in the NMI ISR unless the CSS interrupt
mbed_official	76:aeb1df146756	1478	* pending bit is cleared.
mbed_official	76:aeb1df146756	1479	* @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
mbed_official	76:aeb1df146756	1480	* This parameter can be any combination of the following values:
mbed_official	76:aeb1df146756	1481	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	76:aeb1df146756	1482	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	76:aeb1df146756	1483	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	76:aeb1df146756	1484	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	76:aeb1df146756	1485	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	76:aeb1df146756	1486	* @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official	76:aeb1df146756	1487	* @arg RCC_IT_LSECSS: LSE CSS interrupt
mbed_official	76:aeb1df146756	1488	* @param NewState: new state of the specified RCC interrupts.
mbed_official	76:aeb1df146756	1489	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	1490	* @retval None
mbed_official	76:aeb1df146756	1491	*/
mbed_official	76:aeb1df146756	1492	void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
mbed_official	76:aeb1df146756	1493	{
mbed_official	76:aeb1df146756	1494	/* Check the parameters */
mbed_official	76:aeb1df146756	1495	assert_param(IS_RCC_IT(RCC_IT));
mbed_official	76:aeb1df146756	1496	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	1497
mbed_official	76:aeb1df146756	1498	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	1499	{
mbed_official	76:aeb1df146756	1500	/* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
mbed_official	76:aeb1df146756	1501	(__IO uint8_t ) CIR_BYTE2_ADDRESS \|= RCC_IT;
mbed_official	76:aeb1df146756	1502	}
mbed_official	76:aeb1df146756	1503	else
mbed_official	76:aeb1df146756	1504	{
mbed_official	76:aeb1df146756	1505	/* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
mbed_official	76:aeb1df146756	1506	(__IO uint8_t ) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
mbed_official	76:aeb1df146756	1507	}
mbed_official	76:aeb1df146756	1508	}
mbed_official	76:aeb1df146756	1509
mbed_official	76:aeb1df146756	1510	/**
mbed_official	76:aeb1df146756	1511	* @brief Checks whether the specified RCC flag is set or not.
mbed_official	76:aeb1df146756	1512	* @param RCC_FLAG: specifies the flag to check.
mbed_official	76:aeb1df146756	1513	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	1514	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
mbed_official	76:aeb1df146756	1515	* @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
mbed_official	76:aeb1df146756	1516	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
mbed_official	76:aeb1df146756	1517	* @arg RCC_FLAG_PLLRDY: PLL clock ready
mbed_official	76:aeb1df146756	1518	* @arg RCC_FLAG_LSECSS: LSE oscillator clock CSS detected
mbed_official	76:aeb1df146756	1519	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
mbed_official	76:aeb1df146756	1520	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
mbed_official	76:aeb1df146756	1521	* @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
mbed_official	76:aeb1df146756	1522	* @arg RCC_FLAG_PINRST: Pin reset
mbed_official	76:aeb1df146756	1523	* @arg RCC_FLAG_PORRST: POR/PDR reset
mbed_official	76:aeb1df146756	1524	* @arg RCC_FLAG_SFTRST: Software reset
mbed_official	76:aeb1df146756	1525	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
mbed_official	76:aeb1df146756	1526	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
mbed_official	76:aeb1df146756	1527	* @arg RCC_FLAG_LPWRRST: Low Power reset
mbed_official	76:aeb1df146756	1528	* @retval The new state of RCC_FLAG (SET or RESET).
mbed_official	76:aeb1df146756	1529	*/
mbed_official	76:aeb1df146756	1530	FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
mbed_official	76:aeb1df146756	1531	{
mbed_official	76:aeb1df146756	1532	uint32_t tmp = 0;
mbed_official	76:aeb1df146756	1533	uint32_t statusreg = 0;
mbed_official	76:aeb1df146756	1534	FlagStatus bitstatus = RESET;
mbed_official	76:aeb1df146756	1535
mbed_official	76:aeb1df146756	1536	/* Check the parameters */
mbed_official	76:aeb1df146756	1537	assert_param(IS_RCC_FLAG(RCC_FLAG));
mbed_official	76:aeb1df146756	1538
mbed_official	76:aeb1df146756	1539	/* Get the RCC register index */
mbed_official	76:aeb1df146756	1540	tmp = RCC_FLAG >> 5;
mbed_official	76:aeb1df146756	1541
mbed_official	76:aeb1df146756	1542	if (tmp == 1) /* The flag to check is in CR register */
mbed_official	76:aeb1df146756	1543	{
mbed_official	76:aeb1df146756	1544	statusreg = RCC->CR;
mbed_official	76:aeb1df146756	1545	}
mbed_official	76:aeb1df146756	1546	else /* The flag to check is in CSR register (tmp == 2) */
mbed_official	76:aeb1df146756	1547	{
mbed_official	76:aeb1df146756	1548	statusreg = RCC->CSR;
mbed_official	76:aeb1df146756	1549	}
mbed_official	76:aeb1df146756	1550
mbed_official	76:aeb1df146756	1551	/* Get the flag position */
mbed_official	76:aeb1df146756	1552	tmp = RCC_FLAG & FLAG_MASK;
mbed_official	76:aeb1df146756	1553
mbed_official	76:aeb1df146756	1554	if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
mbed_official	76:aeb1df146756	1555	{
mbed_official	76:aeb1df146756	1556	bitstatus = SET;
mbed_official	76:aeb1df146756	1557	}
mbed_official	76:aeb1df146756	1558	else
mbed_official	76:aeb1df146756	1559	{
mbed_official	76:aeb1df146756	1560	bitstatus = RESET;
mbed_official	76:aeb1df146756	1561	}
mbed_official	76:aeb1df146756	1562	/* Return the flag status */
mbed_official	76:aeb1df146756	1563	return bitstatus;
mbed_official	76:aeb1df146756	1564	}
mbed_official	76:aeb1df146756	1565
mbed_official	76:aeb1df146756	1566	/**
mbed_official	76:aeb1df146756	1567	* @brief Clears the RCC reset flags.
mbed_official	76:aeb1df146756	1568	* The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
mbed_official	76:aeb1df146756	1569	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
mbed_official	76:aeb1df146756	1570	* @param None
mbed_official	76:aeb1df146756	1571	* @retval None
mbed_official	76:aeb1df146756	1572	*/
mbed_official	76:aeb1df146756	1573	void RCC_ClearFlag(void)
mbed_official	76:aeb1df146756	1574	{
mbed_official	76:aeb1df146756	1575	/* Set RMVF bit to clear the reset flags */
mbed_official	76:aeb1df146756	1576	RCC->CSR \|= RCC_CSR_RMVF;
mbed_official	76:aeb1df146756	1577	}
mbed_official	76:aeb1df146756	1578
mbed_official	76:aeb1df146756	1579	/**
mbed_official	76:aeb1df146756	1580	* @brief Checks whether the specified RCC interrupt has occurred or not.
mbed_official	76:aeb1df146756	1581	* @param RCC_IT: specifies the RCC interrupt source to check.
mbed_official	76:aeb1df146756	1582	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	1583	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	76:aeb1df146756	1584	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	76:aeb1df146756	1585	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	76:aeb1df146756	1586	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	76:aeb1df146756	1587	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	76:aeb1df146756	1588	* @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official	76:aeb1df146756	1589	* @arg RCC_IT_LSECSS: LSE CSS interrupt
mbed_official	76:aeb1df146756	1590	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	76:aeb1df146756	1591	* @retval The new state of RCC_IT (SET or RESET).
mbed_official	76:aeb1df146756	1592	*/
mbed_official	76:aeb1df146756	1593	ITStatus RCC_GetITStatus(uint8_t RCC_IT)
mbed_official	76:aeb1df146756	1594	{
mbed_official	76:aeb1df146756	1595	ITStatus bitstatus = RESET;
mbed_official	76:aeb1df146756	1596	/* Check the parameters */
mbed_official	76:aeb1df146756	1597	assert_param(IS_RCC_GET_IT(RCC_IT));
mbed_official	76:aeb1df146756	1598
mbed_official	76:aeb1df146756	1599	/* Check the status of the specified RCC interrupt */
mbed_official	76:aeb1df146756	1600	if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
mbed_official	76:aeb1df146756	1601	{
mbed_official	76:aeb1df146756	1602	bitstatus = SET;
mbed_official	76:aeb1df146756	1603	}
mbed_official	76:aeb1df146756	1604	else
mbed_official	76:aeb1df146756	1605	{
mbed_official	76:aeb1df146756	1606	bitstatus = RESET;
mbed_official	76:aeb1df146756	1607	}
mbed_official	76:aeb1df146756	1608	/* Return the RCC_IT status */
mbed_official	76:aeb1df146756	1609	return bitstatus;
mbed_official	76:aeb1df146756	1610	}
mbed_official	76:aeb1df146756	1611
mbed_official	76:aeb1df146756	1612	/**
mbed_official	76:aeb1df146756	1613	* @brief Clears the RCC's interrupt pending bits.
mbed_official	76:aeb1df146756	1614	* @param RCC_IT: specifies the interrupt pending bit to clear.
mbed_official	76:aeb1df146756	1615	* This parameter can be any combination of the following values:
mbed_official	76:aeb1df146756	1616	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	76:aeb1df146756	1617	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	76:aeb1df146756	1618	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	76:aeb1df146756	1619	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	76:aeb1df146756	1620	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	76:aeb1df146756	1621	* @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official	76:aeb1df146756	1622	* @arg RCC_IT_LSECSS: LSE CSS interrupt
mbed_official	76:aeb1df146756	1623	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	76:aeb1df146756	1624	* @retval None
mbed_official	76:aeb1df146756	1625	*/
mbed_official	76:aeb1df146756	1626	void RCC_ClearITPendingBit(uint8_t RCC_IT)
mbed_official	76:aeb1df146756	1627	{
mbed_official	76:aeb1df146756	1628	/* Check the parameters */
mbed_official	76:aeb1df146756	1629	assert_param(IS_RCC_CLEAR_IT(RCC_IT));
mbed_official	76:aeb1df146756	1630
mbed_official	76:aeb1df146756	1631	/* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
mbed_official	76:aeb1df146756	1632	pending bits */
mbed_official	76:aeb1df146756	1633	(__IO uint8_t ) CIR_BYTE3_ADDRESS = RCC_IT;
mbed_official	76:aeb1df146756	1634	}
mbed_official	76:aeb1df146756	1635
mbed_official	76:aeb1df146756	1636	/**
mbed_official	76:aeb1df146756	1637	* @}
mbed_official	76:aeb1df146756	1638	*/
mbed_official	76:aeb1df146756	1639
mbed_official	76:aeb1df146756	1640	/**
mbed_official	76:aeb1df146756	1641	* @}
mbed_official	76:aeb1df146756	1642	*/
mbed_official	76:aeb1df146756	1643
mbed_official	76:aeb1df146756	1644	/**
mbed_official	76:aeb1df146756	1645	* @}
mbed_official	76:aeb1df146756	1646	*/
mbed_official	76:aeb1df146756	1647
mbed_official	76:aeb1df146756	1648	/**
mbed_official	76:aeb1df146756	1649	* @}
mbed_official	76:aeb1df146756	1650	*/
mbed_official	76:aeb1df146756	1651
mbed_official	76:aeb1df146756	1652	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Repository toolbox

Export to desktop IDE

Repository details

Type:	Library
Created:	13 Sep 2014
Imports:	4
Forks:	0
Commits:	324
Dependents:	1
Dependencies:	0
Followers:	2

targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_rcc.c@323:9e901b0a5aa1, 2014-09-13 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning