shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

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targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_rcc.c@80:66393a7b209d, 2014-01-30 (annotated)

Committer:
mbed_official
Date:
Thu Jan 30 12:15:05 2014 +0000
Revision:
80:66393a7b209d
Parent:
76:aeb1df146756
Child:
106:ced8cbb51063
Synchronized with git revision dba523f83fe09b7fce11fc1299dd1216e9776359



Full URL: https://github.com/mbedmicro/mbed/commit/dba523f83fe09b7fce11fc1299dd1216e9776359/



Update of I2C, SPI, SLEEP for NUCLEO_F103RB and L152RE

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 76:aeb1df146756 1 /**
mbed_official 76:aeb1df146756 2 ******************************************************************************
mbed_official 76:aeb1df146756 3 * @file stm32l1xx_rcc.c
mbed_official 76:aeb1df146756 4 * @author MCD Application Team
mbed_official 80:66393a7b209d 5 * @version V1.3.0
mbed_official 80:66393a7b209d 6 * @date 31-January-2014
mbed_official 76:aeb1df146756 7 * @brief This file provides firmware functions to manage the following
mbed_official 76:aeb1df146756 8 * functionalities of the Reset and clock control (RCC) peripheral:
mbed_official 76:aeb1df146756 9 * + Internal/external clocks, PLL, CSS and MCO configuration
mbed_official 76:aeb1df146756 10 * + System, AHB and APB busses clocks configuration
mbed_official 76:aeb1df146756 11 * + Peripheral clocks configuration
mbed_official 76:aeb1df146756 12 * + Interrupts and flags management
mbed_official 76:aeb1df146756 13 *
mbed_official 76:aeb1df146756 14 @verbatim
mbed_official 76:aeb1df146756 15
mbed_official 76:aeb1df146756 16 ===============================================================================
mbed_official 76:aeb1df146756 17 ##### RCC specific features #####
mbed_official 76:aeb1df146756 18 ===============================================================================
mbed_official 76:aeb1df146756 19 [..] After reset the device is running from MSI (2 MHz) with Flash 0 WS,
mbed_official 76:aeb1df146756 20 all peripherals are off except internal SRAM, Flash and JTAG.
mbed_official 76:aeb1df146756 21 (#) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
mbed_official 76:aeb1df146756 22 all peripherals mapped on these busses are running at MSI speed.
mbed_official 76:aeb1df146756 23 (#) The clock for all peripherals is switched off, except the SRAM and
mbed_official 76:aeb1df146756 24 FLASH.
mbed_official 76:aeb1df146756 25 (#) All GPIOs are in input floating state, except the JTAG pins which
mbed_official 76:aeb1df146756 26 are assigned to be used for debug purpose.
mbed_official 76:aeb1df146756 27 [..] Once the device started from reset, the user application has to:
mbed_official 76:aeb1df146756 28 (#) Configure the clock source to be used to drive the System clock
mbed_official 76:aeb1df146756 29 (if the application needs higher frequency/performance)
mbed_official 76:aeb1df146756 30 (#) Configure the System clock frequency and Flash settings
mbed_official 76:aeb1df146756 31 (#) Configure the AHB and APB busses prescalers
mbed_official 76:aeb1df146756 32 (#) Enable the clock for the peripheral(s) to be used
mbed_official 76:aeb1df146756 33 (#) Configure the clock source(s) for peripherals whose clocks are not
mbed_official 76:aeb1df146756 34 derived from the System clock (ADC, RTC/LCD and IWDG)
mbed_official 76:aeb1df146756 35
mbed_official 76:aeb1df146756 36 @endverbatim
mbed_official 76:aeb1df146756 37
mbed_official 76:aeb1df146756 38 ******************************************************************************
mbed_official 76:aeb1df146756 39 * @attention
mbed_official 76:aeb1df146756 40 *
mbed_official 80:66393a7b209d 41 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
mbed_official 76:aeb1df146756 42 *
mbed_official 76:aeb1df146756 43 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
mbed_official 76:aeb1df146756 44 * You may not use this file except in compliance with the License.
mbed_official 76:aeb1df146756 45 * You may obtain a copy of the License at:
mbed_official 76:aeb1df146756 46 *
mbed_official 76:aeb1df146756 47 * http://www.st.com/software_license_agreement_liberty_v2
mbed_official 76:aeb1df146756 48 *
mbed_official 76:aeb1df146756 49 * Unless required by applicable law or agreed to in writing, software
mbed_official 76:aeb1df146756 50 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 76:aeb1df146756 51 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 76:aeb1df146756 52 * See the License for the specific language governing permissions and
mbed_official 76:aeb1df146756 53 * limitations under the License.
mbed_official 76:aeb1df146756 54 *
mbed_official 76:aeb1df146756 55 ******************************************************************************
mbed_official 76:aeb1df146756 56 */
mbed_official 76:aeb1df146756 57
mbed_official 76:aeb1df146756 58 /* Includes ------------------------------------------------------------------*/
mbed_official 76:aeb1df146756 59 #include "stm32l1xx_rcc.h"
mbed_official 76:aeb1df146756 60
mbed_official 76:aeb1df146756 61 /** @addtogroup STM32L1xx_StdPeriph_Driver
mbed_official 76:aeb1df146756 62 * @{
mbed_official 76:aeb1df146756 63 */
mbed_official 76:aeb1df146756 64
mbed_official 76:aeb1df146756 65 /** @defgroup RCC
mbed_official 76:aeb1df146756 66 * @brief RCC driver modules
mbed_official 76:aeb1df146756 67 * @{
mbed_official 76:aeb1df146756 68 */
mbed_official 76:aeb1df146756 69
mbed_official 76:aeb1df146756 70 /* Private typedef -----------------------------------------------------------*/
mbed_official 76:aeb1df146756 71 /* Private define ------------------------------------------------------------*/
mbed_official 76:aeb1df146756 72
mbed_official 76:aeb1df146756 73 /* ------------ RCC registers bit address in the alias region ----------- */
mbed_official 76:aeb1df146756 74 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
mbed_official 76:aeb1df146756 75
mbed_official 76:aeb1df146756 76 /* --- CR Register ---*/
mbed_official 76:aeb1df146756 77
mbed_official 76:aeb1df146756 78 /* Alias word address of HSION bit */
mbed_official 76:aeb1df146756 79 #define CR_OFFSET (RCC_OFFSET + 0x00)
mbed_official 76:aeb1df146756 80 #define HSION_BitNumber 0x00
mbed_official 76:aeb1df146756 81 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
mbed_official 76:aeb1df146756 82
mbed_official 76:aeb1df146756 83 /* Alias word address of MSION bit */
mbed_official 76:aeb1df146756 84 #define MSION_BitNumber 0x08
mbed_official 76:aeb1df146756 85 #define CR_MSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MSION_BitNumber * 4))
mbed_official 76:aeb1df146756 86
mbed_official 76:aeb1df146756 87 /* Alias word address of PLLON bit */
mbed_official 76:aeb1df146756 88 #define PLLON_BitNumber 0x18
mbed_official 76:aeb1df146756 89 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
mbed_official 76:aeb1df146756 90
mbed_official 76:aeb1df146756 91 /* Alias word address of CSSON bit */
mbed_official 76:aeb1df146756 92 #define CSSON_BitNumber 0x1C
mbed_official 76:aeb1df146756 93 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
mbed_official 76:aeb1df146756 94
mbed_official 76:aeb1df146756 95 /* --- CSR Register ---*/
mbed_official 76:aeb1df146756 96
mbed_official 76:aeb1df146756 97 /* Alias word address of LSION bit */
mbed_official 76:aeb1df146756 98 #define CSR_OFFSET (RCC_OFFSET + 0x34)
mbed_official 76:aeb1df146756 99 #define LSION_BitNumber 0x00
mbed_official 76:aeb1df146756 100 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
mbed_official 76:aeb1df146756 101
mbed_official 76:aeb1df146756 102 /* Alias word address of LSECSSON bit */
mbed_official 76:aeb1df146756 103 #define LSECSSON_BitNumber 0x0B
mbed_official 76:aeb1df146756 104 #define CSR_LSECSSON_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSECSSON_BitNumber * 4))
mbed_official 76:aeb1df146756 105
mbed_official 76:aeb1df146756 106 /* Alias word address of RTCEN bit */
mbed_official 76:aeb1df146756 107 #define RTCEN_BitNumber 0x16
mbed_official 76:aeb1df146756 108 #define CSR_RTCEN_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCEN_BitNumber * 4))
mbed_official 76:aeb1df146756 109
mbed_official 76:aeb1df146756 110 /* Alias word address of RTCRST bit */
mbed_official 76:aeb1df146756 111 #define RTCRST_BitNumber 0x17
mbed_official 76:aeb1df146756 112 #define CSR_RTCRST_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCRST_BitNumber * 4))
mbed_official 76:aeb1df146756 113
mbed_official 76:aeb1df146756 114
mbed_official 76:aeb1df146756 115 /* ---------------------- RCC registers mask -------------------------------- */
mbed_official 76:aeb1df146756 116 /* RCC Flag Mask */
mbed_official 76:aeb1df146756 117 #define FLAG_MASK ((uint8_t)0x1F)
mbed_official 76:aeb1df146756 118
mbed_official 76:aeb1df146756 119 /* CR register byte 3 (Bits[23:16]) base address */
mbed_official 76:aeb1df146756 120 #define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
mbed_official 76:aeb1df146756 121
mbed_official 76:aeb1df146756 122 /* ICSCR register byte 4 (Bits[31:24]) base address */
mbed_official 76:aeb1df146756 123 #define ICSCR_BYTE4_ADDRESS ((uint32_t)0x40023807)
mbed_official 76:aeb1df146756 124
mbed_official 76:aeb1df146756 125 /* CFGR register byte 3 (Bits[23:16]) base address */
mbed_official 76:aeb1df146756 126 #define CFGR_BYTE3_ADDRESS ((uint32_t)0x4002380A)
mbed_official 76:aeb1df146756 127
mbed_official 76:aeb1df146756 128 /* CFGR register byte 4 (Bits[31:24]) base address */
mbed_official 76:aeb1df146756 129 #define CFGR_BYTE4_ADDRESS ((uint32_t)0x4002380B)
mbed_official 76:aeb1df146756 130
mbed_official 76:aeb1df146756 131 /* CIR register byte 2 (Bits[15:8]) base address */
mbed_official 76:aeb1df146756 132 #define CIR_BYTE2_ADDRESS ((uint32_t)0x4002380D)
mbed_official 76:aeb1df146756 133
mbed_official 76:aeb1df146756 134 /* CIR register byte 3 (Bits[23:16]) base address */
mbed_official 76:aeb1df146756 135 #define CIR_BYTE3_ADDRESS ((uint32_t)0x4002380E)
mbed_official 76:aeb1df146756 136
mbed_official 76:aeb1df146756 137 /* CSR register byte 2 (Bits[15:8]) base address */
mbed_official 76:aeb1df146756 138 #define CSR_BYTE2_ADDRESS ((uint32_t)0x40023835)
mbed_official 76:aeb1df146756 139
mbed_official 76:aeb1df146756 140 /* Private macro -------------------------------------------------------------*/
mbed_official 76:aeb1df146756 141 /* Private variables ---------------------------------------------------------*/
mbed_official 76:aeb1df146756 142
mbed_official 76:aeb1df146756 143 static __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
mbed_official 76:aeb1df146756 144 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 76:aeb1df146756 145
mbed_official 76:aeb1df146756 146 /* Private function prototypes -----------------------------------------------*/
mbed_official 76:aeb1df146756 147 /* Private functions ---------------------------------------------------------*/
mbed_official 76:aeb1df146756 148
mbed_official 76:aeb1df146756 149 /** @defgroup RCC_Private_Functions
mbed_official 76:aeb1df146756 150 * @{
mbed_official 76:aeb1df146756 151 */
mbed_official 76:aeb1df146756 152
mbed_official 76:aeb1df146756 153 /** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
mbed_official 76:aeb1df146756 154 * @brief Internal and external clocks, PLL, CSS and MCO configuration functions
mbed_official 76:aeb1df146756 155 *
mbed_official 76:aeb1df146756 156 @verbatim
mbed_official 76:aeb1df146756 157 ===============================================================================
mbed_official 76:aeb1df146756 158 ##### Internal-external clocks, PLL, CSS and MCO configuration functions #####
mbed_official 76:aeb1df146756 159 ===============================================================================
mbed_official 76:aeb1df146756 160 [..] This section provide functions allowing to configure the internal/external
mbed_official 76:aeb1df146756 161 clocks, PLL, CSS and MCO.
mbed_official 76:aeb1df146756 162 (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly
mbed_official 76:aeb1df146756 163 or through the PLL as System clock source.
mbed_official 76:aeb1df146756 164 (#) MSI (multi-speed internal), multispeed low power RC
mbed_official 76:aeb1df146756 165 (65.536 KHz to 4.194 MHz) MHz used as System clock source.
mbed_official 76:aeb1df146756 166 (#) LSI (low-speed internal), 37 KHz low consumption RC used as IWDG
mbed_official 76:aeb1df146756 167 and/or RTC clock source.
mbed_official 76:aeb1df146756 168 (#) HSE (high-speed external), 1 to 24 MHz crystal oscillator used
mbed_official 76:aeb1df146756 169 directly or through the PLL as System clock source. Can be used
mbed_official 76:aeb1df146756 170 also as RTC clock source.
mbed_official 76:aeb1df146756 171 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
mbed_official 76:aeb1df146756 172 (#) PLL (clocked by HSI or HSE), for System clock and USB (48 MHz).
mbed_official 76:aeb1df146756 173 (#) CSS (Clock security system), once enable and if a HSE clock failure
mbed_official 76:aeb1df146756 174 occurs (HSE used directly or through PLL as System clock source),
mbed_official 76:aeb1df146756 175 the System clock is automatically switched to MSI and an interrupt
mbed_official 76:aeb1df146756 176 is generated if enabled.
mbed_official 76:aeb1df146756 177 The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt)
mbed_official 76:aeb1df146756 178 exception vector.
mbed_official 76:aeb1df146756 179 (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, MSI,
mbed_official 76:aeb1df146756 180 HSE, PLL, LSI or LSE clock (through a configurable prescaler) on
mbed_official 76:aeb1df146756 181 PA8 pin.
mbed_official 76:aeb1df146756 182
mbed_official 76:aeb1df146756 183 @endverbatim
mbed_official 76:aeb1df146756 184 * @{
mbed_official 76:aeb1df146756 185 */
mbed_official 76:aeb1df146756 186
mbed_official 76:aeb1df146756 187 /**
mbed_official 76:aeb1df146756 188 * @brief Resets the RCC clock configuration to the default reset state.
mbed_official 76:aeb1df146756 189 * @note The default reset state of the clock configuration is given below:
mbed_official 76:aeb1df146756 190 * @note MSI ON and used as system clock source (MSI range is not modified
mbed_official 76:aeb1df146756 191 * by this function, it keep the value configured by user application)
mbed_official 76:aeb1df146756 192 * @note HSI, HSE and PLL OFF
mbed_official 76:aeb1df146756 193 * @note AHB, APB1 and APB2 prescaler set to 1.
mbed_official 76:aeb1df146756 194 * @note CSS and MCO OFF
mbed_official 76:aeb1df146756 195 * @note All interrupts disabled
mbed_official 76:aeb1df146756 196 * @note However, this function doesn't modify the configuration of the
mbed_official 76:aeb1df146756 197 * @note Peripheral clocks
mbed_official 76:aeb1df146756 198 * @note LSI, LSE and RTC clocks
mbed_official 76:aeb1df146756 199 * @param None
mbed_official 76:aeb1df146756 200 * @retval None
mbed_official 76:aeb1df146756 201 */
mbed_official 76:aeb1df146756 202 void RCC_DeInit(void)
mbed_official 76:aeb1df146756 203 {
mbed_official 76:aeb1df146756 204
mbed_official 76:aeb1df146756 205 /* Set MSION bit */
mbed_official 76:aeb1df146756 206 RCC->CR |= (uint32_t)0x00000100;
mbed_official 76:aeb1df146756 207
mbed_official 76:aeb1df146756 208 /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
mbed_official 76:aeb1df146756 209 RCC->CFGR &= (uint32_t)0x88FFC00C;
mbed_official 76:aeb1df146756 210
mbed_official 76:aeb1df146756 211 /* Reset HSION, HSEON, CSSON and PLLON bits */
mbed_official 76:aeb1df146756 212 RCC->CR &= (uint32_t)0xEEFEFFFE;
mbed_official 76:aeb1df146756 213
mbed_official 76:aeb1df146756 214 /* Reset HSEBYP bit */
mbed_official 76:aeb1df146756 215 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 76:aeb1df146756 216
mbed_official 76:aeb1df146756 217 /* Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
mbed_official 76:aeb1df146756 218 RCC->CFGR &= (uint32_t)0xFF02FFFF;
mbed_official 76:aeb1df146756 219
mbed_official 76:aeb1df146756 220 /* Disable all interrupts */
mbed_official 76:aeb1df146756 221 RCC->CIR = 0x00000000;
mbed_official 76:aeb1df146756 222 }
mbed_official 76:aeb1df146756 223
mbed_official 76:aeb1df146756 224 /**
mbed_official 76:aeb1df146756 225 * @brief Configures the External High Speed oscillator (HSE).
mbed_official 76:aeb1df146756 226 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
mbed_official 76:aeb1df146756 227 * software should wait on HSERDY flag to be set indicating that HSE clock
mbed_official 76:aeb1df146756 228 * is stable and can be used to clock the PLL and/or system clock.
mbed_official 76:aeb1df146756 229 * @note HSE state can not be changed if it is used directly or through the
mbed_official 76:aeb1df146756 230 * PLL as system clock. In this case, you have to select another source
mbed_official 76:aeb1df146756 231 * of the system clock then change the HSE state (ex. disable it).
mbed_official 76:aeb1df146756 232 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
mbed_official 76:aeb1df146756 233 * @note This function reset the CSSON bit, so if the Clock security system(CSS)
mbed_official 76:aeb1df146756 234 * was previously enabled you have to enable it again after calling this
mbed_official 76:aeb1df146756 235 * function.
mbed_official 76:aeb1df146756 236 * @param RCC_HSE: specifies the new state of the HSE.
mbed_official 76:aeb1df146756 237 * This parameter can be one of the following values:
mbed_official 76:aeb1df146756 238 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
mbed_official 76:aeb1df146756 239 * 6 HSE oscillator clock cycles.
mbed_official 76:aeb1df146756 240 * @arg RCC_HSE_ON: turn ON the HSE oscillator
mbed_official 76:aeb1df146756 241 * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
mbed_official 76:aeb1df146756 242 * @retval None
mbed_official 76:aeb1df146756 243 */
mbed_official 76:aeb1df146756 244 void RCC_HSEConfig(uint8_t RCC_HSE)
mbed_official 76:aeb1df146756 245 {
mbed_official 76:aeb1df146756 246 /* Check the parameters */
mbed_official 76:aeb1df146756 247 assert_param(IS_RCC_HSE(RCC_HSE));
mbed_official 76:aeb1df146756 248
mbed_official 76:aeb1df146756 249 /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
mbed_official 76:aeb1df146756 250 *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
mbed_official 76:aeb1df146756 251
mbed_official 76:aeb1df146756 252 /* Set the new HSE configuration -------------------------------------------*/
mbed_official 76:aeb1df146756 253 *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
mbed_official 76:aeb1df146756 254
mbed_official 76:aeb1df146756 255 }
mbed_official 76:aeb1df146756 256
mbed_official 76:aeb1df146756 257 /**
mbed_official 76:aeb1df146756 258 * @brief Waits for HSE start-up.
mbed_official 76:aeb1df146756 259 * @note This functions waits on HSERDY flag to be set and return SUCCESS if
mbed_official 76:aeb1df146756 260 * this flag is set, otherwise returns ERROR if the timeout is reached
mbed_official 76:aeb1df146756 261 * and this flag is not set. The timeout value is defined by the constant
mbed_official 76:aeb1df146756 262 * HSE_STARTUP_TIMEOUT in stm32l1xx.h file. You can tailor it depending
mbed_official 76:aeb1df146756 263 * on the HSE crystal used in your application.
mbed_official 76:aeb1df146756 264 * @param None
mbed_official 76:aeb1df146756 265 * @retval An ErrorStatus enumeration value:
mbed_official 76:aeb1df146756 266 * - SUCCESS: HSE oscillator is stable and ready to use
mbed_official 76:aeb1df146756 267 * - ERROR: HSE oscillator not yet ready
mbed_official 76:aeb1df146756 268 */
mbed_official 76:aeb1df146756 269 ErrorStatus RCC_WaitForHSEStartUp(void)
mbed_official 76:aeb1df146756 270 {
mbed_official 76:aeb1df146756 271 __IO uint32_t StartUpCounter = 0;
mbed_official 76:aeb1df146756 272 ErrorStatus status = ERROR;
mbed_official 76:aeb1df146756 273 FlagStatus HSEStatus = RESET;
mbed_official 76:aeb1df146756 274
mbed_official 76:aeb1df146756 275 /* Wait till HSE is ready and if timeout is reached exit */
mbed_official 76:aeb1df146756 276 do
mbed_official 76:aeb1df146756 277 {
mbed_official 76:aeb1df146756 278 HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
mbed_official 76:aeb1df146756 279 StartUpCounter++;
mbed_official 76:aeb1df146756 280 } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
mbed_official 76:aeb1df146756 281
mbed_official 76:aeb1df146756 282 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
mbed_official 76:aeb1df146756 283 {
mbed_official 76:aeb1df146756 284 status = SUCCESS;
mbed_official 76:aeb1df146756 285 }
mbed_official 76:aeb1df146756 286 else
mbed_official 76:aeb1df146756 287 {
mbed_official 76:aeb1df146756 288 status = ERROR;
mbed_official 76:aeb1df146756 289 }
mbed_official 76:aeb1df146756 290 return (status);
mbed_official 76:aeb1df146756 291 }
mbed_official 76:aeb1df146756 292
mbed_official 76:aeb1df146756 293 /**
mbed_official 76:aeb1df146756 294 * @brief Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
mbed_official 76:aeb1df146756 295 * @note The calibration is used to compensate for the variations in voltage
mbed_official 76:aeb1df146756 296 * and temperature that influence the frequency of the internal MSI RC.
mbed_official 76:aeb1df146756 297 * Refer to the Application Note AN3300 for more details on how to
mbed_official 76:aeb1df146756 298 * calibrate the MSI.
mbed_official 76:aeb1df146756 299 * @param MSICalibrationValue: specifies the MSI calibration trimming value.
mbed_official 76:aeb1df146756 300 * This parameter must be a number between 0 and 0xFF.
mbed_official 76:aeb1df146756 301 * @retval None
mbed_official 76:aeb1df146756 302 */
mbed_official 76:aeb1df146756 303 void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue)
mbed_official 76:aeb1df146756 304 {
mbed_official 76:aeb1df146756 305
mbed_official 76:aeb1df146756 306 /* Check the parameters */
mbed_official 76:aeb1df146756 307 assert_param(IS_RCC_MSI_CALIBRATION_VALUE(MSICalibrationValue));
mbed_official 76:aeb1df146756 308
mbed_official 76:aeb1df146756 309 *(__IO uint8_t *) ICSCR_BYTE4_ADDRESS = MSICalibrationValue;
mbed_official 76:aeb1df146756 310 }
mbed_official 76:aeb1df146756 311
mbed_official 76:aeb1df146756 312 /**
mbed_official 76:aeb1df146756 313 * @brief Configures the Internal Multi Speed oscillator (MSI) clock range.
mbed_official 76:aeb1df146756 314 * @note After restart from Reset or wakeup from STANDBY, the MSI clock is
mbed_official 76:aeb1df146756 315 * around 2.097 MHz. The MSI clock does not change after wake-up from
mbed_official 76:aeb1df146756 316 * STOP mode.
mbed_official 76:aeb1df146756 317 * @note The MSI clock range can be modified on the fly.
mbed_official 76:aeb1df146756 318 * @param RCC_MSIRange: specifies the MSI Clock range.
mbed_official 76:aeb1df146756 319 * This parameter must be one of the following values:
mbed_official 76:aeb1df146756 320 * @arg RCC_MSIRange_0: MSI clock is around 65.536 KHz
mbed_official 76:aeb1df146756 321 * @arg RCC_MSIRange_1: MSI clock is around 131.072 KHz
mbed_official 76:aeb1df146756 322 * @arg RCC_MSIRange_2: MSI clock is around 262.144 KHz
mbed_official 76:aeb1df146756 323 * @arg RCC_MSIRange_3: MSI clock is around 524.288 KHz
mbed_official 76:aeb1df146756 324 * @arg RCC_MSIRange_4: MSI clock is around 1.048 MHz
mbed_official 76:aeb1df146756 325 * @arg RCC_MSIRange_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
mbed_official 76:aeb1df146756 326 * @arg RCC_MSIRange_6: MSI clock is around 4.194 MHz
mbed_official 76:aeb1df146756 327 *
mbed_official 76:aeb1df146756 328 * @retval None
mbed_official 76:aeb1df146756 329 */
mbed_official 76:aeb1df146756 330 void RCC_MSIRangeConfig(uint32_t RCC_MSIRange)
mbed_official 76:aeb1df146756 331 {
mbed_official 76:aeb1df146756 332 uint32_t tmpreg = 0;
mbed_official 76:aeb1df146756 333
mbed_official 76:aeb1df146756 334 /* Check the parameters */
mbed_official 76:aeb1df146756 335 assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_MSIRange));
mbed_official 76:aeb1df146756 336
mbed_official 76:aeb1df146756 337 tmpreg = RCC->ICSCR;
mbed_official 76:aeb1df146756 338
mbed_official 76:aeb1df146756 339 /* Clear MSIRANGE[2:0] bits */
mbed_official 76:aeb1df146756 340 tmpreg &= ~RCC_ICSCR_MSIRANGE;
mbed_official 76:aeb1df146756 341
mbed_official 76:aeb1df146756 342 /* Set the MSIRANGE[2:0] bits according to RCC_MSIRange value */
mbed_official 76:aeb1df146756 343 tmpreg |= (uint32_t)RCC_MSIRange;
mbed_official 76:aeb1df146756 344
mbed_official 76:aeb1df146756 345 /* Store the new value */
mbed_official 76:aeb1df146756 346 RCC->ICSCR = tmpreg;
mbed_official 76:aeb1df146756 347 }
mbed_official 76:aeb1df146756 348
mbed_official 76:aeb1df146756 349 /**
mbed_official 76:aeb1df146756 350 * @brief Enables or disables the Internal Multi Speed oscillator (MSI).
mbed_official 76:aeb1df146756 351 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official 76:aeb1df146756 352 * It is used (enabled by hardware) as system clock source after
mbed_official 76:aeb1df146756 353 * startup from Reset, wakeup from STOP and STANDBY mode, or in case
mbed_official 76:aeb1df146756 354 * of failure of the HSE used directly or indirectly as system clock
mbed_official 76:aeb1df146756 355 * (if the Clock Security System CSS is enabled).
mbed_official 76:aeb1df146756 356 * @note MSI can not be stopped if it is used as system clock source.
mbed_official 76:aeb1df146756 357 * In this case, you have to select another source of the system
mbed_official 76:aeb1df146756 358 * clock then stop the MSI.
mbed_official 76:aeb1df146756 359 * @note After enabling the MSI, the application software should wait on
mbed_official 76:aeb1df146756 360 * MSIRDY flag to be set indicating that MSI clock is stable and can
mbed_official 76:aeb1df146756 361 * be used as system clock source.
mbed_official 76:aeb1df146756 362 * @param NewState: new state of the MSI.
mbed_official 76:aeb1df146756 363 * This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 364 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
mbed_official 76:aeb1df146756 365 * clock cycles.
mbed_official 76:aeb1df146756 366 * @retval None
mbed_official 76:aeb1df146756 367 */
mbed_official 76:aeb1df146756 368 void RCC_MSICmd(FunctionalState NewState)
mbed_official 76:aeb1df146756 369 {
mbed_official 76:aeb1df146756 370 /* Check the parameters */
mbed_official 76:aeb1df146756 371 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 372
mbed_official 76:aeb1df146756 373 *(__IO uint32_t *) CR_MSION_BB = (uint32_t)NewState;
mbed_official 76:aeb1df146756 374 }
mbed_official 76:aeb1df146756 375
mbed_official 76:aeb1df146756 376 /**
mbed_official 76:aeb1df146756 377 * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
mbed_official 76:aeb1df146756 378 * @note The calibration is used to compensate for the variations in voltage
mbed_official 76:aeb1df146756 379 * and temperature that influence the frequency of the internal HSI RC.
mbed_official 76:aeb1df146756 380 * Refer to the Application Note AN3300 for more details on how to
mbed_official 76:aeb1df146756 381 * calibrate the HSI.
mbed_official 76:aeb1df146756 382 * @param HSICalibrationValue: specifies the HSI calibration trimming value.
mbed_official 76:aeb1df146756 383 * This parameter must be a number between 0 and 0x1F.
mbed_official 76:aeb1df146756 384 * @retval None
mbed_official 76:aeb1df146756 385 */
mbed_official 76:aeb1df146756 386 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
mbed_official 76:aeb1df146756 387 {
mbed_official 76:aeb1df146756 388 uint32_t tmpreg = 0;
mbed_official 76:aeb1df146756 389
mbed_official 76:aeb1df146756 390 /* Check the parameters */
mbed_official 76:aeb1df146756 391 assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
mbed_official 76:aeb1df146756 392
mbed_official 76:aeb1df146756 393 tmpreg = RCC->ICSCR;
mbed_official 76:aeb1df146756 394
mbed_official 76:aeb1df146756 395 /* Clear HSITRIM[4:0] bits */
mbed_official 76:aeb1df146756 396 tmpreg &= ~RCC_ICSCR_HSITRIM;
mbed_official 76:aeb1df146756 397
mbed_official 76:aeb1df146756 398 /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
mbed_official 76:aeb1df146756 399 tmpreg |= (uint32_t)HSICalibrationValue << 8;
mbed_official 76:aeb1df146756 400
mbed_official 76:aeb1df146756 401 /* Store the new value */
mbed_official 76:aeb1df146756 402 RCC->ICSCR = tmpreg;
mbed_official 76:aeb1df146756 403 }
mbed_official 76:aeb1df146756 404
mbed_official 76:aeb1df146756 405 /**
mbed_official 76:aeb1df146756 406 * @brief Enables or disables the Internal High Speed oscillator (HSI).
mbed_official 76:aeb1df146756 407 * @note After enabling the HSI, the application software should wait on
mbed_official 76:aeb1df146756 408 * HSIRDY flag to be set indicating that HSI clock is stable and can
mbed_official 76:aeb1df146756 409 * be used to clock the PLL and/or system clock.
mbed_official 76:aeb1df146756 410 * @note HSI can not be stopped if it is used directly or through the PLL
mbed_official 76:aeb1df146756 411 * as system clock. In this case, you have to select another source
mbed_official 76:aeb1df146756 412 * of the system clock then stop the HSI.
mbed_official 76:aeb1df146756 413 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official 76:aeb1df146756 414 * @param NewState: new state of the HSI.
mbed_official 76:aeb1df146756 415 * This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 416 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
mbed_official 76:aeb1df146756 417 * clock cycles.
mbed_official 76:aeb1df146756 418 * @retval None
mbed_official 76:aeb1df146756 419 */
mbed_official 76:aeb1df146756 420 void RCC_HSICmd(FunctionalState NewState)
mbed_official 76:aeb1df146756 421 {
mbed_official 76:aeb1df146756 422 /* Check the parameters */
mbed_official 76:aeb1df146756 423 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 424
mbed_official 76:aeb1df146756 425 *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
mbed_official 76:aeb1df146756 426 }
mbed_official 76:aeb1df146756 427
mbed_official 76:aeb1df146756 428 /**
mbed_official 76:aeb1df146756 429 * @brief Configures the External Low Speed oscillator (LSE).
mbed_official 76:aeb1df146756 430 * @note As the LSE is in the RTC domain and write access is denied to this
mbed_official 76:aeb1df146756 431 * domain after reset, you have to enable write access using
mbed_official 76:aeb1df146756 432 * PWR_RTCAccessCmd(ENABLE) function before to configure the LSE
mbed_official 76:aeb1df146756 433 * (to be done once after reset).
mbed_official 76:aeb1df146756 434 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
mbed_official 76:aeb1df146756 435 * software should wait on LSERDY flag to be set indicating that LSE clock
mbed_official 76:aeb1df146756 436 * is stable and can be used to clock the RTC.
mbed_official 76:aeb1df146756 437 * @param RCC_LSE: specifies the new state of the LSE.
mbed_official 76:aeb1df146756 438 * This parameter can be one of the following values:
mbed_official 76:aeb1df146756 439 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
mbed_official 76:aeb1df146756 440 * 6 LSE oscillator clock cycles.
mbed_official 76:aeb1df146756 441 * @arg RCC_LSE_ON: turn ON the LSE oscillator
mbed_official 76:aeb1df146756 442 * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
mbed_official 76:aeb1df146756 443 * @retval None
mbed_official 76:aeb1df146756 444 */
mbed_official 76:aeb1df146756 445 void RCC_LSEConfig(uint8_t RCC_LSE)
mbed_official 76:aeb1df146756 446 {
mbed_official 76:aeb1df146756 447 /* Check the parameters */
mbed_official 76:aeb1df146756 448 assert_param(IS_RCC_LSE(RCC_LSE));
mbed_official 76:aeb1df146756 449
mbed_official 76:aeb1df146756 450 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
mbed_official 76:aeb1df146756 451 *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE_OFF;
mbed_official 76:aeb1df146756 452
mbed_official 76:aeb1df146756 453 /* Set the new LSE configuration -------------------------------------------*/
mbed_official 76:aeb1df146756 454 *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE;
mbed_official 76:aeb1df146756 455 }
mbed_official 76:aeb1df146756 456
mbed_official 76:aeb1df146756 457 /**
mbed_official 76:aeb1df146756 458 * @brief Enables or disables the Internal Low Speed oscillator (LSI).
mbed_official 76:aeb1df146756 459 * @note After enabling the LSI, the application software should wait on
mbed_official 76:aeb1df146756 460 * LSIRDY flag to be set indicating that LSI clock is stable and can
mbed_official 76:aeb1df146756 461 * be used to clock the IWDG and/or the RTC.
mbed_official 76:aeb1df146756 462 * @note LSI can not be disabled if the IWDG is running.
mbed_official 76:aeb1df146756 463 * @param NewState: new state of the LSI.
mbed_official 76:aeb1df146756 464 * This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 465 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
mbed_official 76:aeb1df146756 466 * clock cycles.
mbed_official 76:aeb1df146756 467 * @retval None
mbed_official 76:aeb1df146756 468 */
mbed_official 76:aeb1df146756 469 void RCC_LSICmd(FunctionalState NewState)
mbed_official 76:aeb1df146756 470 {
mbed_official 76:aeb1df146756 471 /* Check the parameters */
mbed_official 76:aeb1df146756 472 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 473
mbed_official 76:aeb1df146756 474 *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
mbed_official 76:aeb1df146756 475 }
mbed_official 76:aeb1df146756 476
mbed_official 76:aeb1df146756 477 /**
mbed_official 76:aeb1df146756 478 * @brief Configures the PLL clock source and multiplication factor.
mbed_official 76:aeb1df146756 479 * @note This function must be used only when the PLL is disabled.
mbed_official 76:aeb1df146756 480 *
mbed_official 76:aeb1df146756 481 * @param RCC_PLLSource: specifies the PLL entry clock source.
mbed_official 76:aeb1df146756 482 * This parameter can be one of the following values:
mbed_official 76:aeb1df146756 483 * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock source
mbed_official 76:aeb1df146756 484 * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock source
mbed_official 76:aeb1df146756 485 * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as
mbed_official 76:aeb1df146756 486 * PLL source).
mbed_official 76:aeb1df146756 487 *
mbed_official 76:aeb1df146756 488 * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
mbed_official 76:aeb1df146756 489 * This parameter can be:
mbed_official 76:aeb1df146756 490 * @arg RCC_PLLMul_3: PLL clock source multiplied by 3
mbed_official 76:aeb1df146756 491 * @arg RCC_PLLMul_4: PLL clock source multiplied by 4
mbed_official 76:aeb1df146756 492 * @arg RCC_PLLMul_6: PLL clock source multiplied by 6
mbed_official 76:aeb1df146756 493 * @arg RCC_PLLMul_8: PLL clock source multiplied by 8
mbed_official 76:aeb1df146756 494 * @arg RCC_PLLMul_12: PLL clock source multiplied by 12
mbed_official 76:aeb1df146756 495 * @arg RCC_PLLMul_16: PLL clock source multiplied by 16
mbed_official 76:aeb1df146756 496 * @arg RCC_PLLMul_24: PLL clock source multiplied by 24
mbed_official 76:aeb1df146756 497 * @arg RCC_PLLMul_32: PLL clock source multiplied by 32
mbed_official 76:aeb1df146756 498 * @arg RCC_PLLMul_48: PLL clock source multiplied by 48
mbed_official 76:aeb1df146756 499 * @note The application software must set correctly the PLL multiplication
mbed_official 76:aeb1df146756 500 * factor to avoid exceeding:
mbed_official 76:aeb1df146756 501 * - 96 MHz as PLLVCO when the product is in range 1
mbed_official 76:aeb1df146756 502 * - 48 MHz as PLLVCO when the product is in range 2
mbed_official 76:aeb1df146756 503 * - 24 MHz when the product is in range 3
mbed_official 76:aeb1df146756 504 * @note When using the USB the PLLVCO should be 96MHz
mbed_official 76:aeb1df146756 505 *
mbed_official 76:aeb1df146756 506 * @param RCC_PLLDiv: specifies the PLL division factor.
mbed_official 76:aeb1df146756 507 * This parameter can be:
mbed_official 76:aeb1df146756 508 * @arg RCC_PLLDiv_2: PLL Clock output divided by 2
mbed_official 76:aeb1df146756 509 * @arg RCC_PLLDiv_3: PLL Clock output divided by 3
mbed_official 76:aeb1df146756 510 * @arg RCC_PLLDiv_4: PLL Clock output divided by 4
mbed_official 76:aeb1df146756 511 * @note The application software must set correctly the output division to avoid
mbed_official 76:aeb1df146756 512 * exceeding 32 MHz as SYSCLK.
mbed_official 76:aeb1df146756 513 *
mbed_official 76:aeb1df146756 514 * @retval None
mbed_official 76:aeb1df146756 515 */
mbed_official 76:aeb1df146756 516 void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv)
mbed_official 76:aeb1df146756 517 {
mbed_official 76:aeb1df146756 518 /* Check the parameters */
mbed_official 76:aeb1df146756 519 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
mbed_official 76:aeb1df146756 520 assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
mbed_official 76:aeb1df146756 521 assert_param(IS_RCC_PLL_DIV(RCC_PLLDiv));
mbed_official 76:aeb1df146756 522
mbed_official 76:aeb1df146756 523 *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = (uint8_t)(RCC_PLLSource | ((uint8_t)(RCC_PLLMul | (uint8_t)(RCC_PLLDiv))));
mbed_official 76:aeb1df146756 524 }
mbed_official 76:aeb1df146756 525
mbed_official 76:aeb1df146756 526 /**
mbed_official 76:aeb1df146756 527 * @brief Enables or disables the PLL.
mbed_official 76:aeb1df146756 528 * @note After enabling the PLL, the application software should wait on
mbed_official 76:aeb1df146756 529 * PLLRDY flag to be set indicating that PLL clock is stable and can
mbed_official 76:aeb1df146756 530 * be used as system clock source.
mbed_official 76:aeb1df146756 531 * @note The PLL can not be disabled if it is used as system clock source
mbed_official 76:aeb1df146756 532 * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
mbed_official 76:aeb1df146756 533 * @param NewState: new state of the PLL.
mbed_official 76:aeb1df146756 534 * This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 535 * @retval None
mbed_official 76:aeb1df146756 536 */
mbed_official 76:aeb1df146756 537 void RCC_PLLCmd(FunctionalState NewState)
mbed_official 76:aeb1df146756 538 {
mbed_official 76:aeb1df146756 539 /* Check the parameters */
mbed_official 76:aeb1df146756 540 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 541
mbed_official 76:aeb1df146756 542 *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
mbed_official 76:aeb1df146756 543 }
mbed_official 76:aeb1df146756 544
mbed_official 76:aeb1df146756 545 /**
mbed_official 76:aeb1df146756 546 * @brief Enables or disables the Clock Security System.
mbed_official 76:aeb1df146756 547 * @note If a failure is detected on the HSE oscillator clock, this oscillator
mbed_official 76:aeb1df146756 548 * is automatically disabled and an interrupt is generated to inform the
mbed_official 76:aeb1df146756 549 * software about the failure (Clock Security System Interrupt, CSSI),
mbed_official 76:aeb1df146756 550 * allowing the MCU to perform rescue operations. The CSSI is linked to
mbed_official 76:aeb1df146756 551 * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
mbed_official 76:aeb1df146756 552 * @param NewState: new state of the Clock Security System.
mbed_official 76:aeb1df146756 553 * This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 554 * @retval None
mbed_official 76:aeb1df146756 555 */
mbed_official 76:aeb1df146756 556 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
mbed_official 76:aeb1df146756 557 {
mbed_official 76:aeb1df146756 558 /* Check the parameters */
mbed_official 76:aeb1df146756 559 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 560
mbed_official 76:aeb1df146756 561 *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
mbed_official 76:aeb1df146756 562 }
mbed_official 76:aeb1df146756 563
mbed_official 76:aeb1df146756 564 /**
mbed_official 76:aeb1df146756 565 * @brief Enables or disables the LSE Clock Security System.
mbed_official 76:aeb1df146756 566 * @param NewState: new state of the Clock Security System.
mbed_official 76:aeb1df146756 567 * This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 568 * @retval None
mbed_official 76:aeb1df146756 569 */
mbed_official 76:aeb1df146756 570 void RCC_LSEClockSecuritySystemCmd(FunctionalState NewState)
mbed_official 76:aeb1df146756 571 {
mbed_official 76:aeb1df146756 572 /* Check the parameters */
mbed_official 76:aeb1df146756 573 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 574
mbed_official 76:aeb1df146756 575 *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)NewState;
mbed_official 76:aeb1df146756 576 }
mbed_official 76:aeb1df146756 577
mbed_official 76:aeb1df146756 578 /**
mbed_official 76:aeb1df146756 579 * @brief Selects the clock source to output on MCO pin (PA8).
mbed_official 76:aeb1df146756 580 * @note PA8 should be configured in alternate function mode.
mbed_official 76:aeb1df146756 581 * @param RCC_MCOSource: specifies the clock source to output.
mbed_official 76:aeb1df146756 582 * This parameter can be one of the following values:
mbed_official 76:aeb1df146756 583 * @arg RCC_MCOSource_NoClock: No clock selected
mbed_official 76:aeb1df146756 584 * @arg RCC_MCOSource_SYSCLK: System clock selected
mbed_official 76:aeb1df146756 585 * @arg RCC_MCOSource_HSI: HSI oscillator clock selected
mbed_official 76:aeb1df146756 586 * @arg RCC_MCOSource_MSI: MSI oscillator clock selected
mbed_official 76:aeb1df146756 587 * @arg RCC_MCOSource_HSE: HSE oscillator clock selected
mbed_official 76:aeb1df146756 588 * @arg RCC_MCOSource_PLLCLK: PLL clock selected
mbed_official 76:aeb1df146756 589 * @arg RCC_MCOSource_LSI: LSI clock selected
mbed_official 76:aeb1df146756 590 * @arg RCC_MCOSource_LSE: LSE clock selected
mbed_official 76:aeb1df146756 591 * @param RCC_MCODiv: specifies the MCO prescaler.
mbed_official 76:aeb1df146756 592 * This parameter can be one of the following values:
mbed_official 76:aeb1df146756 593 * @arg RCC_MCODiv_1: no division applied to MCO clock
mbed_official 76:aeb1df146756 594 * @arg RCC_MCODiv_2: division by 2 applied to MCO clock
mbed_official 76:aeb1df146756 595 * @arg RCC_MCODiv_4: division by 4 applied to MCO clock
mbed_official 76:aeb1df146756 596 * @arg RCC_MCODiv_8: division by 8 applied to MCO clock
mbed_official 76:aeb1df146756 597 * @arg RCC_MCODiv_16: division by 16 applied to MCO clock
mbed_official 76:aeb1df146756 598 * @retval None
mbed_official 76:aeb1df146756 599 */
mbed_official 76:aeb1df146756 600 void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv)
mbed_official 76:aeb1df146756 601 {
mbed_official 76:aeb1df146756 602 /* Check the parameters */
mbed_official 76:aeb1df146756 603 assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
mbed_official 76:aeb1df146756 604 assert_param(IS_RCC_MCO_DIV(RCC_MCODiv));
mbed_official 76:aeb1df146756 605
mbed_official 76:aeb1df146756 606 /* Select MCO clock source and prescaler */
mbed_official 76:aeb1df146756 607 *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCOSource | RCC_MCODiv;
mbed_official 76:aeb1df146756 608 }
mbed_official 76:aeb1df146756 609
mbed_official 76:aeb1df146756 610 /**
mbed_official 76:aeb1df146756 611 * @}
mbed_official 76:aeb1df146756 612 */
mbed_official 76:aeb1df146756 613
mbed_official 76:aeb1df146756 614 /** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
mbed_official 76:aeb1df146756 615 * @brief System, AHB and APB busses clocks configuration functions
mbed_official 76:aeb1df146756 616 *
mbed_official 76:aeb1df146756 617 @verbatim
mbed_official 76:aeb1df146756 618 ===============================================================================
mbed_official 76:aeb1df146756 619 ##### System, AHB and APB busses clocks configuration functions #####
mbed_official 76:aeb1df146756 620 ===============================================================================
mbed_official 76:aeb1df146756 621 [..] This section provide functions allowing to configure the System, AHB,
mbed_official 76:aeb1df146756 622 APB1 and APB2 busses clocks.
mbed_official 76:aeb1df146756 623 (#) Several clock sources can be used to drive the System clock (SYSCLK):
mbed_official 76:aeb1df146756 624 MSI, HSI, HSE and PLL.
mbed_official 76:aeb1df146756 625 The AHB clock (HCLK) is derived from System clock through configurable
mbed_official 76:aeb1df146756 626 prescaler and used to clock the CPU, memory and peripherals mapped
mbed_official 76:aeb1df146756 627 on AHB bus (DMA and GPIO).APB1 (PCLK1) and APB2 (PCLK2) clocks are
mbed_official 76:aeb1df146756 628 derived from AHB clock through configurable prescalers and used to
mbed_official 76:aeb1df146756 629 clock the peripherals mapped on these busses. You can use
mbed_official 76:aeb1df146756 630 "RCC_GetClocksFreq()" function to retrieve the frequencies of these
mbed_official 76:aeb1df146756 631 clocks.
mbed_official 76:aeb1df146756 632
mbed_official 76:aeb1df146756 633 -@- All the peripheral clocks are derived from the System clock (SYSCLK)
mbed_official 76:aeb1df146756 634 except:
mbed_official 76:aeb1df146756 635 (+@) The USB 48 MHz clock which is derived from the PLL VCO clock.
mbed_official 76:aeb1df146756 636 (+@) The ADC clock which is always the HSI clock. A divider by 1, 2
mbed_official 76:aeb1df146756 637 or 4 allows to adapt the clock frequency to the device operating
mbed_official 76:aeb1df146756 638 conditions.
mbed_official 76:aeb1df146756 639 (+@) The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz
mbed_official 76:aeb1df146756 640 HSE_RTC (HSE divided by a programmable prescaler).
mbed_official 76:aeb1df146756 641 The System clock (SYSCLK) frequency must be higher or equal to
mbed_official 76:aeb1df146756 642 the RTC/LCD clock frequency.
mbed_official 76:aeb1df146756 643 (+@) IWDG clock which is always the LSI clock.
mbed_official 76:aeb1df146756 644
mbed_official 76:aeb1df146756 645 (#) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 32 MHz.
mbed_official 76:aeb1df146756 646 Depending on the device voltage range, the maximum frequency should
mbed_official 76:aeb1df146756 647 be adapted accordingly:
mbed_official 76:aeb1df146756 648
mbed_official 76:aeb1df146756 649 +----------------------------------------------------------------+
mbed_official 76:aeb1df146756 650 | Wait states | HCLK clock frequency (MHz) |
mbed_official 76:aeb1df146756 651 | |------------------------------------------------|
mbed_official 76:aeb1df146756 652 | (Latency) | voltage range | voltage range |
mbed_official 76:aeb1df146756 653 | | 1.65 V - 3.6 V | 2.0 V - 3.6 V |
mbed_official 76:aeb1df146756 654 | |----------------|---------------|---------------|
mbed_official 76:aeb1df146756 655 | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |
mbed_official 76:aeb1df146756 656 |-------------- |----------------|---------------|---------------|
mbed_official 76:aeb1df146756 657 |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |
mbed_official 76:aeb1df146756 658 |---------------|----------------|---------------|---------------|
mbed_official 76:aeb1df146756 659 |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32|
mbed_official 76:aeb1df146756 660 +----------------------------------------------------------------+
mbed_official 76:aeb1df146756 661
mbed_official 76:aeb1df146756 662 (#) After reset, the System clock source is the MSI (2 MHz) with 0 WS,
mbed_official 76:aeb1df146756 663 Flash 32-bit access is enabled and prefetch is disabled.
mbed_official 76:aeb1df146756 664 [..] It is recommended to use the following software sequences to tune the
mbed_official 76:aeb1df146756 665 number of wait states needed to access the Flash memory with the CPU
mbed_official 76:aeb1df146756 666 frequency (HCLK).
mbed_official 76:aeb1df146756 667 (+) Increasing the CPU frequency (in the same voltage range)
mbed_official 76:aeb1df146756 668 (+) Program the Flash 64-bit access, using "FLASH_ReadAccess64Cmd(ENABLE)"
mbed_official 76:aeb1df146756 669 function
mbed_official 76:aeb1df146756 670 (+) Check that 64-bit access is taken into account by reading FLASH_ACR
mbed_official 76:aeb1df146756 671 (+) Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)"
mbed_official 76:aeb1df146756 672 function
mbed_official 76:aeb1df146756 673 (+) Check that the new number of WS is taken into account by reading
mbed_official 76:aeb1df146756 674 FLASH_ACR
mbed_official 76:aeb1df146756 675 (+) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
mbed_official 76:aeb1df146756 676 (+) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()"
mbed_official 76:aeb1df146756 677 function
mbed_official 76:aeb1df146756 678 (+) Check that the new CPU clock source is taken into account by reading
mbed_official 76:aeb1df146756 679 the clock source status, using "RCC_GetSYSCLKSource()" function
mbed_official 76:aeb1df146756 680 (+) Decreasing the CPU frequency (in the same voltage range)
mbed_official 76:aeb1df146756 681 (+) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
mbed_official 76:aeb1df146756 682 (+) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()"
mbed_official 76:aeb1df146756 683 function
mbed_official 76:aeb1df146756 684 (+) Check that the new CPU clock source is taken into account by reading
mbed_official 76:aeb1df146756 685 the clock source status, using "RCC_GetSYSCLKSource()" function
mbed_official 76:aeb1df146756 686 (+) Program the new number of WS, using "FLASH_SetLatency()" function
mbed_official 76:aeb1df146756 687 (+) Check that the new number of WS is taken into account by reading
mbed_official 76:aeb1df146756 688 FLASH_ACR
mbed_official 76:aeb1df146756 689 (+) Enable the Flash 32-bit access, using "FLASH_ReadAccess64Cmd(DISABLE)"
mbed_official 76:aeb1df146756 690 function
mbed_official 76:aeb1df146756 691 (+) Check that 32-bit access is taken into account by reading FLASH_ACR
mbed_official 76:aeb1df146756 692
mbed_official 76:aeb1df146756 693 @endverbatim
mbed_official 76:aeb1df146756 694 * @{
mbed_official 76:aeb1df146756 695 */
mbed_official 76:aeb1df146756 696
mbed_official 76:aeb1df146756 697 /**
mbed_official 76:aeb1df146756 698 * @brief Configures the system clock (SYSCLK).
mbed_official 76:aeb1df146756 699 * @note The MSI is used (enabled by hardware) as system clock source after
mbed_official 76:aeb1df146756 700 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
mbed_official 76:aeb1df146756 701 * of failure of the HSE used directly or indirectly as system clock
mbed_official 76:aeb1df146756 702 * (if the Clock Security System CSS is enabled).
mbed_official 76:aeb1df146756 703 * @note A switch from one clock source to another occurs only if the target
mbed_official 76:aeb1df146756 704 * clock source is ready (clock stable after startup delay or PLL locked).
mbed_official 76:aeb1df146756 705 * If a clock source which is not yet ready is selected, the switch will
mbed_official 76:aeb1df146756 706 * occur when the clock source will be ready.
mbed_official 76:aeb1df146756 707 * You can use RCC_GetSYSCLKSource() function to know which clock is
mbed_official 76:aeb1df146756 708 * currently used as system clock source.
mbed_official 76:aeb1df146756 709 * @param RCC_SYSCLKSource: specifies the clock source used as system clock source
mbed_official 76:aeb1df146756 710 * This parameter can be one of the following values:
mbed_official 76:aeb1df146756 711 * @arg RCC_SYSCLKSource_MSI: MSI selected as system clock source
mbed_official 76:aeb1df146756 712 * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
mbed_official 76:aeb1df146756 713 * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
mbed_official 76:aeb1df146756 714 * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
mbed_official 76:aeb1df146756 715 * @retval None
mbed_official 76:aeb1df146756 716 */
mbed_official 76:aeb1df146756 717 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
mbed_official 76:aeb1df146756 718 {
mbed_official 76:aeb1df146756 719 uint32_t tmpreg = 0;
mbed_official 76:aeb1df146756 720
mbed_official 76:aeb1df146756 721 /* Check the parameters */
mbed_official 76:aeb1df146756 722 assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
mbed_official 76:aeb1df146756 723
mbed_official 76:aeb1df146756 724 tmpreg = RCC->CFGR;
mbed_official 76:aeb1df146756 725
mbed_official 76:aeb1df146756 726 /* Clear SW[1:0] bits */
mbed_official 76:aeb1df146756 727 tmpreg &= ~RCC_CFGR_SW;
mbed_official 76:aeb1df146756 728
mbed_official 76:aeb1df146756 729 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
mbed_official 76:aeb1df146756 730 tmpreg |= RCC_SYSCLKSource;
mbed_official 76:aeb1df146756 731
mbed_official 76:aeb1df146756 732 /* Store the new value */
mbed_official 76:aeb1df146756 733 RCC->CFGR = tmpreg;
mbed_official 76:aeb1df146756 734 }
mbed_official 76:aeb1df146756 735
mbed_official 76:aeb1df146756 736 /**
mbed_official 76:aeb1df146756 737 * @brief Returns the clock source used as system clock.
mbed_official 76:aeb1df146756 738 * @param None
mbed_official 76:aeb1df146756 739 * @retval The clock source used as system clock. The returned value can be one
mbed_official 76:aeb1df146756 740 * of the following values:
mbed_official 76:aeb1df146756 741 * - 0x00: MSI used as system clock
mbed_official 76:aeb1df146756 742 * - 0x04: HSI used as system clock
mbed_official 76:aeb1df146756 743 * - 0x08: HSE used as system clock
mbed_official 76:aeb1df146756 744 * - 0x0C: PLL used as system clock
mbed_official 76:aeb1df146756 745 */
mbed_official 76:aeb1df146756 746 uint8_t RCC_GetSYSCLKSource(void)
mbed_official 76:aeb1df146756 747 {
mbed_official 76:aeb1df146756 748 return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
mbed_official 76:aeb1df146756 749 }
mbed_official 76:aeb1df146756 750
mbed_official 76:aeb1df146756 751 /**
mbed_official 76:aeb1df146756 752 * @brief Configures the AHB clock (HCLK).
mbed_official 76:aeb1df146756 753 * @note Depending on the device voltage range, the software has to set correctly
mbed_official 76:aeb1df146756 754 * these bits to ensure that the system frequency does not exceed the
mbed_official 76:aeb1df146756 755 * maximum allowed frequency (for more details refer to section above
mbed_official 76:aeb1df146756 756 * "CPU, AHB and APB busses clocks configuration functions")
mbed_official 76:aeb1df146756 757 * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
mbed_official 76:aeb1df146756 758 * the system clock (SYSCLK).
mbed_official 76:aeb1df146756 759 * This parameter can be one of the following values:
mbed_official 76:aeb1df146756 760 * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
mbed_official 76:aeb1df146756 761 * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
mbed_official 76:aeb1df146756 762 * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
mbed_official 76:aeb1df146756 763 * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
mbed_official 76:aeb1df146756 764 * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
mbed_official 76:aeb1df146756 765 * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
mbed_official 76:aeb1df146756 766 * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
mbed_official 76:aeb1df146756 767 * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
mbed_official 76:aeb1df146756 768 * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
mbed_official 76:aeb1df146756 769 * @retval None
mbed_official 76:aeb1df146756 770 */
mbed_official 76:aeb1df146756 771 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
mbed_official 76:aeb1df146756 772 {
mbed_official 76:aeb1df146756 773 uint32_t tmpreg = 0;
mbed_official 76:aeb1df146756 774
mbed_official 76:aeb1df146756 775 /* Check the parameters */
mbed_official 76:aeb1df146756 776 assert_param(IS_RCC_HCLK(RCC_SYSCLK));
mbed_official 76:aeb1df146756 777
mbed_official 76:aeb1df146756 778 tmpreg = RCC->CFGR;
mbed_official 76:aeb1df146756 779
mbed_official 76:aeb1df146756 780 /* Clear HPRE[3:0] bits */
mbed_official 76:aeb1df146756 781 tmpreg &= ~RCC_CFGR_HPRE;
mbed_official 76:aeb1df146756 782
mbed_official 76:aeb1df146756 783 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
mbed_official 76:aeb1df146756 784 tmpreg |= RCC_SYSCLK;
mbed_official 76:aeb1df146756 785
mbed_official 76:aeb1df146756 786 /* Store the new value */
mbed_official 76:aeb1df146756 787 RCC->CFGR = tmpreg;
mbed_official 76:aeb1df146756 788 }
mbed_official 76:aeb1df146756 789
mbed_official 76:aeb1df146756 790 /**
mbed_official 76:aeb1df146756 791 * @brief Configures the Low Speed APB clock (PCLK1).
mbed_official 76:aeb1df146756 792 * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
mbed_official 76:aeb1df146756 793 * the AHB clock (HCLK).
mbed_official 76:aeb1df146756 794 * This parameter can be one of the following values:
mbed_official 76:aeb1df146756 795 * @arg RCC_HCLK_Div1: APB1 clock = HCLK
mbed_official 76:aeb1df146756 796 * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
mbed_official 76:aeb1df146756 797 * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
mbed_official 76:aeb1df146756 798 * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
mbed_official 76:aeb1df146756 799 * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
mbed_official 76:aeb1df146756 800 * @retval None
mbed_official 76:aeb1df146756 801 */
mbed_official 76:aeb1df146756 802 void RCC_PCLK1Config(uint32_t RCC_HCLK)
mbed_official 76:aeb1df146756 803 {
mbed_official 76:aeb1df146756 804 uint32_t tmpreg = 0;
mbed_official 76:aeb1df146756 805
mbed_official 76:aeb1df146756 806 /* Check the parameters */
mbed_official 76:aeb1df146756 807 assert_param(IS_RCC_PCLK(RCC_HCLK));
mbed_official 76:aeb1df146756 808
mbed_official 76:aeb1df146756 809 tmpreg = RCC->CFGR;
mbed_official 76:aeb1df146756 810
mbed_official 76:aeb1df146756 811 /* Clear PPRE1[2:0] bits */
mbed_official 76:aeb1df146756 812 tmpreg &= ~RCC_CFGR_PPRE1;
mbed_official 76:aeb1df146756 813
mbed_official 76:aeb1df146756 814 /* Set PPRE1[2:0] bits according to RCC_HCLK value */
mbed_official 76:aeb1df146756 815 tmpreg |= RCC_HCLK;
mbed_official 76:aeb1df146756 816
mbed_official 76:aeb1df146756 817 /* Store the new value */
mbed_official 76:aeb1df146756 818 RCC->CFGR = tmpreg;
mbed_official 76:aeb1df146756 819 }
mbed_official 76:aeb1df146756 820
mbed_official 76:aeb1df146756 821 /**
mbed_official 76:aeb1df146756 822 * @brief Configures the High Speed APB clock (PCLK2).
mbed_official 76:aeb1df146756 823 * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
mbed_official 76:aeb1df146756 824 * the AHB clock (HCLK).
mbed_official 76:aeb1df146756 825 * This parameter can be one of the following values:
mbed_official 76:aeb1df146756 826 * @arg RCC_HCLK_Div1: APB2 clock = HCLK
mbed_official 76:aeb1df146756 827 * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
mbed_official 76:aeb1df146756 828 * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
mbed_official 76:aeb1df146756 829 * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
mbed_official 76:aeb1df146756 830 * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
mbed_official 76:aeb1df146756 831 * @retval None
mbed_official 76:aeb1df146756 832 */
mbed_official 76:aeb1df146756 833 void RCC_PCLK2Config(uint32_t RCC_HCLK)
mbed_official 76:aeb1df146756 834 {
mbed_official 76:aeb1df146756 835 uint32_t tmpreg = 0;
mbed_official 76:aeb1df146756 836
mbed_official 76:aeb1df146756 837 /* Check the parameters */
mbed_official 76:aeb1df146756 838 assert_param(IS_RCC_PCLK(RCC_HCLK));
mbed_official 76:aeb1df146756 839
mbed_official 76:aeb1df146756 840 tmpreg = RCC->CFGR;
mbed_official 76:aeb1df146756 841
mbed_official 76:aeb1df146756 842 /* Clear PPRE2[2:0] bits */
mbed_official 76:aeb1df146756 843 tmpreg &= ~RCC_CFGR_PPRE2;
mbed_official 76:aeb1df146756 844
mbed_official 76:aeb1df146756 845 /* Set PPRE2[2:0] bits according to RCC_HCLK value */
mbed_official 76:aeb1df146756 846 tmpreg |= RCC_HCLK << 3;
mbed_official 76:aeb1df146756 847
mbed_official 76:aeb1df146756 848 /* Store the new value */
mbed_official 76:aeb1df146756 849 RCC->CFGR = tmpreg;
mbed_official 76:aeb1df146756 850 }
mbed_official 76:aeb1df146756 851
mbed_official 76:aeb1df146756 852 /**
mbed_official 76:aeb1df146756 853 * @brief Returns the frequencies of the System, AHB and APB busses clocks.
mbed_official 76:aeb1df146756 854 * @note The frequency returned by this function is not the real frequency
mbed_official 76:aeb1df146756 855 * in the chip. It is calculated based on the predefined constant and
mbed_official 76:aeb1df146756 856 * the source selected by RCC_SYSCLKConfig():
mbed_official 76:aeb1df146756 857 *
mbed_official 76:aeb1df146756 858 * @note If SYSCLK source is MSI, function returns values based on MSI
mbed_official 76:aeb1df146756 859 * Value as defined by the MSI range, refer to RCC_MSIRangeConfig()
mbed_official 76:aeb1df146756 860 *
mbed_official 76:aeb1df146756 861 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
mbed_official 76:aeb1df146756 862 *
mbed_official 76:aeb1df146756 863 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
mbed_official 76:aeb1df146756 864 *
mbed_official 76:aeb1df146756 865 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
mbed_official 76:aeb1df146756 866 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 76:aeb1df146756 867 *
mbed_official 76:aeb1df146756 868 * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
mbed_official 76:aeb1df146756 869 * 16 MHz) but the real value may vary depending on the variations
mbed_official 76:aeb1df146756 870 * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().
mbed_official 76:aeb1df146756 871 *
mbed_official 76:aeb1df146756 872 * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
mbed_official 76:aeb1df146756 873 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 76:aeb1df146756 874 * frequency of the crystal used. Otherwise, this function may
mbed_official 76:aeb1df146756 875 * return wrong result.
mbed_official 76:aeb1df146756 876 *
mbed_official 76:aeb1df146756 877 * - The result of this function could be not correct when using fractional
mbed_official 76:aeb1df146756 878 * value for HSE crystal.
mbed_official 76:aeb1df146756 879 *
mbed_official 76:aeb1df146756 880 * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
mbed_official 76:aeb1df146756 881 * the clocks frequencies.
mbed_official 76:aeb1df146756 882 *
mbed_official 76:aeb1df146756 883 * @note This function can be used by the user application to compute the
mbed_official 76:aeb1df146756 884 * baudrate for the communication peripherals or configure other parameters.
mbed_official 76:aeb1df146756 885 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
mbed_official 76:aeb1df146756 886 * must be called to update the structure's field. Otherwise, any
mbed_official 76:aeb1df146756 887 * configuration based on this function will be incorrect.
mbed_official 76:aeb1df146756 888 *
mbed_official 76:aeb1df146756 889 * @retval None
mbed_official 76:aeb1df146756 890 */
mbed_official 76:aeb1df146756 891 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
mbed_official 76:aeb1df146756 892 {
mbed_official 76:aeb1df146756 893 uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, presc = 0, msirange = 0;
mbed_official 76:aeb1df146756 894
mbed_official 76:aeb1df146756 895 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 76:aeb1df146756 896 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 76:aeb1df146756 897
mbed_official 76:aeb1df146756 898 switch (tmp)
mbed_official 76:aeb1df146756 899 {
mbed_official 76:aeb1df146756 900 case 0x00: /* MSI used as system clock */
mbed_official 76:aeb1df146756 901 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;
mbed_official 76:aeb1df146756 902 RCC_Clocks->SYSCLK_Frequency = (32768 * (1 << (msirange + 1)));
mbed_official 76:aeb1df146756 903 break;
mbed_official 76:aeb1df146756 904 case 0x04: /* HSI used as system clock */
mbed_official 76:aeb1df146756 905 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
mbed_official 76:aeb1df146756 906 break;
mbed_official 76:aeb1df146756 907 case 0x08: /* HSE used as system clock */
mbed_official 76:aeb1df146756 908 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
mbed_official 76:aeb1df146756 909 break;
mbed_official 76:aeb1df146756 910 case 0x0C: /* PLL used as system clock */
mbed_official 76:aeb1df146756 911 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 76:aeb1df146756 912 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
mbed_official 76:aeb1df146756 913 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
mbed_official 76:aeb1df146756 914 pllmul = PLLMulTable[(pllmul >> 18)];
mbed_official 76:aeb1df146756 915 plldiv = (plldiv >> 22) + 1;
mbed_official 76:aeb1df146756 916
mbed_official 76:aeb1df146756 917 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 76:aeb1df146756 918
mbed_official 76:aeb1df146756 919 if (pllsource == 0x00)
mbed_official 76:aeb1df146756 920 {
mbed_official 76:aeb1df146756 921 /* HSI oscillator clock selected as PLL clock source */
mbed_official 76:aeb1df146756 922 RCC_Clocks->SYSCLK_Frequency = (((HSI_VALUE) * pllmul) / plldiv);
mbed_official 76:aeb1df146756 923 }
mbed_official 76:aeb1df146756 924 else
mbed_official 76:aeb1df146756 925 {
mbed_official 76:aeb1df146756 926 /* HSE selected as PLL clock source */
mbed_official 76:aeb1df146756 927 RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE) * pllmul) / plldiv);
mbed_official 76:aeb1df146756 928 }
mbed_official 76:aeb1df146756 929 break;
mbed_official 76:aeb1df146756 930 default: /* MSI used as system clock */
mbed_official 76:aeb1df146756 931 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;
mbed_official 76:aeb1df146756 932 RCC_Clocks->SYSCLK_Frequency = (32768 * (1 << (msirange + 1)));
mbed_official 76:aeb1df146756 933 break;
mbed_official 76:aeb1df146756 934 }
mbed_official 76:aeb1df146756 935 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
mbed_official 76:aeb1df146756 936 /* Get HCLK prescaler */
mbed_official 76:aeb1df146756 937 tmp = RCC->CFGR & RCC_CFGR_HPRE;
mbed_official 76:aeb1df146756 938 tmp = tmp >> 4;
mbed_official 76:aeb1df146756 939 presc = APBAHBPrescTable[tmp];
mbed_official 76:aeb1df146756 940 /* HCLK clock frequency */
mbed_official 76:aeb1df146756 941 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
mbed_official 76:aeb1df146756 942
mbed_official 76:aeb1df146756 943 /* Get PCLK1 prescaler */
mbed_official 76:aeb1df146756 944 tmp = RCC->CFGR & RCC_CFGR_PPRE1;
mbed_official 76:aeb1df146756 945 tmp = tmp >> 8;
mbed_official 76:aeb1df146756 946 presc = APBAHBPrescTable[tmp];
mbed_official 76:aeb1df146756 947 /* PCLK1 clock frequency */
mbed_official 76:aeb1df146756 948 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
mbed_official 76:aeb1df146756 949
mbed_official 76:aeb1df146756 950 /* Get PCLK2 prescaler */
mbed_official 76:aeb1df146756 951 tmp = RCC->CFGR & RCC_CFGR_PPRE2;
mbed_official 76:aeb1df146756 952 tmp = tmp >> 11;
mbed_official 76:aeb1df146756 953 presc = APBAHBPrescTable[tmp];
mbed_official 76:aeb1df146756 954 /* PCLK2 clock frequency */
mbed_official 76:aeb1df146756 955 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
mbed_official 76:aeb1df146756 956 }
mbed_official 76:aeb1df146756 957
mbed_official 76:aeb1df146756 958 /**
mbed_official 76:aeb1df146756 959 * @}
mbed_official 76:aeb1df146756 960 */
mbed_official 76:aeb1df146756 961
mbed_official 76:aeb1df146756 962 /** @defgroup RCC_Group3 Peripheral clocks configuration functions
mbed_official 76:aeb1df146756 963 * @brief Peripheral clocks configuration functions
mbed_official 76:aeb1df146756 964 *
mbed_official 76:aeb1df146756 965 @verbatim
mbed_official 76:aeb1df146756 966 ===============================================================================
mbed_official 76:aeb1df146756 967 ##### Peripheral clocks configuration functions #####
mbed_official 76:aeb1df146756 968 ===============================================================================
mbed_official 76:aeb1df146756 969 [..] This section provide functions allowing to configure the Peripheral clocks.
mbed_official 76:aeb1df146756 970 (#) The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
mbed_official 76:aeb1df146756 971 (HSE divided by a programmable prescaler).
mbed_official 76:aeb1df146756 972 (#) After restart from Reset or wakeup from STANDBY, all peripherals are
mbed_official 76:aeb1df146756 973 off except internal SRAM, Flash and JTAG. Before to start using a
mbed_official 76:aeb1df146756 974 peripheral you have to enable its interface clock. You can do this
mbed_official 76:aeb1df146756 975 using RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and
mbed_official 76:aeb1df146756 976 RCC_APB1PeriphClockCmd() functions.
mbed_official 76:aeb1df146756 977
mbed_official 76:aeb1df146756 978 (#) To reset the peripherals configuration (to the default state after
mbed_official 76:aeb1df146756 979 device reset) you can use RCC_AHBPeriphResetCmd(),
mbed_official 76:aeb1df146756 980 RCC_APB2PeriphResetCmd() and RCC_APB1PeriphResetCmd() functions.
mbed_official 76:aeb1df146756 981 (#) To further reduce power consumption in SLEEP mode the peripheral
mbed_official 76:aeb1df146756 982 clocks can be disabled prior to executing the WFI or WFE instructions.
mbed_official 76:aeb1df146756 983 You can do this using RCC_AHBPeriphClockLPModeCmd(),
mbed_official 76:aeb1df146756 984 RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd()
mbed_official 76:aeb1df146756 985 functions.
mbed_official 76:aeb1df146756 986
mbed_official 76:aeb1df146756 987 @endverbatim
mbed_official 76:aeb1df146756 988 * @{
mbed_official 76:aeb1df146756 989 */
mbed_official 76:aeb1df146756 990
mbed_official 76:aeb1df146756 991 /**
mbed_official 76:aeb1df146756 992 * @brief Configures the RTC and LCD clock (RTCCLK / LCDCLK).
mbed_official 76:aeb1df146756 993 * @note As the RTC clock configuration bits are in the RTC domain and write
mbed_official 76:aeb1df146756 994 * access is denied to this domain after reset, you have to enable write
mbed_official 76:aeb1df146756 995 * access using PWR_RTCAccessCmd(ENABLE) function before to configure
mbed_official 76:aeb1df146756 996 * the RTC clock source (to be done once after reset).
mbed_official 76:aeb1df146756 997 * @note Once the RTC clock is configured it can't be changed unless the RTC
mbed_official 76:aeb1df146756 998 * is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)
mbed_official 76:aeb1df146756 999 * @note The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).
mbed_official 76:aeb1df146756 1000 *
mbed_official 76:aeb1df146756 1001 * @param RCC_RTCCLKSource: specifies the RTC clock source.
mbed_official 76:aeb1df146756 1002 * This parameter can be one of the following values:
mbed_official 76:aeb1df146756 1003 * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
mbed_official 76:aeb1df146756 1004 * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
mbed_official 76:aeb1df146756 1005 * @arg RCC_RTCCLKSource_HSE_Div2: HSE divided by 2 selected as RTC clock
mbed_official 76:aeb1df146756 1006 * @arg RCC_RTCCLKSource_HSE_Div4: HSE divided by 4 selected as RTC clock
mbed_official 76:aeb1df146756 1007 * @arg RCC_RTCCLKSource_HSE_Div8: HSE divided by 8 selected as RTC clock
mbed_official 76:aeb1df146756 1008 * @arg RCC_RTCCLKSource_HSE_Div16: HSE divided by 16 selected as RTC clock
mbed_official 76:aeb1df146756 1009 *
mbed_official 76:aeb1df146756 1010 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
mbed_official 76:aeb1df146756 1011 * work in STOP and STANDBY modes, and can be used as wakeup source.
mbed_official 76:aeb1df146756 1012 * However, when the HSE clock is used as RTC clock source, the RTC
mbed_official 76:aeb1df146756 1013 * cannot be used in STOP and STANDBY modes.
mbed_official 76:aeb1df146756 1014 *
mbed_official 76:aeb1df146756 1015 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
mbed_official 76:aeb1df146756 1016 * RTC clock source).
mbed_official 76:aeb1df146756 1017 *
mbed_official 76:aeb1df146756 1018 * @retval None
mbed_official 76:aeb1df146756 1019 */
mbed_official 76:aeb1df146756 1020 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
mbed_official 76:aeb1df146756 1021 {
mbed_official 76:aeb1df146756 1022 uint32_t tmpreg = 0;
mbed_official 76:aeb1df146756 1023
mbed_official 76:aeb1df146756 1024 /* Check the parameters */
mbed_official 76:aeb1df146756 1025 assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
mbed_official 76:aeb1df146756 1026
mbed_official 76:aeb1df146756 1027 if ((RCC_RTCCLKSource & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE)
mbed_official 76:aeb1df146756 1028 {
mbed_official 76:aeb1df146756 1029 /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
mbed_official 76:aeb1df146756 1030 tmpreg = RCC->CR;
mbed_official 76:aeb1df146756 1031
mbed_official 76:aeb1df146756 1032 /* Clear RTCPRE[1:0] bits */
mbed_official 76:aeb1df146756 1033 tmpreg &= ~RCC_CR_RTCPRE;
mbed_official 76:aeb1df146756 1034
mbed_official 76:aeb1df146756 1035 /* Configure HSE division factor for RTC clock */
mbed_official 76:aeb1df146756 1036 tmpreg |= (RCC_RTCCLKSource & RCC_CR_RTCPRE);
mbed_official 76:aeb1df146756 1037
mbed_official 76:aeb1df146756 1038 /* Store the new value */
mbed_official 76:aeb1df146756 1039 RCC->CR = tmpreg;
mbed_official 76:aeb1df146756 1040 }
mbed_official 76:aeb1df146756 1041
mbed_official 76:aeb1df146756 1042 RCC->CSR &= ~RCC_CSR_RTCSEL;
mbed_official 76:aeb1df146756 1043
mbed_official 76:aeb1df146756 1044 /* Select the RTC clock source */
mbed_official 76:aeb1df146756 1045 RCC->CSR |= (RCC_RTCCLKSource & RCC_CSR_RTCSEL);
mbed_official 76:aeb1df146756 1046 }
mbed_official 76:aeb1df146756 1047
mbed_official 76:aeb1df146756 1048 /**
mbed_official 76:aeb1df146756 1049 * @brief Enables or disables the RTC clock.
mbed_official 76:aeb1df146756 1050 * @note This function must be used only after the RTC clock source was selected
mbed_official 76:aeb1df146756 1051 * using the RCC_RTCCLKConfig function.
mbed_official 76:aeb1df146756 1052 * @param NewState: new state of the RTC clock.
mbed_official 76:aeb1df146756 1053 * This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 1054 * @retval None
mbed_official 76:aeb1df146756 1055 */
mbed_official 76:aeb1df146756 1056 void RCC_RTCCLKCmd(FunctionalState NewState)
mbed_official 76:aeb1df146756 1057 {
mbed_official 76:aeb1df146756 1058 /* Check the parameters */
mbed_official 76:aeb1df146756 1059 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 1060
mbed_official 76:aeb1df146756 1061 *(__IO uint32_t *) CSR_RTCEN_BB = (uint32_t)NewState;
mbed_official 76:aeb1df146756 1062 }
mbed_official 76:aeb1df146756 1063
mbed_official 76:aeb1df146756 1064 /**
mbed_official 76:aeb1df146756 1065 * @brief Forces or releases the RTC peripheral and associated resources reset.
mbed_official 76:aeb1df146756 1066 * @note This function resets the RTC peripheral, RTC clock source selection
mbed_official 76:aeb1df146756 1067 * (in RCC_CSR) and the backup registers.
mbed_official 76:aeb1df146756 1068 * @param NewState: new state of the RTC reset.
mbed_official 76:aeb1df146756 1069 * This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 1070 * @retval None
mbed_official 76:aeb1df146756 1071 */
mbed_official 76:aeb1df146756 1072 void RCC_RTCResetCmd(FunctionalState NewState)
mbed_official 76:aeb1df146756 1073 {
mbed_official 76:aeb1df146756 1074 /* Check the parameters */
mbed_official 76:aeb1df146756 1075 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 1076
mbed_official 76:aeb1df146756 1077 *(__IO uint32_t *) CSR_RTCRST_BB = (uint32_t)NewState;
mbed_official 76:aeb1df146756 1078 }
mbed_official 76:aeb1df146756 1079
mbed_official 76:aeb1df146756 1080 /**
mbed_official 76:aeb1df146756 1081 * @brief Enables or disables the AHB peripheral clock.
mbed_official 76:aeb1df146756 1082 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 76:aeb1df146756 1083 * is disabled and the application software has to enable this clock before
mbed_official 76:aeb1df146756 1084 * using it.
mbed_official 76:aeb1df146756 1085 * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
mbed_official 76:aeb1df146756 1086 * This parameter can be any combination of the following values:
mbed_official 76:aeb1df146756 1087 * @arg RCC_AHBPeriph_GPIOA: GPIOA clock
mbed_official 76:aeb1df146756 1088 * @arg RCC_AHBPeriph_GPIOB: GPIOB clock
mbed_official 76:aeb1df146756 1089 * @arg RCC_AHBPeriph_GPIOC: GPIOC clock
mbed_official 76:aeb1df146756 1090 * @arg RCC_AHBPeriph_GPIOD: GPIOD clock
mbed_official 76:aeb1df146756 1091 * @arg RCC_AHBPeriph_GPIOE: GPIOE clock
mbed_official 76:aeb1df146756 1092 * @arg RCC_AHBPeriph_GPIOH: GPIOH clock
mbed_official 76:aeb1df146756 1093 * @arg RCC_AHBPeriph_GPIOF: GPIOF clock
mbed_official 76:aeb1df146756 1094 * @arg RCC_AHBPeriph_GPIOG: GPIOG clock
mbed_official 76:aeb1df146756 1095 * @arg RCC_AHBPeriph_CRC: CRC clock
mbed_official 76:aeb1df146756 1096 * @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
mbed_official 76:aeb1df146756 1097 * @arg RCC_AHBPeriph_DMA1: DMA1 clock
mbed_official 76:aeb1df146756 1098 * @arg RCC_AHBPeriph_DMA2: DMA2 clock
mbed_official 76:aeb1df146756 1099 * @arg RCC_AHBPeriph_AES: AES clock
mbed_official 76:aeb1df146756 1100 * @arg RCC_AHBPeriph_FSMC: FSMC clock
mbed_official 76:aeb1df146756 1101 * @param NewState: new state of the specified peripheral clock.
mbed_official 76:aeb1df146756 1102 * This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 1103 * @retval None
mbed_official 76:aeb1df146756 1104 */
mbed_official 76:aeb1df146756 1105 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
mbed_official 76:aeb1df146756 1106 {
mbed_official 76:aeb1df146756 1107 /* Check the parameters */
mbed_official 76:aeb1df146756 1108 assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
mbed_official 76:aeb1df146756 1109 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 1110
mbed_official 76:aeb1df146756 1111 if (NewState != DISABLE)
mbed_official 76:aeb1df146756 1112 {
mbed_official 76:aeb1df146756 1113 RCC->AHBENR |= RCC_AHBPeriph;
mbed_official 76:aeb1df146756 1114 }
mbed_official 76:aeb1df146756 1115 else
mbed_official 76:aeb1df146756 1116 {
mbed_official 76:aeb1df146756 1117 RCC->AHBENR &= ~RCC_AHBPeriph;
mbed_official 76:aeb1df146756 1118 }
mbed_official 76:aeb1df146756 1119 }
mbed_official 76:aeb1df146756 1120
mbed_official 76:aeb1df146756 1121 /**
mbed_official 76:aeb1df146756 1122 * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
mbed_official 76:aeb1df146756 1123 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 76:aeb1df146756 1124 * is disabled and the application software has to enable this clock before
mbed_official 76:aeb1df146756 1125 * using it.
mbed_official 76:aeb1df146756 1126 * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
mbed_official 76:aeb1df146756 1127 * This parameter can be any combination of the following values:
mbed_official 76:aeb1df146756 1128 * @arg RCC_APB2Periph_SYSCFG: SYSCFG APB2 Clock.
mbed_official 76:aeb1df146756 1129 * @arg RCC_APB2Periph_TIM9: TIM9 APB2 Clock.
mbed_official 76:aeb1df146756 1130 * @arg RCC_APB2Periph_TIM10: TIM10 APB2 Clock.
mbed_official 76:aeb1df146756 1131 * @arg RCC_APB2Periph_TIM11: TIM11 APB2 Clock.
mbed_official 76:aeb1df146756 1132 * @arg RCC_APB2Periph_ADC1: ADC1 APB2 Clock.
mbed_official 76:aeb1df146756 1133 * @arg RCC_APB2Periph_SDIO: SDIO APB2 Clock.
mbed_official 76:aeb1df146756 1134 * @arg RCC_APB2Periph_SPI1: SPI1 APB2 Clock.
mbed_official 76:aeb1df146756 1135 * @arg RCC_APB2Periph_USART1: USART1 APB2 Clock.
mbed_official 76:aeb1df146756 1136 * @param NewState: new state of the specified peripheral clock.
mbed_official 76:aeb1df146756 1137 * This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 1138 * @retval None
mbed_official 76:aeb1df146756 1139 */
mbed_official 76:aeb1df146756 1140 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
mbed_official 76:aeb1df146756 1141 {
mbed_official 76:aeb1df146756 1142 /* Check the parameters */
mbed_official 76:aeb1df146756 1143 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
mbed_official 76:aeb1df146756 1144 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 1145
mbed_official 76:aeb1df146756 1146 if (NewState != DISABLE)
mbed_official 76:aeb1df146756 1147 {
mbed_official 76:aeb1df146756 1148 RCC->APB2ENR |= RCC_APB2Periph;
mbed_official 76:aeb1df146756 1149 }
mbed_official 76:aeb1df146756 1150 else
mbed_official 76:aeb1df146756 1151 {
mbed_official 76:aeb1df146756 1152 RCC->APB2ENR &= ~RCC_APB2Periph;
mbed_official 76:aeb1df146756 1153 }
mbed_official 76:aeb1df146756 1154 }
mbed_official 76:aeb1df146756 1155
mbed_official 76:aeb1df146756 1156 /**
mbed_official 76:aeb1df146756 1157 * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
mbed_official 76:aeb1df146756 1158 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 76:aeb1df146756 1159 * is disabled and the application software has to enable this clock before
mbed_official 76:aeb1df146756 1160 * using it.
mbed_official 76:aeb1df146756 1161 * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
mbed_official 76:aeb1df146756 1162 * This parameter can be any combination of the following values:
mbed_official 76:aeb1df146756 1163 * @arg RCC_APB1Periph_TIM2: TIM2 clock
mbed_official 76:aeb1df146756 1164 * @arg RCC_APB1Periph_TIM3: TIM3 clock
mbed_official 76:aeb1df146756 1165 * @arg RCC_APB1Periph_TIM4: TIM4 clock
mbed_official 76:aeb1df146756 1166 * @arg RCC_APB1Periph_TIM5: TIM5 clock
mbed_official 76:aeb1df146756 1167 * @arg RCC_APB1Periph_TIM6: TIM6 clock
mbed_official 76:aeb1df146756 1168 * @arg RCC_APB1Periph_TIM7: TIM7 clock
mbed_official 76:aeb1df146756 1169 * @arg RCC_APB1Periph_LCD: LCD clock
mbed_official 76:aeb1df146756 1170 * @arg RCC_APB1Periph_WWDG: WWDG clock
mbed_official 76:aeb1df146756 1171 * @arg RCC_APB1Periph_SPI2: SPI2 clock
mbed_official 76:aeb1df146756 1172 * @arg RCC_APB1Periph_SPI3: SPI3 clock
mbed_official 76:aeb1df146756 1173 * @arg RCC_APB1Periph_USART2: USART2 clock
mbed_official 76:aeb1df146756 1174 * @arg RCC_APB1Periph_USART3: USART3 clock
mbed_official 76:aeb1df146756 1175 * @arg RCC_APB1Periph_UART4: UART4 clock
mbed_official 76:aeb1df146756 1176 * @arg RCC_APB1Periph_UART5: UART5 clock
mbed_official 76:aeb1df146756 1177 * @arg RCC_APB1Periph_I2C1: I2C1 clock
mbed_official 76:aeb1df146756 1178 * @arg RCC_APB1Periph_I2C2: I2C2 clock
mbed_official 76:aeb1df146756 1179 * @arg RCC_APB1Periph_USB: USB clock
mbed_official 76:aeb1df146756 1180 * @arg RCC_APB1Periph_PWR: PWR clock
mbed_official 76:aeb1df146756 1181 * @arg RCC_APB1Periph_DAC: DAC clock
mbed_official 76:aeb1df146756 1182 * @arg RCC_APB1Periph_COMP COMP clock
mbed_official 76:aeb1df146756 1183 * @param NewState: new state of the specified peripheral clock.
mbed_official 76:aeb1df146756 1184 * This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 1185 * @retval None
mbed_official 76:aeb1df146756 1186 */
mbed_official 76:aeb1df146756 1187 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
mbed_official 76:aeb1df146756 1188 {
mbed_official 76:aeb1df146756 1189 /* Check the parameters */
mbed_official 76:aeb1df146756 1190 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
mbed_official 76:aeb1df146756 1191 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 1192
mbed_official 76:aeb1df146756 1193 if (NewState != DISABLE)
mbed_official 76:aeb1df146756 1194 {
mbed_official 76:aeb1df146756 1195 RCC->APB1ENR |= RCC_APB1Periph;
mbed_official 76:aeb1df146756 1196 }
mbed_official 76:aeb1df146756 1197 else
mbed_official 76:aeb1df146756 1198 {
mbed_official 76:aeb1df146756 1199 RCC->APB1ENR &= ~RCC_APB1Periph;
mbed_official 76:aeb1df146756 1200 }
mbed_official 76:aeb1df146756 1201 }
mbed_official 76:aeb1df146756 1202
mbed_official 76:aeb1df146756 1203 /**
mbed_official 76:aeb1df146756 1204 * @brief Forces or releases AHB peripheral reset.
mbed_official 76:aeb1df146756 1205 * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
mbed_official 76:aeb1df146756 1206 * This parameter can be any combination of the following values:
mbed_official 76:aeb1df146756 1207 * @arg RCC_AHBPeriph_GPIOA: GPIOA clock
mbed_official 76:aeb1df146756 1208 * @arg RCC_AHBPeriph_GPIOB: GPIOB clock
mbed_official 76:aeb1df146756 1209 * @arg RCC_AHBPeriph_GPIOC: GPIOC clock
mbed_official 76:aeb1df146756 1210 * @arg RCC_AHBPeriph_GPIOD: GPIOD clock
mbed_official 76:aeb1df146756 1211 * @arg RCC_AHBPeriph_GPIOE: GPIOE clock
mbed_official 76:aeb1df146756 1212 * @arg RCC_AHBPeriph_GPIOH: GPIOH clock
mbed_official 76:aeb1df146756 1213 * @arg RCC_AHBPeriph_GPIOF: GPIOF clock
mbed_official 76:aeb1df146756 1214 * @arg RCC_AHBPeriph_GPIOG: GPIOG clock
mbed_official 76:aeb1df146756 1215 * @arg RCC_AHBPeriph_CRC: CRC clock
mbed_official 76:aeb1df146756 1216 * @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
mbed_official 76:aeb1df146756 1217 * @arg RCC_AHBPeriph_DMA1: DMA1 clock
mbed_official 76:aeb1df146756 1218 * @arg RCC_AHBPeriph_DMA2: DMA2 clock
mbed_official 76:aeb1df146756 1219 * @arg RCC_AHBPeriph_AES: AES clock
mbed_official 76:aeb1df146756 1220 * @arg RCC_AHBPeriph_FSMC: FSMC clock
mbed_official 76:aeb1df146756 1221 * @param NewState: new state of the specified peripheral reset.
mbed_official 76:aeb1df146756 1222 * This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 1223 * @retval None
mbed_official 76:aeb1df146756 1224 */
mbed_official 76:aeb1df146756 1225 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
mbed_official 76:aeb1df146756 1226 {
mbed_official 76:aeb1df146756 1227 /* Check the parameters */
mbed_official 76:aeb1df146756 1228 assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
mbed_official 76:aeb1df146756 1229 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 1230
mbed_official 76:aeb1df146756 1231 if (NewState != DISABLE)
mbed_official 76:aeb1df146756 1232 {
mbed_official 76:aeb1df146756 1233 RCC->AHBRSTR |= RCC_AHBPeriph;
mbed_official 76:aeb1df146756 1234 }
mbed_official 76:aeb1df146756 1235 else
mbed_official 76:aeb1df146756 1236 {
mbed_official 76:aeb1df146756 1237 RCC->AHBRSTR &= ~RCC_AHBPeriph;
mbed_official 76:aeb1df146756 1238 }
mbed_official 76:aeb1df146756 1239 }
mbed_official 76:aeb1df146756 1240
mbed_official 76:aeb1df146756 1241 /**
mbed_official 76:aeb1df146756 1242 * @brief Forces or releases High Speed APB (APB2) peripheral reset.
mbed_official 76:aeb1df146756 1243 * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
mbed_official 76:aeb1df146756 1244 * This parameter can be any combination of the following values:
mbed_official 76:aeb1df146756 1245 * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
mbed_official 76:aeb1df146756 1246 * @arg RCC_APB2Periph_TIM9: TIM9 clock
mbed_official 76:aeb1df146756 1247 * @arg RCC_APB2Periph_TIM10: TIM10 clock
mbed_official 76:aeb1df146756 1248 * @arg RCC_APB2Periph_TIM11: TIM11 clock
mbed_official 76:aeb1df146756 1249 * @arg RCC_APB2Periph_ADC1: ADC1 clock
mbed_official 76:aeb1df146756 1250 * @arg RCC_APB2Periph_SDIO: SDIO clock
mbed_official 76:aeb1df146756 1251 * @arg RCC_APB2Periph_SPI1: SPI1 clock
mbed_official 76:aeb1df146756 1252 * @arg RCC_APB2Periph_USART1: USART1 clock
mbed_official 76:aeb1df146756 1253 * @param NewState: new state of the specified peripheral reset.
mbed_official 76:aeb1df146756 1254 * This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 1255 * @retval None
mbed_official 76:aeb1df146756 1256 */
mbed_official 76:aeb1df146756 1257 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
mbed_official 76:aeb1df146756 1258 {
mbed_official 76:aeb1df146756 1259 /* Check the parameters */
mbed_official 76:aeb1df146756 1260 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
mbed_official 76:aeb1df146756 1261 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 1262
mbed_official 76:aeb1df146756 1263 if (NewState != DISABLE)
mbed_official 76:aeb1df146756 1264 {
mbed_official 76:aeb1df146756 1265 RCC->APB2RSTR |= RCC_APB2Periph;
mbed_official 76:aeb1df146756 1266 }
mbed_official 76:aeb1df146756 1267 else
mbed_official 76:aeb1df146756 1268 {
mbed_official 76:aeb1df146756 1269 RCC->APB2RSTR &= ~RCC_APB2Periph;
mbed_official 76:aeb1df146756 1270 }
mbed_official 76:aeb1df146756 1271 }
mbed_official 76:aeb1df146756 1272
mbed_official 76:aeb1df146756 1273 /**
mbed_official 76:aeb1df146756 1274 * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
mbed_official 76:aeb1df146756 1275 * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
mbed_official 76:aeb1df146756 1276 * This parameter can be any combination of the following values:
mbed_official 76:aeb1df146756 1277 * @arg RCC_APB1Periph_TIM2: TIM2 clock
mbed_official 76:aeb1df146756 1278 * @arg RCC_APB1Periph_TIM3: TIM3 clock
mbed_official 76:aeb1df146756 1279 * @arg RCC_APB1Periph_TIM4: TIM4 clock
mbed_official 76:aeb1df146756 1280 * @arg RCC_APB1Periph_TIM5: TIM5 clock
mbed_official 76:aeb1df146756 1281 * @arg RCC_APB1Periph_TIM6: TIM6 clock
mbed_official 76:aeb1df146756 1282 * @arg RCC_APB1Periph_TIM7: TIM7 clock
mbed_official 76:aeb1df146756 1283 * @arg RCC_APB1Periph_LCD: LCD clock
mbed_official 76:aeb1df146756 1284 * @arg RCC_APB1Periph_WWDG: WWDG clock
mbed_official 76:aeb1df146756 1285 * @arg RCC_APB1Periph_SPI2: SPI2 clock
mbed_official 76:aeb1df146756 1286 * @arg RCC_APB1Periph_SPI3: SPI3 clock
mbed_official 76:aeb1df146756 1287 * @arg RCC_APB1Periph_USART2: USART2 clock
mbed_official 76:aeb1df146756 1288 * @arg RCC_APB1Periph_USART3: USART3 clock
mbed_official 76:aeb1df146756 1289 * @arg RCC_APB1Periph_UART4: UART4 clock
mbed_official 76:aeb1df146756 1290 * @arg RCC_APB1Periph_UART5: UART5 clock
mbed_official 76:aeb1df146756 1291 * @arg RCC_APB1Periph_I2C1: I2C1 clock
mbed_official 76:aeb1df146756 1292 * @arg RCC_APB1Periph_I2C2: I2C2 clock
mbed_official 76:aeb1df146756 1293 * @arg RCC_APB1Periph_USB: USB clock
mbed_official 76:aeb1df146756 1294 * @arg RCC_APB1Periph_PWR: PWR clock
mbed_official 76:aeb1df146756 1295 * @arg RCC_APB1Periph_DAC: DAC clock
mbed_official 76:aeb1df146756 1296 * @arg RCC_APB1Periph_COMP
mbed_official 76:aeb1df146756 1297 * @param NewState: new state of the specified peripheral clock.
mbed_official 76:aeb1df146756 1298 * This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 1299 * @retval None
mbed_official 76:aeb1df146756 1300 */
mbed_official 76:aeb1df146756 1301 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
mbed_official 76:aeb1df146756 1302 {
mbed_official 76:aeb1df146756 1303 /* Check the parameters */
mbed_official 76:aeb1df146756 1304 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
mbed_official 76:aeb1df146756 1305 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 1306
mbed_official 76:aeb1df146756 1307 if (NewState != DISABLE)
mbed_official 76:aeb1df146756 1308 {
mbed_official 76:aeb1df146756 1309 RCC->APB1RSTR |= RCC_APB1Periph;
mbed_official 76:aeb1df146756 1310 }
mbed_official 76:aeb1df146756 1311 else
mbed_official 76:aeb1df146756 1312 {
mbed_official 76:aeb1df146756 1313 RCC->APB1RSTR &= ~RCC_APB1Periph;
mbed_official 76:aeb1df146756 1314 }
mbed_official 76:aeb1df146756 1315 }
mbed_official 76:aeb1df146756 1316
mbed_official 76:aeb1df146756 1317 /**
mbed_official 76:aeb1df146756 1318 * @brief Enables or disables the AHB peripheral clock during SLEEP mode.
mbed_official 76:aeb1df146756 1319 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 76:aeb1df146756 1320 * power consumption.
mbed_official 76:aeb1df146756 1321 * - After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 76:aeb1df146756 1322 * - By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 76:aeb1df146756 1323 * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
mbed_official 76:aeb1df146756 1324 * This parameter can be any combination of the following values:
mbed_official 76:aeb1df146756 1325 * @arg RCC_AHBPeriph_GPIOA: GPIOA clock
mbed_official 76:aeb1df146756 1326 * @arg RCC_AHBPeriph_GPIOB: GPIOB clock
mbed_official 76:aeb1df146756 1327 * @arg RCC_AHBPeriph_GPIOC: GPIOC clock
mbed_official 76:aeb1df146756 1328 * @arg RCC_AHBPeriph_GPIOD: GPIOD clock
mbed_official 76:aeb1df146756 1329 * @arg RCC_AHBPeriph_GPIOE: GPIOE clock
mbed_official 76:aeb1df146756 1330 * @arg RCC_AHBPeriph_GPIOH: GPIOH clock
mbed_official 76:aeb1df146756 1331 * @arg RCC_AHBPeriph_GPIOF: GPIOF clock
mbed_official 76:aeb1df146756 1332 * @arg RCC_AHBPeriph_GPIOG: GPIOG clock
mbed_official 76:aeb1df146756 1333 * @arg RCC_AHBPeriph_CRC: CRC clock
mbed_official 76:aeb1df146756 1334 * @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
mbed_official 76:aeb1df146756 1335 * @arg RCC_AHBPeriph_SRAM: SRAM clock
mbed_official 76:aeb1df146756 1336 * @arg RCC_AHBPeriph_DMA1: DMA1 clock
mbed_official 76:aeb1df146756 1337 * @arg RCC_AHBPeriph_DMA2: DMA2 clock
mbed_official 76:aeb1df146756 1338 * @arg RCC_AHBPeriph_AES: AES clock
mbed_official 76:aeb1df146756 1339 * @arg RCC_AHBPeriph_FSMC: FSMC clock
mbed_official 76:aeb1df146756 1340 * @param NewState: new state of the specified peripheral clock.
mbed_official 76:aeb1df146756 1341 * This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 1342 * @retval None
mbed_official 76:aeb1df146756 1343 */
mbed_official 76:aeb1df146756 1344 void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
mbed_official 76:aeb1df146756 1345 {
mbed_official 76:aeb1df146756 1346 /* Check the parameters */
mbed_official 76:aeb1df146756 1347 assert_param(IS_RCC_AHB_LPMODE_PERIPH(RCC_AHBPeriph));
mbed_official 76:aeb1df146756 1348 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 1349
mbed_official 76:aeb1df146756 1350 if (NewState != DISABLE)
mbed_official 76:aeb1df146756 1351 {
mbed_official 76:aeb1df146756 1352 RCC->AHBLPENR |= RCC_AHBPeriph;
mbed_official 76:aeb1df146756 1353 }
mbed_official 76:aeb1df146756 1354 else
mbed_official 76:aeb1df146756 1355 {
mbed_official 76:aeb1df146756 1356 RCC->AHBLPENR &= ~RCC_AHBPeriph;
mbed_official 76:aeb1df146756 1357 }
mbed_official 76:aeb1df146756 1358 }
mbed_official 76:aeb1df146756 1359
mbed_official 76:aeb1df146756 1360 /**
mbed_official 76:aeb1df146756 1361 * @brief Enables or disables the APB2 peripheral clock during SLEEP mode.
mbed_official 76:aeb1df146756 1362 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 76:aeb1df146756 1363 * power consumption.
mbed_official 76:aeb1df146756 1364 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 76:aeb1df146756 1365 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 76:aeb1df146756 1366 * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
mbed_official 76:aeb1df146756 1367 * This parameter can be any combination of the following values:
mbed_official 76:aeb1df146756 1368 * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
mbed_official 76:aeb1df146756 1369 * @arg RCC_APB2Periph_TIM9: TIM9 clock
mbed_official 76:aeb1df146756 1370 * @arg RCC_APB2Periph_TIM10: TIM10 clock
mbed_official 76:aeb1df146756 1371 * @arg RCC_APB2Periph_TIM11: TIM11 clock
mbed_official 76:aeb1df146756 1372 * @arg RCC_APB2Periph_ADC1: ADC1 clock
mbed_official 76:aeb1df146756 1373 * @arg RCC_APB2Periph_SDIO: SDIO clock
mbed_official 76:aeb1df146756 1374 * @arg RCC_APB2Periph_SPI1: SPI1 clock
mbed_official 76:aeb1df146756 1375 * @arg RCC_APB2Periph_USART1: USART1 clock
mbed_official 76:aeb1df146756 1376 * @param NewState: new state of the specified peripheral clock.
mbed_official 76:aeb1df146756 1377 * This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 1378 * @retval None
mbed_official 76:aeb1df146756 1379 */
mbed_official 76:aeb1df146756 1380 void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
mbed_official 76:aeb1df146756 1381 {
mbed_official 76:aeb1df146756 1382 /* Check the parameters */
mbed_official 76:aeb1df146756 1383 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
mbed_official 76:aeb1df146756 1384 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 1385
mbed_official 76:aeb1df146756 1386 if (NewState != DISABLE)
mbed_official 76:aeb1df146756 1387 {
mbed_official 76:aeb1df146756 1388 RCC->APB2LPENR |= RCC_APB2Periph;
mbed_official 76:aeb1df146756 1389 }
mbed_official 76:aeb1df146756 1390 else
mbed_official 76:aeb1df146756 1391 {
mbed_official 76:aeb1df146756 1392 RCC->APB2LPENR &= ~RCC_APB2Periph;
mbed_official 76:aeb1df146756 1393 }
mbed_official 76:aeb1df146756 1394 }
mbed_official 76:aeb1df146756 1395
mbed_official 76:aeb1df146756 1396 /**
mbed_official 76:aeb1df146756 1397 * @brief Enables or disables the APB1 peripheral clock during SLEEP mode.
mbed_official 76:aeb1df146756 1398 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 76:aeb1df146756 1399 * power consumption.
mbed_official 76:aeb1df146756 1400 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 76:aeb1df146756 1401 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 76:aeb1df146756 1402 * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
mbed_official 76:aeb1df146756 1403 * This parameter can be any combination of the following values:
mbed_official 76:aeb1df146756 1404 * @arg RCC_APB1Periph_TIM2: TIM2 clock
mbed_official 76:aeb1df146756 1405 * @arg RCC_APB1Periph_TIM3: TIM3 clock
mbed_official 76:aeb1df146756 1406 * @arg RCC_APB1Periph_TIM4: TIM4 clock
mbed_official 76:aeb1df146756 1407 * @arg RCC_APB1Periph_TIM5: TIM5 clock
mbed_official 76:aeb1df146756 1408 * @arg RCC_APB1Periph_TIM6: TIM6 clock
mbed_official 76:aeb1df146756 1409 * @arg RCC_APB1Periph_TIM7: TIM7 clock
mbed_official 76:aeb1df146756 1410 * @arg RCC_APB1Periph_LCD: LCD clock
mbed_official 76:aeb1df146756 1411 * @arg RCC_APB1Periph_WWDG: WWDG clock
mbed_official 76:aeb1df146756 1412 * @arg RCC_APB1Periph_SPI2: SPI2 clock
mbed_official 76:aeb1df146756 1413 * @arg RCC_APB1Periph_SPI3: SPI3 clock
mbed_official 76:aeb1df146756 1414 * @arg RCC_APB1Periph_USART2: USART2 clock
mbed_official 76:aeb1df146756 1415 * @arg RCC_APB1Periph_USART3: USART3 clock
mbed_official 76:aeb1df146756 1416 * @arg RCC_APB1Periph_UART4: UART4 clock
mbed_official 76:aeb1df146756 1417 * @arg RCC_APB1Periph_UART5: UART5 clock
mbed_official 76:aeb1df146756 1418 * @arg RCC_APB1Periph_I2C1: I2C1 clock
mbed_official 76:aeb1df146756 1419 * @arg RCC_APB1Periph_I2C2: I2C2 clock
mbed_official 76:aeb1df146756 1420 * @arg RCC_APB1Periph_USB: USB clock
mbed_official 76:aeb1df146756 1421 * @arg RCC_APB1Periph_PWR: PWR clock
mbed_official 76:aeb1df146756 1422 * @arg RCC_APB1Periph_DAC: DAC clock
mbed_official 76:aeb1df146756 1423 * @arg RCC_APB1Periph_COMP: COMP clock
mbed_official 76:aeb1df146756 1424 * @param NewState: new state
mbed_official 76:aeb1df146756 1425 * @param NewState: new state of the specified peripheral clock.
mbed_official 76:aeb1df146756 1426 * This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 1427 * @retval None
mbed_official 76:aeb1df146756 1428 */
mbed_official 76:aeb1df146756 1429 void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
mbed_official 76:aeb1df146756 1430 {
mbed_official 76:aeb1df146756 1431 /* Check the parameters */
mbed_official 76:aeb1df146756 1432 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
mbed_official 76:aeb1df146756 1433 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 1434
mbed_official 76:aeb1df146756 1435 if (NewState != DISABLE)
mbed_official 76:aeb1df146756 1436 {
mbed_official 76:aeb1df146756 1437 RCC->APB1LPENR |= RCC_APB1Periph;
mbed_official 76:aeb1df146756 1438 }
mbed_official 76:aeb1df146756 1439 else
mbed_official 76:aeb1df146756 1440 {
mbed_official 76:aeb1df146756 1441 RCC->APB1LPENR &= ~RCC_APB1Periph;
mbed_official 76:aeb1df146756 1442 }
mbed_official 76:aeb1df146756 1443 }
mbed_official 76:aeb1df146756 1444
mbed_official 76:aeb1df146756 1445 /**
mbed_official 76:aeb1df146756 1446 * @}
mbed_official 76:aeb1df146756 1447 */
mbed_official 76:aeb1df146756 1448
mbed_official 76:aeb1df146756 1449 /** @defgroup RCC_Group4 Interrupts and flags management functions
mbed_official 76:aeb1df146756 1450 * @brief Interrupts and flags management functions
mbed_official 76:aeb1df146756 1451 *
mbed_official 76:aeb1df146756 1452 @verbatim
mbed_official 76:aeb1df146756 1453 ===============================================================================
mbed_official 76:aeb1df146756 1454 ##### Interrupts and flags management functions #####
mbed_official 76:aeb1df146756 1455 ===============================================================================
mbed_official 76:aeb1df146756 1456
mbed_official 76:aeb1df146756 1457 @endverbatim
mbed_official 76:aeb1df146756 1458 * @{
mbed_official 76:aeb1df146756 1459 */
mbed_official 76:aeb1df146756 1460
mbed_official 76:aeb1df146756 1461 /**
mbed_official 76:aeb1df146756 1462 * @brief Enables or disables the specified RCC interrupts.
mbed_official 76:aeb1df146756 1463 * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
mbed_official 76:aeb1df146756 1464 * and if the HSE clock fails, the CSS interrupt occurs and an NMI is
mbed_official 76:aeb1df146756 1465 * automatically generated. The NMI will be executed indefinitely, and
mbed_official 76:aeb1df146756 1466 * since NMI has higher priority than any other IRQ (and main program)
mbed_official 76:aeb1df146756 1467 * the application will be stacked in the NMI ISR unless the CSS interrupt
mbed_official 76:aeb1df146756 1468 * pending bit is cleared.
mbed_official 76:aeb1df146756 1469 * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
mbed_official 76:aeb1df146756 1470 * This parameter can be any combination of the following values:
mbed_official 76:aeb1df146756 1471 * @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official 76:aeb1df146756 1472 * @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official 76:aeb1df146756 1473 * @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official 76:aeb1df146756 1474 * @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official 76:aeb1df146756 1475 * @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official 76:aeb1df146756 1476 * @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official 76:aeb1df146756 1477 * @arg RCC_IT_LSECSS: LSE CSS interrupt
mbed_official 76:aeb1df146756 1478 * @param NewState: new state of the specified RCC interrupts.
mbed_official 76:aeb1df146756 1479 * This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 1480 * @retval None
mbed_official 76:aeb1df146756 1481 */
mbed_official 76:aeb1df146756 1482 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
mbed_official 76:aeb1df146756 1483 {
mbed_official 76:aeb1df146756 1484 /* Check the parameters */
mbed_official 76:aeb1df146756 1485 assert_param(IS_RCC_IT(RCC_IT));
mbed_official 76:aeb1df146756 1486 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 1487
mbed_official 76:aeb1df146756 1488 if (NewState != DISABLE)
mbed_official 76:aeb1df146756 1489 {
mbed_official 76:aeb1df146756 1490 /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
mbed_official 76:aeb1df146756 1491 *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
mbed_official 76:aeb1df146756 1492 }
mbed_official 76:aeb1df146756 1493 else
mbed_official 76:aeb1df146756 1494 {
mbed_official 76:aeb1df146756 1495 /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
mbed_official 76:aeb1df146756 1496 *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
mbed_official 76:aeb1df146756 1497 }
mbed_official 76:aeb1df146756 1498 }
mbed_official 76:aeb1df146756 1499
mbed_official 76:aeb1df146756 1500 /**
mbed_official 76:aeb1df146756 1501 * @brief Checks whether the specified RCC flag is set or not.
mbed_official 76:aeb1df146756 1502 * @param RCC_FLAG: specifies the flag to check.
mbed_official 76:aeb1df146756 1503 * This parameter can be one of the following values:
mbed_official 76:aeb1df146756 1504 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
mbed_official 76:aeb1df146756 1505 * @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
mbed_official 76:aeb1df146756 1506 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
mbed_official 76:aeb1df146756 1507 * @arg RCC_FLAG_PLLRDY: PLL clock ready
mbed_official 76:aeb1df146756 1508 * @arg RCC_FLAG_LSECSS: LSE oscillator clock CSS detected
mbed_official 76:aeb1df146756 1509 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
mbed_official 76:aeb1df146756 1510 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
mbed_official 76:aeb1df146756 1511 * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
mbed_official 76:aeb1df146756 1512 * @arg RCC_FLAG_PINRST: Pin reset
mbed_official 76:aeb1df146756 1513 * @arg RCC_FLAG_PORRST: POR/PDR reset
mbed_official 76:aeb1df146756 1514 * @arg RCC_FLAG_SFTRST: Software reset
mbed_official 76:aeb1df146756 1515 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
mbed_official 76:aeb1df146756 1516 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
mbed_official 76:aeb1df146756 1517 * @arg RCC_FLAG_LPWRRST: Low Power reset
mbed_official 76:aeb1df146756 1518 * @retval The new state of RCC_FLAG (SET or RESET).
mbed_official 76:aeb1df146756 1519 */
mbed_official 76:aeb1df146756 1520 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
mbed_official 76:aeb1df146756 1521 {
mbed_official 76:aeb1df146756 1522 uint32_t tmp = 0;
mbed_official 76:aeb1df146756 1523 uint32_t statusreg = 0;
mbed_official 76:aeb1df146756 1524 FlagStatus bitstatus = RESET;
mbed_official 76:aeb1df146756 1525
mbed_official 76:aeb1df146756 1526 /* Check the parameters */
mbed_official 76:aeb1df146756 1527 assert_param(IS_RCC_FLAG(RCC_FLAG));
mbed_official 76:aeb1df146756 1528
mbed_official 76:aeb1df146756 1529 /* Get the RCC register index */
mbed_official 76:aeb1df146756 1530 tmp = RCC_FLAG >> 5;
mbed_official 76:aeb1df146756 1531
mbed_official 76:aeb1df146756 1532 if (tmp == 1) /* The flag to check is in CR register */
mbed_official 76:aeb1df146756 1533 {
mbed_official 76:aeb1df146756 1534 statusreg = RCC->CR;
mbed_official 76:aeb1df146756 1535 }
mbed_official 76:aeb1df146756 1536 else /* The flag to check is in CSR register (tmp == 2) */
mbed_official 76:aeb1df146756 1537 {
mbed_official 76:aeb1df146756 1538 statusreg = RCC->CSR;
mbed_official 76:aeb1df146756 1539 }
mbed_official 76:aeb1df146756 1540
mbed_official 76:aeb1df146756 1541 /* Get the flag position */
mbed_official 76:aeb1df146756 1542 tmp = RCC_FLAG & FLAG_MASK;
mbed_official 76:aeb1df146756 1543
mbed_official 76:aeb1df146756 1544 if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
mbed_official 76:aeb1df146756 1545 {
mbed_official 76:aeb1df146756 1546 bitstatus = SET;
mbed_official 76:aeb1df146756 1547 }
mbed_official 76:aeb1df146756 1548 else
mbed_official 76:aeb1df146756 1549 {
mbed_official 76:aeb1df146756 1550 bitstatus = RESET;
mbed_official 76:aeb1df146756 1551 }
mbed_official 76:aeb1df146756 1552 /* Return the flag status */
mbed_official 76:aeb1df146756 1553 return bitstatus;
mbed_official 76:aeb1df146756 1554 }
mbed_official 76:aeb1df146756 1555
mbed_official 76:aeb1df146756 1556 /**
mbed_official 76:aeb1df146756 1557 * @brief Clears the RCC reset flags.
mbed_official 76:aeb1df146756 1558 * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
mbed_official 76:aeb1df146756 1559 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
mbed_official 76:aeb1df146756 1560 * @param None
mbed_official 76:aeb1df146756 1561 * @retval None
mbed_official 76:aeb1df146756 1562 */
mbed_official 76:aeb1df146756 1563 void RCC_ClearFlag(void)
mbed_official 76:aeb1df146756 1564 {
mbed_official 76:aeb1df146756 1565 /* Set RMVF bit to clear the reset flags */
mbed_official 76:aeb1df146756 1566 RCC->CSR |= RCC_CSR_RMVF;
mbed_official 76:aeb1df146756 1567 }
mbed_official 76:aeb1df146756 1568
mbed_official 76:aeb1df146756 1569 /**
mbed_official 76:aeb1df146756 1570 * @brief Checks whether the specified RCC interrupt has occurred or not.
mbed_official 76:aeb1df146756 1571 * @param RCC_IT: specifies the RCC interrupt source to check.
mbed_official 76:aeb1df146756 1572 * This parameter can be one of the following values:
mbed_official 76:aeb1df146756 1573 * @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official 76:aeb1df146756 1574 * @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official 76:aeb1df146756 1575 * @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official 76:aeb1df146756 1576 * @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official 76:aeb1df146756 1577 * @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official 76:aeb1df146756 1578 * @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official 76:aeb1df146756 1579 * @arg RCC_IT_LSECSS: LSE CSS interrupt
mbed_official 76:aeb1df146756 1580 * @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official 76:aeb1df146756 1581 * @retval The new state of RCC_IT (SET or RESET).
mbed_official 76:aeb1df146756 1582 */
mbed_official 76:aeb1df146756 1583 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
mbed_official 76:aeb1df146756 1584 {
mbed_official 76:aeb1df146756 1585 ITStatus bitstatus = RESET;
mbed_official 76:aeb1df146756 1586 /* Check the parameters */
mbed_official 76:aeb1df146756 1587 assert_param(IS_RCC_GET_IT(RCC_IT));
mbed_official 76:aeb1df146756 1588
mbed_official 76:aeb1df146756 1589 /* Check the status of the specified RCC interrupt */
mbed_official 76:aeb1df146756 1590 if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
mbed_official 76:aeb1df146756 1591 {
mbed_official 76:aeb1df146756 1592 bitstatus = SET;
mbed_official 76:aeb1df146756 1593 }
mbed_official 76:aeb1df146756 1594 else
mbed_official 76:aeb1df146756 1595 {
mbed_official 76:aeb1df146756 1596 bitstatus = RESET;
mbed_official 76:aeb1df146756 1597 }
mbed_official 76:aeb1df146756 1598 /* Return the RCC_IT status */
mbed_official 76:aeb1df146756 1599 return bitstatus;
mbed_official 76:aeb1df146756 1600 }
mbed_official 76:aeb1df146756 1601
mbed_official 76:aeb1df146756 1602 /**
mbed_official 76:aeb1df146756 1603 * @brief Clears the RCC's interrupt pending bits.
mbed_official 76:aeb1df146756 1604 * @param RCC_IT: specifies the interrupt pending bit to clear.
mbed_official 76:aeb1df146756 1605 * This parameter can be any combination of the following values:
mbed_official 76:aeb1df146756 1606 * @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official 76:aeb1df146756 1607 * @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official 76:aeb1df146756 1608 * @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official 76:aeb1df146756 1609 * @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official 76:aeb1df146756 1610 * @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official 76:aeb1df146756 1611 * @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official 76:aeb1df146756 1612 * @arg RCC_IT_LSECSS: LSE CSS interrupt
mbed_official 76:aeb1df146756 1613 * @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official 76:aeb1df146756 1614 * @retval None
mbed_official 76:aeb1df146756 1615 */
mbed_official 76:aeb1df146756 1616 void RCC_ClearITPendingBit(uint8_t RCC_IT)
mbed_official 76:aeb1df146756 1617 {
mbed_official 76:aeb1df146756 1618 /* Check the parameters */
mbed_official 76:aeb1df146756 1619 assert_param(IS_RCC_CLEAR_IT(RCC_IT));
mbed_official 76:aeb1df146756 1620
mbed_official 76:aeb1df146756 1621 /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
mbed_official 76:aeb1df146756 1622 pending bits */
mbed_official 76:aeb1df146756 1623 *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
mbed_official 76:aeb1df146756 1624 }
mbed_official 76:aeb1df146756 1625
mbed_official 76:aeb1df146756 1626 /**
mbed_official 76:aeb1df146756 1627 * @}
mbed_official 76:aeb1df146756 1628 */
mbed_official 76:aeb1df146756 1629
mbed_official 76:aeb1df146756 1630 /**
mbed_official 76:aeb1df146756 1631 * @}
mbed_official 76:aeb1df146756 1632 */
mbed_official 76:aeb1df146756 1633
mbed_official 76:aeb1df146756 1634 /**
mbed_official 76:aeb1df146756 1635 * @}
mbed_official 76:aeb1df146756 1636 */
mbed_official 76:aeb1df146756 1637
mbed_official 76:aeb1df146756 1638 /**
mbed_official 76:aeb1df146756 1639 * @}
mbed_official 76:aeb1df146756 1640 */
mbed_official 76:aeb1df146756 1641
mbed_official 76:aeb1df146756 1642 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/