mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.c@99:6b967e9f1a5d, 2014-02-19 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Feb 19 09:00:05 2014 +0000
- Revision:
- 99:6b967e9f1a5d
- Parent:
- 82:0b31dbcd4769
- Child:
- 323:9e901b0a5aa1
Synchronized with git revision 00078565b9344c3a16969c962395009d6aca3ca6
Full URL: https://github.com/mbedmicro/mbed/commit/00078565b9344c3a16969c962395009d6aca3ca6/
CMSIS system for KL05Z update
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 99:6b967e9f1a5d | 1 | /* |
mbed_official | 99:6b967e9f1a5d | 2 | ** ################################################################### |
mbed_official | 99:6b967e9f1a5d | 3 | ** Processors: MKL05Z32FK4 |
mbed_official | 99:6b967e9f1a5d | 4 | ** MKL05Z32LC4 |
mbed_official | 99:6b967e9f1a5d | 5 | ** MKL05Z32VLF4 |
mbed_official | 99:6b967e9f1a5d | 6 | ** |
mbed_official | 99:6b967e9f1a5d | 7 | ** Compilers: ARM Compiler |
mbed_official | 99:6b967e9f1a5d | 8 | ** Freescale C/C++ for Embedded ARM |
mbed_official | 99:6b967e9f1a5d | 9 | ** GNU C Compiler |
mbed_official | 99:6b967e9f1a5d | 10 | ** IAR ANSI C/C++ Compiler for ARM |
mbed_official | 99:6b967e9f1a5d | 11 | ** |
mbed_official | 99:6b967e9f1a5d | 12 | ** Reference manual: KL05P48M48SF1RM, Rev.3, Sep 2012 |
mbed_official | 99:6b967e9f1a5d | 13 | ** Version: rev. 1.6, 2013-04-11 |
mbed_official | 99:6b967e9f1a5d | 14 | ** |
mbed_official | 99:6b967e9f1a5d | 15 | ** Abstract: |
mbed_official | 99:6b967e9f1a5d | 16 | ** Provides a system configuration function and a global variable that |
mbed_official | 99:6b967e9f1a5d | 17 | ** contains the system frequency. It configures the device and initializes |
mbed_official | 99:6b967e9f1a5d | 18 | ** the oscillator (PLL) that is part of the microcontroller device. |
mbed_official | 99:6b967e9f1a5d | 19 | ** |
mbed_official | 99:6b967e9f1a5d | 20 | ** Copyright: 2013 Freescale, Inc. All Rights Reserved. |
mbed_official | 99:6b967e9f1a5d | 21 | ** |
mbed_official | 99:6b967e9f1a5d | 22 | ** http: www.freescale.com |
mbed_official | 99:6b967e9f1a5d | 23 | ** mail: support@freescale.com |
mbed_official | 99:6b967e9f1a5d | 24 | ** |
mbed_official | 99:6b967e9f1a5d | 25 | ** Revisions: |
mbed_official | 99:6b967e9f1a5d | 26 | ** - rev. 1.0 (2012-06-08) |
mbed_official | 99:6b967e9f1a5d | 27 | ** Initial version. |
mbed_official | 99:6b967e9f1a5d | 28 | ** - rev. 1.1 (2012-06-21) |
mbed_official | 99:6b967e9f1a5d | 29 | ** Update according to reference manual rev. 1. |
mbed_official | 99:6b967e9f1a5d | 30 | ** - rev. 1.2 (2012-08-01) |
mbed_official | 99:6b967e9f1a5d | 31 | ** Device type UARTLP changed to UART0. |
mbed_official | 99:6b967e9f1a5d | 32 | ** Missing PORTB_IRQn interrupt number definition added. |
mbed_official | 99:6b967e9f1a5d | 33 | ** - rev. 1.3 (2012-10-04) |
mbed_official | 99:6b967e9f1a5d | 34 | ** Update according to reference manual rev. 3. |
mbed_official | 99:6b967e9f1a5d | 35 | ** - rev. 1.4 (2012-11-22) |
mbed_official | 99:6b967e9f1a5d | 36 | ** MCG module - bit LOLS in MCG_S register renamed to LOLS0. |
mbed_official | 99:6b967e9f1a5d | 37 | ** NV registers - bit EZPORT_DIS in NV_FOPT register removed. |
mbed_official | 99:6b967e9f1a5d | 38 | ** - rev. 1.5 (2013-04-05) |
mbed_official | 99:6b967e9f1a5d | 39 | ** Changed start of doxygen comment. |
mbed_official | 99:6b967e9f1a5d | 40 | ** - rev. 1.6 (2013-04-11) |
mbed_official | 99:6b967e9f1a5d | 41 | ** SystemInit methods updated with predefined initialization sequence. |
mbed_official | 99:6b967e9f1a5d | 42 | ** |
mbed_official | 99:6b967e9f1a5d | 43 | ** ################################################################### |
mbed_official | 99:6b967e9f1a5d | 44 | */ |
mbed_official | 99:6b967e9f1a5d | 45 | |
mbed_official | 99:6b967e9f1a5d | 46 | /*! |
mbed_official | 99:6b967e9f1a5d | 47 | * @file MKL05Z4 |
mbed_official | 99:6b967e9f1a5d | 48 | * @version 1.6 |
mbed_official | 99:6b967e9f1a5d | 49 | * @date 2013-04-11 |
mbed_official | 99:6b967e9f1a5d | 50 | * @brief Device specific configuration file for MKL05Z4 (implementation file) |
mbed_official | 99:6b967e9f1a5d | 51 | * |
mbed_official | 99:6b967e9f1a5d | 52 | * Provides a system configuration function and a global variable that contains |
mbed_official | 99:6b967e9f1a5d | 53 | * the system frequency. It configures the device and initializes the oscillator |
mbed_official | 99:6b967e9f1a5d | 54 | * (PLL) that is part of the microcontroller device. |
mbed_official | 99:6b967e9f1a5d | 55 | */ |
mbed_official | 99:6b967e9f1a5d | 56 | |
mbed_official | 82:0b31dbcd4769 | 57 | #include <stdint.h> |
mbed_official | 82:0b31dbcd4769 | 58 | #include "MKL05Z4.h" |
mbed_official | 82:0b31dbcd4769 | 59 | |
mbed_official | 99:6b967e9f1a5d | 60 | #define DISABLE_WDOG 1 |
mbed_official | 82:0b31dbcd4769 | 61 | |
mbed_official | 99:6b967e9f1a5d | 62 | #define CLOCK_SETUP 1 |
mbed_official | 82:0b31dbcd4769 | 63 | /* Predefined clock setups |
mbed_official | 99:6b967e9f1a5d | 64 | 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode |
mbed_official | 82:0b31dbcd4769 | 65 | Reference clock source for MCG module is the slow internal clock source 32.768kHz |
mbed_official | 99:6b967e9f1a5d | 66 | Core clock = 41.94MHz, BusClock = 20.97MHz |
mbed_official | 99:6b967e9f1a5d | 67 | 1 ... Multipurpose Clock Generator (MCG) in FLL Engaged External (FEE) mode |
mbed_official | 99:6b967e9f1a5d | 68 | Reference clock source for MCG module is an external crystal 32.768kHz |
mbed_official | 99:6b967e9f1a5d | 69 | Core clock = 47.97MHz, BusClock = 23.98MHz |
mbed_official | 99:6b967e9f1a5d | 70 | 2 ... Multipurpose Clock Generator (MCG) in FLL Bypassed Low Power Internal (BLPI) mode |
mbed_official | 99:6b967e9f1a5d | 71 | Core clock/Bus clock derived directly from an fast internal 4MHz clock with no multiplication |
mbed_official | 99:6b967e9f1a5d | 72 | Core clock = 4MHz, BusClock = 4MHz |
mbed_official | 82:0b31dbcd4769 | 73 | */ |
mbed_official | 82:0b31dbcd4769 | 74 | |
mbed_official | 99:6b967e9f1a5d | 75 | /*---------------------------------------------------------------------------- |
mbed_official | 99:6b967e9f1a5d | 76 | Define clock source values |
mbed_official | 99:6b967e9f1a5d | 77 | *----------------------------------------------------------------------------*/ |
mbed_official | 99:6b967e9f1a5d | 78 | #if (CLOCK_SETUP == 0) |
mbed_official | 99:6b967e9f1a5d | 79 | #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */ |
mbed_official | 99:6b967e9f1a5d | 80 | #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ |
mbed_official | 99:6b967e9f1a5d | 81 | #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ |
mbed_official | 99:6b967e9f1a5d | 82 | #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */ |
mbed_official | 99:6b967e9f1a5d | 83 | #elif (CLOCK_SETUP == 1) |
mbed_official | 99:6b967e9f1a5d | 84 | #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */ |
mbed_official | 99:6b967e9f1a5d | 85 | #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ |
mbed_official | 99:6b967e9f1a5d | 86 | #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ |
mbed_official | 99:6b967e9f1a5d | 87 | #define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */ |
mbed_official | 99:6b967e9f1a5d | 88 | #elif (CLOCK_SETUP == 2) |
mbed_official | 99:6b967e9f1a5d | 89 | #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */ |
mbed_official | 99:6b967e9f1a5d | 90 | #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ |
mbed_official | 99:6b967e9f1a5d | 91 | #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ |
mbed_official | 99:6b967e9f1a5d | 92 | #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */ |
mbed_official | 99:6b967e9f1a5d | 93 | #endif /* (CLOCK_SETUP == 2) */ |
mbed_official | 99:6b967e9f1a5d | 94 | |
mbed_official | 99:6b967e9f1a5d | 95 | |
mbed_official | 99:6b967e9f1a5d | 96 | /* ---------------------------------------------------------------------------- |
mbed_official | 99:6b967e9f1a5d | 97 | -- Core clock |
mbed_official | 99:6b967e9f1a5d | 98 | ---------------------------------------------------------------------------- */ |
mbed_official | 82:0b31dbcd4769 | 99 | |
mbed_official | 82:0b31dbcd4769 | 100 | uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; |
mbed_official | 82:0b31dbcd4769 | 101 | |
mbed_official | 99:6b967e9f1a5d | 102 | /* ---------------------------------------------------------------------------- |
mbed_official | 99:6b967e9f1a5d | 103 | -- SystemInit() |
mbed_official | 99:6b967e9f1a5d | 104 | ---------------------------------------------------------------------------- */ |
mbed_official | 82:0b31dbcd4769 | 105 | |
mbed_official | 99:6b967e9f1a5d | 106 | void SystemInit (void) { |
mbed_official | 99:6b967e9f1a5d | 107 | #if (DISABLE_WDOG) |
mbed_official | 99:6b967e9f1a5d | 108 | /* Disable the WDOG module */ |
mbed_official | 99:6b967e9f1a5d | 109 | /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */ |
mbed_official | 99:6b967e9f1a5d | 110 | SIM->COPC = (uint32_t)0x00u; |
mbed_official | 99:6b967e9f1a5d | 111 | #endif /* (DISABLE_WDOG) */ |
mbed_official | 99:6b967e9f1a5d | 112 | #if (CLOCK_SETUP == 0) |
mbed_official | 99:6b967e9f1a5d | 113 | /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ |
mbed_official | 99:6b967e9f1a5d | 114 | SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */ |
mbed_official | 99:6b967e9f1a5d | 115 | /* Switch to FEI Mode */ |
mbed_official | 99:6b967e9f1a5d | 116 | /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ |
mbed_official | 99:6b967e9f1a5d | 117 | MCG->C1 = MCG_C1_CLKS(0x00) | |
mbed_official | 99:6b967e9f1a5d | 118 | MCG_C1_FRDIV(0x00) | |
mbed_official | 99:6b967e9f1a5d | 119 | MCG_C1_IREFS_MASK | |
mbed_official | 99:6b967e9f1a5d | 120 | MCG_C1_IRCLKEN_MASK; |
mbed_official | 99:6b967e9f1a5d | 121 | /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */ |
mbed_official | 99:6b967e9f1a5d | 122 | MCG->C2 = MCG_C2_RANGE0(0x00); |
mbed_official | 99:6b967e9f1a5d | 123 | /* MCG_C4: DMX32=0,DRST_DRS=1 */ |
mbed_official | 99:6b967e9f1a5d | 124 | MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)( |
mbed_official | 99:6b967e9f1a5d | 125 | MCG_C4_DMX32_MASK | |
mbed_official | 99:6b967e9f1a5d | 126 | MCG_C4_DRST_DRS(0x02) |
mbed_official | 99:6b967e9f1a5d | 127 | )) | (uint8_t)( |
mbed_official | 99:6b967e9f1a5d | 128 | MCG_C4_DRST_DRS(0x01) |
mbed_official | 99:6b967e9f1a5d | 129 | )); |
mbed_official | 99:6b967e9f1a5d | 130 | /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ |
mbed_official | 99:6b967e9f1a5d | 131 | OSC0->CR = OSC_CR_ERCLKEN_MASK; |
mbed_official | 99:6b967e9f1a5d | 132 | while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */ |
mbed_official | 99:6b967e9f1a5d | 133 | } |
mbed_official | 99:6b967e9f1a5d | 134 | while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */ |
mbed_official | 99:6b967e9f1a5d | 135 | } |
mbed_official | 99:6b967e9f1a5d | 136 | #elif (CLOCK_SETUP == 1) |
mbed_official | 99:6b967e9f1a5d | 137 | /* SIM->SCGC5: PORTA=1 */ |
mbed_official | 99:6b967e9f1a5d | 138 | SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */ |
mbed_official | 99:6b967e9f1a5d | 139 | /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ |
mbed_official | 99:6b967e9f1a5d | 140 | SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */ |
mbed_official | 99:6b967e9f1a5d | 141 | /* PORTA->PCR[3]: ISF=0,MUX=0 */ |
mbed_official | 99:6b967e9f1a5d | 142 | PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); |
mbed_official | 99:6b967e9f1a5d | 143 | /* PORTA->PCR[4]: ISF=0,MUX=0 */ |
mbed_official | 99:6b967e9f1a5d | 144 | PORTA->PCR[4] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); |
mbed_official | 99:6b967e9f1a5d | 145 | /* Switch to FEE Mode */ |
mbed_official | 99:6b967e9f1a5d | 146 | /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ |
mbed_official | 99:6b967e9f1a5d | 147 | MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_EREFS0_MASK); |
mbed_official | 99:6b967e9f1a5d | 148 | /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ |
mbed_official | 99:6b967e9f1a5d | 149 | OSC0->CR = OSC_CR_ERCLKEN_MASK; |
mbed_official | 99:6b967e9f1a5d | 150 | /* MCG->C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ |
mbed_official | 99:6b967e9f1a5d | 151 | MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK); |
mbed_official | 99:6b967e9f1a5d | 152 | /* MCG->C4: DMX32=1,DRST_DRS=1 */ |
mbed_official | 99:6b967e9f1a5d | 153 | MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)( |
mbed_official | 99:6b967e9f1a5d | 154 | MCG_C4_DRST_DRS(0x02) |
mbed_official | 99:6b967e9f1a5d | 155 | )) | (uint8_t)( |
mbed_official | 99:6b967e9f1a5d | 156 | MCG_C4_DMX32_MASK | |
mbed_official | 99:6b967e9f1a5d | 157 | MCG_C4_DRST_DRS(0x01) |
mbed_official | 99:6b967e9f1a5d | 158 | )); |
mbed_official | 99:6b967e9f1a5d | 159 | while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */ |
mbed_official | 99:6b967e9f1a5d | 160 | } |
mbed_official | 99:6b967e9f1a5d | 161 | while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */ |
mbed_official | 99:6b967e9f1a5d | 162 | } |
mbed_official | 99:6b967e9f1a5d | 163 | #elif (CLOCK_SETUP == 2) |
mbed_official | 99:6b967e9f1a5d | 164 | /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ |
mbed_official | 99:6b967e9f1a5d | 165 | SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x00)); /* Update system prescalers */ |
mbed_official | 99:6b967e9f1a5d | 166 | /* MCG->SC: FCRDIV=0 */ |
mbed_official | 99:6b967e9f1a5d | 167 | MCG->SC &= (uint8_t)~(uint8_t)(MCG_SC_FCRDIV(0x07)); |
mbed_official | 99:6b967e9f1a5d | 168 | /* Switch to FBI Mode */ |
mbed_official | 99:6b967e9f1a5d | 169 | /* MCG->C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ |
mbed_official | 99:6b967e9f1a5d | 170 | MCG->C1 = MCG_C1_CLKS(0x01) | |
mbed_official | 99:6b967e9f1a5d | 171 | MCG_C1_FRDIV(0x00) | |
mbed_official | 99:6b967e9f1a5d | 172 | MCG_C1_IREFS_MASK | |
mbed_official | 99:6b967e9f1a5d | 173 | MCG_C1_IRCLKEN_MASK; |
mbed_official | 99:6b967e9f1a5d | 174 | /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=1 */ |
mbed_official | 99:6b967e9f1a5d | 175 | MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_IRCS_MASK); |
mbed_official | 99:6b967e9f1a5d | 176 | /* MCG->C4: DMX32=0,DRST_DRS=0 */ |
mbed_official | 99:6b967e9f1a5d | 177 | MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); |
mbed_official | 99:6b967e9f1a5d | 178 | /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ |
mbed_official | 99:6b967e9f1a5d | 179 | OSC0->CR = OSC_CR_ERCLKEN_MASK; |
mbed_official | 99:6b967e9f1a5d | 180 | while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */ |
mbed_official | 99:6b967e9f1a5d | 181 | } |
mbed_official | 99:6b967e9f1a5d | 182 | while((MCG->S & 0x0CU) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */ |
mbed_official | 99:6b967e9f1a5d | 183 | } |
mbed_official | 99:6b967e9f1a5d | 184 | /* Switch to BLPI Mode */ |
mbed_official | 99:6b967e9f1a5d | 185 | /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=1,IRCS=1 */ |
mbed_official | 99:6b967e9f1a5d | 186 | MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_LP_MASK | MCG_C2_IRCS_MASK); |
mbed_official | 99:6b967e9f1a5d | 187 | while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */ |
mbed_official | 99:6b967e9f1a5d | 188 | } |
mbed_official | 99:6b967e9f1a5d | 189 | while((MCG->S & MCG_S_IRCST_MASK) == 0x00U) { /* Check that the fast external reference clock is selected. */ |
mbed_official | 99:6b967e9f1a5d | 190 | } |
mbed_official | 99:6b967e9f1a5d | 191 | #endif /* (CLOCK_SETUP == 2) */ |
mbed_official | 82:0b31dbcd4769 | 192 | } |
mbed_official | 82:0b31dbcd4769 | 193 | |
mbed_official | 99:6b967e9f1a5d | 194 | /* ---------------------------------------------------------------------------- |
mbed_official | 99:6b967e9f1a5d | 195 | -- SystemCoreClockUpdate() |
mbed_official | 99:6b967e9f1a5d | 196 | ---------------------------------------------------------------------------- */ |
mbed_official | 82:0b31dbcd4769 | 197 | |
mbed_official | 99:6b967e9f1a5d | 198 | void SystemCoreClockUpdate (void) { |
mbed_official | 99:6b967e9f1a5d | 199 | uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ |
mbed_official | 99:6b967e9f1a5d | 200 | uint8_t Divider; |
mbed_official | 82:0b31dbcd4769 | 201 | |
mbed_official | 99:6b967e9f1a5d | 202 | if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) { |
mbed_official | 99:6b967e9f1a5d | 203 | /* Output of FLL is selected */ |
mbed_official | 99:6b967e9f1a5d | 204 | if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) { |
mbed_official | 99:6b967e9f1a5d | 205 | /* External reference clock is selected */ |
mbed_official | 99:6b967e9f1a5d | 206 | MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ |
mbed_official | 99:6b967e9f1a5d | 207 | Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); |
mbed_official | 99:6b967e9f1a5d | 208 | MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ |
mbed_official | 99:6b967e9f1a5d | 209 | } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ |
mbed_official | 99:6b967e9f1a5d | 210 | MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ |
mbed_official | 99:6b967e9f1a5d | 211 | } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ |
mbed_official | 99:6b967e9f1a5d | 212 | /* Select correct multiplier to calculate the MCG output clock */ |
mbed_official | 99:6b967e9f1a5d | 213 | switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { |
mbed_official | 99:6b967e9f1a5d | 214 | case 0x0u: |
mbed_official | 99:6b967e9f1a5d | 215 | MCGOUTClock *= 640u; |
mbed_official | 99:6b967e9f1a5d | 216 | break; |
mbed_official | 99:6b967e9f1a5d | 217 | case 0x20u: |
mbed_official | 99:6b967e9f1a5d | 218 | MCGOUTClock *= 1280u; |
mbed_official | 99:6b967e9f1a5d | 219 | break; |
mbed_official | 99:6b967e9f1a5d | 220 | case 0x40u: |
mbed_official | 99:6b967e9f1a5d | 221 | MCGOUTClock *= 1920u; |
mbed_official | 99:6b967e9f1a5d | 222 | break; |
mbed_official | 99:6b967e9f1a5d | 223 | case 0x60u: |
mbed_official | 99:6b967e9f1a5d | 224 | MCGOUTClock *= 2560u; |
mbed_official | 99:6b967e9f1a5d | 225 | break; |
mbed_official | 99:6b967e9f1a5d | 226 | case 0x80u: |
mbed_official | 99:6b967e9f1a5d | 227 | MCGOUTClock *= 732u; |
mbed_official | 99:6b967e9f1a5d | 228 | break; |
mbed_official | 99:6b967e9f1a5d | 229 | case 0xA0u: |
mbed_official | 99:6b967e9f1a5d | 230 | MCGOUTClock *= 1464u; |
mbed_official | 99:6b967e9f1a5d | 231 | break; |
mbed_official | 99:6b967e9f1a5d | 232 | case 0xC0u: |
mbed_official | 99:6b967e9f1a5d | 233 | MCGOUTClock *= 2197u; |
mbed_official | 99:6b967e9f1a5d | 234 | break; |
mbed_official | 99:6b967e9f1a5d | 235 | case 0xE0u: |
mbed_official | 99:6b967e9f1a5d | 236 | MCGOUTClock *= 2929u; |
mbed_official | 99:6b967e9f1a5d | 237 | break; |
mbed_official | 99:6b967e9f1a5d | 238 | default: |
mbed_official | 99:6b967e9f1a5d | 239 | break; |
mbed_official | 82:0b31dbcd4769 | 240 | } |
mbed_official | 99:6b967e9f1a5d | 241 | } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) { |
mbed_official | 99:6b967e9f1a5d | 242 | /* Internal reference clock is selected */ |
mbed_official | 99:6b967e9f1a5d | 243 | if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) { |
mbed_official | 99:6b967e9f1a5d | 244 | MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ |
mbed_official | 99:6b967e9f1a5d | 245 | } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ |
mbed_official | 99:6b967e9f1a5d | 246 | MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */ |
mbed_official | 99:6b967e9f1a5d | 247 | } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ |
mbed_official | 99:6b967e9f1a5d | 248 | } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) { |
mbed_official | 99:6b967e9f1a5d | 249 | /* External reference clock is selected */ |
mbed_official | 99:6b967e9f1a5d | 250 | MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ |
mbed_official | 99:6b967e9f1a5d | 251 | } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ |
mbed_official | 99:6b967e9f1a5d | 252 | /* Reserved value */ |
mbed_official | 99:6b967e9f1a5d | 253 | return; |
mbed_official | 99:6b967e9f1a5d | 254 | } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ |
mbed_official | 99:6b967e9f1a5d | 255 | SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); |
mbed_official | 82:0b31dbcd4769 | 256 | } |