shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

Fork of mbed-src by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.c@82:0b31dbcd4769, 2014-01-31 (annotated)

Committer:
mbed_official
Date:
Fri Jan 31 10:00:06 2014 +0000
Revision:
82:0b31dbcd4769
Child:
99:6b967e9f1a5d
Synchronized with git revision 74409cbd593d1daab530a57baaa563f30b04b018



Full URL: https://github.com/mbedmicro/mbed/commit/74409cbd593d1daab530a57baaa563f30b04b018/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 82:0b31dbcd4769 1 #include <stdint.h>
mbed_official 82:0b31dbcd4769 2 #include "MKL05Z4.h"
mbed_official 82:0b31dbcd4769 3
mbed_official 82:0b31dbcd4769 4 #define DISABLE_WDOG 1
mbed_official 82:0b31dbcd4769 5
mbed_official 82:0b31dbcd4769 6 /* Predefined clock setups
mbed_official 82:0b31dbcd4769 7 Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
mbed_official 82:0b31dbcd4769 8 Reference clock source for MCG module is the slow internal clock source 32.768kHz
mbed_official 82:0b31dbcd4769 9 Core clock = 47.97MHz, BusClock = 23.48MHz
mbed_official 82:0b31dbcd4769 10 */
mbed_official 82:0b31dbcd4769 11
mbed_official 82:0b31dbcd4769 12 #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 82:0b31dbcd4769 13 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 82:0b31dbcd4769 14 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 82:0b31dbcd4769 15 #define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */
mbed_official 82:0b31dbcd4769 16
mbed_official 82:0b31dbcd4769 17 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
mbed_official 82:0b31dbcd4769 18
mbed_official 82:0b31dbcd4769 19 void SystemInit(void) {
mbed_official 82:0b31dbcd4769 20 #if (DISABLE_WDOG)
mbed_official 82:0b31dbcd4769 21 /* Disable the WDOG module */
mbed_official 82:0b31dbcd4769 22 /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
mbed_official 82:0b31dbcd4769 23 SIM->COPC = (uint32_t)0x00u;
mbed_official 82:0b31dbcd4769 24 #endif /* (DISABLE_WDOG) */
mbed_official 82:0b31dbcd4769 25
mbed_official 82:0b31dbcd4769 26 SIM->SCGC5 |= (SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTA_MASK); /* Enable clock gate for ports to enable pin routing */
mbed_official 82:0b31dbcd4769 27 /* SIM_SCGC5: LPTMR=1 */
mbed_official 82:0b31dbcd4769 28 SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK;
mbed_official 82:0b31dbcd4769 29 /* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
mbed_official 82:0b31dbcd4769 30 SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
mbed_official 82:0b31dbcd4769 31 /* SIM_SOPT1: OSC32KSEL=0 */
mbed_official 82:0b31dbcd4769 32 SIM->SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */
mbed_official 82:0b31dbcd4769 33 /* SIM_SOPT2: TPMSRC=2 */
mbed_official 82:0b31dbcd4769 34 SIM->SOPT2 = (uint32_t)((SIM->SOPT2 & (uint32_t)~(uint32_t)(SIM_SOPT2_TPMSRC(0x01))) |
mbed_official 82:0b31dbcd4769 35 (uint32_t)(SIM_SOPT2_TPMSRC(0x02))); /* Set the TPM clock */
mbed_official 82:0b31dbcd4769 36 /* PORTA_PCR3: ISF=0,MUX=0 */
mbed_official 82:0b31dbcd4769 37 PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
mbed_official 82:0b31dbcd4769 38 /* MCG_SC: FCRDIV=1 */
mbed_official 82:0b31dbcd4769 39 MCG->SC = (uint8_t)((MCG->SC & (uint8_t)~(uint8_t)(MCG_SC_FCRDIV(0x06))) |
mbed_official 82:0b31dbcd4769 40 (uint8_t)(MCG_SC_FCRDIV(0x01)));
mbed_official 82:0b31dbcd4769 41 /* Switch to FEI Mode */
mbed_official 82:0b31dbcd4769 42 /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
mbed_official 82:0b31dbcd4769 43 MCG->C1 = MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) |
mbed_official 82:0b31dbcd4769 44 MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK;
mbed_official 82:0b31dbcd4769 45 /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=1 */
mbed_official 82:0b31dbcd4769 46 MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_IRCS_MASK);
mbed_official 82:0b31dbcd4769 47 /* MCG_C4: DMX32=1,DRST_DRS=1 */
mbed_official 82:0b31dbcd4769 48 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(MCG_C4_DRST_DRS(0x02))) |
mbed_official 82:0b31dbcd4769 49 (uint8_t)(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x01)));
mbed_official 82:0b31dbcd4769 50 /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
mbed_official 82:0b31dbcd4769 51 OSC0->CR = OSC_CR_ERCLKEN_MASK;
mbed_official 82:0b31dbcd4769 52 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
mbed_official 82:0b31dbcd4769 53 }
mbed_official 82:0b31dbcd4769 54 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
mbed_official 82:0b31dbcd4769 55 }
mbed_official 82:0b31dbcd4769 56 }
mbed_official 82:0b31dbcd4769 57
mbed_official 82:0b31dbcd4769 58 void SystemCoreClockUpdate(void) {
mbed_official 82:0b31dbcd4769 59 uint32_t MCGOUTClock;
mbed_official 82:0b31dbcd4769 60 uint8_t Divider;
mbed_official 82:0b31dbcd4769 61
mbed_official 82:0b31dbcd4769 62 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
mbed_official 82:0b31dbcd4769 63 /* FLL is selected */
mbed_official 82:0b31dbcd4769 64 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
mbed_official 82:0b31dbcd4769 65 /* External reference clock is selected */
mbed_official 82:0b31dbcd4769 66 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 82:0b31dbcd4769 67 Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
mbed_official 82:0b31dbcd4769 68 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
mbed_official 82:0b31dbcd4769 69 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
mbed_official 82:0b31dbcd4769 70 MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
mbed_official 82:0b31dbcd4769 71 }
mbed_official 82:0b31dbcd4769 72 } else {
mbed_official 82:0b31dbcd4769 73 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
mbed_official 82:0b31dbcd4769 74 }
mbed_official 82:0b31dbcd4769 75
mbed_official 82:0b31dbcd4769 76 /* Select correct multiplier to calculate the MCG output clock */
mbed_official 82:0b31dbcd4769 77 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
mbed_official 82:0b31dbcd4769 78 case 0x0u:
mbed_official 82:0b31dbcd4769 79 MCGOUTClock *= 640u;
mbed_official 82:0b31dbcd4769 80 break;
mbed_official 82:0b31dbcd4769 81 case 0x20u:
mbed_official 82:0b31dbcd4769 82 MCGOUTClock *= 1280u;
mbed_official 82:0b31dbcd4769 83 break;
mbed_official 82:0b31dbcd4769 84 case 0x40u:
mbed_official 82:0b31dbcd4769 85 MCGOUTClock *= 1920u;
mbed_official 82:0b31dbcd4769 86 break;
mbed_official 82:0b31dbcd4769 87 case 0x60u:
mbed_official 82:0b31dbcd4769 88 MCGOUTClock *= 2560u;
mbed_official 82:0b31dbcd4769 89 break;
mbed_official 82:0b31dbcd4769 90 case 0x80u:
mbed_official 82:0b31dbcd4769 91 MCGOUTClock *= 732u;
mbed_official 82:0b31dbcd4769 92 break;
mbed_official 82:0b31dbcd4769 93 case 0xA0u:
mbed_official 82:0b31dbcd4769 94 MCGOUTClock *= 1464u;
mbed_official 82:0b31dbcd4769 95 break;
mbed_official 82:0b31dbcd4769 96 case 0xC0u:
mbed_official 82:0b31dbcd4769 97 MCGOUTClock *= 2197u;
mbed_official 82:0b31dbcd4769 98 break;
mbed_official 82:0b31dbcd4769 99 case 0xE0u:
mbed_official 82:0b31dbcd4769 100 MCGOUTClock *= 2929u;
mbed_official 82:0b31dbcd4769 101 break;
mbed_official 82:0b31dbcd4769 102 default:
mbed_official 82:0b31dbcd4769 103 break;
mbed_official 82:0b31dbcd4769 104 }
mbed_official 82:0b31dbcd4769 105 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
mbed_official 82:0b31dbcd4769 106 /* Internal reference clock is selected */
mbed_official 82:0b31dbcd4769 107 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
mbed_official 82:0b31dbcd4769 108 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
mbed_official 82:0b31dbcd4769 109 } else {
mbed_official 82:0b31dbcd4769 110 MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
mbed_official 82:0b31dbcd4769 111 }
mbed_official 82:0b31dbcd4769 112 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
mbed_official 82:0b31dbcd4769 113 /* External reference clock is selected */
mbed_official 82:0b31dbcd4769 114 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 82:0b31dbcd4769 115 } else {
mbed_official 82:0b31dbcd4769 116 /* Reserved value */
mbed_official 82:0b31dbcd4769 117 return;
mbed_official 82:0b31dbcd4769 118 }
mbed_official 82:0b31dbcd4769 119
mbed_official 82:0b31dbcd4769 120 SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
mbed_official 82:0b31dbcd4769 121
mbed_official 82:0b31dbcd4769 122 }