mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_rtc.h@149:1fb5f62b92bd, 2014-04-03 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Apr 03 11:45:06 2014 +0100
- Revision:
- 149:1fb5f62b92bd
- Parent:
- targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_rtc.h@146:f64d43ff0c18
Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42
Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 146:f64d43ff0c18 | 1 | /* |
mbed_official | 146:f64d43ff0c18 | 2 | * Copyright (c) 2014, Freescale Semiconductor, Inc. |
mbed_official | 146:f64d43ff0c18 | 3 | * All rights reserved. |
mbed_official | 146:f64d43ff0c18 | 4 | * |
mbed_official | 146:f64d43ff0c18 | 5 | * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED |
mbed_official | 146:f64d43ff0c18 | 6 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
mbed_official | 146:f64d43ff0c18 | 7 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT |
mbed_official | 146:f64d43ff0c18 | 8 | * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
mbed_official | 146:f64d43ff0c18 | 9 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
mbed_official | 146:f64d43ff0c18 | 10 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
mbed_official | 146:f64d43ff0c18 | 11 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
mbed_official | 146:f64d43ff0c18 | 12 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
mbed_official | 146:f64d43ff0c18 | 13 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
mbed_official | 146:f64d43ff0c18 | 14 | * OF SUCH DAMAGE. |
mbed_official | 146:f64d43ff0c18 | 15 | */ |
mbed_official | 146:f64d43ff0c18 | 16 | /* |
mbed_official | 146:f64d43ff0c18 | 17 | * WARNING! DO NOT EDIT THIS FILE DIRECTLY! |
mbed_official | 146:f64d43ff0c18 | 18 | * |
mbed_official | 146:f64d43ff0c18 | 19 | * This file was generated automatically and any changes may be lost. |
mbed_official | 146:f64d43ff0c18 | 20 | */ |
mbed_official | 146:f64d43ff0c18 | 21 | #ifndef __HW_RTC_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 22 | #define __HW_RTC_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 23 | |
mbed_official | 146:f64d43ff0c18 | 24 | #include "regs.h" |
mbed_official | 146:f64d43ff0c18 | 25 | |
mbed_official | 146:f64d43ff0c18 | 26 | /* |
mbed_official | 146:f64d43ff0c18 | 27 | * MK64F12 RTC |
mbed_official | 146:f64d43ff0c18 | 28 | * |
mbed_official | 146:f64d43ff0c18 | 29 | * Secure Real Time Clock |
mbed_official | 146:f64d43ff0c18 | 30 | * |
mbed_official | 146:f64d43ff0c18 | 31 | * Registers defined in this header file: |
mbed_official | 146:f64d43ff0c18 | 32 | * - HW_RTC_TSR - RTC Time Seconds Register |
mbed_official | 146:f64d43ff0c18 | 33 | * - HW_RTC_TPR - RTC Time Prescaler Register |
mbed_official | 146:f64d43ff0c18 | 34 | * - HW_RTC_TAR - RTC Time Alarm Register |
mbed_official | 146:f64d43ff0c18 | 35 | * - HW_RTC_TCR - RTC Time Compensation Register |
mbed_official | 146:f64d43ff0c18 | 36 | * - HW_RTC_CR - RTC Control Register |
mbed_official | 146:f64d43ff0c18 | 37 | * - HW_RTC_SR - RTC Status Register |
mbed_official | 146:f64d43ff0c18 | 38 | * - HW_RTC_LR - RTC Lock Register |
mbed_official | 146:f64d43ff0c18 | 39 | * - HW_RTC_IER - RTC Interrupt Enable Register |
mbed_official | 146:f64d43ff0c18 | 40 | * - HW_RTC_WAR - RTC Write Access Register |
mbed_official | 146:f64d43ff0c18 | 41 | * - HW_RTC_RAR - RTC Read Access Register |
mbed_official | 146:f64d43ff0c18 | 42 | * |
mbed_official | 146:f64d43ff0c18 | 43 | * - hw_rtc_t - Struct containing all module registers. |
mbed_official | 146:f64d43ff0c18 | 44 | */ |
mbed_official | 146:f64d43ff0c18 | 45 | |
mbed_official | 146:f64d43ff0c18 | 46 | //! @name Module base addresses |
mbed_official | 146:f64d43ff0c18 | 47 | //@{ |
mbed_official | 146:f64d43ff0c18 | 48 | #ifndef REGS_RTC_BASE |
mbed_official | 146:f64d43ff0c18 | 49 | #define HW_RTC_INSTANCE_COUNT (1U) //!< Number of instances of the RTC module. |
mbed_official | 146:f64d43ff0c18 | 50 | #define REGS_RTC_BASE (0x4003D000U) //!< Base address for RTC. |
mbed_official | 146:f64d43ff0c18 | 51 | #endif |
mbed_official | 146:f64d43ff0c18 | 52 | //@} |
mbed_official | 146:f64d43ff0c18 | 53 | |
mbed_official | 146:f64d43ff0c18 | 54 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 55 | // HW_RTC_TSR - RTC Time Seconds Register |
mbed_official | 146:f64d43ff0c18 | 56 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 57 | |
mbed_official | 146:f64d43ff0c18 | 58 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 59 | /*! |
mbed_official | 146:f64d43ff0c18 | 60 | * @brief HW_RTC_TSR - RTC Time Seconds Register (RW) |
mbed_official | 146:f64d43ff0c18 | 61 | * |
mbed_official | 146:f64d43ff0c18 | 62 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 63 | */ |
mbed_official | 146:f64d43ff0c18 | 64 | typedef union _hw_rtc_tsr |
mbed_official | 146:f64d43ff0c18 | 65 | { |
mbed_official | 146:f64d43ff0c18 | 66 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 67 | struct _hw_rtc_tsr_bitfields |
mbed_official | 146:f64d43ff0c18 | 68 | { |
mbed_official | 146:f64d43ff0c18 | 69 | uint32_t TSR : 32; //!< [31:0] Time Seconds Register |
mbed_official | 146:f64d43ff0c18 | 70 | } B; |
mbed_official | 146:f64d43ff0c18 | 71 | } hw_rtc_tsr_t; |
mbed_official | 146:f64d43ff0c18 | 72 | #endif |
mbed_official | 146:f64d43ff0c18 | 73 | |
mbed_official | 146:f64d43ff0c18 | 74 | /*! |
mbed_official | 146:f64d43ff0c18 | 75 | * @name Constants and macros for entire RTC_TSR register |
mbed_official | 146:f64d43ff0c18 | 76 | */ |
mbed_official | 146:f64d43ff0c18 | 77 | //@{ |
mbed_official | 146:f64d43ff0c18 | 78 | #define HW_RTC_TSR_ADDR (REGS_RTC_BASE + 0x0U) |
mbed_official | 146:f64d43ff0c18 | 79 | |
mbed_official | 146:f64d43ff0c18 | 80 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 81 | #define HW_RTC_TSR (*(__IO hw_rtc_tsr_t *) HW_RTC_TSR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 82 | #define HW_RTC_TSR_RD() (HW_RTC_TSR.U) |
mbed_official | 146:f64d43ff0c18 | 83 | #define HW_RTC_TSR_WR(v) (HW_RTC_TSR.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 84 | #define HW_RTC_TSR_SET(v) (HW_RTC_TSR_WR(HW_RTC_TSR_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 85 | #define HW_RTC_TSR_CLR(v) (HW_RTC_TSR_WR(HW_RTC_TSR_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 86 | #define HW_RTC_TSR_TOG(v) (HW_RTC_TSR_WR(HW_RTC_TSR_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 87 | #endif |
mbed_official | 146:f64d43ff0c18 | 88 | //@} |
mbed_official | 146:f64d43ff0c18 | 89 | |
mbed_official | 146:f64d43ff0c18 | 90 | /* |
mbed_official | 146:f64d43ff0c18 | 91 | * Constants & macros for individual RTC_TSR bitfields |
mbed_official | 146:f64d43ff0c18 | 92 | */ |
mbed_official | 146:f64d43ff0c18 | 93 | |
mbed_official | 146:f64d43ff0c18 | 94 | /*! |
mbed_official | 146:f64d43ff0c18 | 95 | * @name Register RTC_TSR, field TSR[31:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 96 | * |
mbed_official | 146:f64d43ff0c18 | 97 | * When the time counter is enabled, the TSR is read only and increments once a |
mbed_official | 146:f64d43ff0c18 | 98 | * second provided SR[TOF] or SR[TIF] are not set. The time counter will read as |
mbed_official | 146:f64d43ff0c18 | 99 | * zero when SR[TOF] or SR[TIF] are set. When the time counter is disabled, the |
mbed_official | 146:f64d43ff0c18 | 100 | * TSR can be read or written. Writing to the TSR when the time counter is |
mbed_official | 146:f64d43ff0c18 | 101 | * disabled will clear the SR[TOF] and/or the SR[TIF]. Writing to TSR with zero is |
mbed_official | 146:f64d43ff0c18 | 102 | * supported, but not recommended because TSR will read as zero when SR[TIF] or |
mbed_official | 146:f64d43ff0c18 | 103 | * SR[TOF] are set (indicating the time is invalid). |
mbed_official | 146:f64d43ff0c18 | 104 | */ |
mbed_official | 146:f64d43ff0c18 | 105 | //@{ |
mbed_official | 146:f64d43ff0c18 | 106 | #define BP_RTC_TSR_TSR (0U) //!< Bit position for RTC_TSR_TSR. |
mbed_official | 146:f64d43ff0c18 | 107 | #define BM_RTC_TSR_TSR (0xFFFFFFFFU) //!< Bit mask for RTC_TSR_TSR. |
mbed_official | 146:f64d43ff0c18 | 108 | #define BS_RTC_TSR_TSR (32U) //!< Bit field size in bits for RTC_TSR_TSR. |
mbed_official | 146:f64d43ff0c18 | 109 | |
mbed_official | 146:f64d43ff0c18 | 110 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 111 | //! @brief Read current value of the RTC_TSR_TSR field. |
mbed_official | 146:f64d43ff0c18 | 112 | #define BR_RTC_TSR_TSR (HW_RTC_TSR.U) |
mbed_official | 146:f64d43ff0c18 | 113 | #endif |
mbed_official | 146:f64d43ff0c18 | 114 | |
mbed_official | 146:f64d43ff0c18 | 115 | //! @brief Format value for bitfield RTC_TSR_TSR. |
mbed_official | 146:f64d43ff0c18 | 116 | #define BF_RTC_TSR_TSR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TSR_TSR), uint32_t) & BM_RTC_TSR_TSR) |
mbed_official | 146:f64d43ff0c18 | 117 | |
mbed_official | 146:f64d43ff0c18 | 118 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 119 | //! @brief Set the TSR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 120 | #define BW_RTC_TSR_TSR(v) (HW_RTC_TSR_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 121 | #endif |
mbed_official | 146:f64d43ff0c18 | 122 | //@} |
mbed_official | 146:f64d43ff0c18 | 123 | |
mbed_official | 146:f64d43ff0c18 | 124 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 125 | // HW_RTC_TPR - RTC Time Prescaler Register |
mbed_official | 146:f64d43ff0c18 | 126 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 127 | |
mbed_official | 146:f64d43ff0c18 | 128 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 129 | /*! |
mbed_official | 146:f64d43ff0c18 | 130 | * @brief HW_RTC_TPR - RTC Time Prescaler Register (RW) |
mbed_official | 146:f64d43ff0c18 | 131 | * |
mbed_official | 146:f64d43ff0c18 | 132 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 133 | */ |
mbed_official | 146:f64d43ff0c18 | 134 | typedef union _hw_rtc_tpr |
mbed_official | 146:f64d43ff0c18 | 135 | { |
mbed_official | 146:f64d43ff0c18 | 136 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 137 | struct _hw_rtc_tpr_bitfields |
mbed_official | 146:f64d43ff0c18 | 138 | { |
mbed_official | 146:f64d43ff0c18 | 139 | uint32_t TPR : 16; //!< [15:0] Time Prescaler Register |
mbed_official | 146:f64d43ff0c18 | 140 | uint32_t RESERVED0 : 16; //!< [31:16] |
mbed_official | 146:f64d43ff0c18 | 141 | } B; |
mbed_official | 146:f64d43ff0c18 | 142 | } hw_rtc_tpr_t; |
mbed_official | 146:f64d43ff0c18 | 143 | #endif |
mbed_official | 146:f64d43ff0c18 | 144 | |
mbed_official | 146:f64d43ff0c18 | 145 | /*! |
mbed_official | 146:f64d43ff0c18 | 146 | * @name Constants and macros for entire RTC_TPR register |
mbed_official | 146:f64d43ff0c18 | 147 | */ |
mbed_official | 146:f64d43ff0c18 | 148 | //@{ |
mbed_official | 146:f64d43ff0c18 | 149 | #define HW_RTC_TPR_ADDR (REGS_RTC_BASE + 0x4U) |
mbed_official | 146:f64d43ff0c18 | 150 | |
mbed_official | 146:f64d43ff0c18 | 151 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 152 | #define HW_RTC_TPR (*(__IO hw_rtc_tpr_t *) HW_RTC_TPR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 153 | #define HW_RTC_TPR_RD() (HW_RTC_TPR.U) |
mbed_official | 146:f64d43ff0c18 | 154 | #define HW_RTC_TPR_WR(v) (HW_RTC_TPR.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 155 | #define HW_RTC_TPR_SET(v) (HW_RTC_TPR_WR(HW_RTC_TPR_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 156 | #define HW_RTC_TPR_CLR(v) (HW_RTC_TPR_WR(HW_RTC_TPR_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 157 | #define HW_RTC_TPR_TOG(v) (HW_RTC_TPR_WR(HW_RTC_TPR_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 158 | #endif |
mbed_official | 146:f64d43ff0c18 | 159 | //@} |
mbed_official | 146:f64d43ff0c18 | 160 | |
mbed_official | 146:f64d43ff0c18 | 161 | /* |
mbed_official | 146:f64d43ff0c18 | 162 | * Constants & macros for individual RTC_TPR bitfields |
mbed_official | 146:f64d43ff0c18 | 163 | */ |
mbed_official | 146:f64d43ff0c18 | 164 | |
mbed_official | 146:f64d43ff0c18 | 165 | /*! |
mbed_official | 146:f64d43ff0c18 | 166 | * @name Register RTC_TPR, field TPR[15:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 167 | * |
mbed_official | 146:f64d43ff0c18 | 168 | * When the time counter is enabled, the TPR is read only and increments every |
mbed_official | 146:f64d43ff0c18 | 169 | * 32.768 kHz clock cycle. The time counter will read as zero when SR[TOF] or |
mbed_official | 146:f64d43ff0c18 | 170 | * SR[TIF] are set. When the time counter is disabled, the TPR can be read or |
mbed_official | 146:f64d43ff0c18 | 171 | * written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one |
mbed_official | 146:f64d43ff0c18 | 172 | * to a logic zero. |
mbed_official | 146:f64d43ff0c18 | 173 | */ |
mbed_official | 146:f64d43ff0c18 | 174 | //@{ |
mbed_official | 146:f64d43ff0c18 | 175 | #define BP_RTC_TPR_TPR (0U) //!< Bit position for RTC_TPR_TPR. |
mbed_official | 146:f64d43ff0c18 | 176 | #define BM_RTC_TPR_TPR (0x0000FFFFU) //!< Bit mask for RTC_TPR_TPR. |
mbed_official | 146:f64d43ff0c18 | 177 | #define BS_RTC_TPR_TPR (16U) //!< Bit field size in bits for RTC_TPR_TPR. |
mbed_official | 146:f64d43ff0c18 | 178 | |
mbed_official | 146:f64d43ff0c18 | 179 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 180 | //! @brief Read current value of the RTC_TPR_TPR field. |
mbed_official | 146:f64d43ff0c18 | 181 | #define BR_RTC_TPR_TPR (HW_RTC_TPR.B.TPR) |
mbed_official | 146:f64d43ff0c18 | 182 | #endif |
mbed_official | 146:f64d43ff0c18 | 183 | |
mbed_official | 146:f64d43ff0c18 | 184 | //! @brief Format value for bitfield RTC_TPR_TPR. |
mbed_official | 146:f64d43ff0c18 | 185 | #define BF_RTC_TPR_TPR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TPR_TPR), uint32_t) & BM_RTC_TPR_TPR) |
mbed_official | 146:f64d43ff0c18 | 186 | |
mbed_official | 146:f64d43ff0c18 | 187 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 188 | //! @brief Set the TPR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 189 | #define BW_RTC_TPR_TPR(v) (HW_RTC_TPR_WR((HW_RTC_TPR_RD() & ~BM_RTC_TPR_TPR) | BF_RTC_TPR_TPR(v))) |
mbed_official | 146:f64d43ff0c18 | 190 | #endif |
mbed_official | 146:f64d43ff0c18 | 191 | //@} |
mbed_official | 146:f64d43ff0c18 | 192 | |
mbed_official | 146:f64d43ff0c18 | 193 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 194 | // HW_RTC_TAR - RTC Time Alarm Register |
mbed_official | 146:f64d43ff0c18 | 195 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 196 | |
mbed_official | 146:f64d43ff0c18 | 197 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 198 | /*! |
mbed_official | 146:f64d43ff0c18 | 199 | * @brief HW_RTC_TAR - RTC Time Alarm Register (RW) |
mbed_official | 146:f64d43ff0c18 | 200 | * |
mbed_official | 146:f64d43ff0c18 | 201 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 202 | */ |
mbed_official | 146:f64d43ff0c18 | 203 | typedef union _hw_rtc_tar |
mbed_official | 146:f64d43ff0c18 | 204 | { |
mbed_official | 146:f64d43ff0c18 | 205 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 206 | struct _hw_rtc_tar_bitfields |
mbed_official | 146:f64d43ff0c18 | 207 | { |
mbed_official | 146:f64d43ff0c18 | 208 | uint32_t TAR : 32; //!< [31:0] Time Alarm Register |
mbed_official | 146:f64d43ff0c18 | 209 | } B; |
mbed_official | 146:f64d43ff0c18 | 210 | } hw_rtc_tar_t; |
mbed_official | 146:f64d43ff0c18 | 211 | #endif |
mbed_official | 146:f64d43ff0c18 | 212 | |
mbed_official | 146:f64d43ff0c18 | 213 | /*! |
mbed_official | 146:f64d43ff0c18 | 214 | * @name Constants and macros for entire RTC_TAR register |
mbed_official | 146:f64d43ff0c18 | 215 | */ |
mbed_official | 146:f64d43ff0c18 | 216 | //@{ |
mbed_official | 146:f64d43ff0c18 | 217 | #define HW_RTC_TAR_ADDR (REGS_RTC_BASE + 0x8U) |
mbed_official | 146:f64d43ff0c18 | 218 | |
mbed_official | 146:f64d43ff0c18 | 219 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 220 | #define HW_RTC_TAR (*(__IO hw_rtc_tar_t *) HW_RTC_TAR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 221 | #define HW_RTC_TAR_RD() (HW_RTC_TAR.U) |
mbed_official | 146:f64d43ff0c18 | 222 | #define HW_RTC_TAR_WR(v) (HW_RTC_TAR.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 223 | #define HW_RTC_TAR_SET(v) (HW_RTC_TAR_WR(HW_RTC_TAR_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 224 | #define HW_RTC_TAR_CLR(v) (HW_RTC_TAR_WR(HW_RTC_TAR_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 225 | #define HW_RTC_TAR_TOG(v) (HW_RTC_TAR_WR(HW_RTC_TAR_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 226 | #endif |
mbed_official | 146:f64d43ff0c18 | 227 | //@} |
mbed_official | 146:f64d43ff0c18 | 228 | |
mbed_official | 146:f64d43ff0c18 | 229 | /* |
mbed_official | 146:f64d43ff0c18 | 230 | * Constants & macros for individual RTC_TAR bitfields |
mbed_official | 146:f64d43ff0c18 | 231 | */ |
mbed_official | 146:f64d43ff0c18 | 232 | |
mbed_official | 146:f64d43ff0c18 | 233 | /*! |
mbed_official | 146:f64d43ff0c18 | 234 | * @name Register RTC_TAR, field TAR[31:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 235 | * |
mbed_official | 146:f64d43ff0c18 | 236 | * When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR] |
mbed_official | 146:f64d43ff0c18 | 237 | * equals the TSR[TSR] and the TSR[TSR] increments. Writing to the TAR clears the |
mbed_official | 146:f64d43ff0c18 | 238 | * SR[TAF]. |
mbed_official | 146:f64d43ff0c18 | 239 | */ |
mbed_official | 146:f64d43ff0c18 | 240 | //@{ |
mbed_official | 146:f64d43ff0c18 | 241 | #define BP_RTC_TAR_TAR (0U) //!< Bit position for RTC_TAR_TAR. |
mbed_official | 146:f64d43ff0c18 | 242 | #define BM_RTC_TAR_TAR (0xFFFFFFFFU) //!< Bit mask for RTC_TAR_TAR. |
mbed_official | 146:f64d43ff0c18 | 243 | #define BS_RTC_TAR_TAR (32U) //!< Bit field size in bits for RTC_TAR_TAR. |
mbed_official | 146:f64d43ff0c18 | 244 | |
mbed_official | 146:f64d43ff0c18 | 245 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 246 | //! @brief Read current value of the RTC_TAR_TAR field. |
mbed_official | 146:f64d43ff0c18 | 247 | #define BR_RTC_TAR_TAR (HW_RTC_TAR.U) |
mbed_official | 146:f64d43ff0c18 | 248 | #endif |
mbed_official | 146:f64d43ff0c18 | 249 | |
mbed_official | 146:f64d43ff0c18 | 250 | //! @brief Format value for bitfield RTC_TAR_TAR. |
mbed_official | 146:f64d43ff0c18 | 251 | #define BF_RTC_TAR_TAR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TAR_TAR), uint32_t) & BM_RTC_TAR_TAR) |
mbed_official | 146:f64d43ff0c18 | 252 | |
mbed_official | 146:f64d43ff0c18 | 253 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 254 | //! @brief Set the TAR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 255 | #define BW_RTC_TAR_TAR(v) (HW_RTC_TAR_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 256 | #endif |
mbed_official | 146:f64d43ff0c18 | 257 | //@} |
mbed_official | 146:f64d43ff0c18 | 258 | |
mbed_official | 146:f64d43ff0c18 | 259 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 260 | // HW_RTC_TCR - RTC Time Compensation Register |
mbed_official | 146:f64d43ff0c18 | 261 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 262 | |
mbed_official | 146:f64d43ff0c18 | 263 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 264 | /*! |
mbed_official | 146:f64d43ff0c18 | 265 | * @brief HW_RTC_TCR - RTC Time Compensation Register (RW) |
mbed_official | 146:f64d43ff0c18 | 266 | * |
mbed_official | 146:f64d43ff0c18 | 267 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 268 | */ |
mbed_official | 146:f64d43ff0c18 | 269 | typedef union _hw_rtc_tcr |
mbed_official | 146:f64d43ff0c18 | 270 | { |
mbed_official | 146:f64d43ff0c18 | 271 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 272 | struct _hw_rtc_tcr_bitfields |
mbed_official | 146:f64d43ff0c18 | 273 | { |
mbed_official | 146:f64d43ff0c18 | 274 | uint32_t TCR : 8; //!< [7:0] Time Compensation Register |
mbed_official | 146:f64d43ff0c18 | 275 | uint32_t CIR : 8; //!< [15:8] Compensation Interval Register |
mbed_official | 146:f64d43ff0c18 | 276 | uint32_t TCV : 8; //!< [23:16] Time Compensation Value |
mbed_official | 146:f64d43ff0c18 | 277 | uint32_t CIC : 8; //!< [31:24] Compensation Interval Counter |
mbed_official | 146:f64d43ff0c18 | 278 | } B; |
mbed_official | 146:f64d43ff0c18 | 279 | } hw_rtc_tcr_t; |
mbed_official | 146:f64d43ff0c18 | 280 | #endif |
mbed_official | 146:f64d43ff0c18 | 281 | |
mbed_official | 146:f64d43ff0c18 | 282 | /*! |
mbed_official | 146:f64d43ff0c18 | 283 | * @name Constants and macros for entire RTC_TCR register |
mbed_official | 146:f64d43ff0c18 | 284 | */ |
mbed_official | 146:f64d43ff0c18 | 285 | //@{ |
mbed_official | 146:f64d43ff0c18 | 286 | #define HW_RTC_TCR_ADDR (REGS_RTC_BASE + 0xCU) |
mbed_official | 146:f64d43ff0c18 | 287 | |
mbed_official | 146:f64d43ff0c18 | 288 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 289 | #define HW_RTC_TCR (*(__IO hw_rtc_tcr_t *) HW_RTC_TCR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 290 | #define HW_RTC_TCR_RD() (HW_RTC_TCR.U) |
mbed_official | 146:f64d43ff0c18 | 291 | #define HW_RTC_TCR_WR(v) (HW_RTC_TCR.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 292 | #define HW_RTC_TCR_SET(v) (HW_RTC_TCR_WR(HW_RTC_TCR_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 293 | #define HW_RTC_TCR_CLR(v) (HW_RTC_TCR_WR(HW_RTC_TCR_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 294 | #define HW_RTC_TCR_TOG(v) (HW_RTC_TCR_WR(HW_RTC_TCR_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 295 | #endif |
mbed_official | 146:f64d43ff0c18 | 296 | //@} |
mbed_official | 146:f64d43ff0c18 | 297 | |
mbed_official | 146:f64d43ff0c18 | 298 | /* |
mbed_official | 146:f64d43ff0c18 | 299 | * Constants & macros for individual RTC_TCR bitfields |
mbed_official | 146:f64d43ff0c18 | 300 | */ |
mbed_official | 146:f64d43ff0c18 | 301 | |
mbed_official | 146:f64d43ff0c18 | 302 | /*! |
mbed_official | 146:f64d43ff0c18 | 303 | * @name Register RTC_TCR, field TCR[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 304 | * |
mbed_official | 146:f64d43ff0c18 | 305 | * Configures the number of 32.768 kHz clock cycles in each second. This |
mbed_official | 146:f64d43ff0c18 | 306 | * register is double buffered and writes do not take affect until the end of the |
mbed_official | 146:f64d43ff0c18 | 307 | * current compensation interval. |
mbed_official | 146:f64d43ff0c18 | 308 | * |
mbed_official | 146:f64d43ff0c18 | 309 | * Values: |
mbed_official | 146:f64d43ff0c18 | 310 | * - 10000000 - Time Prescaler Register overflows every 32896 clock cycles. |
mbed_official | 146:f64d43ff0c18 | 311 | * - 11111111 - Time Prescaler Register overflows every 32769 clock cycles. |
mbed_official | 146:f64d43ff0c18 | 312 | * - 0 - Time Prescaler Register overflows every 32768 clock cycles. |
mbed_official | 146:f64d43ff0c18 | 313 | * - 1 - Time Prescaler Register overflows every 32767 clock cycles. |
mbed_official | 146:f64d43ff0c18 | 314 | * - 1111111 - Time Prescaler Register overflows every 32641 clock cycles. |
mbed_official | 146:f64d43ff0c18 | 315 | */ |
mbed_official | 146:f64d43ff0c18 | 316 | //@{ |
mbed_official | 146:f64d43ff0c18 | 317 | #define BP_RTC_TCR_TCR (0U) //!< Bit position for RTC_TCR_TCR. |
mbed_official | 146:f64d43ff0c18 | 318 | #define BM_RTC_TCR_TCR (0x000000FFU) //!< Bit mask for RTC_TCR_TCR. |
mbed_official | 146:f64d43ff0c18 | 319 | #define BS_RTC_TCR_TCR (8U) //!< Bit field size in bits for RTC_TCR_TCR. |
mbed_official | 146:f64d43ff0c18 | 320 | |
mbed_official | 146:f64d43ff0c18 | 321 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 322 | //! @brief Read current value of the RTC_TCR_TCR field. |
mbed_official | 146:f64d43ff0c18 | 323 | #define BR_RTC_TCR_TCR (HW_RTC_TCR.B.TCR) |
mbed_official | 146:f64d43ff0c18 | 324 | #endif |
mbed_official | 146:f64d43ff0c18 | 325 | |
mbed_official | 146:f64d43ff0c18 | 326 | //! @brief Format value for bitfield RTC_TCR_TCR. |
mbed_official | 146:f64d43ff0c18 | 327 | #define BF_RTC_TCR_TCR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TCR_TCR), uint32_t) & BM_RTC_TCR_TCR) |
mbed_official | 146:f64d43ff0c18 | 328 | |
mbed_official | 146:f64d43ff0c18 | 329 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 330 | //! @brief Set the TCR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 331 | #define BW_RTC_TCR_TCR(v) (HW_RTC_TCR_WR((HW_RTC_TCR_RD() & ~BM_RTC_TCR_TCR) | BF_RTC_TCR_TCR(v))) |
mbed_official | 146:f64d43ff0c18 | 332 | #endif |
mbed_official | 146:f64d43ff0c18 | 333 | //@} |
mbed_official | 146:f64d43ff0c18 | 334 | |
mbed_official | 146:f64d43ff0c18 | 335 | /*! |
mbed_official | 146:f64d43ff0c18 | 336 | * @name Register RTC_TCR, field CIR[15:8] (RW) |
mbed_official | 146:f64d43ff0c18 | 337 | * |
mbed_official | 146:f64d43ff0c18 | 338 | * Configures the compensation interval in seconds from 1 to 256 to control how |
mbed_official | 146:f64d43ff0c18 | 339 | * frequently the TCR should adjust the number of 32.768 kHz cycles in each |
mbed_official | 146:f64d43ff0c18 | 340 | * second. The value written should be one less than the number of seconds. For |
mbed_official | 146:f64d43ff0c18 | 341 | * example, write zero to configure for a compensation interval of one second. This |
mbed_official | 146:f64d43ff0c18 | 342 | * register is double buffered and writes do not take affect until the end of the |
mbed_official | 146:f64d43ff0c18 | 343 | * current compensation interval. |
mbed_official | 146:f64d43ff0c18 | 344 | */ |
mbed_official | 146:f64d43ff0c18 | 345 | //@{ |
mbed_official | 146:f64d43ff0c18 | 346 | #define BP_RTC_TCR_CIR (8U) //!< Bit position for RTC_TCR_CIR. |
mbed_official | 146:f64d43ff0c18 | 347 | #define BM_RTC_TCR_CIR (0x0000FF00U) //!< Bit mask for RTC_TCR_CIR. |
mbed_official | 146:f64d43ff0c18 | 348 | #define BS_RTC_TCR_CIR (8U) //!< Bit field size in bits for RTC_TCR_CIR. |
mbed_official | 146:f64d43ff0c18 | 349 | |
mbed_official | 146:f64d43ff0c18 | 350 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 351 | //! @brief Read current value of the RTC_TCR_CIR field. |
mbed_official | 146:f64d43ff0c18 | 352 | #define BR_RTC_TCR_CIR (HW_RTC_TCR.B.CIR) |
mbed_official | 146:f64d43ff0c18 | 353 | #endif |
mbed_official | 146:f64d43ff0c18 | 354 | |
mbed_official | 146:f64d43ff0c18 | 355 | //! @brief Format value for bitfield RTC_TCR_CIR. |
mbed_official | 146:f64d43ff0c18 | 356 | #define BF_RTC_TCR_CIR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TCR_CIR), uint32_t) & BM_RTC_TCR_CIR) |
mbed_official | 146:f64d43ff0c18 | 357 | |
mbed_official | 146:f64d43ff0c18 | 358 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 359 | //! @brief Set the CIR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 360 | #define BW_RTC_TCR_CIR(v) (HW_RTC_TCR_WR((HW_RTC_TCR_RD() & ~BM_RTC_TCR_CIR) | BF_RTC_TCR_CIR(v))) |
mbed_official | 146:f64d43ff0c18 | 361 | #endif |
mbed_official | 146:f64d43ff0c18 | 362 | //@} |
mbed_official | 146:f64d43ff0c18 | 363 | |
mbed_official | 146:f64d43ff0c18 | 364 | /*! |
mbed_official | 146:f64d43ff0c18 | 365 | * @name Register RTC_TCR, field TCV[23:16] (RO) |
mbed_official | 146:f64d43ff0c18 | 366 | * |
mbed_official | 146:f64d43ff0c18 | 367 | * Current value used by the compensation logic for the present second interval. |
mbed_official | 146:f64d43ff0c18 | 368 | * Updated once a second if the CIC equals 0 with the contents of the TCR field. |
mbed_official | 146:f64d43ff0c18 | 369 | * If the CIC does not equal zero then it is loaded with zero (compensation is |
mbed_official | 146:f64d43ff0c18 | 370 | * not enabled for that second increment). |
mbed_official | 146:f64d43ff0c18 | 371 | */ |
mbed_official | 146:f64d43ff0c18 | 372 | //@{ |
mbed_official | 146:f64d43ff0c18 | 373 | #define BP_RTC_TCR_TCV (16U) //!< Bit position for RTC_TCR_TCV. |
mbed_official | 146:f64d43ff0c18 | 374 | #define BM_RTC_TCR_TCV (0x00FF0000U) //!< Bit mask for RTC_TCR_TCV. |
mbed_official | 146:f64d43ff0c18 | 375 | #define BS_RTC_TCR_TCV (8U) //!< Bit field size in bits for RTC_TCR_TCV. |
mbed_official | 146:f64d43ff0c18 | 376 | |
mbed_official | 146:f64d43ff0c18 | 377 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 378 | //! @brief Read current value of the RTC_TCR_TCV field. |
mbed_official | 146:f64d43ff0c18 | 379 | #define BR_RTC_TCR_TCV (HW_RTC_TCR.B.TCV) |
mbed_official | 146:f64d43ff0c18 | 380 | #endif |
mbed_official | 146:f64d43ff0c18 | 381 | //@} |
mbed_official | 146:f64d43ff0c18 | 382 | |
mbed_official | 146:f64d43ff0c18 | 383 | /*! |
mbed_official | 146:f64d43ff0c18 | 384 | * @name Register RTC_TCR, field CIC[31:24] (RO) |
mbed_official | 146:f64d43ff0c18 | 385 | * |
mbed_official | 146:f64d43ff0c18 | 386 | * Current value of the compensation interval counter. If the compensation |
mbed_official | 146:f64d43ff0c18 | 387 | * interval counter equals zero then it is loaded with the contents of the CIR. If the |
mbed_official | 146:f64d43ff0c18 | 388 | * CIC does not equal zero then it is decremented once a second. |
mbed_official | 146:f64d43ff0c18 | 389 | */ |
mbed_official | 146:f64d43ff0c18 | 390 | //@{ |
mbed_official | 146:f64d43ff0c18 | 391 | #define BP_RTC_TCR_CIC (24U) //!< Bit position for RTC_TCR_CIC. |
mbed_official | 146:f64d43ff0c18 | 392 | #define BM_RTC_TCR_CIC (0xFF000000U) //!< Bit mask for RTC_TCR_CIC. |
mbed_official | 146:f64d43ff0c18 | 393 | #define BS_RTC_TCR_CIC (8U) //!< Bit field size in bits for RTC_TCR_CIC. |
mbed_official | 146:f64d43ff0c18 | 394 | |
mbed_official | 146:f64d43ff0c18 | 395 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 396 | //! @brief Read current value of the RTC_TCR_CIC field. |
mbed_official | 146:f64d43ff0c18 | 397 | #define BR_RTC_TCR_CIC (HW_RTC_TCR.B.CIC) |
mbed_official | 146:f64d43ff0c18 | 398 | #endif |
mbed_official | 146:f64d43ff0c18 | 399 | //@} |
mbed_official | 146:f64d43ff0c18 | 400 | |
mbed_official | 146:f64d43ff0c18 | 401 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 402 | // HW_RTC_CR - RTC Control Register |
mbed_official | 146:f64d43ff0c18 | 403 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 404 | |
mbed_official | 146:f64d43ff0c18 | 405 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 406 | /*! |
mbed_official | 146:f64d43ff0c18 | 407 | * @brief HW_RTC_CR - RTC Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 408 | * |
mbed_official | 146:f64d43ff0c18 | 409 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 410 | */ |
mbed_official | 146:f64d43ff0c18 | 411 | typedef union _hw_rtc_cr |
mbed_official | 146:f64d43ff0c18 | 412 | { |
mbed_official | 146:f64d43ff0c18 | 413 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 414 | struct _hw_rtc_cr_bitfields |
mbed_official | 146:f64d43ff0c18 | 415 | { |
mbed_official | 146:f64d43ff0c18 | 416 | uint32_t SWR : 1; //!< [0] Software Reset |
mbed_official | 146:f64d43ff0c18 | 417 | uint32_t WPE : 1; //!< [1] Wakeup Pin Enable |
mbed_official | 146:f64d43ff0c18 | 418 | uint32_t SUP : 1; //!< [2] Supervisor Access |
mbed_official | 146:f64d43ff0c18 | 419 | uint32_t UM : 1; //!< [3] Update Mode |
mbed_official | 146:f64d43ff0c18 | 420 | uint32_t WPS : 1; //!< [4] Wakeup Pin Select |
mbed_official | 146:f64d43ff0c18 | 421 | uint32_t RESERVED0 : 3; //!< [7:5] |
mbed_official | 146:f64d43ff0c18 | 422 | uint32_t OSCE : 1; //!< [8] Oscillator Enable |
mbed_official | 146:f64d43ff0c18 | 423 | uint32_t CLKO : 1; //!< [9] Clock Output |
mbed_official | 146:f64d43ff0c18 | 424 | uint32_t SC16P : 1; //!< [10] Oscillator 16pF Load Configure |
mbed_official | 146:f64d43ff0c18 | 425 | uint32_t SC8P : 1; //!< [11] Oscillator 8pF Load Configure |
mbed_official | 146:f64d43ff0c18 | 426 | uint32_t SC4P : 1; //!< [12] Oscillator 4pF Load Configure |
mbed_official | 146:f64d43ff0c18 | 427 | uint32_t SC2P : 1; //!< [13] Oscillator 2pF Load Configure |
mbed_official | 146:f64d43ff0c18 | 428 | uint32_t RESERVED1 : 18; //!< [31:14] |
mbed_official | 146:f64d43ff0c18 | 429 | } B; |
mbed_official | 146:f64d43ff0c18 | 430 | } hw_rtc_cr_t; |
mbed_official | 146:f64d43ff0c18 | 431 | #endif |
mbed_official | 146:f64d43ff0c18 | 432 | |
mbed_official | 146:f64d43ff0c18 | 433 | /*! |
mbed_official | 146:f64d43ff0c18 | 434 | * @name Constants and macros for entire RTC_CR register |
mbed_official | 146:f64d43ff0c18 | 435 | */ |
mbed_official | 146:f64d43ff0c18 | 436 | //@{ |
mbed_official | 146:f64d43ff0c18 | 437 | #define HW_RTC_CR_ADDR (REGS_RTC_BASE + 0x10U) |
mbed_official | 146:f64d43ff0c18 | 438 | |
mbed_official | 146:f64d43ff0c18 | 439 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 440 | #define HW_RTC_CR (*(__IO hw_rtc_cr_t *) HW_RTC_CR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 441 | #define HW_RTC_CR_RD() (HW_RTC_CR.U) |
mbed_official | 146:f64d43ff0c18 | 442 | #define HW_RTC_CR_WR(v) (HW_RTC_CR.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 443 | #define HW_RTC_CR_SET(v) (HW_RTC_CR_WR(HW_RTC_CR_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 444 | #define HW_RTC_CR_CLR(v) (HW_RTC_CR_WR(HW_RTC_CR_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 445 | #define HW_RTC_CR_TOG(v) (HW_RTC_CR_WR(HW_RTC_CR_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 446 | #endif |
mbed_official | 146:f64d43ff0c18 | 447 | //@} |
mbed_official | 146:f64d43ff0c18 | 448 | |
mbed_official | 146:f64d43ff0c18 | 449 | /* |
mbed_official | 146:f64d43ff0c18 | 450 | * Constants & macros for individual RTC_CR bitfields |
mbed_official | 146:f64d43ff0c18 | 451 | */ |
mbed_official | 146:f64d43ff0c18 | 452 | |
mbed_official | 146:f64d43ff0c18 | 453 | /*! |
mbed_official | 146:f64d43ff0c18 | 454 | * @name Register RTC_CR, field SWR[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 455 | * |
mbed_official | 146:f64d43ff0c18 | 456 | * Values: |
mbed_official | 146:f64d43ff0c18 | 457 | * - 0 - No effect. |
mbed_official | 146:f64d43ff0c18 | 458 | * - 1 - Resets all RTC registers except for the SWR bit and the RTC_WAR and |
mbed_official | 146:f64d43ff0c18 | 459 | * RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software |
mbed_official | 146:f64d43ff0c18 | 460 | * explicitly clearing it. |
mbed_official | 146:f64d43ff0c18 | 461 | */ |
mbed_official | 146:f64d43ff0c18 | 462 | //@{ |
mbed_official | 146:f64d43ff0c18 | 463 | #define BP_RTC_CR_SWR (0U) //!< Bit position for RTC_CR_SWR. |
mbed_official | 146:f64d43ff0c18 | 464 | #define BM_RTC_CR_SWR (0x00000001U) //!< Bit mask for RTC_CR_SWR. |
mbed_official | 146:f64d43ff0c18 | 465 | #define BS_RTC_CR_SWR (1U) //!< Bit field size in bits for RTC_CR_SWR. |
mbed_official | 146:f64d43ff0c18 | 466 | |
mbed_official | 146:f64d43ff0c18 | 467 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 468 | //! @brief Read current value of the RTC_CR_SWR field. |
mbed_official | 146:f64d43ff0c18 | 469 | #define BR_RTC_CR_SWR (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SWR)) |
mbed_official | 146:f64d43ff0c18 | 470 | #endif |
mbed_official | 146:f64d43ff0c18 | 471 | |
mbed_official | 146:f64d43ff0c18 | 472 | //! @brief Format value for bitfield RTC_CR_SWR. |
mbed_official | 146:f64d43ff0c18 | 473 | #define BF_RTC_CR_SWR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SWR), uint32_t) & BM_RTC_CR_SWR) |
mbed_official | 146:f64d43ff0c18 | 474 | |
mbed_official | 146:f64d43ff0c18 | 475 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 476 | //! @brief Set the SWR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 477 | #define BW_RTC_CR_SWR(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SWR) = (v)) |
mbed_official | 146:f64d43ff0c18 | 478 | #endif |
mbed_official | 146:f64d43ff0c18 | 479 | //@} |
mbed_official | 146:f64d43ff0c18 | 480 | |
mbed_official | 146:f64d43ff0c18 | 481 | /*! |
mbed_official | 146:f64d43ff0c18 | 482 | * @name Register RTC_CR, field WPE[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 483 | * |
mbed_official | 146:f64d43ff0c18 | 484 | * The wakeup pin is optional and not available on all devices. |
mbed_official | 146:f64d43ff0c18 | 485 | * |
mbed_official | 146:f64d43ff0c18 | 486 | * Values: |
mbed_official | 146:f64d43ff0c18 | 487 | * - 0 - Wakeup pin is disabled. |
mbed_official | 146:f64d43ff0c18 | 488 | * - 1 - Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt |
mbed_official | 146:f64d43ff0c18 | 489 | * asserts or the wakeup pin is turned on. |
mbed_official | 146:f64d43ff0c18 | 490 | */ |
mbed_official | 146:f64d43ff0c18 | 491 | //@{ |
mbed_official | 146:f64d43ff0c18 | 492 | #define BP_RTC_CR_WPE (1U) //!< Bit position for RTC_CR_WPE. |
mbed_official | 146:f64d43ff0c18 | 493 | #define BM_RTC_CR_WPE (0x00000002U) //!< Bit mask for RTC_CR_WPE. |
mbed_official | 146:f64d43ff0c18 | 494 | #define BS_RTC_CR_WPE (1U) //!< Bit field size in bits for RTC_CR_WPE. |
mbed_official | 146:f64d43ff0c18 | 495 | |
mbed_official | 146:f64d43ff0c18 | 496 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 497 | //! @brief Read current value of the RTC_CR_WPE field. |
mbed_official | 146:f64d43ff0c18 | 498 | #define BR_RTC_CR_WPE (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_WPE)) |
mbed_official | 146:f64d43ff0c18 | 499 | #endif |
mbed_official | 146:f64d43ff0c18 | 500 | |
mbed_official | 146:f64d43ff0c18 | 501 | //! @brief Format value for bitfield RTC_CR_WPE. |
mbed_official | 146:f64d43ff0c18 | 502 | #define BF_RTC_CR_WPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_WPE), uint32_t) & BM_RTC_CR_WPE) |
mbed_official | 146:f64d43ff0c18 | 503 | |
mbed_official | 146:f64d43ff0c18 | 504 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 505 | //! @brief Set the WPE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 506 | #define BW_RTC_CR_WPE(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_WPE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 507 | #endif |
mbed_official | 146:f64d43ff0c18 | 508 | //@} |
mbed_official | 146:f64d43ff0c18 | 509 | |
mbed_official | 146:f64d43ff0c18 | 510 | /*! |
mbed_official | 146:f64d43ff0c18 | 511 | * @name Register RTC_CR, field SUP[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 512 | * |
mbed_official | 146:f64d43ff0c18 | 513 | * Values: |
mbed_official | 146:f64d43ff0c18 | 514 | * - 0 - Non-supervisor mode write accesses are not supported and generate a bus |
mbed_official | 146:f64d43ff0c18 | 515 | * error. |
mbed_official | 146:f64d43ff0c18 | 516 | * - 1 - Non-supervisor mode write accesses are supported. |
mbed_official | 146:f64d43ff0c18 | 517 | */ |
mbed_official | 146:f64d43ff0c18 | 518 | //@{ |
mbed_official | 146:f64d43ff0c18 | 519 | #define BP_RTC_CR_SUP (2U) //!< Bit position for RTC_CR_SUP. |
mbed_official | 146:f64d43ff0c18 | 520 | #define BM_RTC_CR_SUP (0x00000004U) //!< Bit mask for RTC_CR_SUP. |
mbed_official | 146:f64d43ff0c18 | 521 | #define BS_RTC_CR_SUP (1U) //!< Bit field size in bits for RTC_CR_SUP. |
mbed_official | 146:f64d43ff0c18 | 522 | |
mbed_official | 146:f64d43ff0c18 | 523 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 524 | //! @brief Read current value of the RTC_CR_SUP field. |
mbed_official | 146:f64d43ff0c18 | 525 | #define BR_RTC_CR_SUP (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SUP)) |
mbed_official | 146:f64d43ff0c18 | 526 | #endif |
mbed_official | 146:f64d43ff0c18 | 527 | |
mbed_official | 146:f64d43ff0c18 | 528 | //! @brief Format value for bitfield RTC_CR_SUP. |
mbed_official | 146:f64d43ff0c18 | 529 | #define BF_RTC_CR_SUP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SUP), uint32_t) & BM_RTC_CR_SUP) |
mbed_official | 146:f64d43ff0c18 | 530 | |
mbed_official | 146:f64d43ff0c18 | 531 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 532 | //! @brief Set the SUP field to a new value. |
mbed_official | 146:f64d43ff0c18 | 533 | #define BW_RTC_CR_SUP(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SUP) = (v)) |
mbed_official | 146:f64d43ff0c18 | 534 | #endif |
mbed_official | 146:f64d43ff0c18 | 535 | //@} |
mbed_official | 146:f64d43ff0c18 | 536 | |
mbed_official | 146:f64d43ff0c18 | 537 | /*! |
mbed_official | 146:f64d43ff0c18 | 538 | * @name Register RTC_CR, field UM[3] (RW) |
mbed_official | 146:f64d43ff0c18 | 539 | * |
mbed_official | 146:f64d43ff0c18 | 540 | * Allows SR[TCE] to be written even when the Status Register is locked. When |
mbed_official | 146:f64d43ff0c18 | 541 | * set, the SR[TCE] can always be written if the SR[TIF] or SR[TOF] are set or if |
mbed_official | 146:f64d43ff0c18 | 542 | * the SR[TCE] is clear. |
mbed_official | 146:f64d43ff0c18 | 543 | * |
mbed_official | 146:f64d43ff0c18 | 544 | * Values: |
mbed_official | 146:f64d43ff0c18 | 545 | * - 0 - Registers cannot be written when locked. |
mbed_official | 146:f64d43ff0c18 | 546 | * - 1 - Registers can be written when locked under limited conditions. |
mbed_official | 146:f64d43ff0c18 | 547 | */ |
mbed_official | 146:f64d43ff0c18 | 548 | //@{ |
mbed_official | 146:f64d43ff0c18 | 549 | #define BP_RTC_CR_UM (3U) //!< Bit position for RTC_CR_UM. |
mbed_official | 146:f64d43ff0c18 | 550 | #define BM_RTC_CR_UM (0x00000008U) //!< Bit mask for RTC_CR_UM. |
mbed_official | 146:f64d43ff0c18 | 551 | #define BS_RTC_CR_UM (1U) //!< Bit field size in bits for RTC_CR_UM. |
mbed_official | 146:f64d43ff0c18 | 552 | |
mbed_official | 146:f64d43ff0c18 | 553 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 554 | //! @brief Read current value of the RTC_CR_UM field. |
mbed_official | 146:f64d43ff0c18 | 555 | #define BR_RTC_CR_UM (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_UM)) |
mbed_official | 146:f64d43ff0c18 | 556 | #endif |
mbed_official | 146:f64d43ff0c18 | 557 | |
mbed_official | 146:f64d43ff0c18 | 558 | //! @brief Format value for bitfield RTC_CR_UM. |
mbed_official | 146:f64d43ff0c18 | 559 | #define BF_RTC_CR_UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_UM), uint32_t) & BM_RTC_CR_UM) |
mbed_official | 146:f64d43ff0c18 | 560 | |
mbed_official | 146:f64d43ff0c18 | 561 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 562 | //! @brief Set the UM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 563 | #define BW_RTC_CR_UM(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_UM) = (v)) |
mbed_official | 146:f64d43ff0c18 | 564 | #endif |
mbed_official | 146:f64d43ff0c18 | 565 | //@} |
mbed_official | 146:f64d43ff0c18 | 566 | |
mbed_official | 146:f64d43ff0c18 | 567 | /*! |
mbed_official | 146:f64d43ff0c18 | 568 | * @name Register RTC_CR, field WPS[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 569 | * |
mbed_official | 146:f64d43ff0c18 | 570 | * The wakeup pin is optional and not available on all devices. |
mbed_official | 146:f64d43ff0c18 | 571 | * |
mbed_official | 146:f64d43ff0c18 | 572 | * Values: |
mbed_official | 146:f64d43ff0c18 | 573 | * - 0 - Wakeup pin asserts (active low, open drain) if the RTC interrupt |
mbed_official | 146:f64d43ff0c18 | 574 | * asserts or the wakeup pin is turned on. |
mbed_official | 146:f64d43ff0c18 | 575 | * - 1 - Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin |
mbed_official | 146:f64d43ff0c18 | 576 | * is turned on and the 32kHz clock is output to other peripherals. |
mbed_official | 146:f64d43ff0c18 | 577 | */ |
mbed_official | 146:f64d43ff0c18 | 578 | //@{ |
mbed_official | 146:f64d43ff0c18 | 579 | #define BP_RTC_CR_WPS (4U) //!< Bit position for RTC_CR_WPS. |
mbed_official | 146:f64d43ff0c18 | 580 | #define BM_RTC_CR_WPS (0x00000010U) //!< Bit mask for RTC_CR_WPS. |
mbed_official | 146:f64d43ff0c18 | 581 | #define BS_RTC_CR_WPS (1U) //!< Bit field size in bits for RTC_CR_WPS. |
mbed_official | 146:f64d43ff0c18 | 582 | |
mbed_official | 146:f64d43ff0c18 | 583 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 584 | //! @brief Read current value of the RTC_CR_WPS field. |
mbed_official | 146:f64d43ff0c18 | 585 | #define BR_RTC_CR_WPS (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_WPS)) |
mbed_official | 146:f64d43ff0c18 | 586 | #endif |
mbed_official | 146:f64d43ff0c18 | 587 | |
mbed_official | 146:f64d43ff0c18 | 588 | //! @brief Format value for bitfield RTC_CR_WPS. |
mbed_official | 146:f64d43ff0c18 | 589 | #define BF_RTC_CR_WPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_WPS), uint32_t) & BM_RTC_CR_WPS) |
mbed_official | 146:f64d43ff0c18 | 590 | |
mbed_official | 146:f64d43ff0c18 | 591 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 592 | //! @brief Set the WPS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 593 | #define BW_RTC_CR_WPS(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_WPS) = (v)) |
mbed_official | 146:f64d43ff0c18 | 594 | #endif |
mbed_official | 146:f64d43ff0c18 | 595 | //@} |
mbed_official | 146:f64d43ff0c18 | 596 | |
mbed_official | 146:f64d43ff0c18 | 597 | /*! |
mbed_official | 146:f64d43ff0c18 | 598 | * @name Register RTC_CR, field OSCE[8] (RW) |
mbed_official | 146:f64d43ff0c18 | 599 | * |
mbed_official | 146:f64d43ff0c18 | 600 | * Values: |
mbed_official | 146:f64d43ff0c18 | 601 | * - 0 - 32.768 kHz oscillator is disabled. |
mbed_official | 146:f64d43ff0c18 | 602 | * - 1 - 32.768 kHz oscillator is enabled. After setting this bit, wait the |
mbed_official | 146:f64d43ff0c18 | 603 | * oscillator startup time before enabling the time counter to allow the 32.768 |
mbed_official | 146:f64d43ff0c18 | 604 | * kHz clock time to stabilize. |
mbed_official | 146:f64d43ff0c18 | 605 | */ |
mbed_official | 146:f64d43ff0c18 | 606 | //@{ |
mbed_official | 146:f64d43ff0c18 | 607 | #define BP_RTC_CR_OSCE (8U) //!< Bit position for RTC_CR_OSCE. |
mbed_official | 146:f64d43ff0c18 | 608 | #define BM_RTC_CR_OSCE (0x00000100U) //!< Bit mask for RTC_CR_OSCE. |
mbed_official | 146:f64d43ff0c18 | 609 | #define BS_RTC_CR_OSCE (1U) //!< Bit field size in bits for RTC_CR_OSCE. |
mbed_official | 146:f64d43ff0c18 | 610 | |
mbed_official | 146:f64d43ff0c18 | 611 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 612 | //! @brief Read current value of the RTC_CR_OSCE field. |
mbed_official | 146:f64d43ff0c18 | 613 | #define BR_RTC_CR_OSCE (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_OSCE)) |
mbed_official | 146:f64d43ff0c18 | 614 | #endif |
mbed_official | 146:f64d43ff0c18 | 615 | |
mbed_official | 146:f64d43ff0c18 | 616 | //! @brief Format value for bitfield RTC_CR_OSCE. |
mbed_official | 146:f64d43ff0c18 | 617 | #define BF_RTC_CR_OSCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_OSCE), uint32_t) & BM_RTC_CR_OSCE) |
mbed_official | 146:f64d43ff0c18 | 618 | |
mbed_official | 146:f64d43ff0c18 | 619 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 620 | //! @brief Set the OSCE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 621 | #define BW_RTC_CR_OSCE(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_OSCE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 622 | #endif |
mbed_official | 146:f64d43ff0c18 | 623 | //@} |
mbed_official | 146:f64d43ff0c18 | 624 | |
mbed_official | 146:f64d43ff0c18 | 625 | /*! |
mbed_official | 146:f64d43ff0c18 | 626 | * @name Register RTC_CR, field CLKO[9] (RW) |
mbed_official | 146:f64d43ff0c18 | 627 | * |
mbed_official | 146:f64d43ff0c18 | 628 | * Values: |
mbed_official | 146:f64d43ff0c18 | 629 | * - 0 - The 32 kHz clock is output to other peripherals. |
mbed_official | 146:f64d43ff0c18 | 630 | * - 1 - The 32 kHz clock is not output to other peripherals. |
mbed_official | 146:f64d43ff0c18 | 631 | */ |
mbed_official | 146:f64d43ff0c18 | 632 | //@{ |
mbed_official | 146:f64d43ff0c18 | 633 | #define BP_RTC_CR_CLKO (9U) //!< Bit position for RTC_CR_CLKO. |
mbed_official | 146:f64d43ff0c18 | 634 | #define BM_RTC_CR_CLKO (0x00000200U) //!< Bit mask for RTC_CR_CLKO. |
mbed_official | 146:f64d43ff0c18 | 635 | #define BS_RTC_CR_CLKO (1U) //!< Bit field size in bits for RTC_CR_CLKO. |
mbed_official | 146:f64d43ff0c18 | 636 | |
mbed_official | 146:f64d43ff0c18 | 637 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 638 | //! @brief Read current value of the RTC_CR_CLKO field. |
mbed_official | 146:f64d43ff0c18 | 639 | #define BR_RTC_CR_CLKO (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_CLKO)) |
mbed_official | 146:f64d43ff0c18 | 640 | #endif |
mbed_official | 146:f64d43ff0c18 | 641 | |
mbed_official | 146:f64d43ff0c18 | 642 | //! @brief Format value for bitfield RTC_CR_CLKO. |
mbed_official | 146:f64d43ff0c18 | 643 | #define BF_RTC_CR_CLKO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_CLKO), uint32_t) & BM_RTC_CR_CLKO) |
mbed_official | 146:f64d43ff0c18 | 644 | |
mbed_official | 146:f64d43ff0c18 | 645 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 646 | //! @brief Set the CLKO field to a new value. |
mbed_official | 146:f64d43ff0c18 | 647 | #define BW_RTC_CR_CLKO(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_CLKO) = (v)) |
mbed_official | 146:f64d43ff0c18 | 648 | #endif |
mbed_official | 146:f64d43ff0c18 | 649 | //@} |
mbed_official | 146:f64d43ff0c18 | 650 | |
mbed_official | 146:f64d43ff0c18 | 651 | /*! |
mbed_official | 146:f64d43ff0c18 | 652 | * @name Register RTC_CR, field SC16P[10] (RW) |
mbed_official | 146:f64d43ff0c18 | 653 | * |
mbed_official | 146:f64d43ff0c18 | 654 | * Values: |
mbed_official | 146:f64d43ff0c18 | 655 | * - 0 - Disable the load. |
mbed_official | 146:f64d43ff0c18 | 656 | * - 1 - Enable the additional load. |
mbed_official | 146:f64d43ff0c18 | 657 | */ |
mbed_official | 146:f64d43ff0c18 | 658 | //@{ |
mbed_official | 146:f64d43ff0c18 | 659 | #define BP_RTC_CR_SC16P (10U) //!< Bit position for RTC_CR_SC16P. |
mbed_official | 146:f64d43ff0c18 | 660 | #define BM_RTC_CR_SC16P (0x00000400U) //!< Bit mask for RTC_CR_SC16P. |
mbed_official | 146:f64d43ff0c18 | 661 | #define BS_RTC_CR_SC16P (1U) //!< Bit field size in bits for RTC_CR_SC16P. |
mbed_official | 146:f64d43ff0c18 | 662 | |
mbed_official | 146:f64d43ff0c18 | 663 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 664 | //! @brief Read current value of the RTC_CR_SC16P field. |
mbed_official | 146:f64d43ff0c18 | 665 | #define BR_RTC_CR_SC16P (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC16P)) |
mbed_official | 146:f64d43ff0c18 | 666 | #endif |
mbed_official | 146:f64d43ff0c18 | 667 | |
mbed_official | 146:f64d43ff0c18 | 668 | //! @brief Format value for bitfield RTC_CR_SC16P. |
mbed_official | 146:f64d43ff0c18 | 669 | #define BF_RTC_CR_SC16P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SC16P), uint32_t) & BM_RTC_CR_SC16P) |
mbed_official | 146:f64d43ff0c18 | 670 | |
mbed_official | 146:f64d43ff0c18 | 671 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 672 | //! @brief Set the SC16P field to a new value. |
mbed_official | 146:f64d43ff0c18 | 673 | #define BW_RTC_CR_SC16P(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC16P) = (v)) |
mbed_official | 146:f64d43ff0c18 | 674 | #endif |
mbed_official | 146:f64d43ff0c18 | 675 | //@} |
mbed_official | 146:f64d43ff0c18 | 676 | |
mbed_official | 146:f64d43ff0c18 | 677 | /*! |
mbed_official | 146:f64d43ff0c18 | 678 | * @name Register RTC_CR, field SC8P[11] (RW) |
mbed_official | 146:f64d43ff0c18 | 679 | * |
mbed_official | 146:f64d43ff0c18 | 680 | * Values: |
mbed_official | 146:f64d43ff0c18 | 681 | * - 0 - Disable the load. |
mbed_official | 146:f64d43ff0c18 | 682 | * - 1 - Enable the additional load. |
mbed_official | 146:f64d43ff0c18 | 683 | */ |
mbed_official | 146:f64d43ff0c18 | 684 | //@{ |
mbed_official | 146:f64d43ff0c18 | 685 | #define BP_RTC_CR_SC8P (11U) //!< Bit position for RTC_CR_SC8P. |
mbed_official | 146:f64d43ff0c18 | 686 | #define BM_RTC_CR_SC8P (0x00000800U) //!< Bit mask for RTC_CR_SC8P. |
mbed_official | 146:f64d43ff0c18 | 687 | #define BS_RTC_CR_SC8P (1U) //!< Bit field size in bits for RTC_CR_SC8P. |
mbed_official | 146:f64d43ff0c18 | 688 | |
mbed_official | 146:f64d43ff0c18 | 689 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 690 | //! @brief Read current value of the RTC_CR_SC8P field. |
mbed_official | 146:f64d43ff0c18 | 691 | #define BR_RTC_CR_SC8P (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC8P)) |
mbed_official | 146:f64d43ff0c18 | 692 | #endif |
mbed_official | 146:f64d43ff0c18 | 693 | |
mbed_official | 146:f64d43ff0c18 | 694 | //! @brief Format value for bitfield RTC_CR_SC8P. |
mbed_official | 146:f64d43ff0c18 | 695 | #define BF_RTC_CR_SC8P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SC8P), uint32_t) & BM_RTC_CR_SC8P) |
mbed_official | 146:f64d43ff0c18 | 696 | |
mbed_official | 146:f64d43ff0c18 | 697 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 698 | //! @brief Set the SC8P field to a new value. |
mbed_official | 146:f64d43ff0c18 | 699 | #define BW_RTC_CR_SC8P(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC8P) = (v)) |
mbed_official | 146:f64d43ff0c18 | 700 | #endif |
mbed_official | 146:f64d43ff0c18 | 701 | //@} |
mbed_official | 146:f64d43ff0c18 | 702 | |
mbed_official | 146:f64d43ff0c18 | 703 | /*! |
mbed_official | 146:f64d43ff0c18 | 704 | * @name Register RTC_CR, field SC4P[12] (RW) |
mbed_official | 146:f64d43ff0c18 | 705 | * |
mbed_official | 146:f64d43ff0c18 | 706 | * Values: |
mbed_official | 146:f64d43ff0c18 | 707 | * - 0 - Disable the load. |
mbed_official | 146:f64d43ff0c18 | 708 | * - 1 - Enable the additional load. |
mbed_official | 146:f64d43ff0c18 | 709 | */ |
mbed_official | 146:f64d43ff0c18 | 710 | //@{ |
mbed_official | 146:f64d43ff0c18 | 711 | #define BP_RTC_CR_SC4P (12U) //!< Bit position for RTC_CR_SC4P. |
mbed_official | 146:f64d43ff0c18 | 712 | #define BM_RTC_CR_SC4P (0x00001000U) //!< Bit mask for RTC_CR_SC4P. |
mbed_official | 146:f64d43ff0c18 | 713 | #define BS_RTC_CR_SC4P (1U) //!< Bit field size in bits for RTC_CR_SC4P. |
mbed_official | 146:f64d43ff0c18 | 714 | |
mbed_official | 146:f64d43ff0c18 | 715 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 716 | //! @brief Read current value of the RTC_CR_SC4P field. |
mbed_official | 146:f64d43ff0c18 | 717 | #define BR_RTC_CR_SC4P (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC4P)) |
mbed_official | 146:f64d43ff0c18 | 718 | #endif |
mbed_official | 146:f64d43ff0c18 | 719 | |
mbed_official | 146:f64d43ff0c18 | 720 | //! @brief Format value for bitfield RTC_CR_SC4P. |
mbed_official | 146:f64d43ff0c18 | 721 | #define BF_RTC_CR_SC4P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SC4P), uint32_t) & BM_RTC_CR_SC4P) |
mbed_official | 146:f64d43ff0c18 | 722 | |
mbed_official | 146:f64d43ff0c18 | 723 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 724 | //! @brief Set the SC4P field to a new value. |
mbed_official | 146:f64d43ff0c18 | 725 | #define BW_RTC_CR_SC4P(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC4P) = (v)) |
mbed_official | 146:f64d43ff0c18 | 726 | #endif |
mbed_official | 146:f64d43ff0c18 | 727 | //@} |
mbed_official | 146:f64d43ff0c18 | 728 | |
mbed_official | 146:f64d43ff0c18 | 729 | /*! |
mbed_official | 146:f64d43ff0c18 | 730 | * @name Register RTC_CR, field SC2P[13] (RW) |
mbed_official | 146:f64d43ff0c18 | 731 | * |
mbed_official | 146:f64d43ff0c18 | 732 | * Values: |
mbed_official | 146:f64d43ff0c18 | 733 | * - 0 - Disable the load. |
mbed_official | 146:f64d43ff0c18 | 734 | * - 1 - Enable the additional load. |
mbed_official | 146:f64d43ff0c18 | 735 | */ |
mbed_official | 146:f64d43ff0c18 | 736 | //@{ |
mbed_official | 146:f64d43ff0c18 | 737 | #define BP_RTC_CR_SC2P (13U) //!< Bit position for RTC_CR_SC2P. |
mbed_official | 146:f64d43ff0c18 | 738 | #define BM_RTC_CR_SC2P (0x00002000U) //!< Bit mask for RTC_CR_SC2P. |
mbed_official | 146:f64d43ff0c18 | 739 | #define BS_RTC_CR_SC2P (1U) //!< Bit field size in bits for RTC_CR_SC2P. |
mbed_official | 146:f64d43ff0c18 | 740 | |
mbed_official | 146:f64d43ff0c18 | 741 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 742 | //! @brief Read current value of the RTC_CR_SC2P field. |
mbed_official | 146:f64d43ff0c18 | 743 | #define BR_RTC_CR_SC2P (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC2P)) |
mbed_official | 146:f64d43ff0c18 | 744 | #endif |
mbed_official | 146:f64d43ff0c18 | 745 | |
mbed_official | 146:f64d43ff0c18 | 746 | //! @brief Format value for bitfield RTC_CR_SC2P. |
mbed_official | 146:f64d43ff0c18 | 747 | #define BF_RTC_CR_SC2P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SC2P), uint32_t) & BM_RTC_CR_SC2P) |
mbed_official | 146:f64d43ff0c18 | 748 | |
mbed_official | 146:f64d43ff0c18 | 749 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 750 | //! @brief Set the SC2P field to a new value. |
mbed_official | 146:f64d43ff0c18 | 751 | #define BW_RTC_CR_SC2P(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC2P) = (v)) |
mbed_official | 146:f64d43ff0c18 | 752 | #endif |
mbed_official | 146:f64d43ff0c18 | 753 | //@} |
mbed_official | 146:f64d43ff0c18 | 754 | |
mbed_official | 146:f64d43ff0c18 | 755 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 756 | // HW_RTC_SR - RTC Status Register |
mbed_official | 146:f64d43ff0c18 | 757 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 758 | |
mbed_official | 146:f64d43ff0c18 | 759 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 760 | /*! |
mbed_official | 146:f64d43ff0c18 | 761 | * @brief HW_RTC_SR - RTC Status Register (RW) |
mbed_official | 146:f64d43ff0c18 | 762 | * |
mbed_official | 146:f64d43ff0c18 | 763 | * Reset value: 0x00000001U |
mbed_official | 146:f64d43ff0c18 | 764 | */ |
mbed_official | 146:f64d43ff0c18 | 765 | typedef union _hw_rtc_sr |
mbed_official | 146:f64d43ff0c18 | 766 | { |
mbed_official | 146:f64d43ff0c18 | 767 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 768 | struct _hw_rtc_sr_bitfields |
mbed_official | 146:f64d43ff0c18 | 769 | { |
mbed_official | 146:f64d43ff0c18 | 770 | uint32_t TIF : 1; //!< [0] Time Invalid Flag |
mbed_official | 146:f64d43ff0c18 | 771 | uint32_t TOF : 1; //!< [1] Time Overflow Flag |
mbed_official | 146:f64d43ff0c18 | 772 | uint32_t TAF : 1; //!< [2] Time Alarm Flag |
mbed_official | 146:f64d43ff0c18 | 773 | uint32_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 774 | uint32_t TCE : 1; //!< [4] Time Counter Enable |
mbed_official | 146:f64d43ff0c18 | 775 | uint32_t RESERVED1 : 27; //!< [31:5] |
mbed_official | 146:f64d43ff0c18 | 776 | } B; |
mbed_official | 146:f64d43ff0c18 | 777 | } hw_rtc_sr_t; |
mbed_official | 146:f64d43ff0c18 | 778 | #endif |
mbed_official | 146:f64d43ff0c18 | 779 | |
mbed_official | 146:f64d43ff0c18 | 780 | /*! |
mbed_official | 146:f64d43ff0c18 | 781 | * @name Constants and macros for entire RTC_SR register |
mbed_official | 146:f64d43ff0c18 | 782 | */ |
mbed_official | 146:f64d43ff0c18 | 783 | //@{ |
mbed_official | 146:f64d43ff0c18 | 784 | #define HW_RTC_SR_ADDR (REGS_RTC_BASE + 0x14U) |
mbed_official | 146:f64d43ff0c18 | 785 | |
mbed_official | 146:f64d43ff0c18 | 786 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 787 | #define HW_RTC_SR (*(__IO hw_rtc_sr_t *) HW_RTC_SR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 788 | #define HW_RTC_SR_RD() (HW_RTC_SR.U) |
mbed_official | 146:f64d43ff0c18 | 789 | #define HW_RTC_SR_WR(v) (HW_RTC_SR.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 790 | #define HW_RTC_SR_SET(v) (HW_RTC_SR_WR(HW_RTC_SR_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 791 | #define HW_RTC_SR_CLR(v) (HW_RTC_SR_WR(HW_RTC_SR_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 792 | #define HW_RTC_SR_TOG(v) (HW_RTC_SR_WR(HW_RTC_SR_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 793 | #endif |
mbed_official | 146:f64d43ff0c18 | 794 | //@} |
mbed_official | 146:f64d43ff0c18 | 795 | |
mbed_official | 146:f64d43ff0c18 | 796 | /* |
mbed_official | 146:f64d43ff0c18 | 797 | * Constants & macros for individual RTC_SR bitfields |
mbed_official | 146:f64d43ff0c18 | 798 | */ |
mbed_official | 146:f64d43ff0c18 | 799 | |
mbed_official | 146:f64d43ff0c18 | 800 | /*! |
mbed_official | 146:f64d43ff0c18 | 801 | * @name Register RTC_SR, field TIF[0] (RO) |
mbed_official | 146:f64d43ff0c18 | 802 | * |
mbed_official | 146:f64d43ff0c18 | 803 | * The time invalid flag is set on VBAT POR or software reset. The TSR and TPR |
mbed_official | 146:f64d43ff0c18 | 804 | * do not increment and read as zero when this bit is set. This bit is cleared by |
mbed_official | 146:f64d43ff0c18 | 805 | * writing the TSR register when the time counter is disabled. |
mbed_official | 146:f64d43ff0c18 | 806 | * |
mbed_official | 146:f64d43ff0c18 | 807 | * Values: |
mbed_official | 146:f64d43ff0c18 | 808 | * - 0 - Time is valid. |
mbed_official | 146:f64d43ff0c18 | 809 | * - 1 - Time is invalid and time counter is read as zero. |
mbed_official | 146:f64d43ff0c18 | 810 | */ |
mbed_official | 146:f64d43ff0c18 | 811 | //@{ |
mbed_official | 146:f64d43ff0c18 | 812 | #define BP_RTC_SR_TIF (0U) //!< Bit position for RTC_SR_TIF. |
mbed_official | 146:f64d43ff0c18 | 813 | #define BM_RTC_SR_TIF (0x00000001U) //!< Bit mask for RTC_SR_TIF. |
mbed_official | 146:f64d43ff0c18 | 814 | #define BS_RTC_SR_TIF (1U) //!< Bit field size in bits for RTC_SR_TIF. |
mbed_official | 146:f64d43ff0c18 | 815 | |
mbed_official | 146:f64d43ff0c18 | 816 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 817 | //! @brief Read current value of the RTC_SR_TIF field. |
mbed_official | 146:f64d43ff0c18 | 818 | #define BR_RTC_SR_TIF (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TIF)) |
mbed_official | 146:f64d43ff0c18 | 819 | #endif |
mbed_official | 146:f64d43ff0c18 | 820 | //@} |
mbed_official | 146:f64d43ff0c18 | 821 | |
mbed_official | 146:f64d43ff0c18 | 822 | /*! |
mbed_official | 146:f64d43ff0c18 | 823 | * @name Register RTC_SR, field TOF[1] (RO) |
mbed_official | 146:f64d43ff0c18 | 824 | * |
mbed_official | 146:f64d43ff0c18 | 825 | * Time overflow flag is set when the time counter is enabled and overflows. The |
mbed_official | 146:f64d43ff0c18 | 826 | * TSR and TPR do not increment and read as zero when this bit is set. This bit |
mbed_official | 146:f64d43ff0c18 | 827 | * is cleared by writing the TSR register when the time counter is disabled. |
mbed_official | 146:f64d43ff0c18 | 828 | * |
mbed_official | 146:f64d43ff0c18 | 829 | * Values: |
mbed_official | 146:f64d43ff0c18 | 830 | * - 0 - Time overflow has not occurred. |
mbed_official | 146:f64d43ff0c18 | 831 | * - 1 - Time overflow has occurred and time counter is read as zero. |
mbed_official | 146:f64d43ff0c18 | 832 | */ |
mbed_official | 146:f64d43ff0c18 | 833 | //@{ |
mbed_official | 146:f64d43ff0c18 | 834 | #define BP_RTC_SR_TOF (1U) //!< Bit position for RTC_SR_TOF. |
mbed_official | 146:f64d43ff0c18 | 835 | #define BM_RTC_SR_TOF (0x00000002U) //!< Bit mask for RTC_SR_TOF. |
mbed_official | 146:f64d43ff0c18 | 836 | #define BS_RTC_SR_TOF (1U) //!< Bit field size in bits for RTC_SR_TOF. |
mbed_official | 146:f64d43ff0c18 | 837 | |
mbed_official | 146:f64d43ff0c18 | 838 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 839 | //! @brief Read current value of the RTC_SR_TOF field. |
mbed_official | 146:f64d43ff0c18 | 840 | #define BR_RTC_SR_TOF (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TOF)) |
mbed_official | 146:f64d43ff0c18 | 841 | #endif |
mbed_official | 146:f64d43ff0c18 | 842 | //@} |
mbed_official | 146:f64d43ff0c18 | 843 | |
mbed_official | 146:f64d43ff0c18 | 844 | /*! |
mbed_official | 146:f64d43ff0c18 | 845 | * @name Register RTC_SR, field TAF[2] (RO) |
mbed_official | 146:f64d43ff0c18 | 846 | * |
mbed_official | 146:f64d43ff0c18 | 847 | * Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR] |
mbed_official | 146:f64d43ff0c18 | 848 | * increments. This bit is cleared by writing the TAR register. |
mbed_official | 146:f64d43ff0c18 | 849 | * |
mbed_official | 146:f64d43ff0c18 | 850 | * Values: |
mbed_official | 146:f64d43ff0c18 | 851 | * - 0 - Time alarm has not occurred. |
mbed_official | 146:f64d43ff0c18 | 852 | * - 1 - Time alarm has occurred. |
mbed_official | 146:f64d43ff0c18 | 853 | */ |
mbed_official | 146:f64d43ff0c18 | 854 | //@{ |
mbed_official | 146:f64d43ff0c18 | 855 | #define BP_RTC_SR_TAF (2U) //!< Bit position for RTC_SR_TAF. |
mbed_official | 146:f64d43ff0c18 | 856 | #define BM_RTC_SR_TAF (0x00000004U) //!< Bit mask for RTC_SR_TAF. |
mbed_official | 146:f64d43ff0c18 | 857 | #define BS_RTC_SR_TAF (1U) //!< Bit field size in bits for RTC_SR_TAF. |
mbed_official | 146:f64d43ff0c18 | 858 | |
mbed_official | 146:f64d43ff0c18 | 859 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 860 | //! @brief Read current value of the RTC_SR_TAF field. |
mbed_official | 146:f64d43ff0c18 | 861 | #define BR_RTC_SR_TAF (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TAF)) |
mbed_official | 146:f64d43ff0c18 | 862 | #endif |
mbed_official | 146:f64d43ff0c18 | 863 | //@} |
mbed_official | 146:f64d43ff0c18 | 864 | |
mbed_official | 146:f64d43ff0c18 | 865 | /*! |
mbed_official | 146:f64d43ff0c18 | 866 | * @name Register RTC_SR, field TCE[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 867 | * |
mbed_official | 146:f64d43ff0c18 | 868 | * When time counter is disabled the TSR register and TPR register are |
mbed_official | 146:f64d43ff0c18 | 869 | * writeable, but do not increment. When time counter is enabled the TSR register and TPR |
mbed_official | 146:f64d43ff0c18 | 870 | * register are not writeable, but increment. |
mbed_official | 146:f64d43ff0c18 | 871 | * |
mbed_official | 146:f64d43ff0c18 | 872 | * Values: |
mbed_official | 146:f64d43ff0c18 | 873 | * - 0 - Time counter is disabled. |
mbed_official | 146:f64d43ff0c18 | 874 | * - 1 - Time counter is enabled. |
mbed_official | 146:f64d43ff0c18 | 875 | */ |
mbed_official | 146:f64d43ff0c18 | 876 | //@{ |
mbed_official | 146:f64d43ff0c18 | 877 | #define BP_RTC_SR_TCE (4U) //!< Bit position for RTC_SR_TCE. |
mbed_official | 146:f64d43ff0c18 | 878 | #define BM_RTC_SR_TCE (0x00000010U) //!< Bit mask for RTC_SR_TCE. |
mbed_official | 146:f64d43ff0c18 | 879 | #define BS_RTC_SR_TCE (1U) //!< Bit field size in bits for RTC_SR_TCE. |
mbed_official | 146:f64d43ff0c18 | 880 | |
mbed_official | 146:f64d43ff0c18 | 881 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 882 | //! @brief Read current value of the RTC_SR_TCE field. |
mbed_official | 146:f64d43ff0c18 | 883 | #define BR_RTC_SR_TCE (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TCE)) |
mbed_official | 146:f64d43ff0c18 | 884 | #endif |
mbed_official | 146:f64d43ff0c18 | 885 | |
mbed_official | 146:f64d43ff0c18 | 886 | //! @brief Format value for bitfield RTC_SR_TCE. |
mbed_official | 146:f64d43ff0c18 | 887 | #define BF_RTC_SR_TCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_SR_TCE), uint32_t) & BM_RTC_SR_TCE) |
mbed_official | 146:f64d43ff0c18 | 888 | |
mbed_official | 146:f64d43ff0c18 | 889 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 890 | //! @brief Set the TCE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 891 | #define BW_RTC_SR_TCE(v) (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TCE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 892 | #endif |
mbed_official | 146:f64d43ff0c18 | 893 | //@} |
mbed_official | 146:f64d43ff0c18 | 894 | |
mbed_official | 146:f64d43ff0c18 | 895 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 896 | // HW_RTC_LR - RTC Lock Register |
mbed_official | 146:f64d43ff0c18 | 897 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 898 | |
mbed_official | 146:f64d43ff0c18 | 899 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 900 | /*! |
mbed_official | 146:f64d43ff0c18 | 901 | * @brief HW_RTC_LR - RTC Lock Register (RW) |
mbed_official | 146:f64d43ff0c18 | 902 | * |
mbed_official | 146:f64d43ff0c18 | 903 | * Reset value: 0x000000FFU |
mbed_official | 146:f64d43ff0c18 | 904 | */ |
mbed_official | 146:f64d43ff0c18 | 905 | typedef union _hw_rtc_lr |
mbed_official | 146:f64d43ff0c18 | 906 | { |
mbed_official | 146:f64d43ff0c18 | 907 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 908 | struct _hw_rtc_lr_bitfields |
mbed_official | 146:f64d43ff0c18 | 909 | { |
mbed_official | 146:f64d43ff0c18 | 910 | uint32_t RESERVED0 : 3; //!< [2:0] |
mbed_official | 146:f64d43ff0c18 | 911 | uint32_t TCL : 1; //!< [3] Time Compensation Lock |
mbed_official | 146:f64d43ff0c18 | 912 | uint32_t CRL : 1; //!< [4] Control Register Lock |
mbed_official | 146:f64d43ff0c18 | 913 | uint32_t SRL : 1; //!< [5] Status Register Lock |
mbed_official | 146:f64d43ff0c18 | 914 | uint32_t LRL : 1; //!< [6] Lock Register Lock |
mbed_official | 146:f64d43ff0c18 | 915 | uint32_t RESERVED1 : 25; //!< [31:7] |
mbed_official | 146:f64d43ff0c18 | 916 | } B; |
mbed_official | 146:f64d43ff0c18 | 917 | } hw_rtc_lr_t; |
mbed_official | 146:f64d43ff0c18 | 918 | #endif |
mbed_official | 146:f64d43ff0c18 | 919 | |
mbed_official | 146:f64d43ff0c18 | 920 | /*! |
mbed_official | 146:f64d43ff0c18 | 921 | * @name Constants and macros for entire RTC_LR register |
mbed_official | 146:f64d43ff0c18 | 922 | */ |
mbed_official | 146:f64d43ff0c18 | 923 | //@{ |
mbed_official | 146:f64d43ff0c18 | 924 | #define HW_RTC_LR_ADDR (REGS_RTC_BASE + 0x18U) |
mbed_official | 146:f64d43ff0c18 | 925 | |
mbed_official | 146:f64d43ff0c18 | 926 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 927 | #define HW_RTC_LR (*(__IO hw_rtc_lr_t *) HW_RTC_LR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 928 | #define HW_RTC_LR_RD() (HW_RTC_LR.U) |
mbed_official | 146:f64d43ff0c18 | 929 | #define HW_RTC_LR_WR(v) (HW_RTC_LR.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 930 | #define HW_RTC_LR_SET(v) (HW_RTC_LR_WR(HW_RTC_LR_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 931 | #define HW_RTC_LR_CLR(v) (HW_RTC_LR_WR(HW_RTC_LR_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 932 | #define HW_RTC_LR_TOG(v) (HW_RTC_LR_WR(HW_RTC_LR_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 933 | #endif |
mbed_official | 146:f64d43ff0c18 | 934 | //@} |
mbed_official | 146:f64d43ff0c18 | 935 | |
mbed_official | 146:f64d43ff0c18 | 936 | /* |
mbed_official | 146:f64d43ff0c18 | 937 | * Constants & macros for individual RTC_LR bitfields |
mbed_official | 146:f64d43ff0c18 | 938 | */ |
mbed_official | 146:f64d43ff0c18 | 939 | |
mbed_official | 146:f64d43ff0c18 | 940 | /*! |
mbed_official | 146:f64d43ff0c18 | 941 | * @name Register RTC_LR, field TCL[3] (RW) |
mbed_official | 146:f64d43ff0c18 | 942 | * |
mbed_official | 146:f64d43ff0c18 | 943 | * After being cleared, this bit can be set only by VBAT POR or software reset. |
mbed_official | 146:f64d43ff0c18 | 944 | * |
mbed_official | 146:f64d43ff0c18 | 945 | * Values: |
mbed_official | 146:f64d43ff0c18 | 946 | * - 0 - Time Compensation Register is locked and writes are ignored. |
mbed_official | 146:f64d43ff0c18 | 947 | * - 1 - Time Compensation Register is not locked and writes complete as normal. |
mbed_official | 146:f64d43ff0c18 | 948 | */ |
mbed_official | 146:f64d43ff0c18 | 949 | //@{ |
mbed_official | 146:f64d43ff0c18 | 950 | #define BP_RTC_LR_TCL (3U) //!< Bit position for RTC_LR_TCL. |
mbed_official | 146:f64d43ff0c18 | 951 | #define BM_RTC_LR_TCL (0x00000008U) //!< Bit mask for RTC_LR_TCL. |
mbed_official | 146:f64d43ff0c18 | 952 | #define BS_RTC_LR_TCL (1U) //!< Bit field size in bits for RTC_LR_TCL. |
mbed_official | 146:f64d43ff0c18 | 953 | |
mbed_official | 146:f64d43ff0c18 | 954 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 955 | //! @brief Read current value of the RTC_LR_TCL field. |
mbed_official | 146:f64d43ff0c18 | 956 | #define BR_RTC_LR_TCL (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_TCL)) |
mbed_official | 146:f64d43ff0c18 | 957 | #endif |
mbed_official | 146:f64d43ff0c18 | 958 | |
mbed_official | 146:f64d43ff0c18 | 959 | //! @brief Format value for bitfield RTC_LR_TCL. |
mbed_official | 146:f64d43ff0c18 | 960 | #define BF_RTC_LR_TCL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_LR_TCL), uint32_t) & BM_RTC_LR_TCL) |
mbed_official | 146:f64d43ff0c18 | 961 | |
mbed_official | 146:f64d43ff0c18 | 962 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 963 | //! @brief Set the TCL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 964 | #define BW_RTC_LR_TCL(v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_TCL) = (v)) |
mbed_official | 146:f64d43ff0c18 | 965 | #endif |
mbed_official | 146:f64d43ff0c18 | 966 | //@} |
mbed_official | 146:f64d43ff0c18 | 967 | |
mbed_official | 146:f64d43ff0c18 | 968 | /*! |
mbed_official | 146:f64d43ff0c18 | 969 | * @name Register RTC_LR, field CRL[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 970 | * |
mbed_official | 146:f64d43ff0c18 | 971 | * After being cleared, this bit can only be set by VBAT POR. |
mbed_official | 146:f64d43ff0c18 | 972 | * |
mbed_official | 146:f64d43ff0c18 | 973 | * Values: |
mbed_official | 146:f64d43ff0c18 | 974 | * - 0 - Control Register is locked and writes are ignored. |
mbed_official | 146:f64d43ff0c18 | 975 | * - 1 - Control Register is not locked and writes complete as normal. |
mbed_official | 146:f64d43ff0c18 | 976 | */ |
mbed_official | 146:f64d43ff0c18 | 977 | //@{ |
mbed_official | 146:f64d43ff0c18 | 978 | #define BP_RTC_LR_CRL (4U) //!< Bit position for RTC_LR_CRL. |
mbed_official | 146:f64d43ff0c18 | 979 | #define BM_RTC_LR_CRL (0x00000010U) //!< Bit mask for RTC_LR_CRL. |
mbed_official | 146:f64d43ff0c18 | 980 | #define BS_RTC_LR_CRL (1U) //!< Bit field size in bits for RTC_LR_CRL. |
mbed_official | 146:f64d43ff0c18 | 981 | |
mbed_official | 146:f64d43ff0c18 | 982 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 983 | //! @brief Read current value of the RTC_LR_CRL field. |
mbed_official | 146:f64d43ff0c18 | 984 | #define BR_RTC_LR_CRL (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_CRL)) |
mbed_official | 146:f64d43ff0c18 | 985 | #endif |
mbed_official | 146:f64d43ff0c18 | 986 | |
mbed_official | 146:f64d43ff0c18 | 987 | //! @brief Format value for bitfield RTC_LR_CRL. |
mbed_official | 146:f64d43ff0c18 | 988 | #define BF_RTC_LR_CRL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_LR_CRL), uint32_t) & BM_RTC_LR_CRL) |
mbed_official | 146:f64d43ff0c18 | 989 | |
mbed_official | 146:f64d43ff0c18 | 990 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 991 | //! @brief Set the CRL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 992 | #define BW_RTC_LR_CRL(v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_CRL) = (v)) |
mbed_official | 146:f64d43ff0c18 | 993 | #endif |
mbed_official | 146:f64d43ff0c18 | 994 | //@} |
mbed_official | 146:f64d43ff0c18 | 995 | |
mbed_official | 146:f64d43ff0c18 | 996 | /*! |
mbed_official | 146:f64d43ff0c18 | 997 | * @name Register RTC_LR, field SRL[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 998 | * |
mbed_official | 146:f64d43ff0c18 | 999 | * After being cleared, this bit can be set only by VBAT POR or software reset. |
mbed_official | 146:f64d43ff0c18 | 1000 | * |
mbed_official | 146:f64d43ff0c18 | 1001 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1002 | * - 0 - Status Register is locked and writes are ignored. |
mbed_official | 146:f64d43ff0c18 | 1003 | * - 1 - Status Register is not locked and writes complete as normal. |
mbed_official | 146:f64d43ff0c18 | 1004 | */ |
mbed_official | 146:f64d43ff0c18 | 1005 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1006 | #define BP_RTC_LR_SRL (5U) //!< Bit position for RTC_LR_SRL. |
mbed_official | 146:f64d43ff0c18 | 1007 | #define BM_RTC_LR_SRL (0x00000020U) //!< Bit mask for RTC_LR_SRL. |
mbed_official | 146:f64d43ff0c18 | 1008 | #define BS_RTC_LR_SRL (1U) //!< Bit field size in bits for RTC_LR_SRL. |
mbed_official | 146:f64d43ff0c18 | 1009 | |
mbed_official | 146:f64d43ff0c18 | 1010 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1011 | //! @brief Read current value of the RTC_LR_SRL field. |
mbed_official | 146:f64d43ff0c18 | 1012 | #define BR_RTC_LR_SRL (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_SRL)) |
mbed_official | 146:f64d43ff0c18 | 1013 | #endif |
mbed_official | 146:f64d43ff0c18 | 1014 | |
mbed_official | 146:f64d43ff0c18 | 1015 | //! @brief Format value for bitfield RTC_LR_SRL. |
mbed_official | 146:f64d43ff0c18 | 1016 | #define BF_RTC_LR_SRL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_LR_SRL), uint32_t) & BM_RTC_LR_SRL) |
mbed_official | 146:f64d43ff0c18 | 1017 | |
mbed_official | 146:f64d43ff0c18 | 1018 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1019 | //! @brief Set the SRL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1020 | #define BW_RTC_LR_SRL(v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_SRL) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1021 | #endif |
mbed_official | 146:f64d43ff0c18 | 1022 | //@} |
mbed_official | 146:f64d43ff0c18 | 1023 | |
mbed_official | 146:f64d43ff0c18 | 1024 | /*! |
mbed_official | 146:f64d43ff0c18 | 1025 | * @name Register RTC_LR, field LRL[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 1026 | * |
mbed_official | 146:f64d43ff0c18 | 1027 | * After being cleared, this bit can be set only by VBAT POR or software reset. |
mbed_official | 146:f64d43ff0c18 | 1028 | * |
mbed_official | 146:f64d43ff0c18 | 1029 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1030 | * - 0 - Lock Register is locked and writes are ignored. |
mbed_official | 146:f64d43ff0c18 | 1031 | * - 1 - Lock Register is not locked and writes complete as normal. |
mbed_official | 146:f64d43ff0c18 | 1032 | */ |
mbed_official | 146:f64d43ff0c18 | 1033 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1034 | #define BP_RTC_LR_LRL (6U) //!< Bit position for RTC_LR_LRL. |
mbed_official | 146:f64d43ff0c18 | 1035 | #define BM_RTC_LR_LRL (0x00000040U) //!< Bit mask for RTC_LR_LRL. |
mbed_official | 146:f64d43ff0c18 | 1036 | #define BS_RTC_LR_LRL (1U) //!< Bit field size in bits for RTC_LR_LRL. |
mbed_official | 146:f64d43ff0c18 | 1037 | |
mbed_official | 146:f64d43ff0c18 | 1038 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1039 | //! @brief Read current value of the RTC_LR_LRL field. |
mbed_official | 146:f64d43ff0c18 | 1040 | #define BR_RTC_LR_LRL (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_LRL)) |
mbed_official | 146:f64d43ff0c18 | 1041 | #endif |
mbed_official | 146:f64d43ff0c18 | 1042 | |
mbed_official | 146:f64d43ff0c18 | 1043 | //! @brief Format value for bitfield RTC_LR_LRL. |
mbed_official | 146:f64d43ff0c18 | 1044 | #define BF_RTC_LR_LRL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_LR_LRL), uint32_t) & BM_RTC_LR_LRL) |
mbed_official | 146:f64d43ff0c18 | 1045 | |
mbed_official | 146:f64d43ff0c18 | 1046 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1047 | //! @brief Set the LRL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1048 | #define BW_RTC_LR_LRL(v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_LRL) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1049 | #endif |
mbed_official | 146:f64d43ff0c18 | 1050 | //@} |
mbed_official | 146:f64d43ff0c18 | 1051 | |
mbed_official | 146:f64d43ff0c18 | 1052 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1053 | // HW_RTC_IER - RTC Interrupt Enable Register |
mbed_official | 146:f64d43ff0c18 | 1054 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1055 | |
mbed_official | 146:f64d43ff0c18 | 1056 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1057 | /*! |
mbed_official | 146:f64d43ff0c18 | 1058 | * @brief HW_RTC_IER - RTC Interrupt Enable Register (RW) |
mbed_official | 146:f64d43ff0c18 | 1059 | * |
mbed_official | 146:f64d43ff0c18 | 1060 | * Reset value: 0x00000007U |
mbed_official | 146:f64d43ff0c18 | 1061 | */ |
mbed_official | 146:f64d43ff0c18 | 1062 | typedef union _hw_rtc_ier |
mbed_official | 146:f64d43ff0c18 | 1063 | { |
mbed_official | 146:f64d43ff0c18 | 1064 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 1065 | struct _hw_rtc_ier_bitfields |
mbed_official | 146:f64d43ff0c18 | 1066 | { |
mbed_official | 146:f64d43ff0c18 | 1067 | uint32_t TIIE : 1; //!< [0] Time Invalid Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 1068 | uint32_t TOIE : 1; //!< [1] Time Overflow Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 1069 | uint32_t TAIE : 1; //!< [2] Time Alarm Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 1070 | uint32_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 1071 | uint32_t TSIE : 1; //!< [4] Time Seconds Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 1072 | uint32_t RESERVED1 : 2; //!< [6:5] |
mbed_official | 146:f64d43ff0c18 | 1073 | uint32_t WPON : 1; //!< [7] Wakeup Pin On |
mbed_official | 146:f64d43ff0c18 | 1074 | uint32_t RESERVED2 : 24; //!< [31:8] |
mbed_official | 146:f64d43ff0c18 | 1075 | } B; |
mbed_official | 146:f64d43ff0c18 | 1076 | } hw_rtc_ier_t; |
mbed_official | 146:f64d43ff0c18 | 1077 | #endif |
mbed_official | 146:f64d43ff0c18 | 1078 | |
mbed_official | 146:f64d43ff0c18 | 1079 | /*! |
mbed_official | 146:f64d43ff0c18 | 1080 | * @name Constants and macros for entire RTC_IER register |
mbed_official | 146:f64d43ff0c18 | 1081 | */ |
mbed_official | 146:f64d43ff0c18 | 1082 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1083 | #define HW_RTC_IER_ADDR (REGS_RTC_BASE + 0x1CU) |
mbed_official | 146:f64d43ff0c18 | 1084 | |
mbed_official | 146:f64d43ff0c18 | 1085 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1086 | #define HW_RTC_IER (*(__IO hw_rtc_ier_t *) HW_RTC_IER_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1087 | #define HW_RTC_IER_RD() (HW_RTC_IER.U) |
mbed_official | 146:f64d43ff0c18 | 1088 | #define HW_RTC_IER_WR(v) (HW_RTC_IER.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1089 | #define HW_RTC_IER_SET(v) (HW_RTC_IER_WR(HW_RTC_IER_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1090 | #define HW_RTC_IER_CLR(v) (HW_RTC_IER_WR(HW_RTC_IER_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1091 | #define HW_RTC_IER_TOG(v) (HW_RTC_IER_WR(HW_RTC_IER_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1092 | #endif |
mbed_official | 146:f64d43ff0c18 | 1093 | //@} |
mbed_official | 146:f64d43ff0c18 | 1094 | |
mbed_official | 146:f64d43ff0c18 | 1095 | /* |
mbed_official | 146:f64d43ff0c18 | 1096 | * Constants & macros for individual RTC_IER bitfields |
mbed_official | 146:f64d43ff0c18 | 1097 | */ |
mbed_official | 146:f64d43ff0c18 | 1098 | |
mbed_official | 146:f64d43ff0c18 | 1099 | /*! |
mbed_official | 146:f64d43ff0c18 | 1100 | * @name Register RTC_IER, field TIIE[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1101 | * |
mbed_official | 146:f64d43ff0c18 | 1102 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1103 | * - 0 - Time invalid flag does not generate an interrupt. |
mbed_official | 146:f64d43ff0c18 | 1104 | * - 1 - Time invalid flag does generate an interrupt. |
mbed_official | 146:f64d43ff0c18 | 1105 | */ |
mbed_official | 146:f64d43ff0c18 | 1106 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1107 | #define BP_RTC_IER_TIIE (0U) //!< Bit position for RTC_IER_TIIE. |
mbed_official | 146:f64d43ff0c18 | 1108 | #define BM_RTC_IER_TIIE (0x00000001U) //!< Bit mask for RTC_IER_TIIE. |
mbed_official | 146:f64d43ff0c18 | 1109 | #define BS_RTC_IER_TIIE (1U) //!< Bit field size in bits for RTC_IER_TIIE. |
mbed_official | 146:f64d43ff0c18 | 1110 | |
mbed_official | 146:f64d43ff0c18 | 1111 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1112 | //! @brief Read current value of the RTC_IER_TIIE field. |
mbed_official | 146:f64d43ff0c18 | 1113 | #define BR_RTC_IER_TIIE (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TIIE)) |
mbed_official | 146:f64d43ff0c18 | 1114 | #endif |
mbed_official | 146:f64d43ff0c18 | 1115 | |
mbed_official | 146:f64d43ff0c18 | 1116 | //! @brief Format value for bitfield RTC_IER_TIIE. |
mbed_official | 146:f64d43ff0c18 | 1117 | #define BF_RTC_IER_TIIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_TIIE), uint32_t) & BM_RTC_IER_TIIE) |
mbed_official | 146:f64d43ff0c18 | 1118 | |
mbed_official | 146:f64d43ff0c18 | 1119 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1120 | //! @brief Set the TIIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1121 | #define BW_RTC_IER_TIIE(v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TIIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1122 | #endif |
mbed_official | 146:f64d43ff0c18 | 1123 | //@} |
mbed_official | 146:f64d43ff0c18 | 1124 | |
mbed_official | 146:f64d43ff0c18 | 1125 | /*! |
mbed_official | 146:f64d43ff0c18 | 1126 | * @name Register RTC_IER, field TOIE[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 1127 | * |
mbed_official | 146:f64d43ff0c18 | 1128 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1129 | * - 0 - Time overflow flag does not generate an interrupt. |
mbed_official | 146:f64d43ff0c18 | 1130 | * - 1 - Time overflow flag does generate an interrupt. |
mbed_official | 146:f64d43ff0c18 | 1131 | */ |
mbed_official | 146:f64d43ff0c18 | 1132 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1133 | #define BP_RTC_IER_TOIE (1U) //!< Bit position for RTC_IER_TOIE. |
mbed_official | 146:f64d43ff0c18 | 1134 | #define BM_RTC_IER_TOIE (0x00000002U) //!< Bit mask for RTC_IER_TOIE. |
mbed_official | 146:f64d43ff0c18 | 1135 | #define BS_RTC_IER_TOIE (1U) //!< Bit field size in bits for RTC_IER_TOIE. |
mbed_official | 146:f64d43ff0c18 | 1136 | |
mbed_official | 146:f64d43ff0c18 | 1137 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1138 | //! @brief Read current value of the RTC_IER_TOIE field. |
mbed_official | 146:f64d43ff0c18 | 1139 | #define BR_RTC_IER_TOIE (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TOIE)) |
mbed_official | 146:f64d43ff0c18 | 1140 | #endif |
mbed_official | 146:f64d43ff0c18 | 1141 | |
mbed_official | 146:f64d43ff0c18 | 1142 | //! @brief Format value for bitfield RTC_IER_TOIE. |
mbed_official | 146:f64d43ff0c18 | 1143 | #define BF_RTC_IER_TOIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_TOIE), uint32_t) & BM_RTC_IER_TOIE) |
mbed_official | 146:f64d43ff0c18 | 1144 | |
mbed_official | 146:f64d43ff0c18 | 1145 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1146 | //! @brief Set the TOIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1147 | #define BW_RTC_IER_TOIE(v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TOIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1148 | #endif |
mbed_official | 146:f64d43ff0c18 | 1149 | //@} |
mbed_official | 146:f64d43ff0c18 | 1150 | |
mbed_official | 146:f64d43ff0c18 | 1151 | /*! |
mbed_official | 146:f64d43ff0c18 | 1152 | * @name Register RTC_IER, field TAIE[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 1153 | * |
mbed_official | 146:f64d43ff0c18 | 1154 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1155 | * - 0 - Time alarm flag does not generate an interrupt. |
mbed_official | 146:f64d43ff0c18 | 1156 | * - 1 - Time alarm flag does generate an interrupt. |
mbed_official | 146:f64d43ff0c18 | 1157 | */ |
mbed_official | 146:f64d43ff0c18 | 1158 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1159 | #define BP_RTC_IER_TAIE (2U) //!< Bit position for RTC_IER_TAIE. |
mbed_official | 146:f64d43ff0c18 | 1160 | #define BM_RTC_IER_TAIE (0x00000004U) //!< Bit mask for RTC_IER_TAIE. |
mbed_official | 146:f64d43ff0c18 | 1161 | #define BS_RTC_IER_TAIE (1U) //!< Bit field size in bits for RTC_IER_TAIE. |
mbed_official | 146:f64d43ff0c18 | 1162 | |
mbed_official | 146:f64d43ff0c18 | 1163 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1164 | //! @brief Read current value of the RTC_IER_TAIE field. |
mbed_official | 146:f64d43ff0c18 | 1165 | #define BR_RTC_IER_TAIE (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TAIE)) |
mbed_official | 146:f64d43ff0c18 | 1166 | #endif |
mbed_official | 146:f64d43ff0c18 | 1167 | |
mbed_official | 146:f64d43ff0c18 | 1168 | //! @brief Format value for bitfield RTC_IER_TAIE. |
mbed_official | 146:f64d43ff0c18 | 1169 | #define BF_RTC_IER_TAIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_TAIE), uint32_t) & BM_RTC_IER_TAIE) |
mbed_official | 146:f64d43ff0c18 | 1170 | |
mbed_official | 146:f64d43ff0c18 | 1171 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1172 | //! @brief Set the TAIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1173 | #define BW_RTC_IER_TAIE(v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TAIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1174 | #endif |
mbed_official | 146:f64d43ff0c18 | 1175 | //@} |
mbed_official | 146:f64d43ff0c18 | 1176 | |
mbed_official | 146:f64d43ff0c18 | 1177 | /*! |
mbed_official | 146:f64d43ff0c18 | 1178 | * @name Register RTC_IER, field TSIE[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 1179 | * |
mbed_official | 146:f64d43ff0c18 | 1180 | * The seconds interrupt is an edge-sensitive interrupt with a dedicated |
mbed_official | 146:f64d43ff0c18 | 1181 | * interrupt vector. It is generated once a second and requires no software overhead |
mbed_official | 146:f64d43ff0c18 | 1182 | * (there is no corresponding status flag to clear). |
mbed_official | 146:f64d43ff0c18 | 1183 | * |
mbed_official | 146:f64d43ff0c18 | 1184 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1185 | * - 0 - Seconds interrupt is disabled. |
mbed_official | 146:f64d43ff0c18 | 1186 | * - 1 - Seconds interrupt is enabled. |
mbed_official | 146:f64d43ff0c18 | 1187 | */ |
mbed_official | 146:f64d43ff0c18 | 1188 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1189 | #define BP_RTC_IER_TSIE (4U) //!< Bit position for RTC_IER_TSIE. |
mbed_official | 146:f64d43ff0c18 | 1190 | #define BM_RTC_IER_TSIE (0x00000010U) //!< Bit mask for RTC_IER_TSIE. |
mbed_official | 146:f64d43ff0c18 | 1191 | #define BS_RTC_IER_TSIE (1U) //!< Bit field size in bits for RTC_IER_TSIE. |
mbed_official | 146:f64d43ff0c18 | 1192 | |
mbed_official | 146:f64d43ff0c18 | 1193 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1194 | //! @brief Read current value of the RTC_IER_TSIE field. |
mbed_official | 146:f64d43ff0c18 | 1195 | #define BR_RTC_IER_TSIE (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TSIE)) |
mbed_official | 146:f64d43ff0c18 | 1196 | #endif |
mbed_official | 146:f64d43ff0c18 | 1197 | |
mbed_official | 146:f64d43ff0c18 | 1198 | //! @brief Format value for bitfield RTC_IER_TSIE. |
mbed_official | 146:f64d43ff0c18 | 1199 | #define BF_RTC_IER_TSIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_TSIE), uint32_t) & BM_RTC_IER_TSIE) |
mbed_official | 146:f64d43ff0c18 | 1200 | |
mbed_official | 146:f64d43ff0c18 | 1201 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1202 | //! @brief Set the TSIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1203 | #define BW_RTC_IER_TSIE(v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TSIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1204 | #endif |
mbed_official | 146:f64d43ff0c18 | 1205 | //@} |
mbed_official | 146:f64d43ff0c18 | 1206 | |
mbed_official | 146:f64d43ff0c18 | 1207 | /*! |
mbed_official | 146:f64d43ff0c18 | 1208 | * @name Register RTC_IER, field WPON[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 1209 | * |
mbed_official | 146:f64d43ff0c18 | 1210 | * The wakeup pin is optional and not available on all devices. Whenever the |
mbed_official | 146:f64d43ff0c18 | 1211 | * wakeup pin is enabled and this bit is set, the wakeup pin will assert. |
mbed_official | 146:f64d43ff0c18 | 1212 | * |
mbed_official | 146:f64d43ff0c18 | 1213 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1214 | * - 0 - No effect. |
mbed_official | 146:f64d43ff0c18 | 1215 | * - 1 - If the wakeup pin is enabled, then the wakeup pin will assert. |
mbed_official | 146:f64d43ff0c18 | 1216 | */ |
mbed_official | 146:f64d43ff0c18 | 1217 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1218 | #define BP_RTC_IER_WPON (7U) //!< Bit position for RTC_IER_WPON. |
mbed_official | 146:f64d43ff0c18 | 1219 | #define BM_RTC_IER_WPON (0x00000080U) //!< Bit mask for RTC_IER_WPON. |
mbed_official | 146:f64d43ff0c18 | 1220 | #define BS_RTC_IER_WPON (1U) //!< Bit field size in bits for RTC_IER_WPON. |
mbed_official | 146:f64d43ff0c18 | 1221 | |
mbed_official | 146:f64d43ff0c18 | 1222 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1223 | //! @brief Read current value of the RTC_IER_WPON field. |
mbed_official | 146:f64d43ff0c18 | 1224 | #define BR_RTC_IER_WPON (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_WPON)) |
mbed_official | 146:f64d43ff0c18 | 1225 | #endif |
mbed_official | 146:f64d43ff0c18 | 1226 | |
mbed_official | 146:f64d43ff0c18 | 1227 | //! @brief Format value for bitfield RTC_IER_WPON. |
mbed_official | 146:f64d43ff0c18 | 1228 | #define BF_RTC_IER_WPON(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_WPON), uint32_t) & BM_RTC_IER_WPON) |
mbed_official | 146:f64d43ff0c18 | 1229 | |
mbed_official | 146:f64d43ff0c18 | 1230 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1231 | //! @brief Set the WPON field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1232 | #define BW_RTC_IER_WPON(v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_WPON) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1233 | #endif |
mbed_official | 146:f64d43ff0c18 | 1234 | //@} |
mbed_official | 146:f64d43ff0c18 | 1235 | |
mbed_official | 146:f64d43ff0c18 | 1236 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1237 | // HW_RTC_WAR - RTC Write Access Register |
mbed_official | 146:f64d43ff0c18 | 1238 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1239 | |
mbed_official | 146:f64d43ff0c18 | 1240 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1241 | /*! |
mbed_official | 146:f64d43ff0c18 | 1242 | * @brief HW_RTC_WAR - RTC Write Access Register (RW) |
mbed_official | 146:f64d43ff0c18 | 1243 | * |
mbed_official | 146:f64d43ff0c18 | 1244 | * Reset value: 0x000000FFU |
mbed_official | 146:f64d43ff0c18 | 1245 | */ |
mbed_official | 146:f64d43ff0c18 | 1246 | typedef union _hw_rtc_war |
mbed_official | 146:f64d43ff0c18 | 1247 | { |
mbed_official | 146:f64d43ff0c18 | 1248 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 1249 | struct _hw_rtc_war_bitfields |
mbed_official | 146:f64d43ff0c18 | 1250 | { |
mbed_official | 146:f64d43ff0c18 | 1251 | uint32_t TSRW : 1; //!< [0] Time Seconds Register Write |
mbed_official | 146:f64d43ff0c18 | 1252 | uint32_t TPRW : 1; //!< [1] Time Prescaler Register Write |
mbed_official | 146:f64d43ff0c18 | 1253 | uint32_t TARW : 1; //!< [2] Time Alarm Register Write |
mbed_official | 146:f64d43ff0c18 | 1254 | uint32_t TCRW : 1; //!< [3] Time Compensation Register Write |
mbed_official | 146:f64d43ff0c18 | 1255 | uint32_t CRW : 1; //!< [4] Control Register Write |
mbed_official | 146:f64d43ff0c18 | 1256 | uint32_t SRW : 1; //!< [5] Status Register Write |
mbed_official | 146:f64d43ff0c18 | 1257 | uint32_t LRW : 1; //!< [6] Lock Register Write |
mbed_official | 146:f64d43ff0c18 | 1258 | uint32_t IERW : 1; //!< [7] Interrupt Enable Register Write |
mbed_official | 146:f64d43ff0c18 | 1259 | uint32_t RESERVED0 : 24; //!< [31:8] |
mbed_official | 146:f64d43ff0c18 | 1260 | } B; |
mbed_official | 146:f64d43ff0c18 | 1261 | } hw_rtc_war_t; |
mbed_official | 146:f64d43ff0c18 | 1262 | #endif |
mbed_official | 146:f64d43ff0c18 | 1263 | |
mbed_official | 146:f64d43ff0c18 | 1264 | /*! |
mbed_official | 146:f64d43ff0c18 | 1265 | * @name Constants and macros for entire RTC_WAR register |
mbed_official | 146:f64d43ff0c18 | 1266 | */ |
mbed_official | 146:f64d43ff0c18 | 1267 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1268 | #define HW_RTC_WAR_ADDR (REGS_RTC_BASE + 0x800U) |
mbed_official | 146:f64d43ff0c18 | 1269 | |
mbed_official | 146:f64d43ff0c18 | 1270 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1271 | #define HW_RTC_WAR (*(__IO hw_rtc_war_t *) HW_RTC_WAR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1272 | #define HW_RTC_WAR_RD() (HW_RTC_WAR.U) |
mbed_official | 146:f64d43ff0c18 | 1273 | #define HW_RTC_WAR_WR(v) (HW_RTC_WAR.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1274 | #define HW_RTC_WAR_SET(v) (HW_RTC_WAR_WR(HW_RTC_WAR_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1275 | #define HW_RTC_WAR_CLR(v) (HW_RTC_WAR_WR(HW_RTC_WAR_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1276 | #define HW_RTC_WAR_TOG(v) (HW_RTC_WAR_WR(HW_RTC_WAR_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1277 | #endif |
mbed_official | 146:f64d43ff0c18 | 1278 | //@} |
mbed_official | 146:f64d43ff0c18 | 1279 | |
mbed_official | 146:f64d43ff0c18 | 1280 | /* |
mbed_official | 146:f64d43ff0c18 | 1281 | * Constants & macros for individual RTC_WAR bitfields |
mbed_official | 146:f64d43ff0c18 | 1282 | */ |
mbed_official | 146:f64d43ff0c18 | 1283 | |
mbed_official | 146:f64d43ff0c18 | 1284 | /*! |
mbed_official | 146:f64d43ff0c18 | 1285 | * @name Register RTC_WAR, field TSRW[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1286 | * |
mbed_official | 146:f64d43ff0c18 | 1287 | * After being cleared, this bit is set only by system reset. It is not affected |
mbed_official | 146:f64d43ff0c18 | 1288 | * by VBAT POR or software reset. |
mbed_official | 146:f64d43ff0c18 | 1289 | * |
mbed_official | 146:f64d43ff0c18 | 1290 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1291 | * - 0 - Writes to the Time Seconds Register are ignored. |
mbed_official | 146:f64d43ff0c18 | 1292 | * - 1 - Writes to the Time Seconds Register complete as normal. |
mbed_official | 146:f64d43ff0c18 | 1293 | */ |
mbed_official | 146:f64d43ff0c18 | 1294 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1295 | #define BP_RTC_WAR_TSRW (0U) //!< Bit position for RTC_WAR_TSRW. |
mbed_official | 146:f64d43ff0c18 | 1296 | #define BM_RTC_WAR_TSRW (0x00000001U) //!< Bit mask for RTC_WAR_TSRW. |
mbed_official | 146:f64d43ff0c18 | 1297 | #define BS_RTC_WAR_TSRW (1U) //!< Bit field size in bits for RTC_WAR_TSRW. |
mbed_official | 146:f64d43ff0c18 | 1298 | |
mbed_official | 146:f64d43ff0c18 | 1299 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1300 | //! @brief Read current value of the RTC_WAR_TSRW field. |
mbed_official | 146:f64d43ff0c18 | 1301 | #define BR_RTC_WAR_TSRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TSRW)) |
mbed_official | 146:f64d43ff0c18 | 1302 | #endif |
mbed_official | 146:f64d43ff0c18 | 1303 | |
mbed_official | 146:f64d43ff0c18 | 1304 | //! @brief Format value for bitfield RTC_WAR_TSRW. |
mbed_official | 146:f64d43ff0c18 | 1305 | #define BF_RTC_WAR_TSRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_TSRW), uint32_t) & BM_RTC_WAR_TSRW) |
mbed_official | 146:f64d43ff0c18 | 1306 | |
mbed_official | 146:f64d43ff0c18 | 1307 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1308 | //! @brief Set the TSRW field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1309 | #define BW_RTC_WAR_TSRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TSRW) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1310 | #endif |
mbed_official | 146:f64d43ff0c18 | 1311 | //@} |
mbed_official | 146:f64d43ff0c18 | 1312 | |
mbed_official | 146:f64d43ff0c18 | 1313 | /*! |
mbed_official | 146:f64d43ff0c18 | 1314 | * @name Register RTC_WAR, field TPRW[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 1315 | * |
mbed_official | 146:f64d43ff0c18 | 1316 | * After being cleared, this bit is set only by system reset. It is not affected |
mbed_official | 146:f64d43ff0c18 | 1317 | * by VBAT POR or software reset. |
mbed_official | 146:f64d43ff0c18 | 1318 | * |
mbed_official | 146:f64d43ff0c18 | 1319 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1320 | * - 0 - Writes to the Time Prescaler Register are ignored. |
mbed_official | 146:f64d43ff0c18 | 1321 | * - 1 - Writes to the Time Prescaler Register complete as normal. |
mbed_official | 146:f64d43ff0c18 | 1322 | */ |
mbed_official | 146:f64d43ff0c18 | 1323 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1324 | #define BP_RTC_WAR_TPRW (1U) //!< Bit position for RTC_WAR_TPRW. |
mbed_official | 146:f64d43ff0c18 | 1325 | #define BM_RTC_WAR_TPRW (0x00000002U) //!< Bit mask for RTC_WAR_TPRW. |
mbed_official | 146:f64d43ff0c18 | 1326 | #define BS_RTC_WAR_TPRW (1U) //!< Bit field size in bits for RTC_WAR_TPRW. |
mbed_official | 146:f64d43ff0c18 | 1327 | |
mbed_official | 146:f64d43ff0c18 | 1328 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1329 | //! @brief Read current value of the RTC_WAR_TPRW field. |
mbed_official | 146:f64d43ff0c18 | 1330 | #define BR_RTC_WAR_TPRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TPRW)) |
mbed_official | 146:f64d43ff0c18 | 1331 | #endif |
mbed_official | 146:f64d43ff0c18 | 1332 | |
mbed_official | 146:f64d43ff0c18 | 1333 | //! @brief Format value for bitfield RTC_WAR_TPRW. |
mbed_official | 146:f64d43ff0c18 | 1334 | #define BF_RTC_WAR_TPRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_TPRW), uint32_t) & BM_RTC_WAR_TPRW) |
mbed_official | 146:f64d43ff0c18 | 1335 | |
mbed_official | 146:f64d43ff0c18 | 1336 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1337 | //! @brief Set the TPRW field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1338 | #define BW_RTC_WAR_TPRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TPRW) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1339 | #endif |
mbed_official | 146:f64d43ff0c18 | 1340 | //@} |
mbed_official | 146:f64d43ff0c18 | 1341 | |
mbed_official | 146:f64d43ff0c18 | 1342 | /*! |
mbed_official | 146:f64d43ff0c18 | 1343 | * @name Register RTC_WAR, field TARW[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 1344 | * |
mbed_official | 146:f64d43ff0c18 | 1345 | * After being cleared, this bit is set only by system reset. It is not affected |
mbed_official | 146:f64d43ff0c18 | 1346 | * by VBAT POR or software reset. |
mbed_official | 146:f64d43ff0c18 | 1347 | * |
mbed_official | 146:f64d43ff0c18 | 1348 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1349 | * - 0 - Writes to the Time Alarm Register are ignored. |
mbed_official | 146:f64d43ff0c18 | 1350 | * - 1 - Writes to the Time Alarm Register complete as normal. |
mbed_official | 146:f64d43ff0c18 | 1351 | */ |
mbed_official | 146:f64d43ff0c18 | 1352 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1353 | #define BP_RTC_WAR_TARW (2U) //!< Bit position for RTC_WAR_TARW. |
mbed_official | 146:f64d43ff0c18 | 1354 | #define BM_RTC_WAR_TARW (0x00000004U) //!< Bit mask for RTC_WAR_TARW. |
mbed_official | 146:f64d43ff0c18 | 1355 | #define BS_RTC_WAR_TARW (1U) //!< Bit field size in bits for RTC_WAR_TARW. |
mbed_official | 146:f64d43ff0c18 | 1356 | |
mbed_official | 146:f64d43ff0c18 | 1357 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1358 | //! @brief Read current value of the RTC_WAR_TARW field. |
mbed_official | 146:f64d43ff0c18 | 1359 | #define BR_RTC_WAR_TARW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TARW)) |
mbed_official | 146:f64d43ff0c18 | 1360 | #endif |
mbed_official | 146:f64d43ff0c18 | 1361 | |
mbed_official | 146:f64d43ff0c18 | 1362 | //! @brief Format value for bitfield RTC_WAR_TARW. |
mbed_official | 146:f64d43ff0c18 | 1363 | #define BF_RTC_WAR_TARW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_TARW), uint32_t) & BM_RTC_WAR_TARW) |
mbed_official | 146:f64d43ff0c18 | 1364 | |
mbed_official | 146:f64d43ff0c18 | 1365 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1366 | //! @brief Set the TARW field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1367 | #define BW_RTC_WAR_TARW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TARW) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1368 | #endif |
mbed_official | 146:f64d43ff0c18 | 1369 | //@} |
mbed_official | 146:f64d43ff0c18 | 1370 | |
mbed_official | 146:f64d43ff0c18 | 1371 | /*! |
mbed_official | 146:f64d43ff0c18 | 1372 | * @name Register RTC_WAR, field TCRW[3] (RW) |
mbed_official | 146:f64d43ff0c18 | 1373 | * |
mbed_official | 146:f64d43ff0c18 | 1374 | * After being cleared, this bit is set only by system reset. It is not affected |
mbed_official | 146:f64d43ff0c18 | 1375 | * by VBAT POR or software reset. |
mbed_official | 146:f64d43ff0c18 | 1376 | * |
mbed_official | 146:f64d43ff0c18 | 1377 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1378 | * - 0 - Writes to the Time Compensation Register are ignored. |
mbed_official | 146:f64d43ff0c18 | 1379 | * - 1 - Writes to the Time Compensation Register complete as normal. |
mbed_official | 146:f64d43ff0c18 | 1380 | */ |
mbed_official | 146:f64d43ff0c18 | 1381 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1382 | #define BP_RTC_WAR_TCRW (3U) //!< Bit position for RTC_WAR_TCRW. |
mbed_official | 146:f64d43ff0c18 | 1383 | #define BM_RTC_WAR_TCRW (0x00000008U) //!< Bit mask for RTC_WAR_TCRW. |
mbed_official | 146:f64d43ff0c18 | 1384 | #define BS_RTC_WAR_TCRW (1U) //!< Bit field size in bits for RTC_WAR_TCRW. |
mbed_official | 146:f64d43ff0c18 | 1385 | |
mbed_official | 146:f64d43ff0c18 | 1386 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1387 | //! @brief Read current value of the RTC_WAR_TCRW field. |
mbed_official | 146:f64d43ff0c18 | 1388 | #define BR_RTC_WAR_TCRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TCRW)) |
mbed_official | 146:f64d43ff0c18 | 1389 | #endif |
mbed_official | 146:f64d43ff0c18 | 1390 | |
mbed_official | 146:f64d43ff0c18 | 1391 | //! @brief Format value for bitfield RTC_WAR_TCRW. |
mbed_official | 146:f64d43ff0c18 | 1392 | #define BF_RTC_WAR_TCRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_TCRW), uint32_t) & BM_RTC_WAR_TCRW) |
mbed_official | 146:f64d43ff0c18 | 1393 | |
mbed_official | 146:f64d43ff0c18 | 1394 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1395 | //! @brief Set the TCRW field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1396 | #define BW_RTC_WAR_TCRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TCRW) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1397 | #endif |
mbed_official | 146:f64d43ff0c18 | 1398 | //@} |
mbed_official | 146:f64d43ff0c18 | 1399 | |
mbed_official | 146:f64d43ff0c18 | 1400 | /*! |
mbed_official | 146:f64d43ff0c18 | 1401 | * @name Register RTC_WAR, field CRW[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 1402 | * |
mbed_official | 146:f64d43ff0c18 | 1403 | * After being cleared, this bit is set only by system reset. It is not affected |
mbed_official | 146:f64d43ff0c18 | 1404 | * by VBAT POR or software reset. |
mbed_official | 146:f64d43ff0c18 | 1405 | * |
mbed_official | 146:f64d43ff0c18 | 1406 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1407 | * - 0 - Writes to the Control Register are ignored. |
mbed_official | 146:f64d43ff0c18 | 1408 | * - 1 - Writes to the Control Register complete as normal. |
mbed_official | 146:f64d43ff0c18 | 1409 | */ |
mbed_official | 146:f64d43ff0c18 | 1410 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1411 | #define BP_RTC_WAR_CRW (4U) //!< Bit position for RTC_WAR_CRW. |
mbed_official | 146:f64d43ff0c18 | 1412 | #define BM_RTC_WAR_CRW (0x00000010U) //!< Bit mask for RTC_WAR_CRW. |
mbed_official | 146:f64d43ff0c18 | 1413 | #define BS_RTC_WAR_CRW (1U) //!< Bit field size in bits for RTC_WAR_CRW. |
mbed_official | 146:f64d43ff0c18 | 1414 | |
mbed_official | 146:f64d43ff0c18 | 1415 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1416 | //! @brief Read current value of the RTC_WAR_CRW field. |
mbed_official | 146:f64d43ff0c18 | 1417 | #define BR_RTC_WAR_CRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_CRW)) |
mbed_official | 146:f64d43ff0c18 | 1418 | #endif |
mbed_official | 146:f64d43ff0c18 | 1419 | |
mbed_official | 146:f64d43ff0c18 | 1420 | //! @brief Format value for bitfield RTC_WAR_CRW. |
mbed_official | 146:f64d43ff0c18 | 1421 | #define BF_RTC_WAR_CRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_CRW), uint32_t) & BM_RTC_WAR_CRW) |
mbed_official | 146:f64d43ff0c18 | 1422 | |
mbed_official | 146:f64d43ff0c18 | 1423 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1424 | //! @brief Set the CRW field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1425 | #define BW_RTC_WAR_CRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_CRW) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1426 | #endif |
mbed_official | 146:f64d43ff0c18 | 1427 | //@} |
mbed_official | 146:f64d43ff0c18 | 1428 | |
mbed_official | 146:f64d43ff0c18 | 1429 | /*! |
mbed_official | 146:f64d43ff0c18 | 1430 | * @name Register RTC_WAR, field SRW[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 1431 | * |
mbed_official | 146:f64d43ff0c18 | 1432 | * After being cleared, this bit is set only by system reset. It is not affected |
mbed_official | 146:f64d43ff0c18 | 1433 | * by VBAT POR or software reset. |
mbed_official | 146:f64d43ff0c18 | 1434 | * |
mbed_official | 146:f64d43ff0c18 | 1435 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1436 | * - 0 - Writes to the Status Register are ignored. |
mbed_official | 146:f64d43ff0c18 | 1437 | * - 1 - Writes to the Status Register complete as normal. |
mbed_official | 146:f64d43ff0c18 | 1438 | */ |
mbed_official | 146:f64d43ff0c18 | 1439 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1440 | #define BP_RTC_WAR_SRW (5U) //!< Bit position for RTC_WAR_SRW. |
mbed_official | 146:f64d43ff0c18 | 1441 | #define BM_RTC_WAR_SRW (0x00000020U) //!< Bit mask for RTC_WAR_SRW. |
mbed_official | 146:f64d43ff0c18 | 1442 | #define BS_RTC_WAR_SRW (1U) //!< Bit field size in bits for RTC_WAR_SRW. |
mbed_official | 146:f64d43ff0c18 | 1443 | |
mbed_official | 146:f64d43ff0c18 | 1444 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1445 | //! @brief Read current value of the RTC_WAR_SRW field. |
mbed_official | 146:f64d43ff0c18 | 1446 | #define BR_RTC_WAR_SRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_SRW)) |
mbed_official | 146:f64d43ff0c18 | 1447 | #endif |
mbed_official | 146:f64d43ff0c18 | 1448 | |
mbed_official | 146:f64d43ff0c18 | 1449 | //! @brief Format value for bitfield RTC_WAR_SRW. |
mbed_official | 146:f64d43ff0c18 | 1450 | #define BF_RTC_WAR_SRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_SRW), uint32_t) & BM_RTC_WAR_SRW) |
mbed_official | 146:f64d43ff0c18 | 1451 | |
mbed_official | 146:f64d43ff0c18 | 1452 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1453 | //! @brief Set the SRW field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1454 | #define BW_RTC_WAR_SRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_SRW) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1455 | #endif |
mbed_official | 146:f64d43ff0c18 | 1456 | //@} |
mbed_official | 146:f64d43ff0c18 | 1457 | |
mbed_official | 146:f64d43ff0c18 | 1458 | /*! |
mbed_official | 146:f64d43ff0c18 | 1459 | * @name Register RTC_WAR, field LRW[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 1460 | * |
mbed_official | 146:f64d43ff0c18 | 1461 | * After being cleared, this bit is set only by system reset. It is not affected |
mbed_official | 146:f64d43ff0c18 | 1462 | * by VBAT POR or software reset. |
mbed_official | 146:f64d43ff0c18 | 1463 | * |
mbed_official | 146:f64d43ff0c18 | 1464 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1465 | * - 0 - Writes to the Lock Register are ignored. |
mbed_official | 146:f64d43ff0c18 | 1466 | * - 1 - Writes to the Lock Register complete as normal. |
mbed_official | 146:f64d43ff0c18 | 1467 | */ |
mbed_official | 146:f64d43ff0c18 | 1468 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1469 | #define BP_RTC_WAR_LRW (6U) //!< Bit position for RTC_WAR_LRW. |
mbed_official | 146:f64d43ff0c18 | 1470 | #define BM_RTC_WAR_LRW (0x00000040U) //!< Bit mask for RTC_WAR_LRW. |
mbed_official | 146:f64d43ff0c18 | 1471 | #define BS_RTC_WAR_LRW (1U) //!< Bit field size in bits for RTC_WAR_LRW. |
mbed_official | 146:f64d43ff0c18 | 1472 | |
mbed_official | 146:f64d43ff0c18 | 1473 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1474 | //! @brief Read current value of the RTC_WAR_LRW field. |
mbed_official | 146:f64d43ff0c18 | 1475 | #define BR_RTC_WAR_LRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_LRW)) |
mbed_official | 146:f64d43ff0c18 | 1476 | #endif |
mbed_official | 146:f64d43ff0c18 | 1477 | |
mbed_official | 146:f64d43ff0c18 | 1478 | //! @brief Format value for bitfield RTC_WAR_LRW. |
mbed_official | 146:f64d43ff0c18 | 1479 | #define BF_RTC_WAR_LRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_LRW), uint32_t) & BM_RTC_WAR_LRW) |
mbed_official | 146:f64d43ff0c18 | 1480 | |
mbed_official | 146:f64d43ff0c18 | 1481 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1482 | //! @brief Set the LRW field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1483 | #define BW_RTC_WAR_LRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_LRW) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1484 | #endif |
mbed_official | 146:f64d43ff0c18 | 1485 | //@} |
mbed_official | 146:f64d43ff0c18 | 1486 | |
mbed_official | 146:f64d43ff0c18 | 1487 | /*! |
mbed_official | 146:f64d43ff0c18 | 1488 | * @name Register RTC_WAR, field IERW[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 1489 | * |
mbed_official | 146:f64d43ff0c18 | 1490 | * After being cleared, this bit is set only by system reset. It is not affected |
mbed_official | 146:f64d43ff0c18 | 1491 | * by VBAT POR or software reset. |
mbed_official | 146:f64d43ff0c18 | 1492 | * |
mbed_official | 146:f64d43ff0c18 | 1493 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1494 | * - 0 - Writes to the Interupt Enable Register are ignored. |
mbed_official | 146:f64d43ff0c18 | 1495 | * - 1 - Writes to the Interrupt Enable Register complete as normal. |
mbed_official | 146:f64d43ff0c18 | 1496 | */ |
mbed_official | 146:f64d43ff0c18 | 1497 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1498 | #define BP_RTC_WAR_IERW (7U) //!< Bit position for RTC_WAR_IERW. |
mbed_official | 146:f64d43ff0c18 | 1499 | #define BM_RTC_WAR_IERW (0x00000080U) //!< Bit mask for RTC_WAR_IERW. |
mbed_official | 146:f64d43ff0c18 | 1500 | #define BS_RTC_WAR_IERW (1U) //!< Bit field size in bits for RTC_WAR_IERW. |
mbed_official | 146:f64d43ff0c18 | 1501 | |
mbed_official | 146:f64d43ff0c18 | 1502 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1503 | //! @brief Read current value of the RTC_WAR_IERW field. |
mbed_official | 146:f64d43ff0c18 | 1504 | #define BR_RTC_WAR_IERW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_IERW)) |
mbed_official | 146:f64d43ff0c18 | 1505 | #endif |
mbed_official | 146:f64d43ff0c18 | 1506 | |
mbed_official | 146:f64d43ff0c18 | 1507 | //! @brief Format value for bitfield RTC_WAR_IERW. |
mbed_official | 146:f64d43ff0c18 | 1508 | #define BF_RTC_WAR_IERW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_IERW), uint32_t) & BM_RTC_WAR_IERW) |
mbed_official | 146:f64d43ff0c18 | 1509 | |
mbed_official | 146:f64d43ff0c18 | 1510 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1511 | //! @brief Set the IERW field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1512 | #define BW_RTC_WAR_IERW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_IERW) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1513 | #endif |
mbed_official | 146:f64d43ff0c18 | 1514 | //@} |
mbed_official | 146:f64d43ff0c18 | 1515 | |
mbed_official | 146:f64d43ff0c18 | 1516 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1517 | // HW_RTC_RAR - RTC Read Access Register |
mbed_official | 146:f64d43ff0c18 | 1518 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1519 | |
mbed_official | 146:f64d43ff0c18 | 1520 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1521 | /*! |
mbed_official | 146:f64d43ff0c18 | 1522 | * @brief HW_RTC_RAR - RTC Read Access Register (RW) |
mbed_official | 146:f64d43ff0c18 | 1523 | * |
mbed_official | 146:f64d43ff0c18 | 1524 | * Reset value: 0x000000FFU |
mbed_official | 146:f64d43ff0c18 | 1525 | */ |
mbed_official | 146:f64d43ff0c18 | 1526 | typedef union _hw_rtc_rar |
mbed_official | 146:f64d43ff0c18 | 1527 | { |
mbed_official | 146:f64d43ff0c18 | 1528 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 1529 | struct _hw_rtc_rar_bitfields |
mbed_official | 146:f64d43ff0c18 | 1530 | { |
mbed_official | 146:f64d43ff0c18 | 1531 | uint32_t TSRR : 1; //!< [0] Time Seconds Register Read |
mbed_official | 146:f64d43ff0c18 | 1532 | uint32_t TPRR : 1; //!< [1] Time Prescaler Register Read |
mbed_official | 146:f64d43ff0c18 | 1533 | uint32_t TARR : 1; //!< [2] Time Alarm Register Read |
mbed_official | 146:f64d43ff0c18 | 1534 | uint32_t TCRR : 1; //!< [3] Time Compensation Register Read |
mbed_official | 146:f64d43ff0c18 | 1535 | uint32_t CRR : 1; //!< [4] Control Register Read |
mbed_official | 146:f64d43ff0c18 | 1536 | uint32_t SRR : 1; //!< [5] Status Register Read |
mbed_official | 146:f64d43ff0c18 | 1537 | uint32_t LRR : 1; //!< [6] Lock Register Read |
mbed_official | 146:f64d43ff0c18 | 1538 | uint32_t IERR : 1; //!< [7] Interrupt Enable Register Read |
mbed_official | 146:f64d43ff0c18 | 1539 | uint32_t RESERVED0 : 24; //!< [31:8] |
mbed_official | 146:f64d43ff0c18 | 1540 | } B; |
mbed_official | 146:f64d43ff0c18 | 1541 | } hw_rtc_rar_t; |
mbed_official | 146:f64d43ff0c18 | 1542 | #endif |
mbed_official | 146:f64d43ff0c18 | 1543 | |
mbed_official | 146:f64d43ff0c18 | 1544 | /*! |
mbed_official | 146:f64d43ff0c18 | 1545 | * @name Constants and macros for entire RTC_RAR register |
mbed_official | 146:f64d43ff0c18 | 1546 | */ |
mbed_official | 146:f64d43ff0c18 | 1547 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1548 | #define HW_RTC_RAR_ADDR (REGS_RTC_BASE + 0x804U) |
mbed_official | 146:f64d43ff0c18 | 1549 | |
mbed_official | 146:f64d43ff0c18 | 1550 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1551 | #define HW_RTC_RAR (*(__IO hw_rtc_rar_t *) HW_RTC_RAR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1552 | #define HW_RTC_RAR_RD() (HW_RTC_RAR.U) |
mbed_official | 146:f64d43ff0c18 | 1553 | #define HW_RTC_RAR_WR(v) (HW_RTC_RAR.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1554 | #define HW_RTC_RAR_SET(v) (HW_RTC_RAR_WR(HW_RTC_RAR_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1555 | #define HW_RTC_RAR_CLR(v) (HW_RTC_RAR_WR(HW_RTC_RAR_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1556 | #define HW_RTC_RAR_TOG(v) (HW_RTC_RAR_WR(HW_RTC_RAR_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1557 | #endif |
mbed_official | 146:f64d43ff0c18 | 1558 | //@} |
mbed_official | 146:f64d43ff0c18 | 1559 | |
mbed_official | 146:f64d43ff0c18 | 1560 | /* |
mbed_official | 146:f64d43ff0c18 | 1561 | * Constants & macros for individual RTC_RAR bitfields |
mbed_official | 146:f64d43ff0c18 | 1562 | */ |
mbed_official | 146:f64d43ff0c18 | 1563 | |
mbed_official | 146:f64d43ff0c18 | 1564 | /*! |
mbed_official | 146:f64d43ff0c18 | 1565 | * @name Register RTC_RAR, field TSRR[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1566 | * |
mbed_official | 146:f64d43ff0c18 | 1567 | * After being cleared, this bit is set only by system reset. It is not affected |
mbed_official | 146:f64d43ff0c18 | 1568 | * by VBAT POR or software reset. |
mbed_official | 146:f64d43ff0c18 | 1569 | * |
mbed_official | 146:f64d43ff0c18 | 1570 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1571 | * - 0 - Reads to the Time Seconds Register are ignored. |
mbed_official | 146:f64d43ff0c18 | 1572 | * - 1 - Reads to the Time Seconds Register complete as normal. |
mbed_official | 146:f64d43ff0c18 | 1573 | */ |
mbed_official | 146:f64d43ff0c18 | 1574 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1575 | #define BP_RTC_RAR_TSRR (0U) //!< Bit position for RTC_RAR_TSRR. |
mbed_official | 146:f64d43ff0c18 | 1576 | #define BM_RTC_RAR_TSRR (0x00000001U) //!< Bit mask for RTC_RAR_TSRR. |
mbed_official | 146:f64d43ff0c18 | 1577 | #define BS_RTC_RAR_TSRR (1U) //!< Bit field size in bits for RTC_RAR_TSRR. |
mbed_official | 146:f64d43ff0c18 | 1578 | |
mbed_official | 146:f64d43ff0c18 | 1579 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1580 | //! @brief Read current value of the RTC_RAR_TSRR field. |
mbed_official | 146:f64d43ff0c18 | 1581 | #define BR_RTC_RAR_TSRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TSRR)) |
mbed_official | 146:f64d43ff0c18 | 1582 | #endif |
mbed_official | 146:f64d43ff0c18 | 1583 | |
mbed_official | 146:f64d43ff0c18 | 1584 | //! @brief Format value for bitfield RTC_RAR_TSRR. |
mbed_official | 146:f64d43ff0c18 | 1585 | #define BF_RTC_RAR_TSRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_TSRR), uint32_t) & BM_RTC_RAR_TSRR) |
mbed_official | 146:f64d43ff0c18 | 1586 | |
mbed_official | 146:f64d43ff0c18 | 1587 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1588 | //! @brief Set the TSRR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1589 | #define BW_RTC_RAR_TSRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TSRR) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1590 | #endif |
mbed_official | 146:f64d43ff0c18 | 1591 | //@} |
mbed_official | 146:f64d43ff0c18 | 1592 | |
mbed_official | 146:f64d43ff0c18 | 1593 | /*! |
mbed_official | 146:f64d43ff0c18 | 1594 | * @name Register RTC_RAR, field TPRR[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 1595 | * |
mbed_official | 146:f64d43ff0c18 | 1596 | * After being cleared, this bit is set only by system reset. It is not affected |
mbed_official | 146:f64d43ff0c18 | 1597 | * by VBAT POR or software reset. |
mbed_official | 146:f64d43ff0c18 | 1598 | * |
mbed_official | 146:f64d43ff0c18 | 1599 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1600 | * - 0 - Reads to the Time Pprescaler Register are ignored. |
mbed_official | 146:f64d43ff0c18 | 1601 | * - 1 - Reads to the Time Prescaler Register complete as normal. |
mbed_official | 146:f64d43ff0c18 | 1602 | */ |
mbed_official | 146:f64d43ff0c18 | 1603 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1604 | #define BP_RTC_RAR_TPRR (1U) //!< Bit position for RTC_RAR_TPRR. |
mbed_official | 146:f64d43ff0c18 | 1605 | #define BM_RTC_RAR_TPRR (0x00000002U) //!< Bit mask for RTC_RAR_TPRR. |
mbed_official | 146:f64d43ff0c18 | 1606 | #define BS_RTC_RAR_TPRR (1U) //!< Bit field size in bits for RTC_RAR_TPRR. |
mbed_official | 146:f64d43ff0c18 | 1607 | |
mbed_official | 146:f64d43ff0c18 | 1608 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1609 | //! @brief Read current value of the RTC_RAR_TPRR field. |
mbed_official | 146:f64d43ff0c18 | 1610 | #define BR_RTC_RAR_TPRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TPRR)) |
mbed_official | 146:f64d43ff0c18 | 1611 | #endif |
mbed_official | 146:f64d43ff0c18 | 1612 | |
mbed_official | 146:f64d43ff0c18 | 1613 | //! @brief Format value for bitfield RTC_RAR_TPRR. |
mbed_official | 146:f64d43ff0c18 | 1614 | #define BF_RTC_RAR_TPRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_TPRR), uint32_t) & BM_RTC_RAR_TPRR) |
mbed_official | 146:f64d43ff0c18 | 1615 | |
mbed_official | 146:f64d43ff0c18 | 1616 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1617 | //! @brief Set the TPRR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1618 | #define BW_RTC_RAR_TPRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TPRR) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1619 | #endif |
mbed_official | 146:f64d43ff0c18 | 1620 | //@} |
mbed_official | 146:f64d43ff0c18 | 1621 | |
mbed_official | 146:f64d43ff0c18 | 1622 | /*! |
mbed_official | 146:f64d43ff0c18 | 1623 | * @name Register RTC_RAR, field TARR[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 1624 | * |
mbed_official | 146:f64d43ff0c18 | 1625 | * After being cleared, this bit is set only by system reset. It is not affected |
mbed_official | 146:f64d43ff0c18 | 1626 | * by VBAT POR or software reset. |
mbed_official | 146:f64d43ff0c18 | 1627 | * |
mbed_official | 146:f64d43ff0c18 | 1628 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1629 | * - 0 - Reads to the Time Alarm Register are ignored. |
mbed_official | 146:f64d43ff0c18 | 1630 | * - 1 - Reads to the Time Alarm Register complete as normal. |
mbed_official | 146:f64d43ff0c18 | 1631 | */ |
mbed_official | 146:f64d43ff0c18 | 1632 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1633 | #define BP_RTC_RAR_TARR (2U) //!< Bit position for RTC_RAR_TARR. |
mbed_official | 146:f64d43ff0c18 | 1634 | #define BM_RTC_RAR_TARR (0x00000004U) //!< Bit mask for RTC_RAR_TARR. |
mbed_official | 146:f64d43ff0c18 | 1635 | #define BS_RTC_RAR_TARR (1U) //!< Bit field size in bits for RTC_RAR_TARR. |
mbed_official | 146:f64d43ff0c18 | 1636 | |
mbed_official | 146:f64d43ff0c18 | 1637 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1638 | //! @brief Read current value of the RTC_RAR_TARR field. |
mbed_official | 146:f64d43ff0c18 | 1639 | #define BR_RTC_RAR_TARR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TARR)) |
mbed_official | 146:f64d43ff0c18 | 1640 | #endif |
mbed_official | 146:f64d43ff0c18 | 1641 | |
mbed_official | 146:f64d43ff0c18 | 1642 | //! @brief Format value for bitfield RTC_RAR_TARR. |
mbed_official | 146:f64d43ff0c18 | 1643 | #define BF_RTC_RAR_TARR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_TARR), uint32_t) & BM_RTC_RAR_TARR) |
mbed_official | 146:f64d43ff0c18 | 1644 | |
mbed_official | 146:f64d43ff0c18 | 1645 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1646 | //! @brief Set the TARR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1647 | #define BW_RTC_RAR_TARR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TARR) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1648 | #endif |
mbed_official | 146:f64d43ff0c18 | 1649 | //@} |
mbed_official | 146:f64d43ff0c18 | 1650 | |
mbed_official | 146:f64d43ff0c18 | 1651 | /*! |
mbed_official | 146:f64d43ff0c18 | 1652 | * @name Register RTC_RAR, field TCRR[3] (RW) |
mbed_official | 146:f64d43ff0c18 | 1653 | * |
mbed_official | 146:f64d43ff0c18 | 1654 | * After being cleared, this bit is set only by system reset. It is not affected |
mbed_official | 146:f64d43ff0c18 | 1655 | * by VBAT POR or software reset. |
mbed_official | 146:f64d43ff0c18 | 1656 | * |
mbed_official | 146:f64d43ff0c18 | 1657 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1658 | * - 0 - Reads to the Time Compensation Register are ignored. |
mbed_official | 146:f64d43ff0c18 | 1659 | * - 1 - Reads to the Time Compensation Register complete as normal. |
mbed_official | 146:f64d43ff0c18 | 1660 | */ |
mbed_official | 146:f64d43ff0c18 | 1661 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1662 | #define BP_RTC_RAR_TCRR (3U) //!< Bit position for RTC_RAR_TCRR. |
mbed_official | 146:f64d43ff0c18 | 1663 | #define BM_RTC_RAR_TCRR (0x00000008U) //!< Bit mask for RTC_RAR_TCRR. |
mbed_official | 146:f64d43ff0c18 | 1664 | #define BS_RTC_RAR_TCRR (1U) //!< Bit field size in bits for RTC_RAR_TCRR. |
mbed_official | 146:f64d43ff0c18 | 1665 | |
mbed_official | 146:f64d43ff0c18 | 1666 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1667 | //! @brief Read current value of the RTC_RAR_TCRR field. |
mbed_official | 146:f64d43ff0c18 | 1668 | #define BR_RTC_RAR_TCRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TCRR)) |
mbed_official | 146:f64d43ff0c18 | 1669 | #endif |
mbed_official | 146:f64d43ff0c18 | 1670 | |
mbed_official | 146:f64d43ff0c18 | 1671 | //! @brief Format value for bitfield RTC_RAR_TCRR. |
mbed_official | 146:f64d43ff0c18 | 1672 | #define BF_RTC_RAR_TCRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_TCRR), uint32_t) & BM_RTC_RAR_TCRR) |
mbed_official | 146:f64d43ff0c18 | 1673 | |
mbed_official | 146:f64d43ff0c18 | 1674 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1675 | //! @brief Set the TCRR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1676 | #define BW_RTC_RAR_TCRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TCRR) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1677 | #endif |
mbed_official | 146:f64d43ff0c18 | 1678 | //@} |
mbed_official | 146:f64d43ff0c18 | 1679 | |
mbed_official | 146:f64d43ff0c18 | 1680 | /*! |
mbed_official | 146:f64d43ff0c18 | 1681 | * @name Register RTC_RAR, field CRR[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 1682 | * |
mbed_official | 146:f64d43ff0c18 | 1683 | * After being cleared, this bit is set only by system reset. It is not affected |
mbed_official | 146:f64d43ff0c18 | 1684 | * by VBAT POR or software reset. |
mbed_official | 146:f64d43ff0c18 | 1685 | * |
mbed_official | 146:f64d43ff0c18 | 1686 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1687 | * - 0 - Reads to the Control Register are ignored. |
mbed_official | 146:f64d43ff0c18 | 1688 | * - 1 - Reads to the Control Register complete as normal. |
mbed_official | 146:f64d43ff0c18 | 1689 | */ |
mbed_official | 146:f64d43ff0c18 | 1690 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1691 | #define BP_RTC_RAR_CRR (4U) //!< Bit position for RTC_RAR_CRR. |
mbed_official | 146:f64d43ff0c18 | 1692 | #define BM_RTC_RAR_CRR (0x00000010U) //!< Bit mask for RTC_RAR_CRR. |
mbed_official | 146:f64d43ff0c18 | 1693 | #define BS_RTC_RAR_CRR (1U) //!< Bit field size in bits for RTC_RAR_CRR. |
mbed_official | 146:f64d43ff0c18 | 1694 | |
mbed_official | 146:f64d43ff0c18 | 1695 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1696 | //! @brief Read current value of the RTC_RAR_CRR field. |
mbed_official | 146:f64d43ff0c18 | 1697 | #define BR_RTC_RAR_CRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_CRR)) |
mbed_official | 146:f64d43ff0c18 | 1698 | #endif |
mbed_official | 146:f64d43ff0c18 | 1699 | |
mbed_official | 146:f64d43ff0c18 | 1700 | //! @brief Format value for bitfield RTC_RAR_CRR. |
mbed_official | 146:f64d43ff0c18 | 1701 | #define BF_RTC_RAR_CRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_CRR), uint32_t) & BM_RTC_RAR_CRR) |
mbed_official | 146:f64d43ff0c18 | 1702 | |
mbed_official | 146:f64d43ff0c18 | 1703 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1704 | //! @brief Set the CRR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1705 | #define BW_RTC_RAR_CRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_CRR) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1706 | #endif |
mbed_official | 146:f64d43ff0c18 | 1707 | //@} |
mbed_official | 146:f64d43ff0c18 | 1708 | |
mbed_official | 146:f64d43ff0c18 | 1709 | /*! |
mbed_official | 146:f64d43ff0c18 | 1710 | * @name Register RTC_RAR, field SRR[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 1711 | * |
mbed_official | 146:f64d43ff0c18 | 1712 | * After being cleared, this bit is set only by system reset. It is not affected |
mbed_official | 146:f64d43ff0c18 | 1713 | * by VBAT POR or software reset. |
mbed_official | 146:f64d43ff0c18 | 1714 | * |
mbed_official | 146:f64d43ff0c18 | 1715 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1716 | * - 0 - Reads to the Status Register are ignored. |
mbed_official | 146:f64d43ff0c18 | 1717 | * - 1 - Reads to the Status Register complete as normal. |
mbed_official | 146:f64d43ff0c18 | 1718 | */ |
mbed_official | 146:f64d43ff0c18 | 1719 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1720 | #define BP_RTC_RAR_SRR (5U) //!< Bit position for RTC_RAR_SRR. |
mbed_official | 146:f64d43ff0c18 | 1721 | #define BM_RTC_RAR_SRR (0x00000020U) //!< Bit mask for RTC_RAR_SRR. |
mbed_official | 146:f64d43ff0c18 | 1722 | #define BS_RTC_RAR_SRR (1U) //!< Bit field size in bits for RTC_RAR_SRR. |
mbed_official | 146:f64d43ff0c18 | 1723 | |
mbed_official | 146:f64d43ff0c18 | 1724 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1725 | //! @brief Read current value of the RTC_RAR_SRR field. |
mbed_official | 146:f64d43ff0c18 | 1726 | #define BR_RTC_RAR_SRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_SRR)) |
mbed_official | 146:f64d43ff0c18 | 1727 | #endif |
mbed_official | 146:f64d43ff0c18 | 1728 | |
mbed_official | 146:f64d43ff0c18 | 1729 | //! @brief Format value for bitfield RTC_RAR_SRR. |
mbed_official | 146:f64d43ff0c18 | 1730 | #define BF_RTC_RAR_SRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_SRR), uint32_t) & BM_RTC_RAR_SRR) |
mbed_official | 146:f64d43ff0c18 | 1731 | |
mbed_official | 146:f64d43ff0c18 | 1732 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1733 | //! @brief Set the SRR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1734 | #define BW_RTC_RAR_SRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_SRR) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1735 | #endif |
mbed_official | 146:f64d43ff0c18 | 1736 | //@} |
mbed_official | 146:f64d43ff0c18 | 1737 | |
mbed_official | 146:f64d43ff0c18 | 1738 | /*! |
mbed_official | 146:f64d43ff0c18 | 1739 | * @name Register RTC_RAR, field LRR[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 1740 | * |
mbed_official | 146:f64d43ff0c18 | 1741 | * After being cleared, this bit is set only by system reset. It is not affected |
mbed_official | 146:f64d43ff0c18 | 1742 | * by VBAT POR or software reset. |
mbed_official | 146:f64d43ff0c18 | 1743 | * |
mbed_official | 146:f64d43ff0c18 | 1744 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1745 | * - 0 - Reads to the Lock Register are ignored. |
mbed_official | 146:f64d43ff0c18 | 1746 | * - 1 - Reads to the Lock Register complete as normal. |
mbed_official | 146:f64d43ff0c18 | 1747 | */ |
mbed_official | 146:f64d43ff0c18 | 1748 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1749 | #define BP_RTC_RAR_LRR (6U) //!< Bit position for RTC_RAR_LRR. |
mbed_official | 146:f64d43ff0c18 | 1750 | #define BM_RTC_RAR_LRR (0x00000040U) //!< Bit mask for RTC_RAR_LRR. |
mbed_official | 146:f64d43ff0c18 | 1751 | #define BS_RTC_RAR_LRR (1U) //!< Bit field size in bits for RTC_RAR_LRR. |
mbed_official | 146:f64d43ff0c18 | 1752 | |
mbed_official | 146:f64d43ff0c18 | 1753 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1754 | //! @brief Read current value of the RTC_RAR_LRR field. |
mbed_official | 146:f64d43ff0c18 | 1755 | #define BR_RTC_RAR_LRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_LRR)) |
mbed_official | 146:f64d43ff0c18 | 1756 | #endif |
mbed_official | 146:f64d43ff0c18 | 1757 | |
mbed_official | 146:f64d43ff0c18 | 1758 | //! @brief Format value for bitfield RTC_RAR_LRR. |
mbed_official | 146:f64d43ff0c18 | 1759 | #define BF_RTC_RAR_LRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_LRR), uint32_t) & BM_RTC_RAR_LRR) |
mbed_official | 146:f64d43ff0c18 | 1760 | |
mbed_official | 146:f64d43ff0c18 | 1761 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1762 | //! @brief Set the LRR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1763 | #define BW_RTC_RAR_LRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_LRR) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1764 | #endif |
mbed_official | 146:f64d43ff0c18 | 1765 | //@} |
mbed_official | 146:f64d43ff0c18 | 1766 | |
mbed_official | 146:f64d43ff0c18 | 1767 | /*! |
mbed_official | 146:f64d43ff0c18 | 1768 | * @name Register RTC_RAR, field IERR[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 1769 | * |
mbed_official | 146:f64d43ff0c18 | 1770 | * After being cleared, this bit is set only by system reset. It is not affected |
mbed_official | 146:f64d43ff0c18 | 1771 | * by VBAT POR or software reset. |
mbed_official | 146:f64d43ff0c18 | 1772 | * |
mbed_official | 146:f64d43ff0c18 | 1773 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1774 | * - 0 - Reads to the Interrupt Enable Register are ignored. |
mbed_official | 146:f64d43ff0c18 | 1775 | * - 1 - Reads to the Interrupt Enable Register complete as normal. |
mbed_official | 146:f64d43ff0c18 | 1776 | */ |
mbed_official | 146:f64d43ff0c18 | 1777 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1778 | #define BP_RTC_RAR_IERR (7U) //!< Bit position for RTC_RAR_IERR. |
mbed_official | 146:f64d43ff0c18 | 1779 | #define BM_RTC_RAR_IERR (0x00000080U) //!< Bit mask for RTC_RAR_IERR. |
mbed_official | 146:f64d43ff0c18 | 1780 | #define BS_RTC_RAR_IERR (1U) //!< Bit field size in bits for RTC_RAR_IERR. |
mbed_official | 146:f64d43ff0c18 | 1781 | |
mbed_official | 146:f64d43ff0c18 | 1782 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1783 | //! @brief Read current value of the RTC_RAR_IERR field. |
mbed_official | 146:f64d43ff0c18 | 1784 | #define BR_RTC_RAR_IERR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_IERR)) |
mbed_official | 146:f64d43ff0c18 | 1785 | #endif |
mbed_official | 146:f64d43ff0c18 | 1786 | |
mbed_official | 146:f64d43ff0c18 | 1787 | //! @brief Format value for bitfield RTC_RAR_IERR. |
mbed_official | 146:f64d43ff0c18 | 1788 | #define BF_RTC_RAR_IERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_IERR), uint32_t) & BM_RTC_RAR_IERR) |
mbed_official | 146:f64d43ff0c18 | 1789 | |
mbed_official | 146:f64d43ff0c18 | 1790 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1791 | //! @brief Set the IERR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1792 | #define BW_RTC_RAR_IERR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_IERR) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1793 | #endif |
mbed_official | 146:f64d43ff0c18 | 1794 | //@} |
mbed_official | 146:f64d43ff0c18 | 1795 | |
mbed_official | 146:f64d43ff0c18 | 1796 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1797 | // hw_rtc_t - module struct |
mbed_official | 146:f64d43ff0c18 | 1798 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1799 | /*! |
mbed_official | 146:f64d43ff0c18 | 1800 | * @brief All RTC module registers. |
mbed_official | 146:f64d43ff0c18 | 1801 | */ |
mbed_official | 146:f64d43ff0c18 | 1802 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1803 | #pragma pack(1) |
mbed_official | 146:f64d43ff0c18 | 1804 | typedef struct _hw_rtc |
mbed_official | 146:f64d43ff0c18 | 1805 | { |
mbed_official | 146:f64d43ff0c18 | 1806 | __IO hw_rtc_tsr_t TSR; //!< [0x0] RTC Time Seconds Register |
mbed_official | 146:f64d43ff0c18 | 1807 | __IO hw_rtc_tpr_t TPR; //!< [0x4] RTC Time Prescaler Register |
mbed_official | 146:f64d43ff0c18 | 1808 | __IO hw_rtc_tar_t TAR; //!< [0x8] RTC Time Alarm Register |
mbed_official | 146:f64d43ff0c18 | 1809 | __IO hw_rtc_tcr_t TCR; //!< [0xC] RTC Time Compensation Register |
mbed_official | 146:f64d43ff0c18 | 1810 | __IO hw_rtc_cr_t CR; //!< [0x10] RTC Control Register |
mbed_official | 146:f64d43ff0c18 | 1811 | __IO hw_rtc_sr_t SR; //!< [0x14] RTC Status Register |
mbed_official | 146:f64d43ff0c18 | 1812 | __IO hw_rtc_lr_t LR; //!< [0x18] RTC Lock Register |
mbed_official | 146:f64d43ff0c18 | 1813 | __IO hw_rtc_ier_t IER; //!< [0x1C] RTC Interrupt Enable Register |
mbed_official | 146:f64d43ff0c18 | 1814 | uint8_t _reserved0[2016]; |
mbed_official | 146:f64d43ff0c18 | 1815 | __IO hw_rtc_war_t WAR; //!< [0x800] RTC Write Access Register |
mbed_official | 146:f64d43ff0c18 | 1816 | __IO hw_rtc_rar_t RAR; //!< [0x804] RTC Read Access Register |
mbed_official | 146:f64d43ff0c18 | 1817 | } hw_rtc_t; |
mbed_official | 146:f64d43ff0c18 | 1818 | #pragma pack() |
mbed_official | 146:f64d43ff0c18 | 1819 | |
mbed_official | 146:f64d43ff0c18 | 1820 | //! @brief Macro to access all RTC registers. |
mbed_official | 146:f64d43ff0c18 | 1821 | //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, |
mbed_official | 146:f64d43ff0c18 | 1822 | //! use the '&' operator, like <code>&HW_RTC</code>. |
mbed_official | 146:f64d43ff0c18 | 1823 | #define HW_RTC (*(hw_rtc_t *) REGS_RTC_BASE) |
mbed_official | 146:f64d43ff0c18 | 1824 | #endif |
mbed_official | 146:f64d43ff0c18 | 1825 | |
mbed_official | 146:f64d43ff0c18 | 1826 | #endif // __HW_RTC_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 1827 | // v22/130726/0.9 |
mbed_official | 146:f64d43ff0c18 | 1828 | // EOF |