Sinan Divarci / Mbed OS max4146x_comp

max4146x_comp

Dependencies:   MAX14690

max4146x/Max4146x.h@0:0061165683ee, 2020-10-25 (annotated)

Committer:
sdivarci
Date:
Sun Oct 25 20:10:02 2020 +0000
Revision:
0:0061165683ee
sdivarci

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sdivarci 0:0061165683ee 1 /*******************************************************************************
sdivarci 0:0061165683ee 2 * Copyright (C) 2019 Maxim Integrated Products, Inc., All rights Reserved.
sdivarci 0:0061165683ee 3 *
sdivarci 0:0061165683ee 4 * This software is protected by copyright laws of the United States and
sdivarci 0:0061165683ee 5 * of foreign countries. This material may also be protected by patent laws
sdivarci 0:0061165683ee 6 * and technology transfer regulations of the United States and of foreign
sdivarci 0:0061165683ee 7 * countries. This software is furnished under a license agreement and/or a
sdivarci 0:0061165683ee 8 * nondisclosure agreement and may only be used or reproduced in accordance
sdivarci 0:0061165683ee 9 * with the terms of those agreements. Dissemination of this information to
sdivarci 0:0061165683ee 10 * any party or parties not specified in the license agreement and/or
sdivarci 0:0061165683ee 11 * nondisclosure agreement is expressly prohibited.
sdivarci 0:0061165683ee 12 *
sdivarci 0:0061165683ee 13 * The above copyright notice and this permission notice shall be included
sdivarci 0:0061165683ee 14 * in all copies or substantial portions of the Software.
sdivarci 0:0061165683ee 15 *
sdivarci 0:0061165683ee 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
sdivarci 0:0061165683ee 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
sdivarci 0:0061165683ee 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
sdivarci 0:0061165683ee 19 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
sdivarci 0:0061165683ee 20 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
sdivarci 0:0061165683ee 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
sdivarci 0:0061165683ee 22 * OTHER DEALINGS IN THE SOFTWARE.
sdivarci 0:0061165683ee 23 *
sdivarci 0:0061165683ee 24 * Except as contained in this notice, the name of Maxim Integrated
sdivarci 0:0061165683ee 25 * Products, Inc. shall not be used except as stated in the Maxim Integrated
sdivarci 0:0061165683ee 26 * Products, Inc. Branding Policy.
sdivarci 0:0061165683ee 27 *
sdivarci 0:0061165683ee 28 * The mere transfer of this software does not imply any licenses
sdivarci 0:0061165683ee 29 * of trade secrets, proprietary technology, copyrights, patents,
sdivarci 0:0061165683ee 30 * trademarks, maskwork rights, or any other form of intellectual
sdivarci 0:0061165683ee 31 * property whatsoever. Maxim Integrated Products, Inc. retains all
sdivarci 0:0061165683ee 32 * ownership rights.
sdivarci 0:0061165683ee 33 *******************************************************************************
sdivarci 0:0061165683ee 34 */
sdivarci 0:0061165683ee 35
sdivarci 0:0061165683ee 36 #ifndef MAX4146x_H_
sdivarci 0:0061165683ee 37 #define MAX4146x_H_
sdivarci 0:0061165683ee 38
sdivarci 0:0061165683ee 39 #include "mbed.h"
sdivarci 0:0061165683ee 40 #include "Max41460_regs.h"
sdivarci 0:0061165683ee 41 #include "Max41461_2_regs.h"
sdivarci 0:0061165683ee 42 #include "Max41463_4_regs.h"
sdivarci 0:0061165683ee 43
sdivarci 0:0061165683ee 44 #define I2C_ADDRESS 0xD2
sdivarci 0:0061165683ee 45
sdivarci 0:0061165683ee 46 /**
sdivarci 0:0061165683ee 47 * @brief Base Class for All Maxim Max4146x RF Transmitters
sdivarci 0:0061165683ee 48 *
sdivarci 0:0061165683ee 49 * @details The MAX4146X is a UHF sub-GHz ISM/SRD transmitter
sdivarci 0:0061165683ee 50 */
sdivarci 0:0061165683ee 51 template <class REG>
sdivarci 0:0061165683ee 52 class MAX4146X
sdivarci 0:0061165683ee 53 {
sdivarci 0:0061165683ee 54 private:
sdivarci 0:0061165683ee 55 REG *reg;
sdivarci 0:0061165683ee 56 I2C *i2c_handler;
sdivarci 0:0061165683ee 57 SPI *spi_handler;
sdivarci 0:0061165683ee 58 DigitalOut *ssel;
sdivarci 0:0061165683ee 59
sdivarci 0:0061165683ee 60 //manchester coding variables
sdivarci 0:0061165683ee 61 unsigned char *manchester_bit_array;
sdivarci 0:0061165683ee 62 unsigned char *bits_array;
sdivarci 0:0061165683ee 63 static const unsigned char mask = 1; // Bit mask
sdivarci 0:0061165683ee 64 char data_rate;
sdivarci 0:0061165683ee 65 DigitalOut *data_sent; // data sent pin
sdivarci 0:0061165683ee 66
sdivarci 0:0061165683ee 67 uint8_t preset_mode;
sdivarci 0:0061165683ee 68 float crystal_frequency ;
sdivarci 0:0061165683ee 69 float center_frequency;
sdivarci 0:0061165683ee 70 float baud_rate;
sdivarci 0:0061165683ee 71
sdivarci 0:0061165683ee 72 typedef enum {
sdivarci 0:0061165683ee 73 CFG1_ADDR = 0x00,
sdivarci 0:0061165683ee 74 CFG2_ADDR = 0x01,
sdivarci 0:0061165683ee 75 CFG3_ADDR = 0x02,
sdivarci 0:0061165683ee 76 CFG4_ADDR = 0x03,
sdivarci 0:0061165683ee 77 CFG5_ADDR = 0x04,
sdivarci 0:0061165683ee 78 SHDN_ADDR = 0x05,
sdivarci 0:0061165683ee 79 PA1_ADDR = 0x06,
sdivarci 0:0061165683ee 80 PA2_ADDR = 0x07,
sdivarci 0:0061165683ee 81 PLL1_ADDR = 0x08,
sdivarci 0:0061165683ee 82 PLL2_ADDR = 0x09,
sdivarci 0:0061165683ee 83 CFG6_ADDR = 0x0A,
sdivarci 0:0061165683ee 84 PLL3_ADDR = 0x0B,
sdivarci 0:0061165683ee 85 PLL4_ADDR = 0x0C,
sdivarci 0:0061165683ee 86 PLL5_ADDR = 0x0D,
sdivarci 0:0061165683ee 87 PLL6_ADDR = 0x0E,
sdivarci 0:0061165683ee 88 PLL7_ADDR = 0x0F,
sdivarci 0:0061165683ee 89 CFG7_ADDR = 0x10,
sdivarci 0:0061165683ee 90 I2C1_ADDR = 0x11,
sdivarci 0:0061165683ee 91 I2C2_ADDR = 0x12,
sdivarci 0:0061165683ee 92 I2C3_ADDR = 0x13,
sdivarci 0:0061165683ee 93 I2C4_ADDR = 0x14,
sdivarci 0:0061165683ee 94 I2C5_ADDR = 0x15,
sdivarci 0:0061165683ee 95 I2C6_ADDR = 0x16,
sdivarci 0:0061165683ee 96 CFG8_ADDR = 0x17,
sdivarci 0:0061165683ee 97 CFG9_ADDR = 0x18,
sdivarci 0:0061165683ee 98 ADDL1_ADDR = 0x19,
sdivarci 0:0061165683ee 99 ADDL2_ADDR = 0x1A,
sdivarci 0:0061165683ee 100 } register_address_t;
sdivarci 0:0061165683ee 101
sdivarci 0:0061165683ee 102 //Functions
sdivarci 0:0061165683ee 103
sdivarci 0:0061165683ee 104 protected:
sdivarci 0:0061165683ee 105
sdivarci 0:0061165683ee 106 //Functions
sdivarci 0:0061165683ee 107 int io_write(uint8_t *data, uint32_t length);
sdivarci 0:0061165683ee 108
sdivarci 0:0061165683ee 109 public:
sdivarci 0:0061165683ee 110
sdivarci 0:0061165683ee 111 //Constructors
sdivarci 0:0061165683ee 112 MAX4146X(REG *reg, SPI *spi, DigitalOut *cs);
sdivarci 0:0061165683ee 113
sdivarci 0:0061165683ee 114 MAX4146X(REG *reg, SPI *spi);
sdivarci 0:0061165683ee 115
sdivarci 0:0061165683ee 116 MAX4146X(REG *reg, I2C *i2c);
sdivarci 0:0061165683ee 117
sdivarci 0:0061165683ee 118 MAX4146X(DigitalOut *cs);
sdivarci 0:0061165683ee 119
sdivarci 0:0061165683ee 120
sdivarci 0:0061165683ee 121 /**
sdivarci 0:0061165683ee 122 * @brief Register Configuration
sdivarci 0:0061165683ee 123 *
sdivarci 0:0061165683ee 124 * @details
sdivarci 0:0061165683ee 125 * - Register : CFG1(0x00)
sdivarci 0:0061165683ee 126 * - Bit Fields : [7:6]
sdivarci 0:0061165683ee 127 * - Default : 0x2
sdivarci 0:0061165683ee 128 * - Description : Start delay before enabling XO clock to digital block
sdivarci 0:0061165683ee 129 */
sdivarci 0:0061165683ee 130 typedef enum {
sdivarci 0:0061165683ee 131 XOCLKDELAY_0_CYCLE, /**< 0x0: No delay. XO clock is immediately enabled to rest of digital block */
sdivarci 0:0061165683ee 132 XOCLKDELAY_16_CYCLE, /**< 0x1: XO clock is enabled after 16 cycles to rest of digital block */
sdivarci 0:0061165683ee 133 XOCLKDELAY_32_CYCLE, /**< 0x2: XO clock is enabled after 32 cycles to rest of digital block */
sdivarci 0:0061165683ee 134 XOCLKDELAY_64_CYCLE, /**< 0x3: XO clock is enabled after 64 cycles to rest of digital block */
sdivarci 0:0061165683ee 135 } xoclkdelay_t;
sdivarci 0:0061165683ee 136
sdivarci 0:0061165683ee 137 /**
sdivarci 0:0061165683ee 138 * @brief Set start delay before enabling XO clock to digital block
sdivarci 0:0061165683ee 139 *
sdivarci 0:0061165683ee 140 * @param[in] delay delay cycle
sdivarci 0:0061165683ee 141 *
sdivarci 0:0061165683ee 142 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 143 */
sdivarci 0:0061165683ee 144 int set_xoclkdelay(xoclkdelay_t delay);
sdivarci 0:0061165683ee 145
sdivarci 0:0061165683ee 146 /**
sdivarci 0:0061165683ee 147 * @brief Get start delay before enabling XO clock to digital block
sdivarci 0:0061165683ee 148 *
sdivarci 0:0061165683ee 149 * @param[in] delay delay cycle
sdivarci 0:0061165683ee 150 *
sdivarci 0:0061165683ee 151 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 152 */
sdivarci 0:0061165683ee 153 int get_xoclkdelay(xoclkdelay_t *delay);
sdivarci 0:0061165683ee 154
sdivarci 0:0061165683ee 155 /**
sdivarci 0:0061165683ee 156 * @brief Register Configuration
sdivarci 0:0061165683ee 157 *
sdivarci 0:0061165683ee 158 * @details
sdivarci 0:0061165683ee 159 * -Register : CFG1(0x00)
sdivarci 0:0061165683ee 160 * - Bit Fields : [5:4]
sdivarci 0:0061165683ee 161 * - Default : 0x2
sdivarci 0:0061165683ee 162 * - Description : XO clock division ratio for digital block
sdivarci 0:0061165683ee 163 */
sdivarci 0:0061165683ee 164 typedef enum {
sdivarci 0:0061165683ee 165 XOCLKDIV_BY_4, /**< 0x0: Divide XO clock by 4 for digital clock */
sdivarci 0:0061165683ee 166 XOCLKDIV_BY_5, /**< 0x1: Divide XO clock by 5 for digital clock. High time is 2 cycles, low time is 3 cycles */
sdivarci 0:0061165683ee 167 XOCLKDIV_BY_6, /**< 0x2: Divide XO clock by 6 for digital clock */
sdivarci 0:0061165683ee 168 XOCLKDIV_BY_7, /**< 0x3: Divide XO clock by 7 for digital clock. High time is 3 cycles,
sdivarci 0:0061165683ee 169 and low time is 4 cycles */
sdivarci 0:0061165683ee 170 } xoclkdiv_t;
sdivarci 0:0061165683ee 171
sdivarci 0:0061165683ee 172 /**
sdivarci 0:0061165683ee 173 * @brief Set XO clock division ratio for digital block
sdivarci 0:0061165683ee 174 *
sdivarci 0:0061165683ee 175 * @param[in] div division ratio
sdivarci 0:0061165683ee 176 *
sdivarci 0:0061165683ee 177 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 178 */
sdivarci 0:0061165683ee 179 int set_xoclkdiv(xoclkdiv_t div);
sdivarci 0:0061165683ee 180
sdivarci 0:0061165683ee 181 /**
sdivarci 0:0061165683ee 182 * @brief Get XO clock division ratio for digital block
sdivarci 0:0061165683ee 183 *
sdivarci 0:0061165683ee 184 * @param[in] div division ratio
sdivarci 0:0061165683ee 185 *
sdivarci 0:0061165683ee 186 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 187 */
sdivarci 0:0061165683ee 188 int get_xoclkdiv(xoclkdiv_t *div);
sdivarci 0:0061165683ee 189
sdivarci 0:0061165683ee 190 /**
sdivarci 0:0061165683ee 191 * @brief Register Configuration
sdivarci 0:0061165683ee 192 *
sdivarci 0:0061165683ee 193 * @details
sdivarci 0:0061165683ee 194 * - Register : CFG1(0x00)
sdivarci 0:0061165683ee 195 * - Bit Fields : [2]
sdivarci 0:0061165683ee 196 * - Default : 0b0
sdivarci 0:0061165683ee 197 * - Description : Sets the state of FSK Gaussian Shaping
sdivarci 0:0061165683ee 198 */
sdivarci 0:0061165683ee 199 typedef enum {
sdivarci 0:0061165683ee 200 FSKSHAPE_DISABLE, /**< 0x0: FSK Shaping disabled */
sdivarci 0:0061165683ee 201 FSKSHAPE_ENABLE, /**< 0x1: FSK Shaping enabled */
sdivarci 0:0061165683ee 202 } fskshape_t;
sdivarci 0:0061165683ee 203
sdivarci 0:0061165683ee 204 /**
sdivarci 0:0061165683ee 205 * @brief Sets the state of FSK Gaussian Shaping
sdivarci 0:0061165683ee 206 *
sdivarci 0:0061165683ee 207 * @param[in] shape enable/disable fskshaping
sdivarci 0:0061165683ee 208 *
sdivarci 0:0061165683ee 209 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 210 */
sdivarci 0:0061165683ee 211 int set_fskshape(fskshape_t shape);
sdivarci 0:0061165683ee 212
sdivarci 0:0061165683ee 213 /**
sdivarci 0:0061165683ee 214 * @brief Gets the state of FSK Gaussian Shaping
sdivarci 0:0061165683ee 215 *
sdivarci 0:0061165683ee 216 * @param[in] shape enable/disable fskshaping
sdivarci 0:0061165683ee 217 *
sdivarci 0:0061165683ee 218 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 219 */
sdivarci 0:0061165683ee 220 int get_fskshape(fskshape_t *shape);
sdivarci 0:0061165683ee 221
sdivarci 0:0061165683ee 222 /**
sdivarci 0:0061165683ee 223 * @brief Register Configuration
sdivarci 0:0061165683ee 224 *
sdivarci 0:0061165683ee 225 * @details
sdivarci 0:0061165683ee 226 * - Register : CFG1(0x00)
sdivarci 0:0061165683ee 227 * - Bit Fields : [1]
sdivarci 0:0061165683ee 228 * - Default : 0b0
sdivarci 0:0061165683ee 229 * - Description : Controls if clock output acts as an input. When an input,
sdivarci 0:0061165683ee 230 * it will sample the DATA pin.
sdivarci 0:0061165683ee 231 */
sdivarci 0:0061165683ee 232 typedef enum {
sdivarci 0:0061165683ee 233 SYNC_0, /**< 0x0: asynchronous transmission mode */
sdivarci 0:0061165683ee 234 SYNC_1, /**< 0x1: synchronous transmission mode */
sdivarci 0:0061165683ee 235 } sync_t;
sdivarci 0:0061165683ee 236
sdivarci 0:0061165683ee 237 /**
sdivarci 0:0061165683ee 238 * @brief Sets the state of clock pin
sdivarci 0:0061165683ee 239 *
sdivarci 0:0061165683ee 240 * @param[in] state pin state async/sync
sdivarci 0:0061165683ee 241 *
sdivarci 0:0061165683ee 242 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 243 */
sdivarci 0:0061165683ee 244 int set_sync(sync_t state);
sdivarci 0:0061165683ee 245
sdivarci 0:0061165683ee 246 /**
sdivarci 0:0061165683ee 247 * @brief Gets the state of clock pin
sdivarci 0:0061165683ee 248 *
sdivarci 0:0061165683ee 249 * @param[in] state pin state async/sync
sdivarci 0:0061165683ee 250 *
sdivarci 0:0061165683ee 251 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 252 */
sdivarci 0:0061165683ee 253 int get_sync(sync_t *state);
sdivarci 0:0061165683ee 254
sdivarci 0:0061165683ee 255 /**
sdivarci 0:0061165683ee 256 * @brief Register Configuration
sdivarci 0:0061165683ee 257 *
sdivarci 0:0061165683ee 258 * @details
sdivarci 0:0061165683ee 259 * - Register : CFG1(0x00)
sdivarci 0:0061165683ee 260 * - Bit Fields : [0]
sdivarci 0:0061165683ee 261 * - Default : 0b0
sdivarci 0:0061165683ee 262 * - Description : Configures modulator mode
sdivarci 0:0061165683ee 263 */
sdivarci 0:0061165683ee 264 typedef enum {
sdivarci 0:0061165683ee 265 MODMODE_ASK, /**< 0x0: ASK Mode */
sdivarci 0:0061165683ee 266 MODMODE_FSK, /**< 0x1: FSK Mode */
sdivarci 0:0061165683ee 267 } modmode_t;
sdivarci 0:0061165683ee 268
sdivarci 0:0061165683ee 269 /**
sdivarci 0:0061165683ee 270 * @brief Sets modulator mode to ASK or FSK
sdivarci 0:0061165683ee 271 *
sdivarci 0:0061165683ee 272 * @param[in] mode ASK or FSK
sdivarci 0:0061165683ee 273 *
sdivarci 0:0061165683ee 274 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 275 */
sdivarci 0:0061165683ee 276 int set_modmode(modmode_t mode);
sdivarci 0:0061165683ee 277
sdivarci 0:0061165683ee 278 /**
sdivarci 0:0061165683ee 279 * @brief Gets modulator mode
sdivarci 0:0061165683ee 280 *
sdivarci 0:0061165683ee 281 * @param[in] mode ASK or FSK
sdivarci 0:0061165683ee 282 *
sdivarci 0:0061165683ee 283 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 284 */
sdivarci 0:0061165683ee 285 int get_modmode(modmode_t* mode);
sdivarci 0:0061165683ee 286
sdivarci 0:0061165683ee 287 /**
sdivarci 0:0061165683ee 288 * @brief Register Configuration
sdivarci 0:0061165683ee 289 *
sdivarci 0:0061165683ee 290 * @details
sdivarci 0:0061165683ee 291 * - Register : CFG2(0x01)
sdivarci 0:0061165683ee 292 * - Bit Fields : [7:6]
sdivarci 0:0061165683ee 293 * - Default : 0x2
sdivarci 0:0061165683ee 294 * - Description : Selects the delay when CLKOUT starts
sdivarci 0:0061165683ee 295 * toggling upon exiting SHUTDOWN mode,
sdivarci 0:0061165683ee 296 * in divided XO clock cycles
sdivarci 0:0061165683ee 297 */
sdivarci 0:0061165683ee 298 typedef enum {
sdivarci 0:0061165683ee 299 CLKOUT_DELAY_64_CYCLE, /**< 0x0: CLKOUT will start toggling after 64 cycles
sdivarci 0:0061165683ee 300 whenever moving into normal mode from shutdown mode */
sdivarci 0:0061165683ee 301 CLKOUT_DELAY_128_CYCLE, /**< 0x1: CLKOUT will start toggling after 128 cycles
sdivarci 0:0061165683ee 302 whenever moving into normal mode from shutdown mode */
sdivarci 0:0061165683ee 303 CLKOUT_DELAY_256_CYCLE, /**< 0x2: CLKOUT will start toggling after 256 cycles
sdivarci 0:0061165683ee 304 whenever moving into normal mode from shutdown mode */
sdivarci 0:0061165683ee 305 CLKOUT_DELAY_512_CYCLE, /**< 0x3: CLKOUT will start toggling after 512 cycles
sdivarci 0:0061165683ee 306 whenever moving into normal mode from shutdown mode */
sdivarci 0:0061165683ee 307 } clkout_delay_t;
sdivarci 0:0061165683ee 308
sdivarci 0:0061165683ee 309 /**
sdivarci 0:0061165683ee 310 * @brief Sets clkout delay
sdivarci 0:0061165683ee 311 *
sdivarci 0:0061165683ee 312 * @param[in] delay delay cycles
sdivarci 0:0061165683ee 313 *
sdivarci 0:0061165683ee 314 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 315 */
sdivarci 0:0061165683ee 316 int set_clkout_delay(clkout_delay_t delay);
sdivarci 0:0061165683ee 317
sdivarci 0:0061165683ee 318 /**
sdivarci 0:0061165683ee 319 * @brief Gets clkout delay
sdivarci 0:0061165683ee 320 *
sdivarci 0:0061165683ee 321 * @param[in] delay delay cycles
sdivarci 0:0061165683ee 322 *
sdivarci 0:0061165683ee 323 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 324 */
sdivarci 0:0061165683ee 325 int get_clkout_delay(clkout_delay_t* delay);
sdivarci 0:0061165683ee 326
sdivarci 0:0061165683ee 327 /**
sdivarci 0:0061165683ee 328 * @brief Register Configuration
sdivarci 0:0061165683ee 329 *
sdivarci 0:0061165683ee 330 * @details
sdivarci 0:0061165683ee 331 * - Register : CFG2(0x01)
sdivarci 0:0061165683ee 332 * - Bit Fields : [2:0]
sdivarci 0:0061165683ee 333 * - Default : 0x1
sdivarci 0:0061165683ee 334 * - Description : Baud clock post-divider setting.
sdivarci 0:0061165683ee 335 */
sdivarci 0:0061165683ee 336 typedef enum {
sdivarci 0:0061165683ee 337 BCLK_POSTDIV_RESERVED_0, /**< 0x0: RESERVED */
sdivarci 0:0061165683ee 338 BCLK_POSTDIV_BY_1, /**< 0x1: Divide by 1 */
sdivarci 0:0061165683ee 339 BCLK_POSTDIV_BY_2, /**< 0x2: Divide by 2 */
sdivarci 0:0061165683ee 340 BCLK_POSTDIV_BY_3, /**< 0x3: Divide by 3 */
sdivarci 0:0061165683ee 341 BCLK_POSTDIV_BY_4, /**< 0x4: Divide by 4 */
sdivarci 0:0061165683ee 342 BCLK_POSTDIV_BY_5, /**< 0x5: Divide by 5 */
sdivarci 0:0061165683ee 343 BCLK_POSTDIV_RESERVED_6, /**< 0x6: RESERVED */
sdivarci 0:0061165683ee 344 BCLK_POSTDIV_RESERVED_7, /**< 0x7: RESERVED */
sdivarci 0:0061165683ee 345 } bclk_postdiv_t;
sdivarci 0:0061165683ee 346
sdivarci 0:0061165683ee 347 /**
sdivarci 0:0061165683ee 348 * @brief Sets baud clock post-divider
sdivarci 0:0061165683ee 349 *
sdivarci 0:0061165683ee 350 * @param[in] div divider value
sdivarci 0:0061165683ee 351 *
sdivarci 0:0061165683ee 352 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 353 */
sdivarci 0:0061165683ee 354 int set_bclk_postdiv(bclk_postdiv_t div);
sdivarci 0:0061165683ee 355
sdivarci 0:0061165683ee 356 /**
sdivarci 0:0061165683ee 357 * @brief Gets baud clock post-divider
sdivarci 0:0061165683ee 358 *
sdivarci 0:0061165683ee 359 * @param[in] div divider value
sdivarci 0:0061165683ee 360 *
sdivarci 0:0061165683ee 361 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 362 */
sdivarci 0:0061165683ee 363 int get_bclk_postdiv(bclk_postdiv_t* div);
sdivarci 0:0061165683ee 364
sdivarci 0:0061165683ee 365 /**
sdivarci 0:0061165683ee 366 * @brief Register Configuration
sdivarci 0:0061165683ee 367 *
sdivarci 0:0061165683ee 368 * @details
sdivarci 0:0061165683ee 369 * - Register : CFG4(0x03)
sdivarci 0:0061165683ee 370 * - Bit Fields : [1:0]
sdivarci 0:0061165683ee 371 * - Default : 0x0
sdivarci 0:0061165683ee 372 * - Description : Power Down Mode Select.
sdivarci 0:0061165683ee 373 */
sdivarci 0:0061165683ee 374 typedef enum {
sdivarci 0:0061165683ee 375 PWDN_MODE_SHUTDOWN, /**< 0x0: SHUTDOWN low power state is enabled. While entering
sdivarci 0:0061165683ee 376 low power state, XO, PLL, and PA are shutdown. */
sdivarci 0:0061165683ee 377 PWDN_MODE_STANDBY, /**< 0x1: STANDBY low power state is enabled. While entering
sdivarci 0:0061165683ee 378 low power state, XO is enabled. PLL and PA are shutdown */
sdivarci 0:0061165683ee 379 PWDN_MODE_FAST_WAKEUP, /**< 0x2: FAST WAKEUP low power state is enabled. While entering
sdivarci 0:0061165683ee 380 low power state, XO and PLL are enabled. PA is shutdown. */
sdivarci 0:0061165683ee 381 PWDN_MODE_REVERT_TO_FAST_WAKEUP, /**< 0x3: Will revert to 0x2 */
sdivarci 0:0061165683ee 382 } pwdn_mode_t;
sdivarci 0:0061165683ee 383
sdivarci 0:0061165683ee 384 /**
sdivarci 0:0061165683ee 385 * @brief Sets power down mode
sdivarci 0:0061165683ee 386 *
sdivarci 0:0061165683ee 387 * @param[in] pwdn_mode power down mode
sdivarci 0:0061165683ee 388 *
sdivarci 0:0061165683ee 389 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 390 */
sdivarci 0:0061165683ee 391 int set_pwdn_mode(pwdn_mode_t pwdn_mode);
sdivarci 0:0061165683ee 392
sdivarci 0:0061165683ee 393 /**
sdivarci 0:0061165683ee 394 * @brief Gets power down mode
sdivarci 0:0061165683ee 395 *
sdivarci 0:0061165683ee 396 * @param[in] pwdn_mode power down mode
sdivarci 0:0061165683ee 397 *
sdivarci 0:0061165683ee 398 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 399 */
sdivarci 0:0061165683ee 400 int get_pwdn_mode(pwdn_mode_t* pwdn_mode);
sdivarci 0:0061165683ee 401
sdivarci 0:0061165683ee 402 /**
sdivarci 0:0061165683ee 403 * @brief Register Configuration
sdivarci 0:0061165683ee 404 *
sdivarci 0:0061165683ee 405 * @details
sdivarci 0:0061165683ee 406 * - Register : SHDN(0x05)
sdivarci 0:0061165683ee 407 * - Bit Fields : [0]
sdivarci 0:0061165683ee 408 * - Default : 0x0
sdivarci 0:0061165683ee 409 * - Description : Enables a boost in PA output power for frequencies above 850MHz.
sdivarci 0:0061165683ee 410 * This requires a different PA match compared to normal operation.
sdivarci 0:0061165683ee 411 */
sdivarci 0:0061165683ee 412 typedef enum {
sdivarci 0:0061165683ee 413 PA_BOOST_NORMAL_MODE, /**< 0x0: PA Output power in normal operation. */
sdivarci 0:0061165683ee 414 PA_BOOST_BOOST_MODE, /**< 0x1: PA Output power in boost mode for more output power. */
sdivarci 0:0061165683ee 415 } pa_boost_t;
sdivarci 0:0061165683ee 416
sdivarci 0:0061165683ee 417 /**
sdivarci 0:0061165683ee 418 * @brief enable/disable boost mode
sdivarci 0:0061165683ee 419 *
sdivarci 0:0061165683ee 420 * @param[in] pa_boost power amplifier output mode
sdivarci 0:0061165683ee 421 *
sdivarci 0:0061165683ee 422 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 423 */
sdivarci 0:0061165683ee 424 int set_pa_boost(pa_boost_t pa_boost);
sdivarci 0:0061165683ee 425
sdivarci 0:0061165683ee 426 /**
sdivarci 0:0061165683ee 427 * @brief Gets boost mode
sdivarci 0:0061165683ee 428 *
sdivarci 0:0061165683ee 429 * @param[in] pa_boost power amplifier output mode
sdivarci 0:0061165683ee 430 *
sdivarci 0:0061165683ee 431 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 432 */
sdivarci 0:0061165683ee 433 int get_pa_boost(pa_boost_t* pa_boost);
sdivarci 0:0061165683ee 434
sdivarci 0:0061165683ee 435 /**
sdivarci 0:0061165683ee 436 * @brief Register Configuration
sdivarci 0:0061165683ee 437 *
sdivarci 0:0061165683ee 438 * @details
sdivarci 0:0061165683ee 439 * - Register : PA1(0x06)
sdivarci 0:0061165683ee 440 * - Bit Fields : [2:0]
sdivarci 0:0061165683ee 441 * - Default : 0x0
sdivarci 0:0061165683ee 442 * - Description : Controls the PA output power by enabling parallel drivers.
sdivarci 0:0061165683ee 443 */
sdivarci 0:0061165683ee 444 typedef enum {
sdivarci 0:0061165683ee 445 PAPWR_1_DRIVER, /**< 0x0: Minimum, 1 driver */
sdivarci 0:0061165683ee 446 PAPWR_2_DRIVER, /**< 0x1: 2 Drivers */
sdivarci 0:0061165683ee 447 PAPWR_3_DRIVER, /**< 0x2: 3 Drivers */
sdivarci 0:0061165683ee 448 PAPWR_4_DRIVER, /**< 0x3: 4 Drivers */
sdivarci 0:0061165683ee 449 PAPWR_5_DRIVER, /**< 0x4: 5 Drivers */
sdivarci 0:0061165683ee 450 PAPWR_6_DRIVER, /**< 0x5: 6 Drivers */
sdivarci 0:0061165683ee 451 PAPWR_7_DRIVER, /**< 0x6: 7 Drivers */
sdivarci 0:0061165683ee 452 PAPWR_8_DRIVER, /**< 0x7: 8 Drivers */
sdivarci 0:0061165683ee 453 } papwr_t;
sdivarci 0:0061165683ee 454
sdivarci 0:0061165683ee 455 /**
sdivarci 0:0061165683ee 456 * @brief set PA output power by enabling parallel drivers
sdivarci 0:0061165683ee 457 *
sdivarci 0:0061165683ee 458 * @param[in] papwr number of parallel drivers
sdivarci 0:0061165683ee 459 *
sdivarci 0:0061165683ee 460 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 461 */
sdivarci 0:0061165683ee 462 int set_papwr(papwr_t papwr);
sdivarci 0:0061165683ee 463
sdivarci 0:0061165683ee 464 /**
sdivarci 0:0061165683ee 465 * @brief Gets PA output power
sdivarci 0:0061165683ee 466 *
sdivarci 0:0061165683ee 467 * @param[in] papwr number of parallel drivers
sdivarci 0:0061165683ee 468 *
sdivarci 0:0061165683ee 469 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 470 */
sdivarci 0:0061165683ee 471 int get_papwr(papwr_t* papwr);
sdivarci 0:0061165683ee 472
sdivarci 0:0061165683ee 473
sdivarci 0:0061165683ee 474 /**
sdivarci 0:0061165683ee 475 * @brief Register Configuration
sdivarci 0:0061165683ee 476 *
sdivarci 0:0061165683ee 477 * @details
sdivarci 0:0061165683ee 478 * - Register : PA2(0x07)
sdivarci 0:0061165683ee 479 * - Bit Fields : [4:0]
sdivarci 0:0061165683ee 480 * - Default : 0x00
sdivarci 0:0061165683ee 481 * - Description : Controls shunt capacitance on PA output in fF.
sdivarci 0:0061165683ee 482 */
sdivarci 0:0061165683ee 483 typedef enum {
sdivarci 0:0061165683ee 484 PACAP_0_fF,
sdivarci 0:0061165683ee 485 PACAP_175_fF,
sdivarci 0:0061165683ee 486 PACAP_350_fF,
sdivarci 0:0061165683ee 487 PACAP_525_fF,
sdivarci 0:0061165683ee 488 PACAP_700_fF,
sdivarci 0:0061165683ee 489 PACAP_875_fF,
sdivarci 0:0061165683ee 490 PACAP_1050_fF,
sdivarci 0:0061165683ee 491 PACAP_1225_fF,
sdivarci 0:0061165683ee 492 PACAP_1400_fF,
sdivarci 0:0061165683ee 493 PACAP_1575_fF,
sdivarci 0:0061165683ee 494 PACAP_1750_fF,
sdivarci 0:0061165683ee 495 PACAP_1925_fF,
sdivarci 0:0061165683ee 496 PACAP_2100_fF,
sdivarci 0:0061165683ee 497 PACAP_2275_fF,
sdivarci 0:0061165683ee 498 PACAP_2450_fF,
sdivarci 0:0061165683ee 499 PACAP_2625_fF,
sdivarci 0:0061165683ee 500 PACAP_2800_fF,
sdivarci 0:0061165683ee 501 PACAP_2975_fF,
sdivarci 0:0061165683ee 502 PACAP_3150_fF,
sdivarci 0:0061165683ee 503 PACAP_3325_fF,
sdivarci 0:0061165683ee 504 PACAP_3500_fF,
sdivarci 0:0061165683ee 505 PACAP_3675_fF,
sdivarci 0:0061165683ee 506 PACAP_3850_fF,
sdivarci 0:0061165683ee 507 PACAP_4025_fF,
sdivarci 0:0061165683ee 508 PACAP_4200_fF,
sdivarci 0:0061165683ee 509 PACAP_4375_fF,
sdivarci 0:0061165683ee 510 PACAP_4550_fF,
sdivarci 0:0061165683ee 511 PACAP_4725_fF,
sdivarci 0:0061165683ee 512 PACAP_4900_fF,
sdivarci 0:0061165683ee 513 PACAP_5075_fF,
sdivarci 0:0061165683ee 514 PACAP_5250_fF,
sdivarci 0:0061165683ee 515 PACAP_5425_fF,
sdivarci 0:0061165683ee 516 } pacap_t;
sdivarci 0:0061165683ee 517
sdivarci 0:0061165683ee 518 /**
sdivarci 0:0061165683ee 519 * @brief set shunt capacitance value
sdivarci 0:0061165683ee 520 *
sdivarci 0:0061165683ee 521 * @param[in] pacap shunt capacitance value
sdivarci 0:0061165683ee 522 *
sdivarci 0:0061165683ee 523 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 524 */
sdivarci 0:0061165683ee 525 int set_pacap(pacap_t pacap);
sdivarci 0:0061165683ee 526
sdivarci 0:0061165683ee 527 /**
sdivarci 0:0061165683ee 528 * @brief Gets shunt capacitance value
sdivarci 0:0061165683ee 529 *
sdivarci 0:0061165683ee 530 * @param[in] pacap shunt capacitance value
sdivarci 0:0061165683ee 531 *
sdivarci 0:0061165683ee 532 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 533 */
sdivarci 0:0061165683ee 534 int get_pacap(pacap_t* pacap);
sdivarci 0:0061165683ee 535
sdivarci 0:0061165683ee 536 /**
sdivarci 0:0061165683ee 537 * @brief Register Configuration
sdivarci 0:0061165683ee 538 *
sdivarci 0:0061165683ee 539 * @details
sdivarci 0:0061165683ee 540 * - Register : PLL1(0x08)
sdivarci 0:0061165683ee 541 * - Bit Fields : [7:6]
sdivarci 0:0061165683ee 542 * -Default : 0x1
sdivarci 0:0061165683ee 543 * - Description : Sets the level of charge pump offset current
sdivarci 0:0061165683ee 544 * for fractional N mode to improve close in
sdivarci 0:0061165683ee 545 * phase noise. Set to 'DISABLED' for integer N mode.
sdivarci 0:0061165683ee 546 */
sdivarci 0:0061165683ee 547 typedef enum {
sdivarci 0:0061165683ee 548 CPLIN_NO_EXTRA_CURRENT, /**< 0x0: No extra current */
sdivarci 0:0061165683ee 549 CPLIN_CHARGE_PUMP_CURRENT_5_PERCENT, /**< 0x1: 5% of charge pump current */
sdivarci 0:0061165683ee 550 CPLIN_CHARGE_PUMP_CURRENT_10_PERCENT, /**< 0x2: 10% of charge pump current */
sdivarci 0:0061165683ee 551 CPLIN_CHARGE_PUMP_CURRENT_15_PERCENT, /**< 0x3: 15% of charge pump current */
sdivarci 0:0061165683ee 552 } cplin_t;
sdivarci 0:0061165683ee 553
sdivarci 0:0061165683ee 554 /**
sdivarci 0:0061165683ee 555 * @brief set level of charge pump offset current
sdivarci 0:0061165683ee 556 *
sdivarci 0:0061165683ee 557 * @param[in] cplin percentage of charge pump current
sdivarci 0:0061165683ee 558 *
sdivarci 0:0061165683ee 559 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 560 */
sdivarci 0:0061165683ee 561 int set_cplin(cplin_t cplin);
sdivarci 0:0061165683ee 562
sdivarci 0:0061165683ee 563 /**
sdivarci 0:0061165683ee 564 * @brief Gets level of charge pump offset current
sdivarci 0:0061165683ee 565 *
sdivarci 0:0061165683ee 566 * @param[in] cplin percentage of charge pump current
sdivarci 0:0061165683ee 567 *
sdivarci 0:0061165683ee 568 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 569 */
sdivarci 0:0061165683ee 570 int get_cplin(cplin_t* cplin);
sdivarci 0:0061165683ee 571
sdivarci 0:0061165683ee 572
sdivarci 0:0061165683ee 573 /**
sdivarci 0:0061165683ee 574 * @brief Register Configuration
sdivarci 0:0061165683ee 575 *
sdivarci 0:0061165683ee 576 * @details
sdivarci 0:0061165683ee 577 * - Register : PLL1(0x08)
sdivarci 0:0061165683ee 578 * - Bit Fields : [5]
sdivarci 0:0061165683ee 579 * - Default : 0b1
sdivarci 0:0061165683ee 580 * - Description : Sets PLL between fractional-N and integer-N mode.
sdivarci 0:0061165683ee 581 *
sdivarci 0:0061165683ee 582 */
sdivarci 0:0061165683ee 583 typedef enum {
sdivarci 0:0061165683ee 584 FRACMODE_INTEGER_N, /**< 0x0: Integer N Mode */
sdivarci 0:0061165683ee 585 RACMODE_FRACTIONAL_N, /**< 0x1: Fractional N Mode */
sdivarci 0:0061165683ee 586 } fracmode_t;
sdivarci 0:0061165683ee 587
sdivarci 0:0061165683ee 588 /**
sdivarci 0:0061165683ee 589 * @brief set PLL mode
sdivarci 0:0061165683ee 590 *
sdivarci 0:0061165683ee 591 * @param[in] fracmode Integer N/Fractional N mode
sdivarci 0:0061165683ee 592 *
sdivarci 0:0061165683ee 593 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 594 */
sdivarci 0:0061165683ee 595 int set_fracmode(fracmode_t fracmode);
sdivarci 0:0061165683ee 596
sdivarci 0:0061165683ee 597 /**
sdivarci 0:0061165683ee 598 * @brief Gets PLL mode
sdivarci 0:0061165683ee 599 *
sdivarci 0:0061165683ee 600 * @param[in] fracmode Integer N/Fractional N mode
sdivarci 0:0061165683ee 601 *
sdivarci 0:0061165683ee 602 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 603 */
sdivarci 0:0061165683ee 604 int get_fracmode(fracmode_t* fracmode);
sdivarci 0:0061165683ee 605
sdivarci 0:0061165683ee 606 /* Register Configuration
sdivarci 0:0061165683ee 607 *
sdivarci 0:0061165683ee 608 * @Register : PLL1(0x08)
sdivarci 0:0061165683ee 609 * @Bit Fields : [2:1]
sdivarci 0:0061165683ee 610 * @Default : 0x0
sdivarci 0:0061165683ee 611 * @Description :
sdivarci 0:0061165683ee 612 */
sdivarci 0:0061165683ee 613 typedef enum {
sdivarci 0:0061165683ee 614 LODIV_DISABLED, /**< 0x0: Disabled */
sdivarci 0:0061165683ee 615 LODIV_DIVIDE_BY_4, /**< 0x1: LC VCO divided by 4 */
sdivarci 0:0061165683ee 616 LODIV_DIVIDE_BY_8, /**< 0x2: LC VCO divided by 8 */
sdivarci 0:0061165683ee 617 LODIV_DIVIDE_BY_12, /**< 0x3: LC VCO divided by 12 */
sdivarci 0:0061165683ee 618 } lodiv_t;
sdivarci 0:0061165683ee 619
sdivarci 0:0061165683ee 620 /**
sdivarci 0:0061165683ee 621 * @brief set divider of LC VCO
sdivarci 0:0061165683ee 622 *
sdivarci 0:0061165683ee 623 * @param[in] lodiv divider value
sdivarci 0:0061165683ee 624 *
sdivarci 0:0061165683ee 625 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 626 */
sdivarci 0:0061165683ee 627 int set_lodiv(lodiv_t lodiv);
sdivarci 0:0061165683ee 628
sdivarci 0:0061165683ee 629 /**
sdivarci 0:0061165683ee 630 * @brief Gets divider of LC VCO
sdivarci 0:0061165683ee 631 *
sdivarci 0:0061165683ee 632 * @param[in] lodiv divider value
sdivarci 0:0061165683ee 633 *
sdivarci 0:0061165683ee 634 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 635 */
sdivarci 0:0061165683ee 636 int get_lodiv(lodiv_t* lodiv);
sdivarci 0:0061165683ee 637
sdivarci 0:0061165683ee 638 /**
sdivarci 0:0061165683ee 639 * @brief Register Configuration
sdivarci 0:0061165683ee 640 *
sdivarci 0:0061165683ee 641 * @details
sdivarci 0:0061165683ee 642 * - Register : PLL1(0x08)
sdivarci 0:0061165683ee 643 * - Bit Fields : [0]
sdivarci 0:0061165683ee 644 * - Default : 0b0
sdivarci 0:0061165683ee 645 * - Description : Sets LO generation. For lower power, choose LOWCURRENT.
sdivarci 0:0061165683ee 646 * For higher performance, choose LOWNOISE
sdivarci 0:0061165683ee 647 */
sdivarci 0:0061165683ee 648 typedef enum {
sdivarci 0:0061165683ee 649 LOMODE_RING_OSCILLATOR, /**< 0x0: Ring Oscillator Mode */
sdivarci 0:0061165683ee 650 LOMODE_LC_VCO, /**< 0x1: LC VCO Mode */
sdivarci 0:0061165683ee 651 } lomode_t;
sdivarci 0:0061165683ee 652
sdivarci 0:0061165683ee 653 /**
sdivarci 0:0061165683ee 654 * @brief set LO generation
sdivarci 0:0061165683ee 655 *
sdivarci 0:0061165683ee 656 * @param[in] lomode selection of mode
sdivarci 0:0061165683ee 657 *
sdivarci 0:0061165683ee 658 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 659 */
sdivarci 0:0061165683ee 660 int set_lomode(lomode_t lomode);
sdivarci 0:0061165683ee 661
sdivarci 0:0061165683ee 662 /**
sdivarci 0:0061165683ee 663 * @brief Gets LO generation
sdivarci 0:0061165683ee 664 *
sdivarci 0:0061165683ee 665 * @param[in] lomode selection of mode
sdivarci 0:0061165683ee 666 *
sdivarci 0:0061165683ee 667 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 668 */
sdivarci 0:0061165683ee 669 int get_lomode(lomode_t* lomode);
sdivarci 0:0061165683ee 670
sdivarci 0:0061165683ee 671 /**
sdivarci 0:0061165683ee 672 * @brief Register Configuration
sdivarci 0:0061165683ee 673 *
sdivarci 0:0061165683ee 674 * @details
sdivarci 0:0061165683ee 675 * - Register : PLL2(0x09)
sdivarci 0:0061165683ee 676 * - Bit Fields : [1:0]
sdivarci 0:0061165683ee 677 * - Default : 0x0
sdivarci 0:0061165683ee 678 * - Description : Sets Charge Pump Current in microAmpere
sdivarci 0:0061165683ee 679 *
sdivarci 0:0061165683ee 680 */
sdivarci 0:0061165683ee 681 typedef enum {
sdivarci 0:0061165683ee 682 CPVAL_5_UA, /**< 0x0: 5�A */
sdivarci 0:0061165683ee 683 CPVAL_10_UA, /**< 0x1: 10�A */
sdivarci 0:0061165683ee 684 CPVAL_15_UA, /**< 0x2: 15�A */
sdivarci 0:0061165683ee 685 CPVAL_20_UA, /**< 0x3: 20�A */
sdivarci 0:0061165683ee 686 } cpval_t;
sdivarci 0:0061165683ee 687
sdivarci 0:0061165683ee 688 /**
sdivarci 0:0061165683ee 689 * @brief set charge pump current
sdivarci 0:0061165683ee 690 *
sdivarci 0:0061165683ee 691 * @param[in] cpval current value
sdivarci 0:0061165683ee 692 *
sdivarci 0:0061165683ee 693 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 694 */
sdivarci 0:0061165683ee 695 int set_cpval(cpval_t cpval);
sdivarci 0:0061165683ee 696
sdivarci 0:0061165683ee 697 /**
sdivarci 0:0061165683ee 698 * @brief Gets charge pump current
sdivarci 0:0061165683ee 699 *
sdivarci 0:0061165683ee 700 * @param[in] cpval current value
sdivarci 0:0061165683ee 701 *
sdivarci 0:0061165683ee 702 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 703 */
sdivarci 0:0061165683ee 704 int get_cpval(cpval_t* cpval);
sdivarci 0:0061165683ee 705
sdivarci 0:0061165683ee 706 /**
sdivarci 0:0061165683ee 707 * Register Configuration
sdivarci 0:0061165683ee 708 *
sdivarci 0:0061165683ee 709 * @details
sdivarci 0:0061165683ee 710 * - Register : CFG6(0x0A)
sdivarci 0:0061165683ee 711 * - Bit Fields : [2]
sdivarci 0:0061165683ee 712 * - Default : 0b0
sdivarci 0:0061165683ee 713 * - Description : Enables DATA transmission in I2C mode. Aliased address for I2C_TXEN1.
sdivarci 0:0061165683ee 714 */
sdivarci 0:0061165683ee 715 typedef enum {
sdivarci 0:0061165683ee 716 I2C_TXEN1_DISABLE, /**< 0x0: Data transmission not enabled in I2C mode. */
sdivarci 0:0061165683ee 717 I2C_TXEN1_ENABLE, /**< 0x1: Data transmission enabled in I2C mode. */
sdivarci 0:0061165683ee 718 } i2c_txen1_t;
sdivarci 0:0061165683ee 719
sdivarci 0:0061165683ee 720 int set_i2c_txen1(i2c_txen1_t setting); //sdivarci
sdivarci 0:0061165683ee 721
sdivarci 0:0061165683ee 722 /** Register Configuration
sdivarci 0:0061165683ee 723 *
sdivarci 0:0061165683ee 724 * @details
sdivarci 0:0061165683ee 725 * - Register : CFG6(0x0A)
sdivarci 0:0061165683ee 726 * - Bit Fields : [1]
sdivarci 0:0061165683ee 727 * - Default : 0b0
sdivarci 0:0061165683ee 728 * - Description : Transmission enable.
sdivarci 0:0061165683ee 729 */
sdivarci 0:0061165683ee 730 typedef enum {
sdivarci 0:0061165683ee 731 SPI_TXEN1_DISABLE, /**< 0x0: Transmission disabled. */
sdivarci 0:0061165683ee 732 SPI_TXEN1_ENABLE, /**< 0x1: Transmission enabled. */
sdivarci 0:0061165683ee 733 } spi_txen1_t;
sdivarci 0:0061165683ee 734
sdivarci 0:0061165683ee 735 /**
sdivarci 0:0061165683ee 736 * @brief Register Configuration
sdivarci 0:0061165683ee 737 *
sdivarci 0:0061165683ee 738 * @details
sdivarci 0:0061165683ee 739 * - Register : CFG6(0x0A)
sdivarci 0:0061165683ee 740 * - Bit Fields : [0]
sdivarci 0:0061165683ee 741 * - Default : 0b0
sdivarci 0:0061165683ee 742 * - Description : Four wire readback on CLKOUT pin mode.
sdivarci 0:0061165683ee 743 *
sdivarci 0:0061165683ee 744 */
sdivarci 0:0061165683ee 745 typedef enum {
sdivarci 0:0061165683ee 746 FOURWIRE1_READBACK_DISABLE, /**< 0x0: Four wire readback disabled. */
sdivarci 0:0061165683ee 747 FOURWIRE1_READBACK_ENABLE, /**< 0x1: Four wire readback enabled. */
sdivarci 0:0061165683ee 748 } fourwire1_t;
sdivarci 0:0061165683ee 749
sdivarci 0:0061165683ee 750
sdivarci 0:0061165683ee 751 /**
sdivarci 0:0061165683ee 752 * @brief Register Configuration
sdivarci 0:0061165683ee 753 *
sdivarci 0:0061165683ee 754 * @details
sdivarci 0:0061165683ee 755 * - Register : CFG7(0x10)
sdivarci 0:0061165683ee 756 * - Bit Fields : [2]
sdivarci 0:0061165683ee 757 * - Default : 0b0
sdivarci 0:0061165683ee 758 * - Description : Enables DATA transmission in I2C mode. Aliased address for I2C_TXEN1
sdivarci 0:0061165683ee 759 */
sdivarci 0:0061165683ee 760 typedef enum {
sdivarci 0:0061165683ee 761 I2C_TXEN2_DISABLE, /**< 0x0: Data transmission not enabled in I2C mode. */
sdivarci 0:0061165683ee 762 I2C_TXEN2_ENABLE, /**< 0x1: Data transmission enabled in I2C mode. */
sdivarci 0:0061165683ee 763 } i2c_txen2_t;
sdivarci 0:0061165683ee 764
sdivarci 0:0061165683ee 765 int set_i2c_txen2(i2c_txen2_t setting); //sdivarci
sdivarci 0:0061165683ee 766 /**
sdivarci 0:0061165683ee 767 * @brief Register Configuration
sdivarci 0:0061165683ee 768 *
sdivarci 0:0061165683ee 769 * @details
sdivarci 0:0061165683ee 770 * - Register : CFG7(0x10)
sdivarci 0:0061165683ee 771 * - Bit Fields : [1]
sdivarci 0:0061165683ee 772 * - Default : 0b0
sdivarci 0:0061165683ee 773 * - Description : Transmission enable.
sdivarci 0:0061165683ee 774 */
sdivarci 0:0061165683ee 775 typedef enum {
sdivarci 0:0061165683ee 776 SPI_TXEN2_DISABLE, /**< 0x0: Transmission disabled. */
sdivarci 0:0061165683ee 777 SPI_TXEN2_ENABLE, /**< 0x1: Transmission enabled. */
sdivarci 0:0061165683ee 778 } spi_txen2_t;
sdivarci 0:0061165683ee 779
sdivarci 0:0061165683ee 780
sdivarci 0:0061165683ee 781 /**
sdivarci 0:0061165683ee 782 * @brief Register Configuration
sdivarci 0:0061165683ee 783 *
sdivarci 0:0061165683ee 784 * @details
sdivarci 0:0061165683ee 785 * - Register : CFG7(0x10)
sdivarci 0:0061165683ee 786 * - Bit Fields : [0]
sdivarci 0:0061165683ee 787 * - Default : 0b0
sdivarci 0:0061165683ee 788 * - Description : Four wire readback on CLKOUT pin mode. Aliased address for FOURWIRE1
sdivarci 0:0061165683ee 789 */
sdivarci 0:0061165683ee 790 typedef enum {
sdivarci 0:0061165683ee 791 FOURWIRE2_READBACK_DISABLE, /**< 0x0: Four wire readback disabled. */
sdivarci 0:0061165683ee 792 FOURWIRE2_READBACK_ENABLE, /**< 0x1: Four wire readback enabled. */
sdivarci 0:0061165683ee 793 } fourwire2_t;
sdivarci 0:0061165683ee 794
sdivarci 0:0061165683ee 795
sdivarci 0:0061165683ee 796
sdivarci 0:0061165683ee 797 /**
sdivarci 0:0061165683ee 798 * @brief Register Configuration
sdivarci 0:0061165683ee 799 *
sdivarci 0:0061165683ee 800 * @details
sdivarci 0:0061165683ee 801 * - Register : I2C1(0x11)
sdivarci 0:0061165683ee 802 * - Bit Fields : [7]
sdivarci 0:0061165683ee 803 * - Default : 0b0
sdivarci 0:0061165683ee 804 * - Description : Packet Length Mode
sdivarci 0:0061165683ee 805 *
sdivarci 0:0061165683ee 806 */
sdivarci 0:0061165683ee 807 typedef enum {
sdivarci 0:0061165683ee 808 PKTLEN_MODE_SET_LENGTH, /**< 0x0: PKTLEN[14:0] need not be programmed. FIFO underflow event will
sdivarci 0:0061165683ee 809 be treated as end of packet event. For cases where actual packet length
sdivarci 0:0061165683ee 810 is greater than 32767 bits, it is expected that the �C will pad
sdivarci 0:0061165683ee 811 such a packet to make it an integral multiple of 8-bits */
sdivarci 0:0061165683ee 812 PKTLEN_MODE_NO_SET_LENGTH, /**< 0x1: PKTLEN[14:0] will provide the length of packet. Once FIFO is
sdivarci 0:0061165683ee 813 read for PKTLEN[14:0] bits, or if FIFO underflow, MAX4146x will consider
sdivarci 0:0061165683ee 814 that as an end of packet event. */
sdivarci 0:0061165683ee 815 } pktlen_mode_t;
sdivarci 0:0061165683ee 816
sdivarci 0:0061165683ee 817 /**
sdivarci 0:0061165683ee 818 * @brief set packet length
sdivarci 0:0061165683ee 819 *
sdivarci 0:0061165683ee 820 * @param[in] pktlen_mode packet length mode
sdivarci 0:0061165683ee 821 *
sdivarci 0:0061165683ee 822 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 823 */
sdivarci 0:0061165683ee 824 int set_pktlen_mode(pktlen_mode_t pktlen_mode);
sdivarci 0:0061165683ee 825
sdivarci 0:0061165683ee 826 /**
sdivarci 0:0061165683ee 827 * @brief Gets packet length
sdivarci 0:0061165683ee 828 *
sdivarci 0:0061165683ee 829 * @param[in] pktlen_mode packet length mode
sdivarci 0:0061165683ee 830 *
sdivarci 0:0061165683ee 831 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 832 */
sdivarci 0:0061165683ee 833 int get_pktlen_mode(pktlen_mode_t* pktlen_mode);
sdivarci 0:0061165683ee 834
sdivarci 0:0061165683ee 835
sdivarci 0:0061165683ee 836 /**
sdivarci 0:0061165683ee 837 * @brief Register Configuration
sdivarci 0:0061165683ee 838 *
sdivarci 0:0061165683ee 839 * @details
sdivarci 0:0061165683ee 840 * - Register : CFG8(0x17)
sdivarci 0:0061165683ee 841 * - Bit Fields : [0]
sdivarci 0:0061165683ee 842 * - Default : 0b0
sdivarci 0:0061165683ee 843 * - Description : Places DUT into software reset.
sdivarci 0:0061165683ee 844 */
sdivarci 0:0061165683ee 845 typedef enum {
sdivarci 0:0061165683ee 846 SOFTRESET_DEASSERT, /**< 0x0: Deassert the reset */
sdivarci 0:0061165683ee 847 SOFTRESET_RESET, /**< 0x1: Resets the entire digital, until this bit is set to 0 */
sdivarci 0:0061165683ee 848 } softreset_t;
sdivarci 0:0061165683ee 849
sdivarci 0:0061165683ee 850 /**
sdivarci 0:0061165683ee 851 * @brief set softreset bit
sdivarci 0:0061165683ee 852 *
sdivarci 0:0061165683ee 853 * @param[in] softreset enable/disable
sdivarci 0:0061165683ee 854 *
sdivarci 0:0061165683ee 855 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 856 */
sdivarci 0:0061165683ee 857 int set_softreset(softreset_t softreset);
sdivarci 0:0061165683ee 858
sdivarci 0:0061165683ee 859 /**
sdivarci 0:0061165683ee 860 * @brief Operation state of the rf transmitter
sdivarci 0:0061165683ee 861 *
sdivarci 0:0061165683ee 862 * @details
sdivarci 0:0061165683ee 863 * - Default : 0b0
sdivarci 0:0061165683ee 864 * - Description : Places DUT into software reset.
sdivarci 0:0061165683ee 865 */
sdivarci 0:0061165683ee 866 typedef enum {
sdivarci 0:0061165683ee 867 INITIALIZED = 0,
sdivarci 0:0061165683ee 868 UNINITIALIZED = 1,
sdivarci 0:0061165683ee 869 UNKNOWN = 2,
sdivarci 0:0061165683ee 870 } operation_mode_t;
sdivarci 0:0061165683ee 871
sdivarci 0:0061165683ee 872
sdivarci 0:0061165683ee 873 // Indicates whether initialization is successful
sdivarci 0:0061165683ee 874 operation_mode_t operation_mode;
sdivarci 0:0061165683ee 875
sdivarci 0:0061165683ee 876 /**
sdivarci 0:0061165683ee 877 * @brief get fifo flags (I2C6) Read only
sdivarci 0:0061165683ee 878 *
sdivarci 0:0061165683ee 879 * @param[in] fifo_flags 8-bit fifo flags
sdivarci 0:0061165683ee 880 *
sdivarci 0:0061165683ee 881 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 882 */
sdivarci 0:0061165683ee 883 int get_fifo_flags(uint8_t *fifo_flags);
sdivarci 0:0061165683ee 884
sdivarci 0:0061165683ee 885 /**
sdivarci 0:0061165683ee 886 * @brief get pktcomplete bit field flags (I2C4) Read only
sdivarci 0:0061165683ee 887 *
sdivarci 0:0061165683ee 888 * @param[in] pktcomplete 0x0: Packet transmission is not completed
sdivarci 0:0061165683ee 889 * 0x1: Packet transmission is completed
sdivarci 0:0061165683ee 890 *
sdivarci 0:0061165683ee 891 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 892 */
sdivarci 0:0061165683ee 893 int get_pktcomplete(uint8_t *pktcomplete);
sdivarci 0:0061165683ee 894
sdivarci 0:0061165683ee 895 /**
sdivarci 0:0061165683ee 896 * @brief get packet length of transmitted packet
sdivarci 0:0061165683ee 897 *
sdivarci 0:0061165683ee 898 * @param[in] pktlen Provides status information of bits transmitted for the current packet
sdivarci 0:0061165683ee 899 *
sdivarci 0:0061165683ee 900 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 901 */
sdivarci 0:0061165683ee 902 int get_tx_pktlen(uint16_t *pktlen);
sdivarci 0:0061165683ee 903
sdivarci 0:0061165683ee 904
sdivarci 0:0061165683ee 905 /* PUBLIC FUNCTION DECLARATIONS */
sdivarci 0:0061165683ee 906
sdivarci 0:0061165683ee 907 /**
sdivarci 0:0061165683ee 908 * @brief Read from a register.
sdivarci 0:0061165683ee 909 *
sdivarci 0:0061165683ee 910 * @param[in] reg Address of a register to be read.
sdivarci 0:0061165683ee 911 * @param[out] value Pointer to save result value.
sdivarci 0:0061165683ee 912 * @param[in] len Size of result to be read.
sdivarci 0:0061165683ee 913 *
sdivarci 0:0061165683ee 914 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 915 */
sdivarci 0:0061165683ee 916 int read_register(uint8_t reg, uint8_t *value, uint8_t len);
sdivarci 0:0061165683ee 917
sdivarci 0:0061165683ee 918 /**
sdivarci 0:0061165683ee 919 * @brief Write to a register.
sdivarci 0:0061165683ee 920 *
sdivarci 0:0061165683ee 921 * @param[in] reg Address of a register to be written.
sdivarci 0:0061165683ee 922 * @param[out] value Pointer of value to be written to register.
sdivarci 0:0061165683ee 923 * @param[in] len Size of result to be written.
sdivarci 0:0061165683ee 924 *
sdivarci 0:0061165683ee 925 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 926 */
sdivarci 0:0061165683ee 927 int write_register(uint8_t reg, const uint8_t *value, uint8_t len);
sdivarci 0:0061165683ee 928
sdivarci 0:0061165683ee 929 /**
sdivarci 0:0061165683ee 930 * @brief Initial programming steps after power on or soft reset.
sdivarci 0:0061165683ee 931 *
sdivarci 0:0061165683ee 932 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 933 */
sdivarci 0:0061165683ee 934 int initial_programming(void);
sdivarci 0:0061165683ee 935
sdivarci 0:0061165683ee 936 /**
sdivarci 0:0061165683ee 937 * @brief Set Baud clock predivision ratio
sdivarci 0:0061165683ee 938 *
sdivarci 0:0061165683ee 939 * @param[in] prediv values between 3 and 255
sdivarci 0:0061165683ee 940 *
sdivarci 0:0061165683ee 941 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 942 */
sdivarci 0:0061165683ee 943 int set_bclk_prediv(uint8_t prediv);
sdivarci 0:0061165683ee 944
sdivarci 0:0061165683ee 945 /**
sdivarci 0:0061165683ee 946 * @brief Gets Baud clock predivision ratio
sdivarci 0:0061165683ee 947 *
sdivarci 0:0061165683ee 948 * @param[in] prediv values between 3 and 255
sdivarci 0:0061165683ee 949 *
sdivarci 0:0061165683ee 950 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 951 */
sdivarci 0:0061165683ee 952 int get_bclk_prediv(uint8_t* prediv);
sdivarci 0:0061165683ee 953
sdivarci 0:0061165683ee 954 /**
sdivarci 0:0061165683ee 955 * @brief Controls GFSK shaping
sdivarci 0:0061165683ee 956 *
sdivarci 0:0061165683ee 957 * @param[in] tstep values between 0 and 31
sdivarci 0:0061165683ee 958 *
sdivarci 0:0061165683ee 959 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 960 */
sdivarci 0:0061165683ee 961 int set_tstep(uint8_t tstep);
sdivarci 0:0061165683ee 962
sdivarci 0:0061165683ee 963 /**
sdivarci 0:0061165683ee 964 * @brief Gets tstep
sdivarci 0:0061165683ee 965 *
sdivarci 0:0061165683ee 966 * @param[in] tstep values between 0 and 31
sdivarci 0:0061165683ee 967 *
sdivarci 0:0061165683ee 968 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 969 */
sdivarci 0:0061165683ee 970 int get_tstep(uint8_t* tstep);
sdivarci 0:0061165683ee 971
sdivarci 0:0061165683ee 972 /**
sdivarci 0:0061165683ee 973 * @brief Set PLL frequency
sdivarci 0:0061165683ee 974 *
sdivarci 0:0061165683ee 975 * @param[in] freq FREQ value to PLL between 0x00 and 0xFFFFFF
sdivarci 0:0061165683ee 976 *
sdivarci 0:0061165683ee 977 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 978 *
sdivarci 0:0061165683ee 979 * @description LO frequency = FREQ<23:0>/2^16*fXTAL
sdivarci 0:0061165683ee 980 */
sdivarci 0:0061165683ee 981 int set_frequency(uint32_t freq);
sdivarci 0:0061165683ee 982
sdivarci 0:0061165683ee 983 /**
sdivarci 0:0061165683ee 984 * @brief Gets PLL frequency
sdivarci 0:0061165683ee 985 *
sdivarci 0:0061165683ee 986 * @param[in] freq FREQ value to PLL between 0x00 and 0xFFFFFF
sdivarci 0:0061165683ee 987 *
sdivarci 0:0061165683ee 988 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 989 *
sdivarci 0:0061165683ee 990 * @description LO frequency = FREQ<23:0>/2^16*fXTAL
sdivarci 0:0061165683ee 991 */
sdivarci 0:0061165683ee 992 int get_frequency(uint32_t* freq);
sdivarci 0:0061165683ee 993
sdivarci 0:0061165683ee 994 /**
sdivarci 0:0061165683ee 995 * @brief Set frequency deviation from the space frequency for the mark frequency
sdivarci 0:0061165683ee 996 *
sdivarci 0:0061165683ee 997 * @param[in] deltaf frequency deviation value
sdivarci 0:0061165683ee 998 *
sdivarci 0:0061165683ee 999 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 1000 *
sdivarci 0:0061165683ee 1001 * @description fDELTA = DELTAF[6:0]* fXTAL/8192
sdivarci 0:0061165683ee 1002 */
sdivarci 0:0061165683ee 1003 int set_deltaf(uint8_t deltaf);
sdivarci 0:0061165683ee 1004
sdivarci 0:0061165683ee 1005 /**
sdivarci 0:0061165683ee 1006 * @brief Get frequency deviation from the space frequency for the mark frequency
sdivarci 0:0061165683ee 1007 *
sdivarci 0:0061165683ee 1008 * @param[in] deltaf frequency deviation value
sdivarci 0:0061165683ee 1009 *
sdivarci 0:0061165683ee 1010 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 1011 *
sdivarci 0:0061165683ee 1012 * @description fDELTA = DELTAF[6:0]* fXTAL/8192
sdivarci 0:0061165683ee 1013 */
sdivarci 0:0061165683ee 1014 int get_deltaf(uint8_t* deltaf);
sdivarci 0:0061165683ee 1015
sdivarci 0:0061165683ee 1016 /**
sdivarci 0:0061165683ee 1017 * @brief Set frequency deviation from the space frequency for the mark frequency
sdivarci 0:0061165683ee 1018 *
sdivarci 0:0061165683ee 1019 * @param[in] deltaf_shape frequency deviation value
sdivarci 0:0061165683ee 1020 *
sdivarci 0:0061165683ee 1021 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 1022 *
sdivarci 0:0061165683ee 1023 * @description fDELTA = DELTAF_SHAPE[3:0]* fXTAL/81920
sdivarci 0:0061165683ee 1024 */
sdivarci 0:0061165683ee 1025 int set_deltaf_shape(uint8_t deltaf_shape);
sdivarci 0:0061165683ee 1026
sdivarci 0:0061165683ee 1027 /**
sdivarci 0:0061165683ee 1028 * @brief Gets frequency deviation from the space frequency for the mark frequency
sdivarci 0:0061165683ee 1029 *
sdivarci 0:0061165683ee 1030 * @param[in] deltaf_shape frequency deviation value
sdivarci 0:0061165683ee 1031 *
sdivarci 0:0061165683ee 1032 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 1033 *
sdivarci 0:0061165683ee 1034 * @description fDELTA = DELTAF_SHAPE[3:0]* fXTAL/81920
sdivarci 0:0061165683ee 1035 */
sdivarci 0:0061165683ee 1036 int get_deltaf_shape(uint8_t* deltaf_shape);
sdivarci 0:0061165683ee 1037
sdivarci 0:0061165683ee 1038 /**
sdivarci 0:0061165683ee 1039 * @brief Set Packet Length for I2C communication
sdivarci 0:0061165683ee 1040 *
sdivarci 0:0061165683ee 1041 * @param[in] pktlen values between 0x00 and 0x7FF
sdivarci 0:0061165683ee 1042 *
sdivarci 0:0061165683ee 1043 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 1044 */
sdivarci 0:0061165683ee 1045 int set_i2c_pktlen(uint16_t pktlen);
sdivarci 0:0061165683ee 1046
sdivarci 0:0061165683ee 1047 /**
sdivarci 0:0061165683ee 1048 * @brief Gets Packet Length for I2C communication
sdivarci 0:0061165683ee 1049 *
sdivarci 0:0061165683ee 1050 * @param[in] pktlen values between 0x00 and 0x7FF
sdivarci 0:0061165683ee 1051 *
sdivarci 0:0061165683ee 1052 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 1053 */
sdivarci 0:0061165683ee 1054 int get_i2c_pktlen(uint16_t* pktlen);
sdivarci 0:0061165683ee 1055
sdivarci 0:0061165683ee 1056 /**
sdivarci 0:0061165683ee 1057 * @brief Adjust baud rate
sdivarci 0:0061165683ee 1058 *
sdivarci 0:0061165683ee 1059 * @param[in] baud_rate preferred baud rate
sdivarci 0:0061165683ee 1060 *
sdivarci 0:0061165683ee 1061 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 1062 *
sdivarci 0:0061165683ee 1063 * @description It changes only the values of BCLK_PREDIV and BCLK_POSTDIV
sdivarci 0:0061165683ee 1064 * Baud_rate = f_clk/((1+BCLK_PREDIV)x2^(1+BCLK_POSTDIV))
sdivarci 0:0061165683ee 1065 * where f_clk = f_xtal/XOCLKDIV_ratio
sdivarci 0:0061165683ee 1066 * Note that to maintain the internal 3.2MHz time base,
sdivarci 0:0061165683ee 1067 * XOCLKDIV[1:0] (register CFG1, 0x00, bit 4) must be programmed,
sdivarci 0:0061165683ee 1068 * based on the crystal frequency
sdivarci 0:0061165683ee 1069 */
sdivarci 0:0061165683ee 1070 int adjust_baudrate(float rate);
sdivarci 0:0061165683ee 1071
sdivarci 0:0061165683ee 1072 /**
sdivarci 0:0061165683ee 1073 * @brief Gets baud rate
sdivarci 0:0061165683ee 1074 *
sdivarci 0:0061165683ee 1075 * @returns baud rate.
sdivarci 0:0061165683ee 1076 *
sdivarci 0:0061165683ee 1077 */
sdivarci 0:0061165683ee 1078 float get_baudrate();
sdivarci 0:0061165683ee 1079
sdivarci 0:0061165683ee 1080 /**
sdivarci 0:0061165683ee 1081 * @brief Adjust Manchester Bitrate
sdivarci 0:0061165683ee 1082 *
sdivarci 0:0061165683ee 1083 * @param[in] data_rate preferred data rate in (1-50)kbps
sdivarci 0:0061165683ee 1084 *
sdivarci 0:0061165683ee 1085 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 1086 */
sdivarci 0:0061165683ee 1087 int adjust_manchester_bitrate(char rate);
sdivarci 0:0061165683ee 1088
sdivarci 0:0061165683ee 1089 /**
sdivarci 0:0061165683ee 1090 * @brief Get Manchester Bitrate
sdivarci 0:0061165683ee 1091 *
sdivarci 0:0061165683ee 1092 * @returns data rate in (1-50)kbps
sdivarci 0:0061165683ee 1093 */
sdivarci 0:0061165683ee 1094 char get_manchester_bitrate();
sdivarci 0:0061165683ee 1095
sdivarci 0:0061165683ee 1096 /**
sdivarci 0:0061165683ee 1097 * @brief Configures the crystal frequency of the chip (Fxtal)
sdivarci 0:0061165683ee 1098 *
sdivarci 0:0061165683ee 1099 * @param[in] freq crystal frequency values between 12.8 MHz and 19.2 MHz
sdivarci 0:0061165683ee 1100 *
sdivarci 0:0061165683ee 1101 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 1102 */
sdivarci 0:0061165683ee 1103 int set_crystal_frequency(float freq);
sdivarci 0:0061165683ee 1104
sdivarci 0:0061165683ee 1105 /**
sdivarci 0:0061165683ee 1106 * @brief Get the crystal frequency of the chip (Fxtal)
sdivarci 0:0061165683ee 1107 *
sdivarci 0:0061165683ee 1108 * @returns crystal frequency values between 12.8 MHz and 19.2 MHz
sdivarci 0:0061165683ee 1109 */
sdivarci 0:0061165683ee 1110 float get_crystal_frequency();
sdivarci 0:0061165683ee 1111
sdivarci 0:0061165683ee 1112 /**
sdivarci 0:0061165683ee 1113 * @brief Adjust center/carrier frequency of the chip
sdivarci 0:0061165683ee 1114 *
sdivarci 0:0061165683ee 1115 * @param[in] freq center/carrier frequency value between 250 MHz and 950 MHz
sdivarci 0:0061165683ee 1116 *
sdivarci 0:0061165683ee 1117 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 1118 */
sdivarci 0:0061165683ee 1119 int set_center_frequency(float freq);
sdivarci 0:0061165683ee 1120
sdivarci 0:0061165683ee 1121 /**
sdivarci 0:0061165683ee 1122 * @brief Gets center/carrier frequency of the chip
sdivarci 0:0061165683ee 1123 *
sdivarci 0:0061165683ee 1124 * @returns center/carrier frequency value between 250 MHz and 950 MHz
sdivarci 0:0061165683ee 1125 */
sdivarci 0:0061165683ee 1126 float get_center_frequency();
sdivarci 0:0061165683ee 1127
sdivarci 0:0061165683ee 1128 /**
sdivarci 0:0061165683ee 1129 * @brief set the FSK deviation values (Delta_f)
sdivarci 0:0061165683ee 1130 *
sdivarci 0:0061165683ee 1131 * @param[in] deviation deviation value in in kHz baud rate
sdivarci 0:0061165683ee 1132 *
sdivarci 0:0061165683ee 1133 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 1134 *
sdivarci 0:0061165683ee 1135 * @description The mark frequency is defined by the space frequency
sdivarci 0:0061165683ee 1136 * plus a frequency deviation. If frequency shaping is
sdivarci 0:0061165683ee 1137 * disabled by setting FSKSHAPE = 0 (register CFG1, bit 2),
sdivarci 0:0061165683ee 1138 * the frequency deviation is defined by DELTAF[6:0]
sdivarci 0:0061165683ee 1139 * (register PLL6, bits 6:0).
sdivarci 0:0061165683ee 1140 * DELTAF[6 : 0] = (Delta_f * 8192)f_xtal
sdivarci 0:0061165683ee 1141 * If frequency shaping is enabled by setting FSKSHAPE = 1
sdivarci 0:0061165683ee 1142 * (register CFG1, bit 2), the frequency deviation is defined
sdivarci 0:0061165683ee 1143 * by DETLAF_SHAPE[3:0] (register PLL7, bits 3:0).
sdivarci 0:0061165683ee 1144 * DELTAF_SHAPE[3 : 0] = (Delta_f * 8192)/(f_xtal * 10)
sdivarci 0:0061165683ee 1145 */
sdivarci 0:0061165683ee 1146 int adjust_frequency_deviation(float deviation);
sdivarci 0:0061165683ee 1147
sdivarci 0:0061165683ee 1148 /**
sdivarci 0:0061165683ee 1149 * @brief Send data for selected Preset/I2C/SPI mode
sdivarci 0:0061165683ee 1150 *
sdivarci 0:0061165683ee 1151 * @param[in] data data pointer for data to be transferred
sdivarci 0:0061165683ee 1152 * @param[in] length legth of data to be transferred
sdivarci 0:0061165683ee 1153 *
sdivarci 0:0061165683ee 1154 * @returns 0 on success, negative error code on failure.
sdivarci 0:0061165683ee 1155 */
sdivarci 0:0061165683ee 1156 int send_data(uint8_t *data, uint32_t length);
sdivarci 0:0061165683ee 1157
sdivarci 0:0061165683ee 1158 int set_i2c_data(uint8_t setting); //sdivarci
sdivarci 0:0061165683ee 1159 };
sdivarci 0:0061165683ee 1160
sdivarci 0:0061165683ee 1161
sdivarci 0:0061165683ee 1162 /** MAX41460 Device Class
sdivarci 0:0061165683ee 1163 *
sdivarci 0:0061165683ee 1164 * Hold configurations for the MAX41460
sdivarci 0:0061165683ee 1165 */
sdivarci 0:0061165683ee 1166 class MAX41460 : public MAX4146X <max41460_reg_map_t>
sdivarci 0:0061165683ee 1167 {
sdivarci 0:0061165683ee 1168 max41460_reg_map_t regmap;
sdivarci 0:0061165683ee 1169 public:
sdivarci 0:0061165683ee 1170 MAX41460(SPI *spi, DigitalOut *cs) : MAX4146X<max41460_reg_map_t>(&regmap, spi, cs) {}
sdivarci 0:0061165683ee 1171
sdivarci 0:0061165683ee 1172 MAX41460(SPI *spi) : MAX4146X<max41460_reg_map_t>(&regmap, spi) {}
sdivarci 0:0061165683ee 1173
sdivarci 0:0061165683ee 1174 MAX41460(DigitalOut *cs) : MAX4146X(cs) {}
sdivarci 0:0061165683ee 1175
sdivarci 0:0061165683ee 1176 };
sdivarci 0:0061165683ee 1177
sdivarci 0:0061165683ee 1178 /** MAX41461 Device Class
sdivarci 0:0061165683ee 1179 *
sdivarci 0:0061165683ee 1180 * Hold configurations for the MAX41461
sdivarci 0:0061165683ee 1181 */
sdivarci 0:0061165683ee 1182 class MAX41461 : public MAX4146X <max41461_2_reg_map_t>
sdivarci 0:0061165683ee 1183 {
sdivarci 0:0061165683ee 1184 max41461_2_reg_map_t regmap;
sdivarci 0:0061165683ee 1185 public:
sdivarci 0:0061165683ee 1186 MAX41461(I2C *i2c) : MAX4146X<max41461_2_reg_map_t>(&regmap, i2c) {}
sdivarci 0:0061165683ee 1187
sdivarci 0:0061165683ee 1188 MAX41461(DigitalOut *cs) : MAX4146X(cs) {}
sdivarci 0:0061165683ee 1189 };
sdivarci 0:0061165683ee 1190
sdivarci 0:0061165683ee 1191 /** MAX41462 Device Class
sdivarci 0:0061165683ee 1192 *
sdivarci 0:0061165683ee 1193 * Hold configurations for the MAX41462
sdivarci 0:0061165683ee 1194 */
sdivarci 0:0061165683ee 1195 class MAX41462 : public MAX41461
sdivarci 0:0061165683ee 1196 {
sdivarci 0:0061165683ee 1197 public:
sdivarci 0:0061165683ee 1198 MAX41462(I2C *i2c) : MAX41461(i2c) {}
sdivarci 0:0061165683ee 1199
sdivarci 0:0061165683ee 1200 MAX41462(DigitalOut *cs) : MAX41461(cs) {}
sdivarci 0:0061165683ee 1201
sdivarci 0:0061165683ee 1202 };
sdivarci 0:0061165683ee 1203
sdivarci 0:0061165683ee 1204 /** MAX41463 Device Class
sdivarci 0:0061165683ee 1205 *
sdivarci 0:0061165683ee 1206 * Hold configurations for the MAX41463
sdivarci 0:0061165683ee 1207 */
sdivarci 0:0061165683ee 1208 class MAX41463 : public MAX4146X <max41463_4_reg_map_t>
sdivarci 0:0061165683ee 1209 {
sdivarci 0:0061165683ee 1210 max41463_4_reg_map_t regmap;
sdivarci 0:0061165683ee 1211 public:
sdivarci 0:0061165683ee 1212 MAX41463(I2C *i2c) : MAX4146X<max41463_4_reg_map_t>(&regmap, i2c) {}
sdivarci 0:0061165683ee 1213
sdivarci 0:0061165683ee 1214 MAX41463(DigitalOut *cs) : MAX4146X(cs) {}
sdivarci 0:0061165683ee 1215
sdivarci 0:0061165683ee 1216 };
sdivarci 0:0061165683ee 1217
sdivarci 0:0061165683ee 1218 /** MAX41464 Device Class
sdivarci 0:0061165683ee 1219 *
sdivarci 0:0061165683ee 1220 * Hold configurations for the MAX41464
sdivarci 0:0061165683ee 1221 */
sdivarci 0:0061165683ee 1222 class MAX41464 : public MAX41463
sdivarci 0:0061165683ee 1223 {
sdivarci 0:0061165683ee 1224 public:
sdivarci 0:0061165683ee 1225 MAX41464(I2C *i2c) : MAX41463(i2c) {}
sdivarci 0:0061165683ee 1226
sdivarci 0:0061165683ee 1227 MAX41464(DigitalOut *cs) : MAX41463(cs) {}
sdivarci 0:0061165683ee 1228
sdivarci 0:0061165683ee 1229 };
sdivarci 0:0061165683ee 1230
sdivarci 0:0061165683ee 1231
sdivarci 0:0061165683ee 1232 #endif /* MAX4146x_H_ */