Sinan Divarci / Mbed OS max4146x_comp

max4146x_comp

Dependencies:   MAX14690

max4146x/Max41461_2_regs.h@0:0061165683ee, 2020-10-25 (annotated)

Committer:
sdivarci
Date:
Sun Oct 25 20:10:02 2020 +0000
Revision:
0:0061165683ee
sdivarci

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sdivarci 0:0061165683ee 1 /*******************************************************************************
sdivarci 0:0061165683ee 2 * Copyright (C) 2019 Maxim Integrated Products, Inc., All rights Reserved.
sdivarci 0:0061165683ee 3 *
sdivarci 0:0061165683ee 4 * This software is protected by copyright laws of the United States and
sdivarci 0:0061165683ee 5 * of foreign countries. This material may also be protected by patent laws
sdivarci 0:0061165683ee 6 * and technology transfer regulations of the United States and of foreign
sdivarci 0:0061165683ee 7 * countries. This software is furnished under a license agreement and/or a
sdivarci 0:0061165683ee 8 * nondisclosure agreement and may only be used or reproduced in accordance
sdivarci 0:0061165683ee 9 * with the terms of those agreements. Dissemination of this information to
sdivarci 0:0061165683ee 10 * any party or parties not specified in the license agreement and/or
sdivarci 0:0061165683ee 11 * nondisclosure agreement is expressly prohibited.
sdivarci 0:0061165683ee 12 *
sdivarci 0:0061165683ee 13 * The above copyright notice and this permission notice shall be included
sdivarci 0:0061165683ee 14 * in all copies or substantial portions of the Software.
sdivarci 0:0061165683ee 15 *
sdivarci 0:0061165683ee 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
sdivarci 0:0061165683ee 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
sdivarci 0:0061165683ee 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
sdivarci 0:0061165683ee 19 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
sdivarci 0:0061165683ee 20 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
sdivarci 0:0061165683ee 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
sdivarci 0:0061165683ee 22 * OTHER DEALINGS IN THE SOFTWARE.
sdivarci 0:0061165683ee 23 *
sdivarci 0:0061165683ee 24 * Except as contained in this notice, the name of Maxim Integrated
sdivarci 0:0061165683ee 25 * Products, Inc. shall not be used except as stated in the Maxim Integrated
sdivarci 0:0061165683ee 26 * Products, Inc. Branding Policy.
sdivarci 0:0061165683ee 27 *
sdivarci 0:0061165683ee 28 * The mere transfer of this software does not imply any licenses
sdivarci 0:0061165683ee 29 * of trade secrets, proprietary technology, copyrights, patents,
sdivarci 0:0061165683ee 30 * trademarks, maskwork rights, or any other form of intellectual
sdivarci 0:0061165683ee 31 * property whatsoever. Maxim Integrated Products, Inc. retains all
sdivarci 0:0061165683ee 32 * ownership rights.
sdivarci 0:0061165683ee 33 *******************************************************************************
sdivarci 0:0061165683ee 34 */
sdivarci 0:0061165683ee 35
sdivarci 0:0061165683ee 36 #ifndef MAX41461_2_REGS_H_
sdivarci 0:0061165683ee 37 #define MAX41461_2_REGS_H_
sdivarci 0:0061165683ee 38
sdivarci 0:0061165683ee 39 /**
sdivarci 0:0061165683ee 40 * @brief CFG1 (0X00)
sdivarci 0:0061165683ee 41 *
sdivarci 0:0061165683ee 42 */
sdivarci 0:0061165683ee 43 typedef union {
sdivarci 0:0061165683ee 44 unsigned char raw;
sdivarci 0:0061165683ee 45 struct {
sdivarci 0:0061165683ee 46 unsigned char modmode : 1; /**< Configures modulator mode */
sdivarci 0:0061165683ee 47 unsigned char sync : 1; /**< Controls if clock output acts as an input.
sdivarci 0:0061165683ee 48 When an input, it will sample the DATA pin. */
sdivarci 0:0061165683ee 49 unsigned char fskshape : 1; /**< Sets the state of FSK Gaussian Shaping */
sdivarci 0:0061165683ee 50 unsigned char : 1;
sdivarci 0:0061165683ee 51 unsigned char xoclkdiv : 2; /**< XO clock division ratio for digital block */
sdivarci 0:0061165683ee 52 unsigned char xoclkdelay : 2; /**< Start delay before enabling XO clock to digital block */
sdivarci 0:0061165683ee 53 } bits;
sdivarci 0:0061165683ee 54 } max41461_2_reg_cfg1_t;
sdivarci 0:0061165683ee 55
sdivarci 0:0061165683ee 56 /**
sdivarci 0:0061165683ee 57 * @brief CFG2 (0X01)
sdivarci 0:0061165683ee 58 *
sdivarci 0:0061165683ee 59 */
sdivarci 0:0061165683ee 60 typedef union {
sdivarci 0:0061165683ee 61 unsigned char raw;
sdivarci 0:0061165683ee 62 struct {
sdivarci 0:0061165683ee 63 unsigned char bclk_postdiv : 3; /**< Select the Baud Clock Post Division Ratio.
sdivarci 0:0061165683ee 64 Valid values are from 1 to 5. */
sdivarci 0:0061165683ee 65 unsigned char : 3;
sdivarci 0:0061165683ee 66 unsigned char clkout_delay : 2; /**< Selects the delay when CLKOUT starts toggling upon
sdivarci 0:0061165683ee 67 exiting SHUTDOWN mode, in divided XO clock cycles */
sdivarci 0:0061165683ee 68 } bits;
sdivarci 0:0061165683ee 69 } max41461_2_reg_cfg2_t;
sdivarci 0:0061165683ee 70
sdivarci 0:0061165683ee 71 /**
sdivarci 0:0061165683ee 72 * @brief CFG3 (0X02)
sdivarci 0:0061165683ee 73 *
sdivarci 0:0061165683ee 74 */
sdivarci 0:0061165683ee 75 typedef union {
sdivarci 0:0061165683ee 76 unsigned char raw;
sdivarci 0:0061165683ee 77 struct {
sdivarci 0:0061165683ee 78 unsigned char bclk_prediv : 8; /**< Baud clock predivision ratio. Valid values are from 3 to 255 */
sdivarci 0:0061165683ee 79 } bits;
sdivarci 0:0061165683ee 80 } max41461_2_reg_cfg3_t;
sdivarci 0:0061165683ee 81
sdivarci 0:0061165683ee 82 /**
sdivarci 0:0061165683ee 83 * @brief CFG4 (0X03)
sdivarci 0:0061165683ee 84 *
sdivarci 0:0061165683ee 85 */
sdivarci 0:0061165683ee 86 typedef union {
sdivarci 0:0061165683ee 87 unsigned char raw;
sdivarci 0:0061165683ee 88 struct {
sdivarci 0:0061165683ee 89 unsigned char pwdn_mode : 2; /**< Power Down Mode Select */
sdivarci 0:0061165683ee 90 unsigned char : 6;
sdivarci 0:0061165683ee 91 } bits;
sdivarci 0:0061165683ee 92 } max41461_2_reg_cfg4_t;
sdivarci 0:0061165683ee 93
sdivarci 0:0061165683ee 94 /**
sdivarci 0:0061165683ee 95 * @brief CFG5 (0X04)
sdivarci 0:0061165683ee 96 *
sdivarci 0:0061165683ee 97 */
sdivarci 0:0061165683ee 98 typedef union {
sdivarci 0:0061165683ee 99 unsigned char raw;
sdivarci 0:0061165683ee 100 struct {
sdivarci 0:0061165683ee 101 unsigned char tstep : 6; /**< Controls GFSK shaping. See Digital FSK Modulation section. */
sdivarci 0:0061165683ee 102 unsigned char : 2;
sdivarci 0:0061165683ee 103 } bits;
sdivarci 0:0061165683ee 104 } max41461_2_reg_cfg5_t;
sdivarci 0:0061165683ee 105
sdivarci 0:0061165683ee 106 /**
sdivarci 0:0061165683ee 107 * @brief SHDN (0X05)
sdivarci 0:0061165683ee 108 *
sdivarci 0:0061165683ee 109 */
sdivarci 0:0061165683ee 110 typedef union {
sdivarci 0:0061165683ee 111 unsigned char raw;
sdivarci 0:0061165683ee 112 struct {
sdivarci 0:0061165683ee 113 unsigned char pa_boost : 1; /**< Enables a boost in PA output power for frequencies above 850MHz.
sdivarci 0:0061165683ee 114 This requires a different PA match compared to normal operation. */
sdivarci 0:0061165683ee 115 unsigned char : 7;
sdivarci 0:0061165683ee 116 } bits;
sdivarci 0:0061165683ee 117 } max41461_2_reg_shdn_t;
sdivarci 0:0061165683ee 118
sdivarci 0:0061165683ee 119 /**
sdivarci 0:0061165683ee 120 * @brief PA1 (0X06)
sdivarci 0:0061165683ee 121 *
sdivarci 0:0061165683ee 122 */
sdivarci 0:0061165683ee 123 typedef union {
sdivarci 0:0061165683ee 124 unsigned char raw;
sdivarci 0:0061165683ee 125 struct {
sdivarci 0:0061165683ee 126 unsigned char papwr : 3; /**< Controls the PA output power by enabling parallel drivers. */
sdivarci 0:0061165683ee 127 unsigned char : 5;
sdivarci 0:0061165683ee 128 } bits;
sdivarci 0:0061165683ee 129 } max41461_2_reg_pa1_t;
sdivarci 0:0061165683ee 130
sdivarci 0:0061165683ee 131 /**
sdivarci 0:0061165683ee 132 * @brief PA2 (0X07)
sdivarci 0:0061165683ee 133 *
sdivarci 0:0061165683ee 134 */
sdivarci 0:0061165683ee 135 typedef union {
sdivarci 0:0061165683ee 136 unsigned char raw;
sdivarci 0:0061165683ee 137 struct {
sdivarci 0:0061165683ee 138 unsigned char pacap : 5; /**< Controls shunt capacitance on PA output in fF. */
sdivarci 0:0061165683ee 139 unsigned char : 3;
sdivarci 0:0061165683ee 140 } bits;
sdivarci 0:0061165683ee 141 } max41461_2_reg_pa2_t;
sdivarci 0:0061165683ee 142
sdivarci 0:0061165683ee 143 /**
sdivarci 0:0061165683ee 144 * @brief PLL1 (0X08)
sdivarci 0:0061165683ee 145 *
sdivarci 0:0061165683ee 146 */
sdivarci 0:0061165683ee 147 typedef union {
sdivarci 0:0061165683ee 148 unsigned char raw;
sdivarci 0:0061165683ee 149 struct {
sdivarci 0:0061165683ee 150 unsigned char lomode : 1; /**< Sets LO generation. For lower power, choose LOWCURRENT.
sdivarci 0:0061165683ee 151 For higher performance, choose LOWNOISE. */
sdivarci 0:0061165683ee 152 unsigned char lodiv : 2; /**< LC VCO divider value*/
sdivarci 0:0061165683ee 153 unsigned char loopbw : 2; /**< Write to 00 binary.Sets PLL loop bandwidth. */
sdivarci 0:0061165683ee 154 unsigned char fracmode : 1; /**< Sets PLL between fractional-N and integer-N mode. */
sdivarci 0:0061165683ee 155 unsigned char cplin : 2; /**< Sets the level of charge pump offset current for fractional N mode to
sdivarci 0:0061165683ee 156 improve close in phase noise. Set to DISABLED for integer N mode. */
sdivarci 0:0061165683ee 157 } bits;
sdivarci 0:0061165683ee 158 } max41461_2_reg_pll1_t;
sdivarci 0:0061165683ee 159
sdivarci 0:0061165683ee 160 /**
sdivarci 0:0061165683ee 161 * @brief PLL2 (0X09)
sdivarci 0:0061165683ee 162 *
sdivarci 0:0061165683ee 163 */
sdivarci 0:0061165683ee 164 typedef union {
sdivarci 0:0061165683ee 165 unsigned char raw;
sdivarci 0:0061165683ee 166 struct {
sdivarci 0:0061165683ee 167 unsigned char cpval : 2; /**< Sets Charge Pump Current */
sdivarci 0:0061165683ee 168 unsigned char : 4;
sdivarci 0:0061165683ee 169 unsigned char lcvco_fast_start : 1; /**< Write to 0 binary.Enables fast start of LC VCO
sdivarci 0:0061165683ee 170 because of bias filtering */
sdivarci 0:0061165683ee 171 unsigned char lcvco_pwr : 1; /**< Write to 0 binary.Controls power in LC VCO */
sdivarci 0:0061165683ee 172 } bits;
sdivarci 0:0061165683ee 173 } max41461_2_reg_pll2_t;
sdivarci 0:0061165683ee 174
sdivarci 0:0061165683ee 175 /**
sdivarci 0:0061165683ee 176 * @brief CFG6 (0X0A)
sdivarci 0:0061165683ee 177 *
sdivarci 0:0061165683ee 178 */
sdivarci 0:0061165683ee 179 typedef union {
sdivarci 0:0061165683ee 180 unsigned char raw;
sdivarci 0:0061165683ee 181 struct {
sdivarci 0:0061165683ee 182 unsigned char fourwire1 : 1; /**< */
sdivarci 0:0061165683ee 183 unsigned char spi_txen1 : 1; /**< */
sdivarci 0:0061165683ee 184 unsigned char i2c_txen1 : 1; /**< Enables DATA transmission in I2C mode. Aliased address for I2C_TXEN1 */
sdivarci 0:0061165683ee 185 unsigned char : 5;
sdivarci 0:0061165683ee 186 } bits;
sdivarci 0:0061165683ee 187 } max41461_2_reg_cfg6_t;
sdivarci 0:0061165683ee 188
sdivarci 0:0061165683ee 189 /**
sdivarci 0:0061165683ee 190 * @brief PLL3 (0X0B)
sdivarci 0:0061165683ee 191 *
sdivarci 0:0061165683ee 192 */
sdivarci 0:0061165683ee 193 typedef union {
sdivarci 0:0061165683ee 194 unsigned char raw;
sdivarci 0:0061165683ee 195 struct {
sdivarci 0:0061165683ee 196 unsigned char freq_23_to_16 : 8; /**< FREQ value to PLL. LO frequency= FREQ<23:0>/2^16*fXTAL */
sdivarci 0:0061165683ee 197 } bits;
sdivarci 0:0061165683ee 198 } max41461_2_reg_pll3_t;
sdivarci 0:0061165683ee 199
sdivarci 0:0061165683ee 200 /**
sdivarci 0:0061165683ee 201 * @brief PLL4 (0X0C)
sdivarci 0:0061165683ee 202 *
sdivarci 0:0061165683ee 203 */
sdivarci 0:0061165683ee 204 typedef union {
sdivarci 0:0061165683ee 205 unsigned char raw;
sdivarci 0:0061165683ee 206 struct {
sdivarci 0:0061165683ee 207 unsigned char freq_15_to_8 : 8; /**< FREQ value to PLL */
sdivarci 0:0061165683ee 208 } bits;
sdivarci 0:0061165683ee 209 } max41461_2_reg_pll4_t;
sdivarci 0:0061165683ee 210
sdivarci 0:0061165683ee 211 /**
sdivarci 0:0061165683ee 212 * @brief PLL5 (0X0D)
sdivarci 0:0061165683ee 213 *
sdivarci 0:0061165683ee 214 */
sdivarci 0:0061165683ee 215 typedef union {
sdivarci 0:0061165683ee 216 unsigned char raw;
sdivarci 0:0061165683ee 217 struct {
sdivarci 0:0061165683ee 218 unsigned char freq_7_to_0 : 8; /**< FREQ value to PLL */
sdivarci 0:0061165683ee 219 } bits;
sdivarci 0:0061165683ee 220 } max41461_2_reg_pll5_t;
sdivarci 0:0061165683ee 221
sdivarci 0:0061165683ee 222 /**
sdivarci 0:0061165683ee 223 * @brief PLL6 (0X0E)
sdivarci 0:0061165683ee 224 *
sdivarci 0:0061165683ee 225 */
sdivarci 0:0061165683ee 226 typedef union {
sdivarci 0:0061165683ee 227 unsigned char raw;
sdivarci 0:0061165683ee 228 struct {
sdivarci 0:0061165683ee 229 unsigned char deltaf : 7; /**< For FSK mode, MODMODE=1 and FSKSHAPE=0, sets the frequency deviation from the
sdivarci 0:0061165683ee 230 space frequency for the mark frequency. fDELTA = DELTAF[6:0]*fXTAL/8192 */
sdivarci 0:0061165683ee 231 unsigned char : 1;
sdivarci 0:0061165683ee 232 } bits;
sdivarci 0:0061165683ee 233 } max41461_2_reg_pll6_t;
sdivarci 0:0061165683ee 234
sdivarci 0:0061165683ee 235 /**
sdivarci 0:0061165683ee 236 * @brief PLL7 (0X0F)
sdivarci 0:0061165683ee 237 *
sdivarci 0:0061165683ee 238 */
sdivarci 0:0061165683ee 239 typedef union {
sdivarci 0:0061165683ee 240 unsigned char raw;
sdivarci 0:0061165683ee 241 struct {
sdivarci 0:0061165683ee 242 unsigned char deltaf_shape : 4; /**< For FSK mode, MODMODE = 1 and FSKSHAPE = 1, sets the frequency deviation
sdivarci 0:0061165683ee 243 from the space frequency for the mark frequency.
sdivarci 0:0061165683ee 244 fDELTA = DELTAF_SHAPE[3:0]*fXTAL/81920 */
sdivarci 0:0061165683ee 245 unsigned char : 4;
sdivarci 0:0061165683ee 246 } bits;
sdivarci 0:0061165683ee 247 } max41461_2_reg_pll7_t;
sdivarci 0:0061165683ee 248
sdivarci 0:0061165683ee 249 /**
sdivarci 0:0061165683ee 250 * @brief CFG7 (0X10)
sdivarci 0:0061165683ee 251 *
sdivarci 0:0061165683ee 252 */
sdivarci 0:0061165683ee 253 typedef union {
sdivarci 0:0061165683ee 254 unsigned char raw;
sdivarci 0:0061165683ee 255 struct {
sdivarci 0:0061165683ee 256 unsigned char fourwire2 : 1; /**< */
sdivarci 0:0061165683ee 257 unsigned char spi_txen2 : 1; /**< */
sdivarci 0:0061165683ee 258 unsigned char i2c_txen2 : 1; /**< When set, enables DATA transmission in I2C mode.
sdivarci 0:0061165683ee 259 Aliased address for I2C_TXEN1 */
sdivarci 0:0061165683ee 260 unsigned char : 5;
sdivarci 0:0061165683ee 261 } bits;
sdivarci 0:0061165683ee 262 } max41461_2_reg_cfg7_t;
sdivarci 0:0061165683ee 263
sdivarci 0:0061165683ee 264 /**
sdivarci 0:0061165683ee 265 * @brief I2C1 (0X11)
sdivarci 0:0061165683ee 266 *
sdivarci 0:0061165683ee 267 */
sdivarci 0:0061165683ee 268 typedef union {
sdivarci 0:0061165683ee 269 unsigned char raw;
sdivarci 0:0061165683ee 270 struct {
sdivarci 0:0061165683ee 271 unsigned char pktlen_14_to_8 : 7; /**< Packet Length */
sdivarci 0:0061165683ee 272 unsigned char pktlen_mode : 1; /**< Packet Length Mode */
sdivarci 0:0061165683ee 273 } bits;
sdivarci 0:0061165683ee 274 } max41461_2_reg_i2c1_t;
sdivarci 0:0061165683ee 275
sdivarci 0:0061165683ee 276 /**
sdivarci 0:0061165683ee 277 * @brief I2C2 (0X012)
sdivarci 0:0061165683ee 278 *
sdivarci 0:0061165683ee 279 */
sdivarci 0:0061165683ee 280 typedef union {
sdivarci 0:0061165683ee 281 unsigned char raw;
sdivarci 0:0061165683ee 282 struct {
sdivarci 0:0061165683ee 283 unsigned char pktlen_7_to_0 : 8; /**< Packet Length */
sdivarci 0:0061165683ee 284 } bits;
sdivarci 0:0061165683ee 285 } max41461_2_reg_i2c2_t;
sdivarci 0:0061165683ee 286
sdivarci 0:0061165683ee 287 /**
sdivarci 0:0061165683ee 288 * @brief I2C3 (0X13)
sdivarci 0:0061165683ee 289 *
sdivarci 0:0061165683ee 290 */
sdivarci 0:0061165683ee 291 typedef union {
sdivarci 0:0061165683ee 292 unsigned char raw;
sdivarci 0:0061165683ee 293 struct {
sdivarci 0:0061165683ee 294 unsigned char i2c_tx_data : 8; /**< Transmit data to be written into FIFO for I2C mode of operation.
sdivarci 0:0061165683ee 295 At this address, I2C register address will not auto increment within an
sdivarci 0:0061165683ee 296 I2C transaction burst, and subsequent writes will keep going to FIFO */
sdivarci 0:0061165683ee 297 } bits;
sdivarci 0:0061165683ee 298 } max41461_2_reg_i2c3_t;
sdivarci 0:0061165683ee 299
sdivarci 0:0061165683ee 300 /**
sdivarci 0:0061165683ee 301 * @brief I2C4 (0X14)
sdivarci 0:0061165683ee 302 *
sdivarci 0:0061165683ee 303 */
sdivarci 0:0061165683ee 304 typedef union {
sdivarci 0:0061165683ee 305 unsigned char raw;
sdivarci 0:0061165683ee 306 struct {
sdivarci 0:0061165683ee 307 unsigned char tx_pktlen_14_to_8 : 7; /**< Provides status information of bits
sdivarci 0:0061165683ee 308 transmitted for the current packet */
sdivarci 0:0061165683ee 309 unsigned char pktcomplete : 1; /**< Indicates if Packet transmission is completed */
sdivarci 0:0061165683ee 310 } bits;
sdivarci 0:0061165683ee 311 } max41461_2_reg_i2c4_t;
sdivarci 0:0061165683ee 312
sdivarci 0:0061165683ee 313 /**
sdivarci 0:0061165683ee 314 * @brief I2C5 (0X15)
sdivarci 0:0061165683ee 315 *
sdivarci 0:0061165683ee 316 */
sdivarci 0:0061165683ee 317 typedef union {
sdivarci 0:0061165683ee 318 unsigned char raw;
sdivarci 0:0061165683ee 319 struct {
sdivarci 0:0061165683ee 320 unsigned char tx_pktlen_7_to_0 : 8; /**< Provides status information of bits
sdivarci 0:0061165683ee 321 transmitted for the current packet */
sdivarci 0:0061165683ee 322 } bits;
sdivarci 0:0061165683ee 323 } max41461_2_reg_i2c5_t;
sdivarci 0:0061165683ee 324
sdivarci 0:0061165683ee 325 /**
sdivarci 0:0061165683ee 326 * @brief I2C6 (0X16)
sdivarci 0:0061165683ee 327 *
sdivarci 0:0061165683ee 328 */
sdivarci 0:0061165683ee 329 typedef union {
sdivarci 0:0061165683ee 330 unsigned char raw;
sdivarci 0:0061165683ee 331 struct {
sdivarci 0:0061165683ee 332 unsigned char fifo_words : 3; /**< This field captures the number of locations currently filled in FIFO.
sdivarci 0:0061165683ee 333 Each location corresponds to 8-bit data word */
sdivarci 0:0061165683ee 334 unsigned char : 1;
sdivarci 0:0061165683ee 335 unsigned char fifo_full : 1; /**< FIFO Full Status */
sdivarci 0:0061165683ee 336 unsigned char fifo_empty : 1; /**< FIFO Empty Status */
sdivarci 0:0061165683ee 337 unsigned char oflow : 1; /**< FIFO Overflow status */
sdivarci 0:0061165683ee 338 unsigned char uflow : 1; /**< FIFO Underflow status */
sdivarci 0:0061165683ee 339 } bits;
sdivarci 0:0061165683ee 340 } max41461_2_reg_i2c6_t;
sdivarci 0:0061165683ee 341
sdivarci 0:0061165683ee 342 /**
sdivarci 0:0061165683ee 343 * @brief CFG8 (0X17)
sdivarci 0:0061165683ee 344 *
sdivarci 0:0061165683ee 345 */
sdivarci 0:0061165683ee 346 typedef union {
sdivarci 0:0061165683ee 347 unsigned char raw;
sdivarci 0:0061165683ee 348 struct {
sdivarci 0:0061165683ee 349 unsigned char softreset : 1; /**< Places DUT into software reset. */
sdivarci 0:0061165683ee 350 unsigned char : 7;
sdivarci 0:0061165683ee 351 } bits;
sdivarci 0:0061165683ee 352 } max41461_2_reg_cfg8_t;
sdivarci 0:0061165683ee 353
sdivarci 0:0061165683ee 354 /**
sdivarci 0:0061165683ee 355 * @brief CFG9 (0X18)
sdivarci 0:0061165683ee 356 *
sdivarci 0:0061165683ee 357 */
sdivarci 0:0061165683ee 358 typedef union {
sdivarci 0:0061165683ee 359 unsigned char raw;
sdivarci 0:0061165683ee 360 struct {
sdivarci 0:0061165683ee 361 unsigned char xoen : 1; /**< Write to 0 binary.XO Enable register for test purpose */
sdivarci 0:0061165683ee 362 unsigned char pllen : 1; /**< Write to 0 binary.PLL Enable register for test purpose */
sdivarci 0:0061165683ee 363 unsigned char paen : 1; /**< Write to 0 binary.PA Enable register for test purpose */
sdivarci 0:0061165683ee 364 unsigned char test_ana : 5; /**< Write to 0_0000 binary.Test modes for analog block */
sdivarci 0:0061165683ee 365 } bits;
sdivarci 0:0061165683ee 366 } max41461_2_reg_cfg9_t;
sdivarci 0:0061165683ee 367
sdivarci 0:0061165683ee 368 /**
sdivarci 0:0061165683ee 369 * @brief ADDL1 (0X19)
sdivarci 0:0061165683ee 370 *
sdivarci 0:0061165683ee 371 */
sdivarci 0:0061165683ee 372 typedef union {
sdivarci 0:0061165683ee 373 unsigned char raw;
sdivarci 0:0061165683ee 374 struct {
sdivarci 0:0061165683ee 375 unsigned char ring_bias : 2; /**< Write to 00 binary.Controls the current mirror ratio in Ring Oscillator
sdivarci 0:0061165683ee 376 control. For lower frequencies, the number can be reduced for
sdivarci 0:0061165683ee 377 slightly better phase noise. */
sdivarci 0:0061165683ee 378 unsigned char ring_trim : 2; /**< Write to 00 binary.
sdivarci 0:0061165683ee 379 Adjusts the current control value for ring oscillator. */
sdivarci 0:0061165683ee 380 unsigned char bias_trim : 2; /**< Write to 00 binary.
sdivarci 0:0061165683ee 381 Adjusts bias current for PLL block. */
sdivarci 0:0061165683ee 382 unsigned char xtal_gm : 2; /**< Write to 00 binary.
sdivarci 0:0061165683ee 383 Controls crystal oscillator GM current for startup time control */
sdivarci 0:0061165683ee 384 } bits;
sdivarci 0:0061165683ee 385 } max41461_2_reg_addl1_t;
sdivarci 0:0061165683ee 386
sdivarci 0:0061165683ee 387 /**
sdivarci 0:0061165683ee 388 * @brief ADDL2 (0X1A)
sdivarci 0:0061165683ee 389 *
sdivarci 0:0061165683ee 390 */
sdivarci 0:0061165683ee 391 typedef union {
sdivarci 0:0061165683ee 392 unsigned char raw;
sdivarci 0:0061165683ee 393 struct {
sdivarci 0:0061165683ee 394 unsigned char addlctrl2 : 7; /**< Write to 000_0000 binary.Additional control fields for future use */
sdivarci 0:0061165683ee 395 unsigned char scl_stretch_dly : 1; /**< Write to 1 binary. I2C SCL Stretch Release delay enable */
sdivarci 0:0061165683ee 396 } bits;
sdivarci 0:0061165683ee 397 } max41461_2_reg_addl2_t;
sdivarci 0:0061165683ee 398
sdivarci 0:0061165683ee 399 /**
sdivarci 0:0061165683ee 400 * @brief Register Set
sdivarci 0:0061165683ee 401 *
sdivarci 0:0061165683ee 402 */
sdivarci 0:0061165683ee 403 typedef struct {
sdivarci 0:0061165683ee 404 max41461_2_reg_cfg1_t reg_cfg1;
sdivarci 0:0061165683ee 405 max41461_2_reg_cfg2_t reg_cfg2;
sdivarci 0:0061165683ee 406 max41461_2_reg_cfg3_t reg_cfg3;
sdivarci 0:0061165683ee 407 max41461_2_reg_cfg4_t reg_cfg4;
sdivarci 0:0061165683ee 408 max41461_2_reg_cfg5_t reg_cfg5;
sdivarci 0:0061165683ee 409 max41461_2_reg_shdn_t reg_shdn;
sdivarci 0:0061165683ee 410 max41461_2_reg_pa1_t reg_pa1;
sdivarci 0:0061165683ee 411 max41461_2_reg_pa2_t reg_pa2;
sdivarci 0:0061165683ee 412 max41461_2_reg_pll1_t reg_pll1;
sdivarci 0:0061165683ee 413 max41461_2_reg_pll2_t reg_pll2;
sdivarci 0:0061165683ee 414 max41461_2_reg_cfg6_t reg_cfg6;
sdivarci 0:0061165683ee 415 max41461_2_reg_pll3_t reg_pll3;
sdivarci 0:0061165683ee 416 max41461_2_reg_pll4_t reg_pll4;
sdivarci 0:0061165683ee 417 max41461_2_reg_pll5_t reg_pll5;
sdivarci 0:0061165683ee 418 max41461_2_reg_pll6_t reg_pll6;
sdivarci 0:0061165683ee 419 max41461_2_reg_pll7_t reg_pll7;
sdivarci 0:0061165683ee 420 max41461_2_reg_cfg7_t reg_cfg7;
sdivarci 0:0061165683ee 421 max41461_2_reg_i2c1_t reg_i2c1;
sdivarci 0:0061165683ee 422 max41461_2_reg_i2c2_t reg_i2c2;
sdivarci 0:0061165683ee 423 max41461_2_reg_i2c3_t reg_i2c3;
sdivarci 0:0061165683ee 424 max41461_2_reg_i2c4_t reg_i2c4;
sdivarci 0:0061165683ee 425 max41461_2_reg_i2c5_t reg_i2c5;
sdivarci 0:0061165683ee 426 max41461_2_reg_i2c6_t reg_i2c6;
sdivarci 0:0061165683ee 427 max41461_2_reg_cfg8_t reg_cfg8;
sdivarci 0:0061165683ee 428 max41461_2_reg_cfg9_t reg_cfg9;
sdivarci 0:0061165683ee 429 max41461_2_reg_addl1_t reg_addl1;
sdivarci 0:0061165683ee 430 max41461_2_reg_addl2_t reg_addl2;
sdivarci 0:0061165683ee 431 } max41461_2_reg_map_t;
sdivarci 0:0061165683ee 432
sdivarci 0:0061165683ee 433
sdivarci 0:0061165683ee 434 #endif /* MAX41461_2_REGS_H_ */