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NVIC_Type Struct Reference
[Nested Vectored Interrupt Controller (NVIC)]
Structure type to access the Nested Vectored Interrupt Controller (NVIC). More...
#include <core_cm0.h>
Data Fields | |
| __IO uint32_t | ISER [1] |
| __IO uint32_t | ICER [1] |
| __IO uint32_t | ISPR [1] |
| __IO uint32_t | ICPR [1] |
| __IO uint32_t | IP [8] |
| __IO uint32_t | IABR [8] |
| __IO uint8_t | IP [240] |
| __O uint32_t | STIR |
Detailed Description
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition at line 263 of file core_cm0.h.
Field Documentation
| __IO uint32_t IABR[8] |
Offset: 0x200 (R/W) Interrupt Active bit Register
Definition at line 289 of file core_cm3.h.
| __IO uint32_t ICER |
Offset: 0x080 (R/W) Interrupt Clear Enable Register
Definition at line 267 of file core_cm0.h.
| __IO uint32_t ICPR |
Offset: 0x180 (R/W) Interrupt Clear Pending Register
Definition at line 271 of file core_cm0.h.
| __IO uint32_t IP[8] |
Offset: 0x300 (R/W) Interrupt Priority Register
Definition at line 274 of file core_cm0.h.
| __IO uint8_t IP[240] |
Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)
Definition at line 291 of file core_cm3.h.
| __IO uint32_t ISER |
Offset: 0x000 (R/W) Interrupt Set Enable Register
Definition at line 265 of file core_cm0.h.
| __IO uint32_t ISPR |
Offset: 0x100 (R/W) Interrupt Set Pending Register
Definition at line 269 of file core_cm0.h.
| __O uint32_t STIR |
Offset: 0xE00 ( /W) Software Trigger Interrupt Register
Definition at line 293 of file core_cm3.h.
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