Stanley Cohen / SLCD_minus_mod

Modified so > maps to - sign

Dependents:   ACC_LCD_341_Basic ESeif-SSD541-HW141 SBart_ACC_LCD_341_Basic ACC_LCD_341_Basic_Final_ALM

Fork of SLCD by Erik -

SLCD.cpp@4:ec7b3c9b2aeb, 2014-02-27 (annotated)

Committer:
Sissors
Date:
Thu Feb 27 21:57:22 2014 +0000
Revision:
4:ec7b3c9b2aeb
Parent:
3:f70873bc6121
Child:
6:f4773221794b
Switched clock source to 4MHz oscillator.

; Added option to enable/disable it in deepsleep mode

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sissors 0:d04758e76d5b 1 #include "SLCD.h"
star297 1:1579bcd31410 2 #include "LCDconfig.h"
Sissors 0:d04758e76d5b 3
Sissors 0:d04758e76d5b 4
Sissors 0:d04758e76d5b 5 const uint8_t WF_ORDERING_TABLE[ ] =
Sissors 0:d04758e76d5b 6 {
Sissors 0:d04758e76d5b 7 CHAR1a, // LCD81 --- Pin:5 LCDnAddress=51
Sissors 0:d04758e76d5b 8 CHAR1b, // LCD82 --- Pin:6 LCDnAddress=52
Sissors 0:d04758e76d5b 9 CHAR2a, // LCD83 --- Pin:7 LCDnAddress=53
Sissors 0:d04758e76d5b 10 CHAR2b, // LCD84 --- Pin:8 LCDnAddress=54
Sissors 0:d04758e76d5b 11 CHAR3a, // LCD85 --- Pin:9 LCDnAddress=55
star297 1:1579bcd31410 12 CHAR3b, // LCD86 --- Pin:10 LCDnAddress=56
star297 1:1579bcd31410 13 CHAR4a, // LCD87 --- Pin:11 LCDnAddress=57
star297 1:1579bcd31410 14 CHAR4b, // LCD88 --- Pin:12 LCDnAddress=58
star297 1:1579bcd31410 15 CHARCOM0, // LCD77 --- Pin:1 LCDnAddress=4D
star297 1:1579bcd31410 16 CHARCOM1, // LCD78 --- Pin:2 LCDnAddress=4E
star297 1:1579bcd31410 17 CHARCOM2, // LCD79 --- Pin:3 LCDnAddress=4F
star297 1:1579bcd31410 18 CHARCOM3, // LCD80 --- Pin:4 LCDnAddress=50
Sissors 0:d04758e76d5b 19 };
Sissors 0:d04758e76d5b 20
Sissors 0:d04758e76d5b 21 const char ASCII_TO_WF_CODIFICATION_TABLE [ ] =
Sissors 0:d04758e76d5b 22 {
star297 1:1579bcd31410 23
star297 1:1579bcd31410 24 /*
star297 1:1579bcd31410 25 segA
star297 1:1579bcd31410 26 ________
star297 1:1579bcd31410 27 | |
star297 1:1579bcd31410 28 segF | | segB
star297 1:1579bcd31410 29 | |
star297 1:1579bcd31410 30 -segG--
star297 1:1579bcd31410 31 | |
star297 1:1579bcd31410 32 segE | | segC
star297 1:1579bcd31410 33 |________|
star297 1:1579bcd31410 34 segD
star297 1:1579bcd31410 35 */
star297 1:1579bcd31410 36
Sissors 0:d04758e76d5b 37 ( SEGD+ SEGE+ SEGF+!SEGG) , ( SEGC+ SEGB+ SEGA) ,//Char = 0, offset=0
Sissors 0:d04758e76d5b 38 (!SEGD+!SEGE+!SEGF+!SEGG) , ( SEGC+ SEGB+!SEGA) ,//Char = 1, offset=4
Sissors 0:d04758e76d5b 39 ( SEGD+ SEGE+!SEGF+ SEGG) , (!SEGC+ SEGB+ SEGA) ,//Char = 2, offset=8
Sissors 0:d04758e76d5b 40 ( SEGD+!SEGE+!SEGF+ SEGG) , ( SEGC+ SEGB+ SEGA) ,//Char = 3, offset=12
Sissors 0:d04758e76d5b 41 (!SEGD+!SEGE+ SEGF+ SEGG) , ( SEGC+ SEGB+!SEGA) ,//Char = 4, offset=16
Sissors 0:d04758e76d5b 42 ( SEGD+!SEGE+ SEGF+ SEGG) , ( SEGC+!SEGB+ SEGA) ,//Char = 5, offset=20
Sissors 0:d04758e76d5b 43 ( SEGD+ SEGE+ SEGF+ SEGG) , ( SEGC+!SEGB+ SEGA) ,//Char = 6, offset=24
Sissors 0:d04758e76d5b 44 (!SEGD+!SEGE+!SEGF+!SEGG) , ( SEGC+ SEGB+ SEGA) ,//Char = 7, offset=28
Sissors 0:d04758e76d5b 45 ( SEGD+ SEGE+ SEGF+ SEGG) , ( SEGC+ SEGB+ SEGA) ,//Char = 8, offset=32
Sissors 0:d04758e76d5b 46 ( SEGD+!SEGE+ SEGF+ SEGG) , ( SEGC+ SEGB+ SEGA) ,//Char = 9, offset=36
Sissors 0:d04758e76d5b 47 (!SEGD+!SEGE+!SEGF+!SEGG) , (!SEGC+!SEGB+!SEGA) ,//Char = :, offset=40
Sissors 0:d04758e76d5b 48 (!SEGD+!SEGE+!SEGF+!SEGG) , (!SEGC+!SEGB+!SEGA) ,//Char = ;, offset=44
Sissors 0:d04758e76d5b 49 (!SEGD+!SEGE+!SEGF+!SEGG) , (!SEGC+!SEGB+!SEGA) ,//Char = <, offset=48
Sissors 0:d04758e76d5b 50 ( SEGD+!SEGE+!SEGF+ SEGG) , (!SEGC+!SEGB+!SEGA) ,//Char = =, offset=52
Sissors 0:d04758e76d5b 51 (!SEGD+!SEGE+!SEGF+!SEGG) , (!SEGC+!SEGB+!SEGA) ,//Char = >, offset=56
Sissors 0:d04758e76d5b 52 (!SEGD+!SEGE+!SEGF+!SEGG) , (!SEGC+!SEGB+ SEGA) ,//Char = ?, offset=60
Sissors 0:d04758e76d5b 53 ( SEGD+ SEGE+ SEGF+ SEGG) , ( SEGC+ SEGB+ SEGA) ,//Char = @, offset=64
Sissors 0:d04758e76d5b 54 (!SEGD+ SEGE+ SEGF+ SEGG) , ( SEGC+ SEGB+ SEGA) ,//Char = A, offset=68
Sissors 0:d04758e76d5b 55 ( SEGD+ SEGE+ SEGF+ SEGG) , ( SEGC+!SEGB+!SEGA) ,//Char = B, offset=72
Sissors 0:d04758e76d5b 56 ( SEGD+ SEGE+ SEGF+!SEGG) , (!SEGC+!SEGB+ SEGA) ,//Char = C, offset=76
star297 1:1579bcd31410 57 ( SEGD+ SEGE+!SEGF+ SEGG) , ( SEGC+ SEGB+!SEGA) ,//Char = D, offset=80
Sissors 0:d04758e76d5b 58 ( SEGD+ SEGE+ SEGF+ SEGG) , (!SEGC+!SEGB+ SEGA) ,//Char = E, offset=84
Sissors 0:d04758e76d5b 59 (!SEGD+ SEGE+ SEGF+ SEGG) , (!SEGC+!SEGB+ SEGA) ,//Char = F, offset=88
Sissors 0:d04758e76d5b 60 ( SEGD+ SEGE+ SEGF+ SEGG) , ( SEGC+!SEGB+ SEGA) ,//Char = G, offset=92
Sissors 0:d04758e76d5b 61 (!SEGD+ SEGE+ SEGF+ SEGG) , ( SEGC+ SEGB+!SEGA) ,//Char = H, offset=96
Sissors 0:d04758e76d5b 62 (!SEGD+!SEGE+!SEGF+!SEGG) , ( SEGC+!SEGB+!SEGA) ,//Char = I, offset=100
Sissors 0:d04758e76d5b 63 ( SEGD+ SEGE+!SEGF+!SEGG) , ( SEGC+ SEGB+!SEGA) ,//Char = J, offset=104
star297 1:1579bcd31410 64 (!SEGD+ SEGE+ SEGF+ SEGG) , ( SEGC+!SEGB+ SEGA) ,//Char = K, offset=108
Sissors 0:d04758e76d5b 65 ( SEGD+ SEGE+ SEGF+!SEGG) , (!SEGC+!SEGB+!SEGA) ,//Char = L, offset=112
star297 3:f70873bc6121 66 (!SEGD+ SEGE+ SEGF+!SEGG) , ( SEGC+ SEGB+ SEGA) ,//Char = M, offset=116
Sissors 0:d04758e76d5b 67 (!SEGD+ SEGE+!SEGF+ SEGG) , ( SEGC+!SEGB+!SEGA) ,//Char = N, offset=120
Sissors 0:d04758e76d5b 68 ( SEGD+ SEGE+!SEGF+ SEGG) , ( SEGC+!SEGB+!SEGA) ,//Char = O, offset=124
star297 1:1579bcd31410 69 (!SEGD+ SEGE+ SEGF+ SEGG) , (!SEGC+ SEGB+ SEGA) ,//Char = P, offset=128
Sissors 0:d04758e76d5b 70 ( SEGD+!SEGE+ SEGF+ SEGG) , ( SEGC+ SEGB+ SEGA) ,//Char = Q, offset=132
star297 1:1579bcd31410 71 (!SEGD+ SEGE+!SEGF+ SEGG) , (!SEGC+!SEGB+!SEGA) ,//Char = R, offset=136
Sissors 0:d04758e76d5b 72 ( SEGD+!SEGE+ SEGF+ SEGG) , ( SEGC+!SEGB+ SEGA) ,//Char = S, offset=140
Sissors 0:d04758e76d5b 73 ( SEGD+ SEGE+ SEGF+ SEGG) , (!SEGC+!SEGB+!SEGA) ,//Char = T, offset=144
Sissors 0:d04758e76d5b 74 ( SEGD+ SEGE+ SEGF+!SEGG) , ( SEGC+ SEGB+!SEGA) ,//Char = U, offset=148
star297 1:1579bcd31410 75 ( SEGD+ SEGE+!SEGF+!SEGG) , ( SEGC+!SEGB+!SEGA) ,//Char = V, offset=152
star297 1:1579bcd31410 76 ( SEGD+ SEGE+ SEGF+!SEGG) , ( SEGC+ SEGB+!SEGA) ,//Char = W, offset=156
star297 1:1579bcd31410 77 (!SEGD+ SEGE+ SEGF+ SEGG) , ( SEGC+ SEGB+!SEGA) ,//Char = X, offset=160
star297 1:1579bcd31410 78 ( SEGD+!SEGE+ SEGF+ SEGG) , ( SEGC+ SEGB+!SEGA) ,//Char = Y, offset=164
star297 1:1579bcd31410 79 ( SEGD+!SEGE+!SEGF+ SEGG) , (!SEGC+!SEGB+!SEGA) ,//Char = Z, offset=168
Sissors 0:d04758e76d5b 80 ( SEGD+!SEGE+!SEGF+!SEGG) , (!SEGC+!SEGB+ SEGA) ,//Char = [, offset=172
Sissors 0:d04758e76d5b 81 ( SEGD+!SEGE+!SEGF+!SEGG) , (!SEGC+!SEGB+ SEGA) ,//Char = \, offset=176
Sissors 0:d04758e76d5b 82 ( SEGD+!SEGE+!SEGF+!SEGG) , (!SEGC+!SEGB+ SEGA) ,//Char = ], offset=180
Sissors 0:d04758e76d5b 83 ( SEGD+!SEGE+!SEGF+!SEGG) , (!SEGC+!SEGB+ SEGA) ,//Char = ^, offset=184
Sissors 0:d04758e76d5b 84 ( SEGD+!SEGE+!SEGF+!SEGG) , (!SEGC+!SEGB+ SEGA) ,//Char = _, offset=188
Sissors 0:d04758e76d5b 85 ( SEGD+!SEGE+!SEGF+!SEGG) , (!SEGC+!SEGB+ SEGA) ,//Char = `, offset=192
Sissors 0:d04758e76d5b 86 };
Sissors 0:d04758e76d5b 87
Sissors 0:d04758e76d5b 88 SLCD::SLCD() {
Sissors 0:d04758e76d5b 89 init();
star297 3:f70873bc6121 90 CharPosition = 0;
star297 1:1579bcd31410 91 }
Sissors 0:d04758e76d5b 92
Sissors 0:d04758e76d5b 93 void SLCD::init(){
Sissors 0:d04758e76d5b 94 SIM->SCGC5 |= SIM_SCGC5_SLCD_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK;
Sissors 0:d04758e76d5b 95
star297 3:f70873bc6121 96 // configure pins for LCD operation
Sissors 0:d04758e76d5b 97 PORTC->PCR[20] = 0x00000000; //VLL2
Sissors 0:d04758e76d5b 98 PORTC->PCR[21] = 0x00000000; //VLL1
Sissors 0:d04758e76d5b 99 PORTC->PCR[22] = 0x00000000; //VCAP2
star297 3:f70873bc6121 100 PORTC->PCR[23] = 0x00000000; //VCAP1
star297 3:f70873bc6121 101 // Enable IRCLK
Sissors 4:ec7b3c9b2aeb 102 MCG->C1 |= MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK;
Sissors 4:ec7b3c9b2aeb 103 MCG->C2 |= MCG_C2_IRCS_MASK ; //0 32KHZ internal reference clock; 1= 4MHz irc
Sissors 4:ec7b3c9b2aeb 104
Sissors 4:ec7b3c9b2aeb 105 //Check if the Fast reference has its divide by 2 enabled (default):
Sissors 4:ec7b3c9b2aeb 106 if ((MCG->SC & MCG_SC_FCRDIV_MASK) != 1<<1)
Sissors 4:ec7b3c9b2aeb 107 error("Invalid clock configuration for SLCD\n");
Sissors 0:d04758e76d5b 108 LCD->GCR = 0x0;
Sissors 4:ec7b3c9b2aeb 109 LCD->AR = 0x0;
Sissors 4:ec7b3c9b2aeb 110
star297 3:f70873bc6121 111 // LCD configurartion
star297 1:1579bcd31410 112 LCD->GCR = ( LCD_GCR_RVEN_MASK*_LCDRVEN
star297 1:1579bcd31410 113 | LCD_GCR_RVTRIM(_LCDRVTRIM) //0-15
Sissors 0:d04758e76d5b 114 | LCD_GCR_CPSEL_MASK*_LCDCPSEL
star297 1:1579bcd31410 115 | LCD_GCR_LADJ(_LCDLOADADJUST) //0-3
star297 1:1579bcd31410 116 | LCD_GCR_VSUPPLY_MASK*_LCDSUPPLY //0-1
Sissors 0:d04758e76d5b 117 |!LCD_GCR_FDCIEN_MASK
Sissors 4:ec7b3c9b2aeb 118 | LCD_GCR_ALTDIV(1) //divide by something
Sissors 0:d04758e76d5b 119 |!LCD_GCR_LCDDOZE_MASK
Sissors 0:d04758e76d5b 120 |!LCD_GCR_LCDSTP_MASK
star297 1:1579bcd31410 121 |!LCD_GCR_LCDEN_MASK //WILL BE ENABLE ON SUBSEQUENT STEP
Sissors 4:ec7b3c9b2aeb 122 | LCD_GCR_SOURCE_MASK*1
Sissors 4:ec7b3c9b2aeb 123 | LCD_GCR_ALTSOURCE_MASK*0
Sissors 4:ec7b3c9b2aeb 124 | LCD_GCR_LCLK(0) //0-7
Sissors 0:d04758e76d5b 125 | LCD_GCR_DUTY(_LCDDUTY) //0-7
Sissors 0:d04758e76d5b 126 );
Sissors 0:d04758e76d5b 127 uint8_t i;
Sissors 0:d04758e76d5b 128 uint32_t *p_pen;
Sissors 0:d04758e76d5b 129 uint8_t pen_offset; // 0 or 1
star297 1:1579bcd31410 130 uint8_t pen_bit; // 0 to 31
Sissors 0:d04758e76d5b 131 LCD->PEN[0] = 0x0;
Sissors 0:d04758e76d5b 132 LCD->PEN[1] = 0x0;
Sissors 0:d04758e76d5b 133 LCD->BPEN[0] = 0x0;
star297 3:f70873bc6121 134 LCD->BPEN[1] = 0x0;
Sissors 0:d04758e76d5b 135 p_pen = (uint32_t *)&LCD->PEN[0];
Sissors 0:d04758e76d5b 136 for (i=0;i<_LCDUSEDPINS;i++)
Sissors 0:d04758e76d5b 137 {
Sissors 0:d04758e76d5b 138 pen_offset = WF_ORDERING_TABLE[i]/32;
Sissors 0:d04758e76d5b 139 pen_bit = WF_ORDERING_TABLE[i]%32;
Sissors 0:d04758e76d5b 140 p_pen[pen_offset] |= 1 << pen_bit;
Sissors 0:d04758e76d5b 141 if (i>= _LCDFRONTPLANES) // Pin is a backplane
Sissors 0:d04758e76d5b 142 {
Sissors 0:d04758e76d5b 143 p_pen[pen_offset+2] |= 1 << pen_bit; // Enable BPEN
Sissors 0:d04758e76d5b 144 LCD->WF8B[(uint8_t)WF_ORDERING_TABLE[i]] = 1 << (i - _LCDFRONTPLANES); // fill with 0x01, 0x02, etc
Sissors 0:d04758e76d5b 145 }
star297 3:f70873bc6121 146 }
star297 3:f70873bc6121 147 LCD->GCR |= LCD_GCR_LCDEN_MASK;
star297 3:f70873bc6121 148 }
Sissors 0:d04758e76d5b 149
star297 3:f70873bc6121 150 int SLCD::_putc(int c) {
star297 3:f70873bc6121 151 Write_Char(c);
star297 3:f70873bc6121 152 return 0;
star297 3:f70873bc6121 153 }
Sissors 0:d04758e76d5b 154
star297 3:f70873bc6121 155 void SLCD::Write_Char (char lbValue) {
Sissors 0:d04758e76d5b 156 uint8_t char_val;
Sissors 0:d04758e76d5b 157 uint8_t temp;
Sissors 0:d04758e76d5b 158 uint8_t *lbpLCDWF;
Sissors 0:d04758e76d5b 159 uint8_t lbCounter;
Sissors 0:d04758e76d5b 160 uint16_t arrayOffset;
Sissors 0:d04758e76d5b 161 uint8_t position;
Sissors 0:d04758e76d5b 162
star297 3:f70873bc6121 163 if (CharPosition >= _CHARNUM)
star297 3:f70873bc6121 164 CharPosition = 0;
Sissors 0:d04758e76d5b 165 lbpLCDWF = (uint8_t *)&LCD->WF8B[0];
Sissors 0:d04758e76d5b 166 /* only ascii character if value not writeable write as @ */
Sissors 0:d04758e76d5b 167 if (lbValue>='a' && lbValue<='z') {
Sissors 0:d04758e76d5b 168 lbValue -= 32; // UpperCase
Sissors 0:d04758e76d5b 169 }
Sissors 0:d04758e76d5b 170 if (lbValue<ASCCI_TABLE_START || lbValue >ASCCI_TABLE_END) {
Sissors 0:d04758e76d5b 171 lbValue = BLANK_CHARACTER; // default value as space
Sissors 0:d04758e76d5b 172 }
Sissors 0:d04758e76d5b 173 lbValue -=ASCCI_TABLE_START; // Remove the offset to search in the ascci table
Sissors 0:d04758e76d5b 174 arrayOffset = (lbValue * _CHAR_SIZE); // Compensate matrix offset
Sissors 0:d04758e76d5b 175 // ensure bLCD position is in valid limit
Sissors 0:d04758e76d5b 176 lbCounter = 0; //number of writings to complete one char
Sissors 0:d04758e76d5b 177 while (lbCounter<_CHAR_SIZE) {
star297 3:f70873bc6121 178 position = (CharPosition) *_LCDTYPE + lbCounter;
Sissors 0:d04758e76d5b 179 temp=0;
Sissors 0:d04758e76d5b 180 if (lbCounter==1) {
Sissors 0:d04758e76d5b 181 temp = lbpLCDWF[WF_ORDERING_TABLE[position]] & 0x01;//bit 0 has the special symbol information
Sissors 0:d04758e76d5b 182 }
Sissors 0:d04758e76d5b 183 char_val = ASCII_TO_WF_CODIFICATION_TABLE[arrayOffset + lbCounter];
Sissors 0:d04758e76d5b 184 lbpLCDWF[WF_ORDERING_TABLE[position]] = char_val | temp;
Sissors 0:d04758e76d5b 185 // if (char_val==0) lbCounter = _CHAR_SIZE; //end of this character
Sissors 0:d04758e76d5b 186 lbCounter++;
star297 3:f70873bc6121 187 }
star297 3:f70873bc6121 188 CharPosition++;
Sissors 0:d04758e76d5b 189 }
Sissors 0:d04758e76d5b 190
star297 3:f70873bc6121 191 void SLCD::Home (void)
star297 1:1579bcd31410 192 {
star297 3:f70873bc6121 193 CharPosition = 0;
star297 1:1579bcd31410 194 }
star297 1:1579bcd31410 195
star297 3:f70873bc6121 196 void SLCD::Contrast (uint8_t lbContrast)
star297 3:f70873bc6121 197 {
star297 1:1579bcd31410 198 lbContrast &= 0x0F; //Forced to the only values accepted
star297 1:1579bcd31410 199 LCD->GCR |= LCD_GCR_RVTRIM(lbContrast);
star297 1:1579bcd31410 200 }
star297 1:1579bcd31410 201
star297 3:f70873bc6121 202 void SLCD::All_Segments (int mode)
star297 1:1579bcd31410 203 {
star297 1:1579bcd31410 204 uint8_t lbTotalBytes = _CHARNUM * _LCDTYPE;
star297 1:1579bcd31410 205 uint8_t lbCounter=0;
star297 1:1579bcd31410 206 uint8_t *lbpLCDWF;
star297 1:1579bcd31410 207
star297 1:1579bcd31410 208 lbpLCDWF = (uint8_t *)&LCD->WF8B[0];
star297 1:1579bcd31410 209 while (lbCounter < lbTotalBytes)
star297 1:1579bcd31410 210 {
star297 3:f70873bc6121 211 if (mode==1){lbpLCDWF[(uint8_t)WF_ORDERING_TABLE[lbCounter++]]=_ALLON;}
star297 3:f70873bc6121 212 else {lbpLCDWF[WF_ORDERING_TABLE[lbCounter++]]=0;}
star297 1:1579bcd31410 213 }
star297 1:1579bcd31410 214 }
star297 1:1579bcd31410 215
star297 3:f70873bc6121 216 void SLCD::DP1 (int mode)
star297 1:1579bcd31410 217 {
star297 1:1579bcd31410 218 uint8_t *lbpLCDWF;
star297 1:1579bcd31410 219 lbpLCDWF = (uint8_t *)&LCD->WF8B[0];
star297 3:f70873bc6121 220 if (mode==1){lbpLCDWF[(uint8_t)WF_ORDERING_TABLE[1]]|=1;}
star297 3:f70873bc6121 221 else {lbpLCDWF[(uint8_t)WF_ORDERING_TABLE[1]]&=~1;}
star297 1:1579bcd31410 222 }
star297 3:f70873bc6121 223
star297 3:f70873bc6121 224 void SLCD::DP2 (int mode)
star297 1:1579bcd31410 225 {
star297 1:1579bcd31410 226 uint8_t *lbpLCDWF;
star297 1:1579bcd31410 227 lbpLCDWF = (uint8_t *)&LCD->WF8B[0];
star297 3:f70873bc6121 228 if (mode==1){lbpLCDWF[(uint8_t)WF_ORDERING_TABLE[3]]|=1;}
star297 3:f70873bc6121 229 else {lbpLCDWF[(uint8_t)WF_ORDERING_TABLE[3]]&=~1;}
star297 3:f70873bc6121 230 }
star297 1:1579bcd31410 231
star297 3:f70873bc6121 232 void SLCD::DP3 (int mode)
star297 1:1579bcd31410 233 {
star297 1:1579bcd31410 234 uint8_t *lbpLCDWF;
star297 3:f70873bc6121 235 lbpLCDWF = (uint8_t *)&LCD->WF8B[0];
star297 3:f70873bc6121 236 if (mode==1){lbpLCDWF[(uint8_t)WF_ORDERING_TABLE[5]]|=1;}
star297 3:f70873bc6121 237 else {lbpLCDWF[(uint8_t)WF_ORDERING_TABLE[5]]&=~1;}
star297 1:1579bcd31410 238 }
star297 3:f70873bc6121 239
star297 3:f70873bc6121 240 void SLCD::Colon (int mode)
star297 1:1579bcd31410 241 {
star297 1:1579bcd31410 242 uint8_t *lbpLCDWF;
star297 3:f70873bc6121 243 lbpLCDWF = (uint8_t *)&LCD->WF8B[0];
star297 3:f70873bc6121 244 if (mode==1){lbpLCDWF[(uint8_t)WF_ORDERING_TABLE[7]]|=1;}
star297 3:f70873bc6121 245 else {lbpLCDWF[(uint8_t)WF_ORDERING_TABLE[7]]&=~1;}
star297 1:1579bcd31410 246 }
star297 3:f70873bc6121 247
Sissors 4:ec7b3c9b2aeb 248 void SLCD::blink(int blink) {
Sissors 4:ec7b3c9b2aeb 249 if (( blink > 7) || (blink < 0))
Sissors 4:ec7b3c9b2aeb 250 LCD->AR &= ~LCD_AR_BLINK_MASK;
Sissors 4:ec7b3c9b2aeb 251 else
Sissors 4:ec7b3c9b2aeb 252 LCD->AR |= LCD_AR_BLINK_MASK | blink;
Sissors 4:ec7b3c9b2aeb 253 }
Sissors 4:ec7b3c9b2aeb 254
Sissors 4:ec7b3c9b2aeb 255 void SLCD::deepsleepEnable(bool enable) {
Sissors 4:ec7b3c9b2aeb 256 MCG->C1 &= ~MCG_C1_IREFSTEN_MASK;
Sissors 4:ec7b3c9b2aeb 257 MCG->C1 |= enable << MCG_C1_IREFSTEN_SHIFT;
Sissors 4:ec7b3c9b2aeb 258 LCD->GCR &= ~LCD_GCR_LCDSTP_MASK;
Sissors 4:ec7b3c9b2aeb 259 LCD->GCR |= (!enable) << LCD_GCR_LCDSTP_SHIFT;
Sissors 4:ec7b3c9b2aeb 260 }