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Dependents:   STM32_F103-C8T6basecanblink_led

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targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ticker.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Child:
147:30b64687e01f
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file ticker.h
<> 144:ef7eb2e8f9f7 4 * @brief Microcontroller uSec ticker
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor.
<> 144:ef7eb2e8f9f7 7 * $Rev:
<> 144:ef7eb2e8f9f7 8 * $Date:
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 */
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 #ifndef TICKER_H_
<> 144:ef7eb2e8f9f7 25 #define TICKER_H_
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 #include "types.h"
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 /** Core frequency definitions. /
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 * These definitions should be adjusted to setup Orion core frequencies.
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33 #define CPU_CLOCK_ROOT_HZ ( ( unsigned long ) 32000000) /**< <b> Orion 32MHz root frequency </b> */
<> 144:ef7eb2e8f9f7 34 #define CPU_CLOCK_DIV_32M ( 1 ) /**< <b> Divider to set up core frequency at 32MHz </b> */
<> 144:ef7eb2e8f9f7 35 #define CPU_CLOCK_DIV_16M ( 2 ) /**< <b> Divider to set up core frequency at 16MHz </b> */
<> 144:ef7eb2e8f9f7 36 #define CPU_CLOCK_DIV_8M ( 4 ) /**< <b> Divider to set up core frequency at 8MHz </b> */
<> 144:ef7eb2e8f9f7 37 #define CPU_CLOCK_DIV_4M ( 8 ) /**< <b> Divider to set up core frequency at 4MHz </b> */
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 #define CPU_CLOCK_DIV CPU_CLOCK_DIV_32M /**< <b> Selected divider to be used by application code </b> */
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #define configCPU_CLOCK_HZ ( ( unsigned long ) (CPU_CLOCK_ROOT_HZ/CPU_CLOCK_DIV) )
<> 144:ef7eb2e8f9f7 42 #define configTICK_RATE_HZ ( ( unsigned long ) 1000000 ) // 1uSec ticker rate
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 /* Lowest priority */
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 #define configKERNEL_INTERRUPT_PRIORITY ( 0xFF )
<> 144:ef7eb2e8f9f7 48 #define configMAX_SYSCALL_INTERRUPT_PRIORITY ( 0x8F )
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /* Constants required to manipulate the core. Registers first... */
<> 144:ef7eb2e8f9f7 53 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )
<> 144:ef7eb2e8f9f7 54 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile unsigned long * ) 0xe000e014 ) )
<> 144:ef7eb2e8f9f7 55 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile unsigned long * ) 0xe000e018 ) )
<> 144:ef7eb2e8f9f7 56 #define portNVIC_INT_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )
<> 144:ef7eb2e8f9f7 57 #define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /* ...then bits in the registers. */
<> 144:ef7eb2e8f9f7 60 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
<> 144:ef7eb2e8f9f7 61 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
<> 144:ef7eb2e8f9f7 62 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
<> 144:ef7eb2e8f9f7 63 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /* Orion has 4 interrupt priority bits
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67 #define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 /* API definitions */
<> 144:ef7eb2e8f9f7 70 void fSysTickInit(void);
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 void fSysTickHandler(void);
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 uint32_t fSysTickRead(void);
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 void fSysTickEnableInterrupt (void);
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 void fSysTickDisableInterrupt (void);
<> 144:ef7eb2e8f9f7 79 #endif // TICKER_H_