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targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ticker.h@147:30b64687e01f, 2016-09-16 (annotated)

Committer:
<>
Date:
Fri Sep 16 16:24:25 2016 +0100
Revision:
147:30b64687e01f
Parent:
144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v126

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file ticker.h
<> 144:ef7eb2e8f9f7 4 * @brief Microcontroller uSec ticker
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor.
<> 144:ef7eb2e8f9f7 7 * $Rev:
<> 144:ef7eb2e8f9f7 8 * $Date:
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 147:30b64687e01f 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 147:30b64687e01f 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 147:30b64687e01f 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 147:30b64687e01f 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 147:30b64687e01f 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 147:30b64687e01f 15 * if applicable the software license agreement. Do not use this software and/or
<> 147:30b64687e01f 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 147:30b64687e01f 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 147:30b64687e01f 18 * terms and conditions.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 25 * @endinternal
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 *
<> 144:ef7eb2e8f9f7 28 */
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 #ifndef TICKER_H_
<> 144:ef7eb2e8f9f7 31 #define TICKER_H_
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #include "types.h"
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /** Core frequency definitions. /
<> 144:ef7eb2e8f9f7 36 *
<> 144:ef7eb2e8f9f7 37 * These definitions should be adjusted to setup Orion core frequencies.
<> 144:ef7eb2e8f9f7 38 */
<> 144:ef7eb2e8f9f7 39 #define CPU_CLOCK_ROOT_HZ ( ( unsigned long ) 32000000) /**< <b> Orion 32MHz root frequency </b> */
<> 144:ef7eb2e8f9f7 40 #define CPU_CLOCK_DIV_32M ( 1 ) /**< <b> Divider to set up core frequency at 32MHz </b> */
<> 144:ef7eb2e8f9f7 41 #define CPU_CLOCK_DIV_16M ( 2 ) /**< <b> Divider to set up core frequency at 16MHz </b> */
<> 144:ef7eb2e8f9f7 42 #define CPU_CLOCK_DIV_8M ( 4 ) /**< <b> Divider to set up core frequency at 8MHz </b> */
<> 144:ef7eb2e8f9f7 43 #define CPU_CLOCK_DIV_4M ( 8 ) /**< <b> Divider to set up core frequency at 4MHz </b> */
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 #define CPU_CLOCK_DIV CPU_CLOCK_DIV_32M /**< <b> Selected divider to be used by application code </b> */
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 #define configCPU_CLOCK_HZ ( ( unsigned long ) (CPU_CLOCK_ROOT_HZ/CPU_CLOCK_DIV) )
<> 144:ef7eb2e8f9f7 48 #define configTICK_RATE_HZ ( ( unsigned long ) 1000000 ) // 1uSec ticker rate
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /* Lowest priority */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 #define configKERNEL_INTERRUPT_PRIORITY ( 0xFF )
<> 144:ef7eb2e8f9f7 54 #define configMAX_SYSCALL_INTERRUPT_PRIORITY ( 0x8F )
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /* Constants required to manipulate the core. Registers first... */
<> 144:ef7eb2e8f9f7 59 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )
<> 144:ef7eb2e8f9f7 60 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile unsigned long * ) 0xe000e014 ) )
<> 144:ef7eb2e8f9f7 61 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile unsigned long * ) 0xe000e018 ) )
<> 144:ef7eb2e8f9f7 62 #define portNVIC_INT_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )
<> 144:ef7eb2e8f9f7 63 #define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /* ...then bits in the registers. */
<> 144:ef7eb2e8f9f7 66 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
<> 144:ef7eb2e8f9f7 67 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
<> 144:ef7eb2e8f9f7 68 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
<> 144:ef7eb2e8f9f7 69 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /* Orion has 4 interrupt priority bits
<> 144:ef7eb2e8f9f7 72 */
<> 144:ef7eb2e8f9f7 73 #define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /* API definitions */
<> 144:ef7eb2e8f9f7 76 void fSysTickInit(void);
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 void fSysTickHandler(void);
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 uint32_t fSysTickRead(void);
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 void fSysTickEnableInterrupt (void);
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 void fSysTickDisableInterrupt (void);
<> 144:ef7eb2e8f9f7 85 #endif // TICKER_H_