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targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc.c@147:30b64687e01f, 2016-09-16 (annotated)

Committer:
<>
Date:
Fri Sep 16 16:24:25 2016 +0100
Revision:
147:30b64687e01f
Parent:
144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v126

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 *******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file rtc.c
<> 144:ef7eb2e8f9f7 4 * @brief Implementation of a Rtc driver
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 3525 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2015-07-20 15:24:25 +0530 (Mon, 20 Jul 2015) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 147:30b64687e01f 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 147:30b64687e01f 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 147:30b64687e01f 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 147:30b64687e01f 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 147:30b64687e01f 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 147:30b64687e01f 15 * if applicable the software license agreement. Do not use this software and/or
<> 147:30b64687e01f 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 147:30b64687e01f 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 147:30b64687e01f 18 * terms and conditions.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 25 * @endinternal
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * @ingroup rtc
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * @details
<> 144:ef7eb2e8f9f7 30 * A real-time clock (RTC) is a computer clock ,that keeps track of the current time. The heart of the RTC is a series of
<> 144:ef7eb2e8f9f7 31 * freely running counters one for each time unit, The series of counters is linked as follows: a roll over event of
<> 144:ef7eb2e8f9f7 32 * the seconds counter produces a minutes enable pulse; a roll over event of the minutes counter produces an hours
<> 144:ef7eb2e8f9f7 33 * enable pulse, etc.Note that all Counter registers are in an undefined state on power-up.
<> 144:ef7eb2e8f9f7 34 * Use the Reset bit in the Control Register to reset the counters to their default values.
<> 144:ef7eb2e8f9f7 35 * DIVISOR is the register containing the value to divide the clock frequency to produce 1Hz strobe ; 1Hz strobe is used
<> 144:ef7eb2e8f9f7 36 * internally to time the incrementing of the Seconds Counter.
<> 144:ef7eb2e8f9f7 37 * There is a set of register to set the values in the counter for each time unit.from where time is start to increment.
<> 144:ef7eb2e8f9f7 38 * There is another set of register to set the ALARM ...Each of the Alarm Registers can be programmed with a value that
<> 144:ef7eb2e8f9f7 39 * is used to compare to a Counter Register in order to produce an alarm (an interrupt) when the values match.
<> 144:ef7eb2e8f9f7 40 * There is a programmable bit in each Alarm Register that determines if the alarm occurs upon a value match, or
<> 144:ef7eb2e8f9f7 41 * if the alarm occurs upon a Counter increment condition.
<> 144:ef7eb2e8f9f7 42 *
<> 144:ef7eb2e8f9f7 43 */
<> 144:ef7eb2e8f9f7 44 #include "rtc.h"
<> 144:ef7eb2e8f9f7 45 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 static uint16_t SubSecond;
<> 144:ef7eb2e8f9f7 48 static uint64_t LastRtcTimeus;
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /* See rtc.h for details */
<> 144:ef7eb2e8f9f7 51 void fRtcInit(void)
<> 144:ef7eb2e8f9f7 52 {
<> 144:ef7eb2e8f9f7 53 CLOCK_ENABLE(CLOCK_RTC); /* enable rtc peripheral */
<> 144:ef7eb2e8f9f7 54 CLOCKREG->CCR.BITS.RTCEN = True; /* Enable RTC clock 32K */
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /* Reset RTC control register */
<> 144:ef7eb2e8f9f7 57 RTCREG->CONTROL.WORD = False;
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /* Initialize all counters */
<> 144:ef7eb2e8f9f7 60 RTCREG->SECOND_COUNTER = False;
<> 144:ef7eb2e8f9f7 61 RTCREG->SUB_SECOND_COUNTER = False;
<> 144:ef7eb2e8f9f7 62 RTCREG->SECOND_ALARM = False;
<> 144:ef7eb2e8f9f7 63 RTCREG->SUB_SECOND_ALARM = False;
<> 144:ef7eb2e8f9f7 64 LastRtcTimeus = 0;
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 /* Reset RTC Status register */
<> 144:ef7eb2e8f9f7 67 RTCREG->STATUS.WORD = False;
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 /* Clear interrupt status */
<> 144:ef7eb2e8f9f7 70 RTCREG->INT_CLEAR.WORD = False;
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 /* Start sec & sub_sec counter */
<> 144:ef7eb2e8f9f7 73 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);/* Wait previous write to complete */
<> 144:ef7eb2e8f9f7 74 RTCREG->CONTROL.WORD |= ((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
<> 144:ef7eb2e8f9f7 75 (True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /* enable interruption associated with the rtc at NVIC level */
<> 144:ef7eb2e8f9f7 78 NVIC_SetVector(Rtc_IRQn,(uint32_t)fRtcHandler); /* TODO define lp_ticker_isr */
<> 144:ef7eb2e8f9f7 79 NVIC_ClearPendingIRQ(Rtc_IRQn);
<> 144:ef7eb2e8f9f7 80 NVIC_EnableIRQ(Rtc_IRQn);
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 return;
<> 144:ef7eb2e8f9f7 85 }
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /* See rtc.h for details */
<> 144:ef7eb2e8f9f7 88 void fRtcFree(void)
<> 144:ef7eb2e8f9f7 89 {
<> 144:ef7eb2e8f9f7 90 /* Reset RTC control register */
<> 144:ef7eb2e8f9f7 91 RTCREG->CONTROL.WORD = False;
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /* disable interruption associated with the rtc */
<> 144:ef7eb2e8f9f7 94 NVIC_DisableIRQ(Rtc_IRQn);
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 144:ef7eb2e8f9f7 97 }
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /* See rtc.h for details */
<> 144:ef7eb2e8f9f7 100 void fRtcSetInterrupt(uint32_t timestamp)
<> 144:ef7eb2e8f9f7 101 {
<> 144:ef7eb2e8f9f7 102 SubSecond = False;
<> 144:ef7eb2e8f9f7 103 uint32_t Second = False;
<> 144:ef7eb2e8f9f7 104 uint8_t DividerAdjust = 1;
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 if(timestamp) {
<> 144:ef7eb2e8f9f7 107 if(timestamp >= RTC_SEC_TO_US) {
<> 144:ef7eb2e8f9f7 108 /* TimeStamp is big enough to set second alarm */
<> 144:ef7eb2e8f9f7 109 Second = ((timestamp / RTC_SEC_TO_US) & RTC_SEC_MASK); /* Convert micro second to second */
<> 144:ef7eb2e8f9f7 110 RTCREG->SECOND_ALARM = Second; /* Write to alarm register */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /* Enable second interrupt */
<> 144:ef7eb2e8f9f7 113 RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
<> 144:ef7eb2e8f9f7 114 }
<> 144:ef7eb2e8f9f7 115 timestamp = timestamp - Second * RTC_SEC_TO_US; /* Take out micro second for sub second alarm */
<> 144:ef7eb2e8f9f7 116 if(timestamp > False) {
<> 144:ef7eb2e8f9f7 117 /* We have some thing for sub second */
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /* Convert micro second to sub_seconds(each count = 30.5 us) */
<> 144:ef7eb2e8f9f7 120 if(timestamp > 131000) {
<> 144:ef7eb2e8f9f7 121 DividerAdjust = 100;
<> 144:ef7eb2e8f9f7 122 }
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 volatile uint64_t Temp = (timestamp / DividerAdjust * RTC_CLOCK_HZ);
<> 144:ef7eb2e8f9f7 125 timestamp = (uint64_t)(Temp / RTC_SEC_TO_US * DividerAdjust);
<> 144:ef7eb2e8f9f7 126 SubSecond = Temp & RTC_SUB_SEC_MASK;
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 if(SubSecond <= 5) {
<> 144:ef7eb2e8f9f7 129 SubSecond = 0;
<> 144:ef7eb2e8f9f7 130 }
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 if(SubSecond > False) {
<> 144:ef7eb2e8f9f7 134 /* Second interrupt not enabled */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /* Set SUB SEC_ALARM */
<> 144:ef7eb2e8f9f7 137 RTCREG->SUB_SECOND_ALARM = SubSecond; /* Write to sub second alarm */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /* Enable sub second interrupt */
<> 144:ef7eb2e8f9f7 140 RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
<> 144:ef7eb2e8f9f7 141 }
<> 144:ef7eb2e8f9f7 142 }
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 144:ef7eb2e8f9f7 145 }
<> 144:ef7eb2e8f9f7 146 return;
<> 144:ef7eb2e8f9f7 147 }
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /* See rtc.h for details */
<> 144:ef7eb2e8f9f7 150 void fRtcDisableInterrupt(void)
<> 144:ef7eb2e8f9f7 151 {
<> 144:ef7eb2e8f9f7 152 /* Disable subsec/sec interrupt */
<> 144:ef7eb2e8f9f7 153 RTCREG->CONTROL.WORD &= ~((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
<> 144:ef7eb2e8f9f7 154 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 144:ef7eb2e8f9f7 155 }
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /* See rtc.h for details */
<> 144:ef7eb2e8f9f7 158 void fRtcEnableInterrupt(void)
<> 144:ef7eb2e8f9f7 159 {
<> 144:ef7eb2e8f9f7 160 /* Disable subsec/sec interrupt */
<> 144:ef7eb2e8f9f7 161 RTCREG->CONTROL.WORD |= ((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
<> 144:ef7eb2e8f9f7 162 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 144:ef7eb2e8f9f7 163 }
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /* See rtc.h for details */
<> 144:ef7eb2e8f9f7 166 void fRtcClearInterrupt(void)
<> 144:ef7eb2e8f9f7 167 {
<> 144:ef7eb2e8f9f7 168 /* Disable subsec/sec interrupt */
<> 144:ef7eb2e8f9f7 169 /* Clear sec & sub_sec interrupts */
<> 144:ef7eb2e8f9f7 170 RTCREG->INT_CLEAR.WORD = ((True << RTC_INT_CLR_SUB_SEC_BIT_POS) |
<> 144:ef7eb2e8f9f7 171 (True << RTC_INT_CLR_SEC_BIT_POS));
<> 144:ef7eb2e8f9f7 172 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 144:ef7eb2e8f9f7 173 }
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /* See rtc.h for details */
<> 144:ef7eb2e8f9f7 176 uint64_t fRtcRead(void)
<> 144:ef7eb2e8f9f7 177 {
<> 144:ef7eb2e8f9f7 178 uint32_t Second;
<> 144:ef7eb2e8f9f7 179 uint16_t SubSecond;
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /* Hardware Bug fix: The rollover of the sub-second counter initiates the increment of the second counter.
<> 144:ef7eb2e8f9f7 182 * That means there is one cycle where the sub-second has rolled back to zero and the second counter has not incremented
<> 144:ef7eb2e8f9f7 183 * and a read during that cycle will be incorrect. That will occur for one RTC cycle and that is about 31us of exposure.
<> 144:ef7eb2e8f9f7 184 * If you read a zero in the sub-second counter then increment the second counter by 1.
<> 144:ef7eb2e8f9f7 185 * Alternatively, subtract 1 from the Sub-seconds counter to align the Second and Sub-Second rollover.
<> 144:ef7eb2e8f9f7 186 */
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /* Read the Second and Sub-second counters, then read the Second counter again.
<> 144:ef7eb2e8f9f7 189 * If it changed, then the Second rolled over while reading Sub-seconds, so go back and read them both again.
<> 144:ef7eb2e8f9f7 190 */
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 do {
<> 144:ef7eb2e8f9f7 193 Second = RTCREG->SECOND_COUNTER; /* Get SEC_COUNTER reg value */
<> 144:ef7eb2e8f9f7 194 SubSecond = (RTCREG->SUB_SECOND_COUNTER - 1) & 0x7FFF; /* Get SUB_SEC_COUNTER reg value */
<> 144:ef7eb2e8f9f7 195 } while (Second != RTCREG->SECOND_COUNTER); /* Repeat if the second has changed */
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 //note: casting to float removed to avoid reduction in resolution
<> 144:ef7eb2e8f9f7 198 uint64_t RtcTimeus = ((uint64_t)SubSecond * RTC_SEC_TO_US / RTC_CLOCK_HZ) + ((uint64_t)Second * RTC_SEC_TO_US);
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /*check that the time did not go backwards */
<> 144:ef7eb2e8f9f7 201 MBED_ASSERT(RtcTimeus >= LastRtcTimeus);
<> 144:ef7eb2e8f9f7 202 LastRtcTimeus = RtcTimeus;
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 return RtcTimeus;
<> 144:ef7eb2e8f9f7 205 }
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /* See rtc.h for details */
<> 144:ef7eb2e8f9f7 208 void fRtcWrite(uint64_t RtcTimeus)
<> 144:ef7eb2e8f9f7 209 {
<> 144:ef7eb2e8f9f7 210 uint32_t Second = 0;
<> 144:ef7eb2e8f9f7 211 uint16_t SubSecond = 0;
<> 144:ef7eb2e8f9f7 212 /* Stop RTC */
<> 144:ef7eb2e8f9f7 213 RTCREG->CONTROL.WORD &= ~((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
<> 144:ef7eb2e8f9f7 214 (True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 if(RtcTimeus > RTC_SEC_TO_US) {
<> 144:ef7eb2e8f9f7 217 /* TimeStamp is big enough to set second counter */
<> 144:ef7eb2e8f9f7 218 Second = ((RtcTimeus / RTC_SEC_TO_US) & RTC_SEC_MASK);
<> 144:ef7eb2e8f9f7 219 }
<> 144:ef7eb2e8f9f7 220 RTCREG->SECOND_COUNTER = Second;
<> 144:ef7eb2e8f9f7 221 RtcTimeus = RtcTimeus - (Second * RTC_SEC_TO_US);
<> 144:ef7eb2e8f9f7 222 if(RtcTimeus > False) {
<> 144:ef7eb2e8f9f7 223 /* Convert TimeStamp to sub_seconds */
<> 144:ef7eb2e8f9f7 224 SubSecond = (uint16_t)((float)(RtcTimeus * RTC_CLOCK_HZ / RTC_SEC_TO_US)) & RTC_SUB_SEC_MASK;
<> 144:ef7eb2e8f9f7 225 }
<> 144:ef7eb2e8f9f7 226 /* Set SUB_SEC_ALARM */
<> 144:ef7eb2e8f9f7 227 RTCREG->SUB_SECOND_COUNTER = SubSecond;
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 144:ef7eb2e8f9f7 230 /* Start RTC */
<> 144:ef7eb2e8f9f7 231 RTCREG->CONTROL.WORD |= ((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
<> 144:ef7eb2e8f9f7 232 (True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 144:ef7eb2e8f9f7 235 }
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /* See rtc.h for details */
<> 144:ef7eb2e8f9f7 238 void fRtcHandler(void)
<> 144:ef7eb2e8f9f7 239 {
<> 144:ef7eb2e8f9f7 240 /* SUB_SECOND/SECOND interrupt occured */
<> 144:ef7eb2e8f9f7 241 volatile uint32_t TempStatus = RTCREG->STATUS.WORD;
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /* disable all interrupts */
<> 144:ef7eb2e8f9f7 244 RTCREG->CONTROL.WORD &= ~((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* Clear sec & sub_sec interrupts */
<> 144:ef7eb2e8f9f7 247 RTCREG->INT_CLEAR.WORD = ((True << RTC_INT_CLR_SUB_SEC_BIT_POS) |
<> 144:ef7eb2e8f9f7 248 (True << RTC_INT_CLR_SEC_BIT_POS));
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /* TODO ANDing SUB_SEC & SEC interrupt - work around for RTC issue - will be solved in REV G */
<> 144:ef7eb2e8f9f7 251 if(TempStatus & RTC_SEC_INT_STATUS_MASK) {
<> 144:ef7eb2e8f9f7 252 /* Second interrupt occured */
<> 144:ef7eb2e8f9f7 253 if(SubSecond > False) {
<> 144:ef7eb2e8f9f7 254 /* Set SUB SEC_ALARM */
<> 144:ef7eb2e8f9f7 255 RTCREG->SUB_SECOND_ALARM = SubSecond + RTCREG->SUB_SECOND_COUNTER;
<> 144:ef7eb2e8f9f7 256 /* Enable sub second interrupt */
<> 144:ef7eb2e8f9f7 257 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
<> 144:ef7eb2e8f9f7 258 RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
<> 144:ef7eb2e8f9f7 259 } else {
<> 144:ef7eb2e8f9f7 260 /* We reach here after second interrupt is occured */
<> 144:ef7eb2e8f9f7 261 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
<> 144:ef7eb2e8f9f7 262 RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
<> 144:ef7eb2e8f9f7 263 (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
<> 144:ef7eb2e8f9f7 264 }
<> 144:ef7eb2e8f9f7 265 } else {
<> 144:ef7eb2e8f9f7 266 /* We reach here after sub_second or (Sub second + second) interrupt occured */
<> 144:ef7eb2e8f9f7 267 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
<> 144:ef7eb2e8f9f7 268 RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
<> 144:ef7eb2e8f9f7 269 (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
<> 144:ef7eb2e8f9f7 270 }
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 144:ef7eb2e8f9f7 273 }
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 boolean fIsRtcEnabled(void)
<> 144:ef7eb2e8f9f7 276 {
<> 144:ef7eb2e8f9f7 277 if(RTCREG->CONTROL.BITS.SUB_SEC_COUNTER_EN | RTCREG->CONTROL.BITS.SEC_COUNTER_EN) {
<> 144:ef7eb2e8f9f7 278 return True;
<> 144:ef7eb2e8f9f7 279 } else {
<> 144:ef7eb2e8f9f7 280 return False;
<> 144:ef7eb2e8f9f7 281 }
<> 144:ef7eb2e8f9f7 282 }