jaewook shin / Mbed OS SCHMME_NIBP

SCH MME NIBP ref. code

Dependencies:   Adafruit_GFX

ADS1115.h@1:63bc0088a8ed, 2020-11-09 (annotated)

Committer:
schmme
Date:
Mon Nov 09 04:48:47 2020 +0000
Revision:
1:63bc0088a8ed
Parent:
0:8edd7b830280 
adc_data conversion to decimal

Who changed what in which revision?

UserRevisionLine numberNew contents of line
schmme 0:8edd7b830280 1 #include <mbed.h>
schmme 0:8edd7b830280 2
schmme 0:8edd7b830280 3 /*=========================================================================
schmme 0:8edd7b830280 4 I2C ADDRESS/BITS
schmme 0:8edd7b830280 5 -----------------------------------------------------------------------*/
schmme 0:8edd7b830280 6 #define ADS1115_ADDRESS (0x49) // 100 1001 (ADDR = VDD)
schmme 0:8edd7b830280 7 /*=========================================================================*/
schmme 0:8edd7b830280 8
schmme 0:8edd7b830280 9 /*=========================================================================
schmme 0:8edd7b830280 10 CONVERSION DELAY (in mS)
schmme 0:8edd7b830280 11 -----------------------------------------------------------------------*/
schmme 0:8edd7b830280 12 #define ADS1115_CONVERSIONDELAY (8)
schmme 0:8edd7b830280 13 /*=========================================================================*/
schmme 0:8edd7b830280 14
schmme 0:8edd7b830280 15 /*=========================================================================
schmme 0:8edd7b830280 16 POINTER REGISTER
schmme 0:8edd7b830280 17 -----------------------------------------------------------------------*/
schmme 0:8edd7b830280 18 #define ADS1115_REG_POINTER_MASK (0x03)
schmme 0:8edd7b830280 19 #define ADS1115_REG_POINTER_CONVERT (0x00)
schmme 0:8edd7b830280 20 #define ADS1115_REG_POINTER_CONFIG (0x01)
schmme 0:8edd7b830280 21 #define ADS1115_REG_POINTER_LOWTHRESH (0x02)
schmme 0:8edd7b830280 22 #define ADS1115_REG_POINTER_HITHRESH (0x03)
schmme 0:8edd7b830280 23 /*=========================================================================*/
schmme 0:8edd7b830280 24
schmme 0:8edd7b830280 25 /*=========================================================================
schmme 0:8edd7b830280 26 CONFIG REGISTER
schmme 0:8edd7b830280 27 -----------------------------------------------------------------------*/
schmme 0:8edd7b830280 28 #define ADS1115_REG_CONFIG_OS_MASK (0x8000)
schmme 0:8edd7b830280 29 #define ADS1115_REG_CONFIG_OS_SINGLE (0x8000) // Write: Set to start a single-conversion
schmme 0:8edd7b830280 30 #define ADS1115_REG_CONFIG_OS_BUSY (0x0000) // Read: Bit = 0 when conversion is in progress
schmme 0:8edd7b830280 31 #define ADS1115_REG_CONFIG_OS_NOTBUSY (0x8000) // Read: Bit = 1 when device is not performing a conversion
schmme 0:8edd7b830280 32
schmme 0:8edd7b830280 33 #define ADS1115_REG_CONFIG_MUX_MASK (0x7000)
schmme 0:8edd7b830280 34 #define ADS1115_REG_CONFIG_MUX_DIFF_0_1 (0x0000) // Differential P = AIN0, N = AIN1 (default)
schmme 0:8edd7b830280 35 #define ADS1115_REG_CONFIG_MUX_DIFF_0_3 (0x1000) // Differential P = AIN0, N = AIN3
schmme 0:8edd7b830280 36 #define ADS1115_REG_CONFIG_MUX_DIFF_1_3 (0x2000) // Differential P = AIN1, N = AIN3
schmme 0:8edd7b830280 37 #define ADS1115_REG_CONFIG_MUX_DIFF_2_3 (0x3000) // Differential P = AIN2, N = AIN3
schmme 0:8edd7b830280 38 #define ADS1115_REG_CONFIG_MUX_SINGLE_0 (0x4000) // Single-ended AIN0
schmme 0:8edd7b830280 39 #define ADS1115_REG_CONFIG_MUX_SINGLE_1 (0x5000) // Single-ended AIN1
schmme 0:8edd7b830280 40 #define ADS1115_REG_CONFIG_MUX_SINGLE_2 (0x6000) // Single-ended AIN2
schmme 0:8edd7b830280 41 #define ADS1115_REG_CONFIG_MUX_SINGLE_3 (0x7000) // Single-ended AIN3
schmme 0:8edd7b830280 42
schmme 0:8edd7b830280 43 #define ADS1115_REG_CONFIG_PGA_MASK (0x0E00)
schmme 0:8edd7b830280 44 #define ADS1115_REG_CONFIG_PGA_6_144V (0x0000) // +/-6.144V range = Gain 2/3
schmme 0:8edd7b830280 45 #define ADS1115_REG_CONFIG_PGA_4_096V (0x0200) // +/-4.096V range = Gain 1
schmme 0:8edd7b830280 46 #define ADS1115_REG_CONFIG_PGA_2_048V (0x0400) // +/-2.048V range = Gain 2 (default)
schmme 0:8edd7b830280 47 #define ADS1115_REG_CONFIG_PGA_1_024V (0x0600) // +/-1.024V range = Gain 4
schmme 0:8edd7b830280 48 #define ADS1115_REG_CONFIG_PGA_0_512V (0x0800) // +/-0.512V range = Gain 8
schmme 0:8edd7b830280 49 #define ADS1115_REG_CONFIG_PGA_0_256V (0x0A00) // +/-0.256V range = Gain 16
schmme 0:8edd7b830280 50
schmme 0:8edd7b830280 51 #define ADS1115_REG_CONFIG_MODE_MASK (0x0100)
schmme 0:8edd7b830280 52 #define ADS1115_REG_CONFIG_MODE_CONTIN (0x0000) // Continuous conversion mode
schmme 0:8edd7b830280 53 #define ADS1115_REG_CONFIG_MODE_SINGLE (0x0100) // Power-down single-shot mode (default)
schmme 0:8edd7b830280 54
schmme 0:8edd7b830280 55 #define ADS1115_REG_CONFIG_DR_MASK (0x00E0)
schmme 1:63bc0088a8ed 56 #define ADS1115_REG_CONFIG_DR_128SPS (0x0000) // 128SPS
schmme 1:63bc0088a8ed 57 #define ADS1115_REG_CONFIG_DR_250SPS (0x0020) // 250SPS
schmme 1:63bc0088a8ed 58 #define ADS1115_REG_CONFIG_DR_490SPS (0x0040) // 490SPS
schmme 1:63bc0088a8ed 59 #define ADS1115_REG_CONFIG_DR_920SPS (0x0060) // 920SPS
schmme 1:63bc0088a8ed 60 #define ADS1115_REG_CONFIG_DR_1600SPS (0x0080) // 1600SPS (default)
schmme 1:63bc0088a8ed 61 #define ADS1115_REG_CONFIG_DR_2400SPS (0x00A0) // 2400SPS
schmme 1:63bc0088a8ed 62 #define ADS1115_REG_CONFIG_DR_3300SPS (0x00C0) // 3300SPS
schmme 1:63bc0088a8ed 63 #define ADS1115_REG_CONFIG_DR_3300SPS (0x00E0) // 3300SPS
schmme 1:63bc0088a8ed 64
schmme 1:63bc0088a8ed 65 // #define ADS1115_REG_CONFIG_DR_8SPS (0x0000) // 8SPS
schmme 1:63bc0088a8ed 66 // #define ADS1115_REG_CONFIG_DR_16SPS (0x0020) // 16SPS
schmme 1:63bc0088a8ed 67 // #define ADS1115_REG_CONFIG_DR_32SPS (0x0040) // 32SPS
schmme 1:63bc0088a8ed 68 // #define ADS1115_REG_CONFIG_DR_64SPS (0x0060) // 64SPS
schmme 1:63bc0088a8ed 69 // #define ADS1115_REG_CONFIG_DR_128SPS (0x0080) // 128SPS (default)
schmme 1:63bc0088a8ed 70 // #define ADS1115_REG_CONFIG_DR_475SPS (0x00A0) // 475SPS
schmme 1:63bc0088a8ed 71 // #define ADS1115_REG_CONFIG_DR_860SPS (0x00C0) // 860SPS
schmme 0:8edd7b830280 72
schmme 0:8edd7b830280 73 #define ADS1115_REG_CONFIG_CMODE_MASK (0x0010)
schmme 0:8edd7b830280 74 #define ADS1115_REG_CONFIG_CMODE_TRAD (0x0000) // Traditional comparator with hysteresis (default)
schmme 0:8edd7b830280 75 #define ADS1115_REG_CONFIG_CMODE_WINDOW (0x0010) // Window comparator
schmme 0:8edd7b830280 76
schmme 0:8edd7b830280 77 #define ADS1115_REG_CONFIG_CPOL_MASK (0x0008)
schmme 0:8edd7b830280 78 #define ADS1115_REG_CONFIG_CPOL_ACTVLOW (0x0000) // ALERT/RDY pin is low when active (default)
schmme 0:8edd7b830280 79 #define ADS1115_REG_CONFIG_CPOL_ACTVHI (0x0008) // ALERT/RDY pin is high when active
schmme 0:8edd7b830280 80
schmme 0:8edd7b830280 81 #define ADS1115_REG_CONFIG_CLAT_MASK (0x0004) // Determines if ALERT/RDY pin latches once asserted
schmme 0:8edd7b830280 82 #define ADS1115_REG_CONFIG_CLAT_NONLAT (0x0000) // Non-latching comparator (default)
schmme 0:8edd7b830280 83 #define ADS1115_REG_CONFIG_CLAT_LATCH (0x0004) // Latching comparator
schmme 0:8edd7b830280 84
schmme 0:8edd7b830280 85 #define ADS1115_REG_CONFIG_CQUE_MASK (0x0003)
schmme 0:8edd7b830280 86 #define ADS1115_REG_CONFIG_CQUE_1CONV (0x0000) // Assert ALERT/RDY after one conversions
schmme 0:8edd7b830280 87 #define ADS1115_REG_CONFIG_CQUE_2CONV (0x0001) // Assert ALERT/RDY after two conversions
schmme 0:8edd7b830280 88 #define ADS1115_REG_CONFIG_CQUE_4CONV (0x0002) // Assert ALERT/RDY after four conversions
schmme 0:8edd7b830280 89 #define ADS1115_REG_CONFIG_CQUE_NONE (0x0003) // Disable the comparator and put ALERT/RDY in high state (default)
schmme 0:8edd7b830280 90 /*=========================================================================*/
schmme 0:8edd7b830280 91
schmme 0:8edd7b830280 92 typedef enum {
schmme 0:8edd7b830280 93 GAIN_TWOTHIRDS = ADS1115_REG_CONFIG_PGA_6_144V,
schmme 0:8edd7b830280 94 GAIN_ONE = ADS1115_REG_CONFIG_PGA_4_096V,
schmme 0:8edd7b830280 95 GAIN_TWO = ADS1115_REG_CONFIG_PGA_2_048V,
schmme 0:8edd7b830280 96 GAIN_FOUR = ADS1115_REG_CONFIG_PGA_1_024V,
schmme 0:8edd7b830280 97 GAIN_EIGHT = ADS1115_REG_CONFIG_PGA_0_512V,
schmme 0:8edd7b830280 98 GAIN_SIXTEEN = ADS1115_REG_CONFIG_PGA_0_256V
schmme 0:8edd7b830280 99 } adsGain_t;
schmme 0:8edd7b830280 100
schmme 0:8edd7b830280 101 uint8_t m_i2cAddress;
schmme 0:8edd7b830280 102 uint8_t m_conversionDelay;
schmme 0:8edd7b830280 103 uint8_t m_bitShift;
schmme 0:8edd7b830280 104 adsGain_t m_gain;
schmme 0:8edd7b830280 105 I2C* m_i2c;
schmme 0:8edd7b830280 106
schmme 0:8edd7b830280 107 void ADS1115_Init(I2C* i2c, uint8_t i2cAddress)
schmme 0:8edd7b830280 108 {
schmme 0:8edd7b830280 109 // shift 7 bit address 1 left: read expects 8 bit address, see I2C.h
schmme 0:8edd7b830280 110 m_i2cAddress = i2cAddress << 1;
schmme 0:8edd7b830280 111 m_conversionDelay = ADS1115_CONVERSIONDELAY;
schmme 0:8edd7b830280 112 m_gain = GAIN_TWOTHIRDS; /* +/- 6.144V range (limited to VDD +0.3V max!) */
schmme 0:8edd7b830280 113 m_i2c = i2c;
schmme 0:8edd7b830280 114 }
schmme 0:8edd7b830280 115
schmme 0:8edd7b830280 116 uint16_t ADS1115_readRegister(uint8_t i2cAddress, uint8_t reg)
schmme 0:8edd7b830280 117 {
schmme 0:8edd7b830280 118 char data[2];
schmme 0:8edd7b830280 119 data[0] = reg; // temporary use this to send address to conversion register
schmme 0:8edd7b830280 120 m_i2c->write(i2cAddress, data, 1);
schmme 0:8edd7b830280 121 m_i2c->read(i2cAddress, data, 2);
schmme 0:8edd7b830280 122 return (data[0] << 8 | data [1]);
schmme 0:8edd7b830280 123 }
schmme 0:8edd7b830280 124
schmme 0:8edd7b830280 125 void ADS1115_writeRegister(uint8_t i2cAddress, uint8_t reg, uint16_t value)
schmme 0:8edd7b830280 126 {
schmme 0:8edd7b830280 127 char cmd[3];
schmme 0:8edd7b830280 128 cmd[0] = (char)reg;
schmme 0:8edd7b830280 129 cmd[1] = (char)(value>>8);
schmme 0:8edd7b830280 130 cmd[2] = (char)(value & 0xFF);
schmme 0:8edd7b830280 131 m_i2c->write(i2cAddress, cmd, 3);
schmme 0:8edd7b830280 132 }
schmme 0:8edd7b830280 133
schmme 0:8edd7b830280 134
schmme 0:8edd7b830280 135 uint16_t ADS1115_setConti_ADC_SingleEnded(uint8_t channel)
schmme 0:8edd7b830280 136 {
schmme 0:8edd7b830280 137 if (channel > 3) {
schmme 0:8edd7b830280 138 return 0;
schmme 0:8edd7b830280 139 }
schmme 0:8edd7b830280 140
schmme 0:8edd7b830280 141 // Start with default values
schmme 0:8edd7b830280 142 uint16_t config = ADS1115_REG_CONFIG_CQUE_1CONV | // Assert ALERT/RDY after one conversions
schmme 0:8edd7b830280 143 ADS1115_REG_CONFIG_CLAT_NONLAT | // Non-latching (default val)
schmme 0:8edd7b830280 144 ADS1115_REG_CONFIG_CPOL_ACTVLOW | // Alert/Rdy active low (default val)
schmme 0:8edd7b830280 145 ADS1115_REG_CONFIG_CMODE_TRAD | // Traditional comparator (default val)
schmme 1:63bc0088a8ed 146 ADS1115_REG_CONFIG_DR_490SPS | // 490SPS
schmme 0:8edd7b830280 147 ADS1115_REG_CONFIG_MODE_CONTIN; // Countinuous-conversion mode
schmme 0:8edd7b830280 148
schmme 0:8edd7b830280 149 // Set PGA/voltage range
schmme 0:8edd7b830280 150 config |= m_gain;
schmme 0:8edd7b830280 151
schmme 0:8edd7b830280 152 // Set single-ended input channel
schmme 0:8edd7b830280 153 switch (channel) {
schmme 0:8edd7b830280 154 case (0):
schmme 0:8edd7b830280 155 config |= ADS1115_REG_CONFIG_MUX_SINGLE_0;
schmme 0:8edd7b830280 156 break;
schmme 0:8edd7b830280 157 case (1):
schmme 0:8edd7b830280 158 config |= ADS1115_REG_CONFIG_MUX_SINGLE_1;
schmme 0:8edd7b830280 159 break;
schmme 0:8edd7b830280 160 case (2):
schmme 0:8edd7b830280 161 config |= ADS1115_REG_CONFIG_MUX_SINGLE_2;
schmme 0:8edd7b830280 162 break;
schmme 0:8edd7b830280 163 case (3):
schmme 0:8edd7b830280 164 config |= ADS1115_REG_CONFIG_MUX_SINGLE_3;
schmme 0:8edd7b830280 165 break;
schmme 0:8edd7b830280 166 }
schmme 0:8edd7b830280 167 ADS1115_writeRegister(m_i2cAddress, ADS1115_REG_POINTER_LOWTHRESH, 0x7fff);
schmme 0:8edd7b830280 168 ADS1115_writeRegister(m_i2cAddress, ADS1115_REG_POINTER_HITHRESH, 0x8000);
schmme 0:8edd7b830280 169 ADS1115_writeRegister(m_i2cAddress, ADS1115_REG_POINTER_CONFIG, config);
schmme 0:8edd7b830280 170
schmme 0:8edd7b830280 171 return 0;
schmme 0:8edd7b830280 172 }
schmme 0:8edd7b830280 173
schmme 0:8edd7b830280 174 int16_t ADS1115_getConti_ADC_SingleEnded()
schmme 0:8edd7b830280 175 {
schmme 0:8edd7b830280 176 uint16_t res = ADS1115_readRegister(m_i2cAddress, ADS1115_REG_POINTER_CONVERT);
schmme 0:8edd7b830280 177 return (int16_t)res;
schmme 0:8edd7b830280 178 }