publishing to check changes in cdms code
Dependencies: FreescaleIAP SimpleDMA mbed-rtos mbed
Fork of CDMS_CODE_samp_23SEP_DMA_flag by
Diff: i2c.h
- Revision:
- 209:63e9c8f8b5d2
- Parent:
- 198:17200a427e71
- Child:
- 214:6848a51af734
- Child:
- 227:05e929bdd4dc
- Child:
- 283:5ea9ea429b55
- Child:
- 290:3159ff1081a2
diff -r d2ac4580960d -r 63e9c8f8b5d2 i2c.h --- a/i2c.h Sat Jul 02 14:25:11 2016 +0000 +++ b/i2c.h Sat Jul 02 14:54:52 2016 +0000 @@ -7,78 +7,156 @@ bool read_ack = false; const int addr_pl = 0x20<<1; //PL address const int addr_bae = 0x20; ///bae address -uint8_t rcv_isr = 0; +//uint8_t rcv_isr = 0; int count = 0; char PL_I2C_DATA[134];//Payload i2c array uint8_t PL_TM_SIZE;//size of data to bev read from i2c - -void FCTN_I2C_WRITE_PL(char *data2,uint8_t tc_len2) -{ - write_ack = master.write(addr_pl|0x00,data2,tc_len2);//address to be defined in payload - if(write_ack == 0) - {gPC.printf("\n\rData sent to PL \n");} - if(write_ack == 1) - { - gPC.printf("\n\rdata not sent\n"); - } -} +uint32_t pdirr1; +uint32_t pdirw1; -void FCTN_I2C_READ_PL(char *data,int length) -{ - PYLD_I2C_GPIO = 1; - //t_read.start(); +void I2C_busreset() +{ + PORTE->PCR[1] &= 0xfffffffb; //Enabling high slew rates for SDA and SCL lines + PORTE->PCR[0] &= 0xfffffffb; //Enabling high slew rates for SDA and SCL lines + I2C0->C1 &= 0x7f; //Disabling I2C module + SIM->SCGC4 &= 0xffffffbf; //Disabling clock to I2C module + SIM->SCGC4 |= 0x00000040; //Enabling clock to I2C module + I2C0->C1 |= 0x80; //Enabling I2C module + PORTE->PCR[1] |= 0x00000004; //Disabling high slew rates for SDA and SCL lines + PORTE->PCR[0] |= 0x00000004; //Disabling high slew rates for SDA and SCL lines + Thread::wait(1); //Wait for all I2C registers to be updates to their their values +} +bool FCTN_I2C_READ_PL(char *data,int length) // Returns 0 for success +{ + PL_I2C_GPIO = 1; read_ack = master.read(addr_pl|1,data,length); - //t_read.stop(); - - if(read_ack == 0) - gPC.printf("\n\rData received from PL \n"); - if (read_ack == 1) + Thread::wait(1); //as per tests Thread::wait not required on master side. But its safe to give 1ms + pdirr1=PTE->PDIR; + uint8_t i2c_count = 0; + if(read_ack == 0) //if read_ack says success, it may or may not be successful.Hence we check SCL and SDA + { + while(((pdirr1 & 0x03000000)!=0x03000000)&& i2c_count<10)//checking SCL and SDA for time=10ms + { + Thread::wait(1); + pdirr1=PTE->PDIR; + i2c_count++; + } + if(((pdirr1 & 0x03000000)==0x03000000))//if SCL and SDA are both high + { + gPC.printf("\n\rData received from BAE"); + } + else + { + I2C_busreset(); + read_ack = 1; + } + } + else if (read_ack == 1) { - gPC.printf("\n \r data not received \n"); + I2C_busreset(); } - PYLD_I2C_GPIO = 0; + PL_I2C_GPIO = 0; + i2c_count = 0; + return read_ack; + } - -int FCTN_I2C_READ(char *data,int length) +bool FCTN_I2C_WRITE_PL(char *data2,uint8_t tc_len2) // Returns 0 for success +{ + write_ack = master.write(addr_pl|0x00,data2,tc_len2);//address to be defined in payload + Thread::wait(1); //As per the tests Thread::wait is not required on master side but its safe to give 1ms + pdirw1=PTE->PDIR; + uint8_t i2c_count = 0; + if(write_ack == 0) + { + while(((pdirw1 & 0x03000000)!=0x03000000)&& i2c_count<10) + { + Thread::wait(1); + pdirw1=PTE->PDIR; + i2c_count++; + } + if(((pdirw1 & 0x03000000)==0x03000000)) + { + gPC.printf("\n\r Data sent"); + } + else + { + I2C_busreset(); + write_ack = 1; + } + } + if (write_ack == 1) + { + I2C_busreset(); + } + i2c_count = 0; + return write_ack; +} +bool FCTN_I2C_READ(char *data,int length) // Returns 0 for success { CDMS_I2C_GPIO = 1; - //t_read.start(); read_ack = master.read(addr_bae|1,data,length); - //t_read.stop(); - - if(read_ack == 0) - gPC.printf("\n\rData received from BAE \n"); - if (read_ack == 1) + Thread::wait(1); //as per tests Thread::wait not required on master side. But its safe to give 1ms + pdirr1=PTE->PDIR; + uint8_t i2c_count = 0; + if(read_ack == 0) //if read_ack says success, it may or may not be successful.Hence we check SCL and SDA { - gPC.printf("\n \r data not received \n"); + while(((pdirr1 & 0x03000000)!=0x03000000)&& i2c_count<10)//checking SCL and SDA for time=10ms + { + Thread::wait(1); + pdirr1=PTE->PDIR; + i2c_count++; + } + if(((pdirr1 & 0x03000000)==0x03000000))//if SCL and SDA are both high + { + gPC.printf("\n\rData received from BAE"); + } + else + { + I2C_busreset(); + read_ack = 1; + } } -//if(read_ack == 1) -//pc.printf("\n \r data not received \n"); - + else if (read_ack == 1) + { + I2C_busreset(); + } CDMS_I2C_GPIO = 0; - //gPC.printf("\n\r %d \n",t.read_us()); - //t.reset(); + i2c_count = 0; return read_ack; } -void FCTN_I2C_WRITE(char *data,uint8_t tc_len2) -{ +bool FCTN_I2C_WRITE(char *data,int tc_len2) // Returns 0 for success +{ CDMS_I2C_GPIO = 1; - //t.start(); - write_ack = master.write(addr_bae|0x00,data,tc_len2); - //t.stop(); - //if(write_ack == 0) - //gPC.printf("\n\r data not sent \n"); - -if (write_ack == 1) + write_ack = master.write(addr_bae|0x00,data,tc_len2); + Thread::wait(1); //As per the tests Thread::wait is not required on master side but its safe to give 1ms + pdirw1=PTE->PDIR; + uint8_t i2c_count = 0; + if(write_ack == 0) { -// led2 = 1; - gPC.printf("\n\r data not sent \n"); -// led2 = 0; + while(((pdirw1 & 0x03000000)!=0x03000000)&& i2c_count<10) + { + Thread::wait(1); + pdirw1=PTE->PDIR; + i2c_count++; + } + if(((pdirw1 & 0x03000000)==0x03000000)) + { + gPC.printf("\n\r Data sent"); + } + else + { + I2C_busreset(); + write_ack = 1; + } + } + if (write_ack == 1) + { + I2C_busreset(); } CDMS_I2C_GPIO = 0; - //gPC.printf("\n\r %d \n",t.read_us()); - //t.reset(); + i2c_count = 0; + return write_ack; } \ No newline at end of file