publishing to check changes in cdms code
Dependencies: FreescaleIAP SimpleDMA mbed-rtos mbed
Fork of CDMS_CODE_samp_23SEP_DMA_flag by
Diff: i2c.h
- Revision:
- 207:28a07943dded
- Parent:
- 206:fba4aeebf004
diff -r fba4aeebf004 -r 28a07943dded i2c.h --- a/i2c.h Thu Jun 30 14:00:33 2016 +0000 +++ b/i2c.h Sat Jul 02 10:48:30 2016 +0000 @@ -28,7 +28,7 @@ PORTE->PCR[0] |= 0x00000004; //Disabling high slew rates for SDA and SCL lines Thread::wait(1); //Wait for all I2C registers to be updates to their their values } -bool FCTN_I2C_READ_PL(char *data,int length) +bool FCTN_I2C_READ_PL(char *data,int length) // Returns 0 for success { PL_I2C_GPIO = 1; read_ack = master.read(addr_pl|1,data,length); @@ -62,7 +62,7 @@ return read_ack; } -bool FCTN_I2C_WRITE_PL(char *data2,uint8_t tc_len2) +bool FCTN_I2C_WRITE_PL(char *data2,uint8_t tc_len2) // Returns 0 for success { write_ack = master.write(addr_pl|0x00,data2,tc_len2);//address to be defined in payload Thread::wait(1); //As per the tests Thread::wait is not required on master side but its safe to give 1ms @@ -93,8 +93,8 @@ i2c_count = 0; return write_ack; } -bool FCTN_I2C_READ(char *data,int length) -{ +bool FCTN_I2C_READ(char *data,int length) // Returns 0 for success +{ CDMS_I2C_GPIO = 1; read_ack = master.read(addr_bae|1,data,length); Thread::wait(1); //as per tests Thread::wait not required on master side. But its safe to give 1ms @@ -127,7 +127,7 @@ return read_ack; } -bool FCTN_I2C_WRITE(char *data,int tc_len2) +bool FCTN_I2C_WRITE(char *data,int tc_len2) // Returns 0 for success { CDMS_I2C_GPIO = 1; write_ack = master.write(addr_bae|0x00,data,tc_len2);