LSM303DLH_RegisterDef.h

00001 /*
00002  *
00003  * This file is subject to the terms and conditions of the GNU Lesser
00004  * General Public License v2.1. See the file LICENSE in the top level
00005  * directory for more details.
00006  */
00007 
00008 #ifndef __LSM303DLH_REGISTERDEF_H_
00009 #define __LSM303DLH_REGISTERDEF_H_
00010 
00011 /** @defgroup LSM303_Register
00012   * @author      Salco <JeSuisSalco@gmail.com>
00013   */
00014 
00015 /** @defgroup regA
00016   * Register for accelerometer
00017   * @ingroup LSM303_Register 
00018   * @{        
00019   */
00020 
00021 //#if defined(DOXYGEN_ONLY)
00022 
00023 /**@note add LSM303DLH:: to use the docc doxygen for no reason*/
00024 
00025 /** CTRL_REG1_A structure definition
00026  */ 
00027 union Ctrl_Reg1_A_t 
00028 {
00029     uint8_t byte; /**< Value in byte.*/
00030     struct{
00031         uint8_t Xen:1; /**< X axis enable. Default value: 1.*/
00032         uint8_t Yen:1; /**< Y axis enable. Default value: 1.*/
00033         uint8_t Zen:1; /**< Z axis enable. Default value: 1.*/
00034         uint8_t LPen:1;/**< Low-power mode enable. Default value: 0.*/
00035         uint8_t ODR:4; /**< Data rate selection. Default value: 0.*/
00036     };    
00037 };
00038 
00039 /** CTRL_REG2_A structure definition
00040  */ 
00041 union Ctrl_Reg2_A_t
00042 {
00043     uint8_t byte; /**< Value in byte.*/
00044     struct{
00045         uint8_t HPIS1:1;    /**< High pass filter enabled for AOI function on Interrupt 1.*/
00046         uint8_t HPIS2:1;    /**< High pass filter enabled for AOI function on Interrupt 2.*/
00047         uint8_t HPCLICK:1;  /**< High pass filter enabled for CLICK function.*/
00048         uint8_t FDS:1;      /**< Filtered data selection. Default value: 0.*/
00049         uint8_t HPCF:2;     /**< High pass filter cut-off frequency selection.*/
00050         uint8_t HPM:2;      /**< High pass filter mode selection. Default value: 00*/
00051     };    
00052 };
00053 
00054 /** CTRL_REG3_A structure definition
00055  */ 
00056 union Ctrl_Reg3_A_t
00057 {
00058     uint8_t byte; /**< Value in byte.*/
00059     struct{
00060         uint8_t _Reserved:1;    /**< Do not use.*/
00061         uint8_t I1_OVERRUN:1;  /**< FIFO overrun interrupt on INT1. Default value 0.*/
00062         uint8_t I1_WTM:1;      /**< FIFO watermark interrupt on INT1. Default value 0.*/
00063         uint8_t I1_DRDY2:1;    /**< DRDY2 interrupt on INT1. Default value 0.*/
00064         uint8_t I1_DRDY1:1;    /**< DRDY1 interrupt on INT1. Default value 0.*/
00065         uint8_t I1_AOI2:1;     /**< AOI2 interrupt on INT1. Default value 0.*/
00066         uint8_t I1_AOI1:1;     /**< AOI1 interrupt on INT1. Default value 0.*/
00067         uint8_t I1_CLICK:1;    /**< CLICK interrupt on INT1. Default value 0.*/
00068     };    
00069 };
00070 
00071 /** CTRL_REG4_A structure definition
00072  */ 
00073 union Ctrl_Reg4_A_t
00074 {
00075     uint8_t byte; /**< Value in byte.*/
00076     struct{
00077         uint8_t SIM:1;      /**< SPI serial interface mode selection. Default value: 0.*/
00078         uint8_t _Reserved:2; /**< Do not use.*/
00079         uint8_t HR:1;       /**< High resolution output mode: Default value: 0.*/
00080         uint8_t FS:2;       /**< Full-scale selection. Default value: 00.*/
00081         uint8_t BLE:1;      /**< Big/little endian data selection. Default value 0.*/
00082         uint8_t BDU:1;      /**< Block data update. Default value: 0.*/
00083     };    
00084 };
00085 
00086 /** CTRL_REG5_A structure definition
00087  */ 
00088 union Ctrl_Reg5_A_t
00089 {
00090     uint8_t byte; /**< Value in byte.*/
00091     struct{
00092         uint8_t D4D_INT2:1;      /**< 4D detection is enabled on INT2 when 6D bit on INT2_CFG is set to 1.*/                
00093         uint8_t LIR_INT2:1;      /**< Latch interrupt request on INT2_SRC register, with INT2_SRC register 
00094                                       cleared by reading INT2_SRC itself. Default value: 0.*/
00095         uint8_t D4D_INT1:1;      /**< 4D detection is enabled on INT1 when 6D bit on INT1_CFG is set to 1.*/                
00096         uint8_t LIR_INT1:1;      /**< Latch interrupt request on INT1_SRC register, with INT1_SRC register 
00097                                       cleared by reading INT1_SRC itself. Default value: 0.*/
00098         uint8_t _Reserved:2;      /**< Do not use.*/
00099         uint8_t FIFO_EN:1;       /**< FIFO enable. Default value: 0.*/
00100         uint8_t BOOT:1;          /**< Reboot memory content. Default value: 0.*/
00101     };   
00102 };
00103 
00104 
00105 
00106 /** CTRL_REG6_A structure definition
00107  */ 
00108 union Ctrl_Reg6_A_t
00109 {
00110     uint8_t byte; /**< Value in byte.*/
00111     struct{
00112         uint8_t _Reserved:1;     /**< Do not use.*/
00113         uint8_t H_LACTIVE:1;    /**< Interrupt active high, low. Default value 0.*/    
00114         uint8_t __Reserved:1;     /**< Do not use.*/            
00115         uint8_t P2_ACT:1;       /**< Active function status on PAD2. Default value 0.*/
00116         uint8_t BOOT_I1:1;      /**< Reboot memory content on PAD2. Default value: 0.*/                
00117         uint8_t I2_INT2:1;      /**< Interrupt 2 on PAD2. Default value 0.*/
00118         uint8_t I2_INT1:1;      /**< Interrupt 1 on PAD2. Default value 0.*/
00119         uint8_t I2_CLICKen:1;   /**< CLICK interrupt on PAD2. Default value 0.*/
00120     };   
00121 };
00122 
00123  /** Status_Reg_A structure definition
00124  */ 
00125 union Status_Reg_A_t
00126 {
00127     uint8_t byte; /**< Value in byte.*/
00128     struct{
00129         
00130         uint8_t XDA:1;          /**< X axis new data available. Default value: 0.*/    
00131         uint8_t YDA:1;          /**< Y axis new data available. Default value: 0.*/            
00132         uint8_t ZDA:1;          /**< Z axis new data available. Default value: 0.*/
00133         uint8_t ZYXDA:1;        /**< X, Y, and Z axis new data available. Default value: 0.*/                
00134         uint8_t XOR:1;          /**< X axis data overrun. Default value: 0.*/
00135         uint8_t YOR:1;          /**< Y axis data overrun. Default value: 0.*/
00136         uint8_t ZOR:1;          /**< Z axis data overrun. Default value: 0.*/
00137         uint8_t ZYXOR:1;        /**< X, Y, and Z axis data overrun. Default value: 0.*/
00138     };   
00139 };
00140 
00141 /** OUT_XYZ structure. The value is expressed in 2’s complement
00142 */
00143 union OUT_XYZ_t
00144 {
00145     int16_t value;      /**< Value in signed integer.*/
00146     uint8_t byte[2];
00147     struct{
00148         uint8_t UT_L_A; /**< Low register.*/
00149         uint8_t UT_H_A; /**< High register.*/
00150     };
00151 };
00152 /** @} */ // end of regA
00153 
00154 /** @defgroup regM  
00155   *  Register for magnetometer
00156   * @ingroup LSM303_Register 
00157   *  @{        
00158   */
00159  
00160 /** SR_Reg_M structure definition
00161  */ 
00162 union SR_Reg_M_t
00163 {
00164     uint8_t byte; /**< Value in byte.*/
00165     struct{
00166         uint8_t DRDY:1;      /**< Data output register lock.*/                
00167         uint8_t LOCK:1;      /**< Data ready bit.*/ 
00168         uint8_t _Reserved:8; /**< Do not use.*/
00169     };   
00170 };
00171 
00172 /** CRA_REG_M structure definition
00173  */ 
00174 union CRA_REG_M_t
00175 {
00176     uint8_t byte; /**< Value in byte.*/
00177     struct{
00178         uint8_t _Reserved:2;    /**< Do not use.  Must be set to 0*/
00179         uint8_t DO:3;           /**< Data output rate bits.*/
00180         uint8_t __Reserved:2;   /**< Do not use.  Must be set to 0*/
00181         uint8_t TEMP_EN:1;      /**< Temperature sensor enable.*/
00182     };   
00183 };
00184 
00185 /** CRB_REG_M structure definition
00186  */ 
00187 union CRB_REG_M_t
00188 {
00189     uint8_t byte; /**< Value in byte.*/
00190     struct{
00191         uint8_t _Reserved:5;      /**< Do not use.  Must be set to ‘0*/
00192         uint8_t GN:3;           /**< Gain configuration.*/                               
00193     };   
00194 };
00195 
00196 /** MR_REG_M structure definition
00197  */ 
00198 union MR_REG_M_t
00199 {
00200     uint8_t byte; /**< Value in byte.*/
00201     struct{
00202         uint8_t MD:2;           /**< Mode select bits. These bits select the operation mode of this device.*/    
00203         uint8_t _Reserved:6;    /**< Do not use.  Must be set to 0*/
00204                                    
00205     };   
00206 };
00207 /** @} */ // end of regM
00208 
00209 #endif //__LSM303DLH_REGISTERDEF_H_